JVC TH-A10 Service Manual page 36

TH-A10
MN102LP25G-01(IC401):UNIT CPU
Symbol
I/O
Pin No.
1
I
WAIT
2
O
RE
3
MUTE O
4
O
WEM
5
CS0 O
6
O
CS1
7
O
CS2
8
CS3 O
9
O
TCLOSE
10
TOPEN O
11
I
LSIRST
12
O
WORD
13
A0 O
14
O
A1
15
A2 O
16
O
A3
17
-
VDD
18
SYSCLK O
19
-
VSS
20
XI -
21
-
XO
22
-
VDD
23
OSCI I
24
-
OSCO
25
MODE I
26
O
A4
27
O
A5
28
A6 O
29
O
A7
30
A8 O
31
O
A9
32
O
A10
33
A11 O
34
-
VDD
35
A12 O
36
O
A13
37
O
A14
38
A15 O
39
O
A16
40
A17 O
41
O
A18
42
A19 O
43
VSS -
44
O
A20
45
- -
46
-
STOP
47
ADPD -
48
- -
49
-
-
50
TRVSW I
1-36
Function
Micon wait signal input
Read enable
Driver mute
Write enable
Non connect
Chip select for ODC
Chip select for ZIVA
Chip select for outer ROM
Tray close signal output
Tray open signal output
LSI reset
Bus selection input
Address bus 0 for CPU
Address bus 1 for CPU
Address bus 2 for CPU
Address bus 3 for CPU
Power supply
System clock signal output
Power supply
Non connect
Non connect
Power supply
Clock signal input(13.5MHz)
Non connect
CPU Mode selection input
Address bus 4 for CPU
Address bus 5 for CPU
Address bus 6 for CPU
Address bus 7 for CPU
Address bus 8 for CPU
Address bus 9 for CPU
Address bus 10 for CPU
Address bus 11 for CPU
Power supply
Address bus 12 for CPU
Address bus 13 for CPU
Address bus 14 for CPU
Address bus 15 for CPU
Address bus 16 for CPU
Address bus 17 for CPU
Address bus 18 for CPU
Address bus 19 for CPU
Power supply
Address bus 20 for CPU
Non connect
Non connect
Non connect
Non connect
Non connect
Detection switch of traverse
inside
Symbol
I/O
Pin No.
I
51 SWCLOSE
I
52 SWOPEN
53 ADSCEN O
-
54 VDD
55 EFPEN O
O
56 SLEEP
I
57 BUSY
58 REQ O
O
59 WEROM
60 WPROM O
-
61 VSS
O
62 EECS
63 EECK O
I
64 EEDI
65 EEDO O
-
66 VDD
I
67 SCLK0
68 S2UDT I
O
69 S2SDT
70 CPSCK O
I
71 SDIN
O
72 SDOUT
73 - -
-
74 -
75 NMI -
I
76 ADSCIRQ
I
77 ODCIRQ
78 DECIRQ I
O
79 WAKEUP
80 ODCIRQ2 I
I
81 ADSEP
I
82 RST
83 VDD -
I
84 TEST1
85 TEST2 I
I
86 TEST3
I
87 TEST4
88 TEST5 I
I
89 TEST6
90 TEST7 I
I
91 TEST8
92 VSS -
93 D0 I/O
I/O
94 D1
95 D2 I/O
I/O
96 D3
97 D4 I/O
98 D5 I/O
I/O
99 D6
100 D7 I/O
Function
Detection switch of tray close
Detection switch of tray open
Serial enable signal for ADSC
Non connect
Serial enable signal for FEP
Standby signal for FEP
Communication busy
Communication Request
Non connect
Non connect
Power supply
Chip select signal for EEPROM
Clock signal for EEPROM
Input data for EEPROM
Output data for EEPROM
Power supply
Communication clock
Communication input data
Communication output data
Clock for ADSC serial
ADSC serial data input
ADSC serial data output
Non connect
Non connect
Non connect
Interrupt input of ADSC
Interrupt input of ODC
Interrupt input of ZIVA
Non connect
Non connect
Address data selection input
Reset input
Power supply
Test signal 1 input
Test signal 2 input
Test signal 3 input
Test signal 4 input
Test signal 5 input
Test signal 6 input
Test signal 7 input
Test signal 8 input
Power supply
Data bus 0 of CPU
Data bus 1 of CPU
Data bus 2 of CPU
Data bus 3 of CPU
Data bus 4 of CPU
Data bus 5 of CPU
Data bus 6 of CPU
Data bus 7 of CPU