JVC TH-A10 Service Manual page 35

MC44724AVFU (IC554) : VIDEO ENCODER
1.Terminal layout
64 ~ 49
48
1
33
16
17 ~ 32
3.Pin function
No. Symbol
I/O
1
O Analog composite drive signal (+)
CVBS/Cb/B1
2
O Analog composite drive signal (-)
CVBS/Cb/B1
3
- Power supply for CVBS/Cb/B DAC1
CVBS/Cb/B1Vdd
4
O Analog brightness signal/G drive signal (+)
Y/G1
5
O Analog brightness signal/G drive signal (-)
Y/G1
6
- Power supply for Y/G DAC
Y/G1/Vdd
7
O Analog chroma signal (+)
C/Cr/R1
8
O Analog chroma signal (-)
C/Cr/R1
9
- Power supply for C/Cr/RDAC
C/Cr/R1Vdd
10
- Connect to ground for DAC
DAVss
11
O Standard BIAS for DAC1
TBIAS1
12
- Standard voltage for DAC1
Vref1
13
- Power supply for DAC
DAVdd
14
- Standard voltage for DAC2
Vref2
15
O Standard BIAS for DAC2
TBIAS2
16
- Non connect
NC
17
O
Analog composite drive signal (+)
CVBS/Cb/B2
18
O Analog composite drive signal (-)
CVBS/Cb/B2
19
- Power supply for CVBS/Cb/B DAC2
CVBS/Cb/B2Vdd
20
O Analog brightness signal/G drive signal (+)
Y/G2
21
O Analog brightness signal/G drive signal (-)
Y/G2
22
-
Power supply for Y/G DAC
Y/GVdd
23
O Analog chroma signal (+)
C/Cr/R2
24
O Analog chroma signal (-)
C/Cr/R2
25
- Power supply for C/Cr/RDAC2
C/Cr/R2Vdd
26
- Chip address selection
ChipA
27
I Connect to test pin
TEST
28
- Digital ground
DVdd
29
I Clock signal input (27MHz)
CLOCK
30
- Power supply for digital circuit
DVss
31
I Reset signal input L:ON
Reset
32
I Selection NTSC/PAL NTSC:L PAL:H
PAL/NTSC
2.Block diagrams
ChipA
DVdd
DVdd
DVss
DVss
0
H.V
DVIN[7:0] Y
DEMAX
0
TP[8:1]
cb
TVIN
cr
TP[0]IN
Clock
Reset
12C / SPI
PAL/NTSC
Function
Copy,
Sync_ generator
protection
CGMS,
CCwss gen
wss gen
0
+
off_set
0
+
0
0
Modulator
sub carrier
gen
0
0
RGB
matrix
0
TEST
No. Symbol I/O
-
33 SO Non connect
I
34 SDA/SI SPI Mode : Serial data input
I
35 SCL/SCK Serial clock input
I
36 SEL Power supply for serial data,chip select,digital
--
37 DVdd Power supply for digital circuit
--
38 DVss Digital ground
I/O
39 DVIN7 Y data input / test data I/O
I/O
40 DVIN6 Y data input / test data I/O
I/O
41 DVIN5 Y data input / test data I/O
I/O
42 DVIN4 Y data input / test data I/O
I/O
43 DVIN3 Y data input / test data I/O
I/O
44 DVIN2 Y data input / test data I/O
I/O
45 DVIN1 Y data input / test data I/O
I/O
46 DVIN0 Y data input / test data I/O
I
47 TVIN VIDEO mute on Reset(0:nomal, 1:mute)
I/O
48 EXT Frame output / VBI information input
I/O
49 F/Vsyac
Frame / Vertical, synchronous I/O
I/O
50 Chsyac The horizontal, synchronous I/O
I
51 DATST Data input
I/O
52 TP-8 Multiplex data input
I/O
53 TP7 Multiplex data input
I/O
54 TP6
Multiplex data input
I/O
55 TP5 Multiplex data input
-
56 DVss Ground for digital circuit
-
57 DVdd Power supply for digital circuit
I/O
58 TP4 Data input / Test data I/O
I/O
59 TP3 Data input / Test data I/O
I/O
60 TP2 Data input / Test data I/O
I/O
61 TP1 Data input / Test data I/O
I/O
62 TP0 Data input / Test data I/O
-
63 DLVdd Power supply for D/A converter
-
64 DLVss Ground for D/A converter
Y/G1Vdd
bus
CVBS/Cb/B1Vdd
C/Cr/R1Vdd
Y/G1
Y/G1
CVBS/Cb/B1
CVBS/Cb/B1
C/Cr/R1
C/Cr/R1
Vref1
iBIAS1
Y/G2
Y/G2
CVBS/Cb/B2
CVBS/Cb/B2
C/Cr/R2
C/Cr/R2
Vref2
Ibias
DAVdd
DAVss
Function
TH-A10
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