Nuvoton NuMicro MS51 Series Technical Reference Manual
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Nuvoton NuMicro MS51 Series Technical Reference Manual

8-bit microcontroller
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Technical Reference Manual
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
Dec. 17, 2019
®
NuMicro
Family
MS51 Series
MS51FB9AE
MS51XB9AE
MS51XB9BE
www.nuvoton.com
Page 1 of 316
1T 8051
8-bit Microcontroller
MS51
Rev 1.01

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  • Page 1 The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions.

  • Page 2: Table Of Contents

    MS51 TABLE OF CONTENTS 1 GENERAL DESCRIPTION ................8 2 FEATURES ...................... 9 3 PARTS INFORMATION ................. 12 3.1 Package Type ......................12 3.2 MS51 Series Selection Guide ..................12 3.3 MS51 Series Selection Code ..................13 4 PIN CONFIGURATION .................. 14 4.1 MS51 16KB Series Multi Function Pin Diagram .............
  • Page 3 MS51 6.2.16 External Interrupt Pins ....................169 6.3 Flash Memory Contorl ....................180 6.3.1 In-Application-Programming (IAP) ................180 6.3.2 In-Circuit-Programming (ICP) ..................190 6.3.3 ON-CHIP-DEBUGGER (OCD) ................... 190 6.3.4 96-Bit Unique Code ...................... 192 6.4 General Purpose IO (GPIO) ..................193 6.4.1 GPIO Mode ........................
  • Page 4 MS51 6.10.5 I C Interrupt ........................275 6.10.6 Control Registers ......................275 6.10.7 Typical Structure of I C Interrupt Service Routine ........... 279 6.11 Pulse Width Modulated (PWM) ................. 283 6.11.1 PWM Generator ......................283 6.11.2 PWM Types ........................286 6.11.3 Operation Modes ......................
  • Page 5 MS51 LIST OF FIGURES Figure 4.1-1 Pin Assignment of TSSOP-20 Package ..............14 Figure 4.1-2 Pin Assignment of QFN-20 Package ................. 15 Figure 4.1-3 Pin Assignment of QFN-20 Package ................. 16 Figure 5.1-1 Functional Block Diagram ..................20 Figure 6.1-1 MS51 Program Memory Map and Boot Select ............22 Figure 6.1-2 SPROM Memory Mapping And SPROM Security Mode ...........
  • Page 6 MS51 Figure 6.9-6 SPI Clock and Data Format with CPHA = 1 ............259 Figure 6.9-7 SPI Overrun Waveform .................... 261 Figure 6.9-8 SPI Interrupt Request ....................261 Figure 6.10-1 I C Bus Interconnection ..................265 Figure 6.10-2 I C Bus Protocol ....................266 Figure 6.10-3 START, Repeated START, and STOP Conditions ..........
  • Page 7 MS51 List of Tables Table 6.1-1 Special Function Register Memory Map ..............34 Table 6.1-2 SFR Definitions and Reset Values ................38 Table 6.2-1 Interrupt Vectors ....................... 166 Table 6.2-2 Interrupt Priority Level Setting .................. 167 Table 6.2-3 Characteristics of Each Interrupt Source ..............168 Table 6.3-1 IAP Modes and Command Codes ................

  • Page 8: General Description

    MS51 GENERAL DESCRIPTION The MS51 16KB series are embedded flash type, 8-bit high performance 1T 8051-based microcontroller. The instruction set is fully compatible with the standard 80C51 and performance enhanced. The MS51 16KB series contains a up of main Flash called APROM, in which the contents of User Code resides.

  • Page 9: Features

    MS51 FEATURES Core and System  Fully static design 8-bit high performance 1T 8051-based CMOS microcontroller.  Instruction set fully compatible with MCS-51. 8051  4-priority-level interrupts capability.  Dual Data Pointers (DPTRs). Power On Reset (POR)  POR with 1.15V threshold voltage level ...
  • Page 10 MS51  Two 16-bit Timers/Counters 0 and 1 compatible with standard 8051.  One 16-bit Timer2 with three-channel input capture module 16-bit Timer and 9 input pin can be selected.  One 16-bit auto-reload Timer3, which can be the baud rate clock source of UART0 and UART1.
  • Page 11 MS51  Supports up to 2 UARTs: UART0 & UART1  Full-duplex asynchronous communications UART  Programmable 9 bit.  TXD and RXD of UART0 pins exchangeable via software.  1 sets of I C devices  Master/Slave mode  Bidirectional data transfer between masters and slaves ...

  • Page 12: Parts Information

    MS51 PARTS INFORMATION Package Type MSOP10 TSSOP14 TSSOP20 QFN20 TSSOP28 LQFP32 QFN33 MS51BA9AE MS51DA9AE MS51FB9AE MS51XB9AE MS51EC0AE MS51PC0AE MS51TC0AE Part MS51FC0AE MS51XB9BE MS51XC0BE MS51 Series Selection Guide Connectivity Part Number MS51BA9AE 5-ch MSOP10 MS51DA9AE 7-ch TSSOP14 MS51XB9AE 8-ch QFN20 MS51XB9BE 8-ch QFN20 MS51FB9AE...

  • Page 13: Ms51 Series Selection Code

    MS51 MS51 Series Selection Code Core Line Package Flash SRAM Reserve Temperature 1T 8051 51: Base B: MSOP10 (3x3 mm) A: 8 KB 0: 2 KB E:-40 ~ 105°C Industry D: TSSOP14 (4.4x5.0 mm) B: 16 KB 1: 4 KB E: TSSOP28 (4.4x9.7 mm) C: 32 KB 2: 8/12 KB...

  • Page 14: Pin Configuration

    Users can find pin configuaration informations by using NuTool - PinConfigure. The NuTool - ® PinConfigure contains all Nuvoton NuMicro Family chip series with all part number, and helps users configure GPIO multi-function correctly and handily. MS51 16KB Series Multi Function Pin Diagram 4.1.1...

  • Page 15: Qfn 20-Pin Package Pin Diagram

    MS51 4.1.2 QFN 20-pin Package Pin Diagram 4.1.2.1 MS51XB9AE Pin Diagram Corresponding Part Number: MS51XB9AE 15 14 13 12 11 ADC_CH5 / STADC / PWM0_CH3 / IC3 / P0.4 P1.4 / PWM0_CH1 / I2C0_SDA / PWM0_BRAKE INT0 / OSCIN / ADC_CH1 / P3.0 P1.2 / PWM0_CH0 / IC0 nRESET / P2.0 P1.1 / PWM0_CH1 / IC1 / ADC_CH7 /CLKO...

  • Page 16: Figure 4.1-3 Pin Assignment Of Qfn-20 Package

    MS51 4.1.2.2 MS51XB9BE Pin Diagram Corresponding Part Number: MS51XB9BE 15 14 13 12 11 PWM0_CH5 / IC5 / ADC_CH6 / P0.3 P1.2 / PWM0_CH0 / IC0 ADC_CH5 / STADC / PWM0_CH3 / IC3 / P0.4 P1.3 / I2C0_SCL / [STADC] PWM0_CH2 / IC6 / T0 / ADC_CH4 / P0.5 MS51XB9BE P1.4 / PWM0_CH1 / I2C0_SDA / PWM0_BRAKE...

  • Page 17: Ms51 16Kb Series Pin Description

    MS51 MS51 16KB Series Pin Description Pin Number Symbol Multi-Function Description MS51FB9AE MS51XB9AE MS51XB9BE POWER SUPPLY: Supply voltage V for operation. GROUND: Ground potential. P0.0 Port 0 bit 0. PWM0_CH3 PWM0 output channel 3. SPI0_MOSI SPI master output/slave input. Input capture channel 3. External count input to Timer/Counter 1 or its toggle output.
  • Page 18 MS51 Pin Number Symbol Multi-Function Description MS51FB9AE MS51XB9AE MS51XB9BE ADC_CH3 ADC input channel 3. P0.7 Port 0 bit 7. UART0_RXD Serial port 0 receive input. ADC_CH2 ADC input channel 2. P1.0 Port 1 bit 0. PWM0_CH2 PWM0 output channel 2. Input capture channel 2.
  • Page 19 MS51 Pin Number Symbol Multi-Function Description MS51FB9AE MS51XB9AE MS51XB9BE ADC_CH0 ADC input channel 0. Port 2 bit 0 input pin available when RPD (CONFIG0.2) is P2.0/ programmed as 0. nRESET pin is a Schmitt trigger input pin for hardware device reset.

  • Page 20: Block Diagram

    MS51 BLOCK DIAGRAM MS51 16KB Series Block Diagram Figure 5.1-1 Functional Block Diagram shows the MS51 functional block diagram and gives the outline of the device. User can find all the peripheral functions of the device in the diagram. Power-on Reset 1T High Power and Brown-out...

  • Page 21: Function Description

    MS51 FUNCTION DESCRIPTION Memory Organization A standard 80C51 based microcontroller divides the memory into two different sections, Program Memory and Data Memory. The Program Memory is used to store the instruction codes, whereas the Data Memory is used to store data or variations during the program execution. The Data Memory occupies a separate address space from Program Memory.

  • Page 22: Figure 6.1-1 Ms51 Program Memory Map And Boot Select

    MS51 CONFIG1 LDSIZE[2:0] Factory default value: 1111 1111b Name Description LDSIZE[2:0] LDROM size select This field selects the size of LDROM. 111 = No LDROM. APROM is 16K Bytes. 110 = LDROM is 1K Bytes. APROM is 15K Bytes. 101 = LDROM is 2K Bytes. APROM is 14K Bytes. 100 = LDROM is 3K Bytes.

  • Page 23: Data Flash

    MS51 6.1.2 Data Flash MS51 Series Data Flash is shared with APROM or LDROM. Any page of APROM or LDROM can be used as non-volatile data flash storage and size no need special configuration. The base address of Data Flash is determined by applying IAP, For IAP details, please see Chapter 6.3 Flash Memory Contorl In-Application-Programming (IAP).

  • Page 24: Figure 6.1-3 Config0 Any Reset Reloading

    MS51 CONFIG0 OCDPWM OCDEN LOCK Factory default value: 1111 1111b Name Description CONFIG boot select This bit defines from which block that MCU re-boots after resets except software reset. 1 = MCU will re-boot from APROM after resets except software reset. 0 = MCU will re-boot from LDROM after resets except software reset.
  • Page 25 MS51 CONFIG1 LDSIZE[2:0] Factory default value: 1111 1111b Name Description LDROM size select LDSIZE[2:0] 111 = No LDROM. APROM is 16 Kbytes. 110 = LDROM is 1 Kbytes. APROM is 15 Kbytes. 101 = LDROM is 2 Kbytes. APROM is 14 Kbytes. 100 = LDROM is 3 Kbytes.

  • Page 26: Figure 6.1-4 Config2 Power-On Reset Reloading

    MS51 CONFIG2 CBODEN CBOV[2:0] BOIAP CBORST Factory default value: 1111 1111b Name Description CONFIG brown-out detect enable CBODEN 1 = Brown-out detection circuit on. 0 = Brown-out detection circuit off. CONFIG brown-out voltage select CBOV[1:0] 11 = V is 2.2V. 10 = V is 2.7V.
  • Page 27 MS51 CONFIG4 WDTEN[3:0] Factory default value: 1111 1111b Name Description WDT enable WDTEN[3:0] This field configures the WDT behavior after MCU execution. 1111 = WDT is Disabled. WDT can be used as a general purpose timer via software control. 0101 = WDT is Enabled as a time-out reset timer and it stops running during Idle or Power- down mode.

  • Page 28: Data Memory

    MS51 6.1.5 Data Memory 6.1.5.1 Internal Data Memory 0FFFH Upper 128 Bytes 07FFH internal RAM (direct addressing) 03FFH (indirect addressing) Lower 128 Bytes internal RAM 1KByte XRAM (direct or indirect (MOVX addressing) addressing) 0000H Figure 6.1-5 Data Memory Map Figure 6.1-5 Data Memory Map shows the internal Data Memory spaces available on MS51. Internal Data Memory occupies a separate address space from Program Memory.

  • Page 29: Figure 6.1-6 Internal 256 Bytes Ram Addressing

    MS51 Indirect Accessing RAM Direct or Indirect Accessing RAM Bit-addressable Register Bank 3 Register Bank 2 General Purpose General Purpose Registers Registers Register Bank 1 Register Bank 0 Figure 6.1-6 Internal 256 Bytes RAM Addressing Dec. 17, 2019 Page 29 of 316 Rev 1.01...

  • Page 30: Special Function Register (Sfr)

    MS51 6.1.5.2 On-Chip XRAM The MS51 provides additional on-chip 1 Kbytes auxiliary RAM called XRAM to enlarge the RAM space. It occupies the address space from 00H through FFH. The 1 Kbytes of XRAM are indirectly accessed by move external instruction MOVX @DPTR or MOVX @Ri. (See the demo code below.) Note that the stack pointer cannot be located in any part of XRAM.
  • Page 31 MS51 Name Description SFRPAGE SFR page select 0 = Instructions access SFR page 0. 1 = Instructions access SFR page 1. Switch SFR page demo code: TA,#0AAH ;switch to SFR page 1 TA,#55H SFRS,#01H TA,#0AAH ;switch to SFR page 0 TA,#55H SFRS,#00H Dec.
  • Page 32 MS51 6.1.6.2 Timed Access Protection (TA) The MS51 has several features such as WDT and Brown-out detection that are crucial to proper operation of the system. If leaving these control registers unprotected, errant code may write undetermined value into them and results in incorrect operation and loss of control. To prevent this risk, the MS51 has a protection scheme, which limits the write access to critical SFR.
  • Page 33 MS51 TA – Timed Access TA[7:0] Address: C7H, all pages Reset value: 0000 0000b Name Description TA[7:0] Timed access The timed access register controls the access to protected SFR. To access protected bits, user should first write AAH to the TA and immediately followed by a write of 55H to TA. After these two steps, a writing permission window is opened for 4 clock cycles during this period that user may write to protected SFR.

  • Page 34: Table 6.1-1 Special Function Register Memory Map

    MS51 BODCON0,#data ;4 clock cycles In the first example, the writing to the protected bits is done before the 3-clock-cycle window closes. In example 2, however, the writing to BODCON0 does not complete during the window opening, there will be no change of the value of BODCON0. In example 3, the WDCON is successful written but the BODCON0 write is out of the 3-clock-cycle window.
  • Page 35 MS51 6.1.6.4 SFR Bit Description And Reset Value Addr Reset Symbol Definition Page Value[2] Extensive interrupt EIPH1 PWKTH PT3H PSH_1 0000 0000b priority high 1 Extensive interrupt EIP1 PWKT PS_1 0000 0000b priority 1 PWM mask data PMD5 PMD4 PMD3 PMD2 PMD1 PMD0...
  • Page 36 MS51 PWM negative PNP5 PNP4 PNP3 PNP2 PNP1 PNP0 0000 0000b polarity PWM0 channel 3 PWM3H PWM3[15:8] 0000 0000b duty high byte PWM0 channel 2 PWM2H PWM2[15:8] 0000 0000b duty high byte PWM0 channel 1 PWM1H PWM1[15:8] 0000 0000b duty high byte PWM0 channel 0 PWM0H PWM0[15:8]...
  • Page 37 MS51 P0SR P0 slew rate P0SR.7 P0SR.6 P0SR.5 P0SR.4 P0SR.3 P0SR.2 P0SR.1 P0SR.0 0000 0000b P0M2 P0 mode select 2 P0M2.7 P0M2.6 P0M2.5 P0M2.4 P0M2.3 P0M2.2 P0M2.1 P0M2.0 0000 0000b P0 Schmitt trigger P0S.7 P0S.6 P0S.5 P0S.4 P0S.3 P0S.2 P0S.1 P0S.0 0000 0000b input...

  • Page 38: Table 6.1-2 Sfr Definitions And Reset Values

    MS51 Output latch, 1111 1111b Port 1 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 Input XXXX XXXXb Self Wake-up Timer WKCON WKTF WKTR WKPS[2:0] 0000 0000b control CKCON Clock control PWMCKS CLOEN 0000 0000b Timer 1 high byte TH1[7:0] 0000 0000b Timer 0 high byte TH0[7:0]...
  • Page 39 MS51 Pn – Port n (Bit-addressable) Regiser Address Reset Value 80H, all pages, bit addressable 1111_1111 b 90H, all pages, bit addressable 1111_1111 b A0H, all pages, bit addressable 0000_0001 b B0H, all pages, bit addressable 0000_0001 b Pn.7 Pn.6 Pn.5 Pn.4 Pn.3...
  • Page 40 MS51 P0 / P1 Name Description P0[7:0] Port 0 Port 0 is an maximum 8-bit general purpose I/O port. Name Description P2.0 Port 2 bit 0 P2.0 is an input-only pin when RPD (CONFIG0.2) is programmed as 0. When leaving RPD un- programmed, P2.0 is always read as 0.
  • Page 41 MS51 SP – Stack Pointer Regiser Address Reset Value 81H, all pages 0000_0111b SP[7:0] Name Description SP[7:0] Stack pointer The Stack Pointer stores the scratch-pad RAM address where the stack begins. It is incremented before data is stored during PUSH or CALL instructions. Note that the default value of SP is 07H. This causes the stack to begin at location 08H.
  • Page 42 MS51 DPL – Data Pointer Low Byte Regiser Address Reset Value 82H, all pages 0000_0000b DPL[7:0] Name Description Data pointer low byte DPL[7:0] This is the low byte of 16-bit data pointer. DPL combined with DPH serve as a 16-bit data pointer DPTR to access indirect addressed RAM or Program Memory.
  • Page 43 MS51 DPH – Data Pointer High Byte Regiser Address Reset Value 83H, all pages 0000_0000b DPH[7:0] Name Description Data pointer high byte DPH[7:0] This is the high byte of 16-bit data pointer. DPH combined with DPL serve as a 16-bit data pointer DPTR to access indirect addressed RAM or Program Memory.
  • Page 44 MS51 RCTRIM0 – High Speed Internal Oscillator 16 MHz Trim 0 Regiser Address Reset Value RCTRIM0 84H, all pages, TA protected Default 16MHz HIRC value HIRCTRIM[8:1] Dec. 17, 2019 Page 44 of 316 Rev 1.01...
  • Page 45 MS51 RCTRIM1 – High Speed Internal Oscillator 16 MHz Trim 1 Regiser Address Reset Value RCTRIM1 85H, all pages, TA protected default 16MHz HIRC value HIRC24 HIRCTRIM.0 Dec. 17, 2019 Page 45 of 316 Rev 1.01...
  • Page 46 MS51 RWK – Self Wake-up Timer Reload Byte Regiser Address Reset Value 86H, all pages 0000_0000b RWK[7:0] Name Description RWK[7:0] WKT reload byte It holds the 8-bit reload value of WKT. Note that RWK should not be FFH if the pre-scale is 1/1 for implement limitation.
  • Page 47 MS51 PCON – Power Control Regiser Address Reset Value POR, 0001_0000b PCON 87H, all pages Others,000U_0000b SMOD SMOD0 Name Description Serial port 0 double baud rate enable SMOD Setting this bit doubles the serial port baud rate when UART0 is in Mode 2 or when Timer 1 overflow is used as the baud rate source of UART0 Mode 1 or 3.
  • Page 48 MS51 TCON – Timer 0 and 1 Control Regiser Address Reset Value TCON 88H, all pages, Bit-addressable 0000_0000b R (level) R (level) R/W (edge) R/W (edge) Name Description Timer 1 overflow flag This bit is set when Timer 1 overflows. It is automatically cleared by hardware when the program executes the Timer 1 interrupt service routine.
  • Page 49 MS51 TMOD – Timer 0 and 1 Mode Regiser Address Reset Value RCTRIM1 89H, all pages 0000_0000b C/T ̅ C/T ̅ GATE GATE Name Description Timer 1 gate control GATE ̅̅̅̅̅̅̅ logic level. 0 = Timer 1 will clock when TR1 is 1 regardless of INT1 ̅̅̅̅̅̅̅...
  • Page 50 MS51 TL0 – Timer 0 Low Byte Regiser Address Reset Value 8AH, all pages 0000_0000b TL0[7:0] Name Description TL0[7:0] Timer 0 low byte The TL0 register is the low byte of the 16-bit counting register of Timer 0. Dec. 17, 2019 Page 50 of 316 Rev 1.01...
  • Page 51 MS51 TL1 – Timer 1 Low Byte Regiser Address Reset Value 8BH, all pages 0000_0000b TL1[7:0] Name Description Timer 1 low byte TL1[7:0] The TL1 register is the low byte of the 16-bit counting register of Timer 1. Dec. 17, 2019 Page 51 of 316 Rev 1.01...
  • Page 52 MS51 TH0 – Timer 0 High Byte Regiser Address Reset Value 8CH, all pages 0000_0000b TH0[7:0] Name Description Timer 0 high byte TH0[7:0] The TH0 register is the high byte of the 16-bit counting register of Timer 0. Dec. 17, 2019 Page 52 of 316 Rev 1.01...
  • Page 53 MS51 TH1 – Timer 1 High Byte Regiser Address Reset Value 8DH, all pages 0000_0000b TH1[7:0] Name Description Timer 1 high byte TH1[7:0] The TH1 register is the high byte of the 16-bit counting register of Timer 1. Dec. 17, 2019 Page 53 of 316 Rev 1.01...
  • Page 54 MS51 CKCON – Clock Control Regiser Address Reset Value CKCON 8EH, all pages 0000_0000b PWMCKS CLOEN Name Description PWM clock source select PWMCKS 0 = The clock source of PWM is the system clock F 1 = The clock source of PWM is the overflow of Timer 1. Timer 1 clock mode select 0 = The clock source of Timer 1 is the system clock divided by 12.
  • Page 55 MS51 WKCON – Self Wake-up Timer Control Regiser Address Reset Value WKCON 8FH, all pages 0000_0000b WKTF WKTR WKPS[2:0] Name Description WKT overflow flag WKTF This bit is set when WKT overflows. If the WKT interrupt and the global interrupt are enabled, setting this bit will make CPU execute WKT interrupt service routine.
  • Page 56 MS51 SFRS – SFR Page Selection Regiser Address Reset Value SFRS 91H, all pages，TA protected 0000_0000b SFRPAGE Name Description SFRPAGE SFR page select 0 = Instructions access SFR page 0. 1 = Instructions access SFR page 1. Dec. 17, 2019 Page 56 of 316 Rev 1.01...
  • Page 57 MS51 CAPCON0 – Input Capture Control 0 Regiser Address Reset Value CAPCON0 92H, all pages 0000_0000b CAPEN2 CAPEN1 CAPEN0 CAPF2 CAPF1 CAPF0 Name Description Input capture 2 enable CAPEN2 0 = Input capture channel 2 Disabled. 1 = Input capture channel 2 Enabled. Input capture 1 enable CAPEN1 0 = Input capture channel 1 Disabled.
  • Page 58 MS51 CAPCON1 – Input Capture Control 1 Regiser Address Reset Value CAPCON1 93H, all pages 0000_0000b CAP2LS[1:0] CAP1LS[1:0] CAP0LS[1:0] Name Description Input capture 2 level select CAP2LS[1:0] 00 = Falling edge. 01 = Rising edge. 10 = Either Rising or falling edge. 11 = Reserved.
  • Page 59 MS51 CAPCON2 – Input Capture Control 2 Regiser Address Reset Value CAPCON2 94H, all pages 0000_0000b ENF2 ENF1 ENF0 Name Description Enable noise filer on input capture 2 ENF2 0 = Noise filter on input capture channel 2 Disabled. 1 = Noise filter on input capture channel 2 Enabled. Enable noise filer on input capture 1 ENF1 0 = Noise filter on input capture channel 1 Disabled.
  • Page 60 MS51 CKDIV – Clock Divider Regiser Address Reset Value CKDIV 95H, all pages 0000_0000b CKDIV[7:0] Name Description CKDIV[7:0] Clock divider The system clock frequency F follows the equation below according to CKDIV value. , while CKDIV = 00H, and × CKDIV , while CKDIV = 01H to FFH.
  • Page 61 MS51 CKSWT – Clock Switch (TA protected) Regiser Address Reset Value CKSWT 96H, all pages, TA protected 0011_0000b HIRCST LIRCST ECLKST OSC[1:0] Name Description Reserved HIRCST High-speed internal oscillator 16 MHz status 0 = High-speed internal oscillator is not stable or disabled. 1 = High-speed internal oscillator is enabled and stable.
  • Page 62 MS51 CKEN – Clock Enable Regiser Address Reset Value CKEN 97H, all pages, TA protected 0011_0000b EXTEN[1:0] HIRCEN CKSWTF Name Description External clock source enable EXTEN[1:0] 11 = External clock input via X Enabled. Others = external clock input is disable. P30 work as general purpose I/O. High-speed internal oscillator 16 MHz enable HIRCEN 0 = The high-speed internal oscillator Disabled.
  • Page 63 MS51 SCON – Serial Port Control Regiser Address Reset Value SCON 98H, all pages, Bit addressable 0000_0000b SM0/FE Name Description Serial port mode select SM0/FE SMOD0 (PCON.6) = 0: See Table 6.8-1 Serial Port UART0 Mode / baudrate Description for details. SMOD0 (PCON.6) = 1: SM0/FE bit is used as frame error (FE) status flag.
  • Page 64 MS51 SBUF – Serial Port 0 Data Buffer Regiser Address Reset Value SBUF 99H, all pages 0000_0000b SBUF[7:0] Name Description Serial port 0 data buffer SBUF[7:0] This byte actually consists two separate registers. One is the receiving resister, and the other is the transmitting buffer.
  • Page 65 MS51 SBUF_1 – Serial Port 1 Data Buffer Regiser Address Reset Value SBUF_1 9AH, all pages 0000_0000b SBUF _ 1[7:0] Name Description Serial port 1 data buffer SBUF _ 1[7:0] This byte actually consists two separate registers. One is the receiving resister, and the other is the transmitting buffer.
  • Page 66 MS51 EIE – Extensive Interrupt Enable Regiser Address Reset Value 9BH, all pages 0000_0000b ESPI EWDT EPWM ECAP EI2C Name Description Enable Timer 2 interrupt 0 = Timer 2 interrupt Disabled. 1 = Interrupt generated by TF2 (T2CON.7) Enabled. Enable SPI interrupt ESPI 0 = SPI interrupt Disabled.
  • Page 67 MS51 EIE1 – Extensive Interrupt Enable 1 Regiser Address Reset Value EIE1 9CH, all pages 0000_0000b EWKT ES _ 1 Name Description Enable WKT interrupt EWKT 0 = WKT interrupt Disabled. 1 = Interrupt generated by WKTF (WKCON.4) Enabled. Enable Timer 3 interrupt 0 = Timer 3 interrupt Disabled.
  • Page 68 MS51 RSR – Reset Flag Register Regiser Address Reset Value POR, 0001_0000b BOD, 000U_0100 9DH, all pages Software, 000U_0U01 nReset pin, 0U0U_ Others 000U_0U0U HardF RSTPINF BORF WDTRF SWRF (mirrored from (mirrored from (mirrored from (mirrored from (mirrored from (mirrored from AUXR1.5) PCON.4) AUXR1.6)
  • Page 69 MS51 CHPCON – Chip Control Regiser Address Reset Value Software: 0000_00U0b CHPCON 9FH, all pages,TA protected Others 0000_00C0b SWRST IAPFF IAPEN Name Description IAP fault fla IAPFF The hardware will set this bit after IAPGO (ISPTRG.0) is set if any of the following condition is met: (1) The accessing address is oversize.
  • Page 70 MS51 AUXR1 – Auxiliary Register 1 Regiser Address Reset Value POR 0000_0000b, Software 1U00_0000b AUXR1 A2H, all pages nRESET pin U100_0000b Others UUU0_0000b SWRF RSTPINF HardF SLOW UART0PX Name Description Software reset flag SWRF When the MCU is reset via software reset, this bit will be set via hardware. It is recommended that the flag be cleared via software.
  • Page 71 MS51 BODCON0 – Brown-out Detection Control 0 Regiser Address Reset Value POR,CCCC_XC0Xb BODCON0 A3H, all pages,TA protected BOD, UUUU_XU1Xb Others,UUUU_XUUXb BODEN BOV[1:0] BORST BORF Name Description Brown-out detection enable BODEN 0 = Brown-out detection circuit off. 1 = Brown-out detection circuit on. Note that BOD output is not available until 2~3 LIRC clocks after enabling.
  • Page 72 MS51 IAPTRG – IAP Trigger Regiser Address Reset Value IAPTRG A4H, all pages,TA protected 0000_0000b IAPGO Name Description IAPGO IAP go IAP begins by setting this bit as logic 1. After this instruction, the CPU holds the Program Counter (PC) and the IAP hardware automation takes over to control the progress. After IAP action completed, the Program Counter continues to run the following instruction.
  • Page 73 MS51 IAPUEN – IAP Updating Enable Regiser Address Reset Value IAPUEN A5H, all pages,TA protected 0000_0000b CFUEN LDUEN APUEN Name Description CONFIG bytes updated enable CFUEN 0 = Inhibit erasing or programming CONFIG bytes by IAP. 1 = Allow erasing or programming CONFIG bytes by IAP. LDROM updated enable LDUEN 0 = Inhibit erasing or programming LDROM by IAP.
  • Page 74 MS51 IAPAL – IAP Address Low Byte Regiser Address Reset Value IAPAL A6H, all pages 0000_0000b IAPA[7:0] Name Description IAPA[7:0] IAP address low byte IAPAL contains address IAPA[7:0] for IAP operations. Dec. 17, 2019 Page 74 of 316 Rev 1.01...
  • Page 75 MS51 IAPAH – IAP Address High Byte Regiser Address Reset Value IAPAH A7H, all pages 0000_0000b IAPA[15:8] Name Description IAPA[15:8] IAP address high byte IAPAH contains address IAPA[15:8] for IAP operations. Dec. 17, 2019 Page 75 of 316 Rev 1.01...
  • Page 76 MS51 IE – Interrupt Enable (Bit-addressable) Regiser Address Reset Value A8H, all pages,Bit addressable 0000_0000b EADC EBOD Name Description Enable all interrupt This bit globally enables/disables all interrupts that are individually enabled. 0 = All interrupt sources Disabled. 1 = Each interrupt Enabled depending on its individual mask setting. Individual interrupts will occur if enabled.
  • Page 77 MS51 SADDR – Slave 0 Address Regiser Address Reset Value SADDR A9H, all pages 0000_0000b SADDR[7:0] Name Description SADDR[7:0] Slave 0 address This byte specifies the microcontroller’s own slave address for UATR0 multi-processor communication. WDCON – Watchdog Timer Control Regiser Address Reset Value POR 0000_0111b...
  • Page 78 MS51 Name Description WDT clock pre-scalar select WDPS[2:0] These bits determine the pre-scale of WDT clock from 1/1 through 1/256. Note: 1. WDTRF will be cleared after power-on reset, be set after WDT reset, and remains unchanged after any other resets. 2.
  • Page 79 MS51 BODCON1 – Brown-out Detection Control 1 Regiser Address Reset Value POR 0000 0001b BODCON1 ABH, all pages, TA protected Others 0000 0UUUb LPBOD[1:0] BODFLT Name Description Reserved LPBOD[1:0] Low power BOD enable 00 = BOD normal mode. BOD circuit is always enabled. 01 = BOD low power mode 1 by turning on BOD circuit every 1.6 ms periodically.
  • Page 80 MS51 IAPFD – IAP Flash Data Regiser Address Reset Value IAPFD AEH, all pages 0000_0000b IAPFD[7:0] Name Description IAP flash data IAPFD[7:0] This byte contains flash data, which is read from or is going to be written to the Flash Memory. User should write data into IAPFD for program mode before triggering IAP processing and read data from IAPFD for read/verify mode after IAP processing is finished.
  • Page 81 MS51 IAPCN – IAP Control Regiser Address Reset Value IAPCN AFH, all pages 0011_0000b IAPB[1:0] FOEN FCEN FCTRL[3:0] Name Description IAPB[1:0] IAP control This byte is used for IAP command. For details, see Table 6.3-1 IAP Modes and Command Codes. FOEN FCEN FCTRL[3:0]...
  • Page 82 MS51 PnM1 – Port n Mode Select 1 Regiser Address Reset Value P0M1 B1H, Page 0 1111_1111 b P1M1 B3H, Page 0 1111_1111 b P3M1 ACH, Page 1 1111_1111 b PnM1.7 PnM1.6 PnM1.5 PnM1.4 PnM1.3 PnM1.2 PnM1.1 PnM1.0 Name Description P0M1[7:0] Port n mode select 1 NOTE: PxM1 and PxM2 are used in combination to determine the I/O mode of each pin of Port.
  • Page 83 MS51 PnS – Port n Schmitt Triggered Input Regiser Address Reset Value 99H, Page 1 0000_0000 b 9BH, Page1 0000_0000 b ACH, Page1 0000_0000 b P0S.7 P0S.6 P0S.5 P0S.4 P0S.3 P0S.2 P0S.1 P0S.0 Name Description P0S.n P0.n Schmitt triggered input 0 = TTL level input of P0.n.
  • Page 84 MS51 PnSR – Port n Slew Rate Regiser Address Reset Value P0SR B2H, Page 1 0000_0000 b P1SR B4H, Page 1 0000_0000 b P3SR ADH, Page 1 0000_0000 b P0SR.7 P0SR.6 P0SR.5 P0SR.4 P0SR.3 P0SR.2 P0SR.1 P0SR.0 Name Description P0.n slew rate P0SR.n 0 = P0.n normal output slew rate.
  • Page 85 MS51 P2S – P20 Setting and Timer01 Output Enable Regiser Address Reset Value B5H, all pages 0000_0000 b P20UP T1OE T0OE P2S.0 Name Description P2.0 pull-up enable P20UP 0 = P2.0 pull-up Disabled. 1 = P2.0 pull-up Enabled. This bit is valid only when RPD (CONFIG0.2) is programmed as 0. When selecting as a ̅̅̅̅̅̅̅̅̅̅̅ pin, the pull-up is always enabled.
  • Page 86 MS51 IPH – Interrupt Priority High Regiser Address Reset Value B7H, Page 0 0000_0000 b PADCH PBODH PT1H PX1H PT0H PX0H Name Description PADC ADC interrupt priority high bit PBOD Brown-out detection interrupt priority high bit Serial port 0 interrupt priority high bit PT1H Timer 1 interrupt priority high bit PX1H...
  • Page 87 MS51 PWMINTC – PWM Interrupt Control Regiser Address Reset Value PWMINTC B7H, Page 1 0000_0000 b INTTYP1 INTTYP0 INTSEL2 INTSEL1 INTSEL0 Name Description PWM interrupt type select INTTYP[1:0] These bit select PWM interrupt type. 00 = Falling edge on PWM0 channel 0/1/2/3/4/5 pin. 01 = Rising edge on PWM0 channel 0/1/2/3/4/5 pin.
  • Page 88 MS51 IP – Interrupt Priority Regiser Address Reset Value B8H, all pages, Bit addressable 0000_0000 b PADC PBOD Name Description PADC ADC interrupt priority low bit PBOD Brown-out detection interrupt priority low bit Serial port 0 interrupt priority low bit Timer 1 interrupt priority low bit External interrupt 1 priority low bit Timer 0 interrupt priority low bit...
  • Page 89 MS51 SADEN – Slave 0 Address Mask Regiser Address Reset Value SADEN B9H, all pages 0000_0000 b SADEN[7:0] Name Description SADEN[7:0] Slave 0 address mask This byte is a mask byte of UART0 that contains “don’t-care” bits (defined by zeros) to form the device’s “Given”...
  • Page 90 MS51 SADEN_1 – Slave 1 Address Mask Regiser Address Reset Value SADEN_1 BAH, all pages 0000_0000 b SADEN _ 1[7:0] Name Description Slave 1 address mask SADEN _ 1[7:0] This byte is a mask byte of UART1 that contains “don’t-care” bits (defined by zeros) to form the device’s “Given”...
  • Page 91 MS51 SADDR_1 – Slave 1 Address Regiser Address Reset Value SADDR_1 BBH, all pages 0000_0000 b SADDR _ 1[7:0] Name Description SADDR _ 1[7:0] Slave 1 address This byte specifies the microcontroller’s own slave address for UART1 multi-processor communication. Dec. 17, 2019 Page 91 of 316 Rev 1.01...
  • Page 92 MS51 I2DAT – I C Data Regiser Address Reset Value I2DAT BCH, all pages 0000_0000 b I2DAT[7:0] Name Description C data I2DAT[7:0] I2DAT contains a byte of the I C data to be transmitted or a byte, which has just received. Data in I2DAT remains as long as SI is logic 1.
  • Page 93 MS51 I2STAT – I C Status Regiser Address Reset Value I2STAT BDH, all pages 1111_1000 b I2STAT[7:3] Name Description I2STAT[7:3] C status code The MSB five bits of I2STAT contains the status code. There are 27 possible status codes. When I2STAT is F8H, no relevant state information is available and SI flag keeps 0. All other 26 status codes correspond to the I C states.
  • Page 94 MS51 I2CLK – I C Clock Regiser Address Reset Value I2CLK BEH, all pages 0000_1001 b I2CLK[7:0] Name Description C clock setting I2CLK[7:0] In master mode: This register determines the clock rate of I C bus when the device is in a master mode. The clock rate follows the equation, ×...
  • Page 95 MS51 I2TOC – I C Time-out Counter Regiser Address Reset Value I2TOC BFH, all pages 0000_1001 b I2TOCEN I2TOF Name Description C time-out counter enable I2TOCEN 0 = I C time-out counter Disabled. 1 = I C time-out counter Enabled. C time-out counter clock divider 0 = The clock of I C time-out counter is F...
  • Page 96 MS51 I2CON – I C Control Regiser Address Reset Value I2CON C0H, all pages, Bit addressable 0000_0000 b I2CEN I2CPX Name Description C bus enable I2CEN 0 = I C bus Disabled. 1 = I C bus Enabled. Before enabling the I C, I2C0_SCL and I2C0_SDA port latches should be set to logic 1.
  • Page 97 MS51 Name Description I2C pins select I2CPX 0 = Assign I2C0_SCL to P1.3 and I2C0_SDA to P1.4. 1 = Assign I2C0_SCL to P0.2 and I2C0_SDA to P1.6. Note that I2C pins will exchange immediately once setting or clearing this bit. Dec.
  • Page 98 MS51 I2ADDR – I C Own Slave Address Regiser Address Reset Value I2ADDR C1H, all pages 0000_0000b I2ADDR[7:1] Name Description C device’s own slave address I2ADDR[7:1] In master mode: These bits have no effect. In slave mode: These 7 bits define the slave address of this I C device by user.
  • Page 99 MS51 ADCRL – ADC Result Low Byte Regiser Address Reset Value ADCRL C2H, page 0 0000_0000b ADCR[3:0] Name Description ADCR[3:0] ADC result low byte The least significant 4 bits of the ADC result stored in this register. Dec. 17, 2019 Page 99 of 316 Rev 1.01...
  • Page 100 MS51 ADCRH – ADC Result High Byte Regiser Address Reset Value ADCRH C3H, page 0 0000_0000b ADCR[11:4] Name Description ADCR[11:4] ADC result high byte The most significant 8 bits of the ADC result stored in this register. Dec. 17, 2019 Page 100 of 316 Rev 1.01...
  • Page 101 MS51 T3CON – Timer 3 Control Regiser Address Reset Value T3CON C4H, Page 0 0000_0000b SMOD _ 1 SMOD0 _ 1 BRCK T3PS[2:0] Name Description Serial port 1 double baud rate enable SMOD _ 1 Setting this bit doubles the serial port baud rate when UART1 is in Mode 2. See Table 6.8-2 Serial Port UART1 Mode / baudrate Description for details.
  • Page 102 MS51 RL3 – Timer 3 Reload Low Byte Regiser Address Reset Value C5H, Page 0 0000_0000b RL3[7:0] Name Description RL3[7:0] Timer 3 reload low byte It holds the low byte of the reload value of Timer 3. Dec. 17, 2019 Page 102 of 316 Rev 1.01...
  • Page 103 MS51 RH3 – Timer 3 Reload High Byte Regiser Address Reset Value C6H, Page 0 0000_0000b RH3[7:0] Name Description RH3[7:0] Timer 3 reload high byte It holds the high byte of the reload value of Time 3. Dec. 17, 2019 Page 103 of 316 Rev 1.01...
  • Page 104 MS51 PIOCON1 – PWM or I/O Select Regiser Address Reset Value PIOCON1 C6H, Page 1 0000_0000b PIO15 PIO13 PIO12 PIO11 Name Description P1.5/PWM0_CH5 pin function select PIO15 0 = P1.5/PWM0_CH5 pin functions as P1.5. 1 = P1.5/PWM0_CH5 pin functions as PWM0 channel 5 output. P0.4/PWM3 pin function select PIO13 0 = P0.4/PWM0_CH3 pin functions as P0.4.
  • Page 105 MS51 TA – Timed Access Regiser Address Reset Value C7H, all pages 0000_0000b TA[7:0] Name Description Timed access TA[7:0] The timed access register controls the access to protected SFRs. To access protected bits, user should first write AAH to the TA and immediately followed by a write of 55H to TA. After these two steps, a writing permission window is opened for 4 clock cycles during this period that user may write to protected SFRs.
  • Page 106 MS51 T2CON – Timer 2 Control Regiser Address Reset Value T2CON C8H, all pages 0000_0000b ̅̅̅̅̅̅ CM/RL2 Name Description Timer 2 overflow flag This bit is set when Timer 2 overflows or a compare match occurs. If the Timer 2 interrupt and the global interrupt are enable, setting this bit will make CPU execute Timer 2 interrupt service routine.
  • Page 107 MS51 T2MOD – Timer 2 Mode Regiser Address Reset Value T2MOD C9H, all pages 0000_0000b LDEN T2DIV[2:0] CAPCR CMPCR LDTS[1:0] Name Description Enable auto-reload LDEN 0 = Reloading RCMP2H and RCMP2L to TH2 and TL2 Disabled. 1 = Reloading RCMP2H and RCMP2L to TH2 and TL2 Enabled. Timer 2 clock divider T2DIV[2:0] 000 = Timer 2 clock divider is 1/1.
  • Page 108 MS51 RCMP2L – Timer 2 Reload/Compare Low Byte Regiser Address Reset Value RCMP2L CAH, all pages 0000_0000b RCMP2L[7:0] Name Description Timer 2 reload/compare low byte RCMP2L[7:0] This register stores the low byte of compare value when Timer 2 is configured in compare mode.
  • Page 109 MS51 RCMP2H – Timer 2 Reload/Compare High Byte Regiser Address Reset Value RCMP2H CBH, all pages 0000_0000b RCMP2H[7:0] Name Description Timer 2 reload/compare high byte RCMP2H[7:0] This register stores the high byte of compare value when Timer 2 is configured in compare mode.
  • Page 110 MS51 TL2 – Timer 2 Low Byte Regiser Address Reset Value CCH, all pages 0000_0000b TL2[7:0] Name Description Timer 2 low byte TL2[7:0] The TL2 register is the low byte of the 16-bit counting register of Timer 2. Dec. 17, 2019 Page 110 of 316 Rev 1.01...
  • Page 111 MS51 TH2 – Timer 2 High Byte Regiser Address Reset Value CDH, Page 0 0000_0000b TH2[7:0] Name Description TH2[7:0] Timer 2 high byte The TH2 register is the high byte of the 16-bit counting register of Timer 2. Dec. 17, 2019 Page 111 of 316 Rev 1.01...
  • Page 112 MS51 ADCMPL – ADC Compare Low Byte Regiser Address Reset Value ADCMPL CEH, page 0 0000_0000b ADCMP[3:0] Name Description ADCMP[3:0] ADC compare low byte The least significant 4 bits of the ADC compare value stores in this register. Dec. 17, 2019 Page 112 of 316 Rev 1.01...
  • Page 113 MS51 ADCMPH – ADC Compare High Byte Regiser Address Reset Value ADCMPH CFH, page 0 0000_0000b ADCMP[11:4] Name Description ADCMP[11:4] ADC compare high byte The most significant 8 bits of the ADC compare value stores in this register. Dec. 17, 2019 Page 113 of 316 Rev 1.01...
  • Page 114 MS51 PSW – Program Status Word Regiser Address Reset Value D0H, all pages, Bit addressable 0000_0000b Name Description Carry flag For a adding or subtracting operation, CY will be set when the previous operation resulted in a carry-out from or a borrow-in to the Most Significant bit, otherwise cleared. If the previous operation is MUL or DIV, CY is always 0.
  • Page 115 MS51 PWMPH – PWM Period High Byte Regiser Address Reset Value PWMPH D1H, all pages 0000_0000b PWMP[15:8] Name Description PWMP[15:8] PWM period high byte This byte with PWMPL controls the period of the PWM generator signal. Dec. 17, 2019 Page 115 of 316 Rev 1.01...
  • Page 116 MS51 PWM0H – PWM0 Duty High Byte Regiser Address Reset Value PWM0H D1H, all pages 0000 _0000 b PWM1H D3H, all pages 0000 _0000 b PWM2H D4H, all pages 0000 _0000 b PWM3H D5H, all pages 0000 _0000 b PWM4H C4H, page 1 0000 _0000 b PWM5H...
  • Page 117 MS51 PNP – PWM Negative Polarity Regiser Address Reset Value D6H, all pages 0000_0000b PNP5 PNP4 PNP3 PNP2 PNP1 PNP0 Name Description PWMn negative polarity output enable PNPn 0 = PWMn signal outputs directly on PWMn pin. 1 = PWMn signal outputs inversely on PWMn pin. Dec.
  • Page 118 MS51 FBD – PWM Fault Brake Data Regiser Address Reset Value D7H, all pages 0000_0000b FBINLS FBD5 FBD4 FBD3 FBD2 FBD1 FBD0 Name Description Fault Brake flag This flag is set when FBINEN is set as 1 and FB pin detects an edge, which matches FBINLS (FBD.6) selection.
  • Page 119 MS51 PWMCON0 – PWM Control 0 Regiser Address Reset Value PWMCON0 D7H, all pages, Bit addressable 0000_0000b PWMRUN LOAD PWMF CLRPWM Name Description PWM run enable PWMRUN 0 = PWM stays in idle. 1 = PWM starts running. PWM new period and duty load LOAD This bit is used to load period and duty control registers in their buffer if new period or duty value needs to be updated.
  • Page 120 MS51 PWMPL – PWM Period Low Byte Regiser Address Reset Value PWMPL D9H, all pages 0000_0000b PWMP[7:0] Name Description PWMP[7:0] PWM period low byte This byte with PWMPH controls the period of the PWM generator signal. Dec. 17, 2019 Page 120 of 316 Rev 1.01...
  • Page 121 MS51 PWMnL – PWM0 Duty Low Byte Regiser Address Reset Value PWM0L DAH, all pages 0000 _0000 b PWM1L DBH, all pages 0000 _0000 b PWM2L DCH, all pages 0000 _0000 b PWM3L DDH, all pages 0000 _0000 b PWM4L CCH, Page 1 0000 _0000 b PWM5L...
  • Page 122 MS51 PIOCON0 – PWM or I/O Select Regiser Address Reset Value PIOCON0 DEH, all pages 0000_0000b PIO05 PIO04 PIO03 PIO02 PIO01 PIO00 Name Description P0.3/PWM0 channel 5 pin function select PIO05 0 = P0.3/PWM0_CH5 pin functions as P0.3. 1 = P0.3/PWM0_CH5 pin functions as PWM0_CH5 output. P0.1/PWM0 channel 4 pin function select PIO04 0 = P0.1/PWM0_CH4 pin functions as P0.1.
  • Page 123 MS51 PWMCON1 – PWM Control 1 Regiser Address Reset Value PIOCON1 DFH, all pages 0000_0000b PWMMOD[1:0] PWMTYP FBINEN PWMDIV[2:0] Name Description Group mode enable This bit enables the group mode. If enabled, the duty of first three pairs of PWM are decided by PWM01H and PWM01L rather than their original duty control registers.
  • Page 124 MS51 A or ACC – Accumulator Regiser Address Reset Value E0H, all pages, Bit addressable 0000_0000b ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 Name Description Accumulator ACC[7:0] The A or ACC register is the standard 80C51 accumulator for arithmetic operation. Dec.
  • Page 125 MS51 ADCCON1 – ADC Control 1 Regiser Address Reset Value ADCCON1 E1H, page 0 0000_0000b STADCPX ADCDIV[1:0] ETGTYP[1:0] ADCEX ADCEN Name Description External start ADC trigger pin select STADCPX 0 = Assign STADC to P0.4. 1 = Assign STADC to P1.3. Note that STADC will exchange immediately once setting or clearing this bit.
  • Page 126 MS51 ADCCON2 – ADC Control 2 Regiser Address Reset Value ADCCON2 E2H, page0 0000_0000b ADFBEN ADCMPOP ADCMPEN ADCMPO ADCAQT[2:0] ADCDLY.8 Name Description ADC compare result asserting Fault Brake enable ADFBEN 0 = ADC asserting Fault Brake Disabled. 1 = ADC asserting Fault Brake Enabled. Fault Brake is asserted once its compare result ADCMPO is 1.
  • Page 127 MS51 ADCDLY – ADC Trigger Delay Counter Regiser Address Reset Value ADCDLY E3H, all pages 0000_0000b ADCDLY[7:0] Name Description ADC external trigger delay counter low byte ADCDLY[7:0] This 8-bit field combined with ADCCON2.0 forms a 9-bit counter. This counter inserts a delay after detecting the external trigger.
  • Page 128 MS51 CnL – Capture n Low Byte Regiser Address Reset Value E4H, all pages 0000_0000b E6H, all pages 0000_0000b EDH, all pages 0000_0000b C0L[7:0] Name Description CnL[7:0] Input capture n result low byte The C0L register is the low byte of the 16-bit result captured by input capture 0. Dec.
  • Page 129 MS51 CnH – Capture n High Byte Regiser Address Reset Value E4H, all pages 0000_0000b E7H, all pages 0000_0000b EEH, all pages 0000_0000b C0H[7:0] Name Description CnH[7:0] Input capture n result high byte The C0H register is the high byte of the 16-bit result captured by input capture 0. Dec.
  • Page 130 MS51 ADCCON0 – ADC Control 0 Regiser Address Reset Value ADCCON0 E8H, page 0 , Bit addressable 0000_0000b ADCF ADCS ETGSEL1 ETGSEL0 ADCHS3 ADCHS2 ADCHS1 ADCHS0 Name Description ADC flag ADCF This flag is set when an A/D conversion is completed. The ADC result can be read. While this flag is 1, ADC cannot start a new converting.
  • Page 131 MS51 PICON – Pin Interrupt Control Regiser Address Reset Value PICON E9H, all pages 0000_0000b PIT67 PIT45 PIT3 PIT2 PIT1 PIT0 PIPS[1:0] Name Description Pin interrupt channel 6 and 7 type select PIT67 This bit selects which type that pin interrupt channel 6 and 7 is triggered. 0 = Level triggered.
  • Page 132 MS51 PINEN – Pin Interrupt Negative Polarity Enable Regiser Address Reset Value PINEN EAH, all pages 0000_0000b PINEN7 PINEN6 PINEN5 PINEN4 PINEN3 PINEN2 PINEN1 PINEN0 Name Description Pin interrupt channel n negative polarity enable PINENn This bit enables low-level/falling edge triggering pin interrupt channel n. The level or edge triggered selection depends on each control bit PITn in PICON.
  • Page 133 MS51 PIPEN – Pin Interrupt Positive Polarity Enable Regiser Address Reset Value PIPEN EBH, all pages 0000_0000b PIPEN7 PIPEN6 PIPEN5 PIPEN4 PIPEN3 PIPEN2 PIPEN1 PIPEN0 Name Description Pin interrupt channel n positive polarity enable PIPENn This bit enables high-level/rising edge triggering pin interrupt channel n. The level or edge triggered selection depends on each control bit PITn in PICON.
  • Page 134 MS51 PIF – Pin Interrupt Flags Regiser Address Reset Value ECH, all pages 0000_0000b PIF7 PIF6 PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 R (level) R (level) R (level) R (level) R (level) R (level) R (level) R (level) R/W (edge) R/W (edge) R/W (edge) R/W (edge)
  • Page 135 MS51 EIP – Extensive Interrupt Priority Regiser Address Reset Value EFH, all pages 0000_0000b PSPI PWDT PPWM PCAP PI2C Name Description Timer 2 interrupt priority low bit PSPI SPI interrupt priority low bit Fault Brake interrupt priority low bit PWDT WDT interrupt priority low bit PPWM PWM interrupt priority low bit...
  • Page 136 MS51 B – B Register Regiser Address Reset Value F0H, all pages,bit addressable 0000_0000b Name Description B[7:0] B register The B register is the other accumulator of the standard 80C51 .It is used mainly for MUL and DIV instructions. Dec. 17, 2019 Page 136 of 316 Rev 1.01...
  • Page 137 MS51 CAPCON3 – Input Capture Control 3 Regiser Address Reset Value CAPCON3 F1H, all pages 0000_0000b CAP13 CAP12 CAP11 CAP10 CAP03 CAP02 CAP01 CAP00 Name Description Input capture channel 0 input pin select [7:4] CAP1[3:0] 0000 = P1.2/IC0 0001 = P1.1/IC1 0010 = P1.0/IC2 0011 = P0.0/IC3 0100 = P0.4/IC3...
  • Page 138 MS51 CAPCON4 – Input Capture Control 4 Regiser Address Reset Value CAPCON4 F2H, all pages 0000_0000b CAP23 CAP22 CAP21 CAP20 Name Description Input capture channel 0 input pin select [3:0] CAP2[3:0] 0000 = P1.2/IC0 0001 = P1.1/IC1 0010 = P1.0/IC2 0011 = P0.0/IC3 0100 = P0.4/IC3 0101 = P0.1/IC4...
  • Page 139 MS51 SPCR – Serial Peripheral Control Register Regiser Address Reset Value SPCR F3H, page 0 0000_0000b SSOE SPIEN LSBFE MSTR CPOL CPHA SPR1 SPR0 Name Description Slave select output enable SSOE ̅̅̅̅ pin This bit is used in combination with the DISMODF (SPSR.3) bit to determine the feature of SS as shown in ̅̅̅̅...
  • Page 140 MS51 SPCR2 – Serial Peripheral Control Register 2 Regiser Address Reset Value SPCR2 F3H, page 1 0000_0000b SPIS1 SPIS0 Name Description Reserved SPIS[1:0] SPI Interval time selection between adjacent bytes SPIS[1:0] and CPHA select eight grades of SPI interval time selection between adjacent bytes. As below table: CPHA SPIS1...
  • Page 141 MS51 SPSR – Serial Peripheral Status Register Regiser Address Reset Value SPSR F4H, all page 0000_0000b SPIF WCOL SPIOVF MODF DISMODF TXBUF Name Description SPI complete flag SPIF This bit is set to logic 1 via hardware while an SPI data transfer is complete or an receiving data has been moved into the SPI read buffer.
  • Page 142 MS51 SPDR – Serial Peripheral Data Register Regiser Address Reset Value SPDR F5H, all page 0000_0000b SPDR[7:0] Name Description Serial peripheral data SPDR[7:0] This byte is used for transmitting or receiving data on SPI bus. A write of this byte is a write to the shift register.
  • Page 143 MS51 AINDIDS – ADC Channel Digital Input Disconnect Regiser Address Reset Value AINDIDS F6H, all page 0000_0000b P11DIDS P03DIDS P04DIDS P05DIDS P06DIDS P07DIDS P30DIDS P17DIDS Name Description ADC Channel digital input disable PnDIDS 0 = ADC channel n digital input Enabled. 1 = ADC channel n digital input Disabled.
  • Page 144 MS51 EIPH – Extensive Interrupt Priority High Regiser Address Reset Value EIPH F7H, all page 0000_0000b PT2H PSPIH PFBH PWDTH PPWMH PCAPH PPIH PI2CH Name Description PT2H Timer 2 interrupt priority high bit PSPIH SPI interrupt priority high bit PFBH Fault Brake interrupt priority high bit PWDTH WDT interrupt priority high bit...
  • Page 145 MS51 SCON _ 1 – Serial Port 1 Control Regiser Address Reset Value SCON_1 F8H, all page, bit addressable 0000_0000b SM0 _ 1/FE _ 1 SM1 _ 1 SM2 _ 1 REN _ 1 TB8 _ 1 RB8 _ 1 TI _ 1 RI _ 1 Name...
  • Page 146 MS51 PDTEN – PWM Dead-time Enable Regiser Address Reset Value PDTEN F9H, all page, TA protected 0000_0000b PDTCNT.8 PDT45EN PDT23EN PDT01EN Name Description PWM dead-time counter bit 8 PDTCNT.8 See PDTCNT register. PWM0_CH4/ PWM0_CH5 pair dead-time insertion enable PDT45EN This bit is valid only when PWM4/5 is under complementary mode. 0 = No delay on GP4/GP5 pair signals.
  • Page 147 MS51 PDTCNT – PWM Dead-time Counter Regiser Address Reset Value PDTCNT FAH, all page, TA protected 0000_0000b PDTCNT[7:0] Name Description PWM dead-time counter low byte PDTCNT[7:0] This 8-bit field combined with PDTEN.4 forms a 9-bit PWM dead-time counter PDTCNT. This counter is valid only when PWM is under complementary mode and the correspond PDTEN bit for PWM pair is set.
  • Page 148 MS51 PMEN – PWM Mask Enable Regiser Address Reset Value PMEN FBH, all page 0000_0000b PMEN5 PMEN4 PMEN3 PMEN2 PMEN1 PMEN0 Name Description PMENn PWMn mask enable 0 = PWMn signal outputs from its PWM generator. 1 = PWMn signal is masked by PMDn. Dec.
  • Page 149 MS51 PMD – PWM Mask Data Regiser Address Reset Value FCH, all page 0000_0000b PMD5 PMD4 PMD3 PMD2 PMD1 PMD0 Name Description PMDn PWMn mask data The PWMn signal outputs mask data once its corresponding PMENn is set. 0 = PWMn signal is masked by 0. 1 = PWMn signal is masked by 1.
  • Page 150 MS51 PORDIS – POR disable (TA protected) Regiser Address Reset Value PORDIS FDH, all page, TA protected 0000_0000b PORDIS[7:0] Name Description PORDIS[7:0] POR disable To first writing 5AH to the PORDIS and immediately followed by a writing of A5H will disable POR.
  • Page 151 MS51 EIP1 – Extensive Interrupt Priority 1 Regiser Address Reset Value EIP1 FEH, page 0 0000_0000b PWKT PS _ 1 Name Description PWKT WKT interrupt priority low bit Timer 3 interrupt priority low bit PS _ 1 Serial port 1 interrupt priority low bit Note: EIP1 is used in combination with the EIPH1 to determine the priority of each interrupt source.
  • Page 152 MS51 EIPH1 – Extensive Interrupt Priority High 1 Regiser Address Reset Value EIPH1 FFH, page 0 0000_0000b PWKTH PT3H PSH _ 1 Name Description PWKTH WKT interrupt priority high bit PT3H Timer 3 interrupt priority high bit PSH _ 1 Serial port 1 interrupt priority high bit Note: EIPH1 is used in combination with the EIP1 to determine the priority of each interrupt source.

  • Page 153: System Manager

    MS51 System Manager 6.2.1 Clock System The MS51 has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. The MS51 provides three options of the system clock sources including internal oscillator, or external clock from pin via software.
  • Page 154 MS51 RCTRIM0 –High Speed Internal Oscillator 16 MHz Trim 0 (TA protected) HIRCTRIM[8:1] Address: 84H Reset value: 16 MHz HIRC value RCTRIM1 –High Speed Internal Oscillator 16 MHz Trim 1 (TA protected) HIRC24 HIRCTRIM.0 Address: 85H Reset value: 16 MHz HIRC value Note: since defaut RCTRIM0 and RCTRIM1 value is base on 16MHz, if base on this value then modify HIRC24(RCTIM1.4) to enable 24MHz HIRC mode, the real HIRC deviation will more than 1%.
  • Page 155 MS51 CKSWT – Clock Switch (TA protected) Regiser Address Reset Value CKSWT 96H, all pages, TA protected 0011_0000b HIRCST ECLKST OSC[1:0] Name Description Reserved HIRCST High-speed internal oscillator 16 MHz status 0 = High-speed internal oscillator is not stable or disabled. 1 = High-speed internal oscillator is enabled and stable.
  • Page 156 MS51 CKEN – Clock Enable Regiser Address Reset Value CKEN 97H, all pages, TA protected 0011_0000b EXTEN[1:0] HIRCEN CKSWTF Name Description External clock source enable EXTEN[1:0] 11 = External clock input via X Enabled. Others = external clock input is disable. P30 work as general purpose I/O. High-speed internal oscillator 16 MHz enable HIRCEN 0 = The high-speed internal oscillator Disabled.
  • Page 157 MS51 CKDIV – Clock Divider Regiser Address Reset Value CKDIV 95H, all pages 0000_0000b CKDIV[7:0] Name Description Clock divider CKDIV[7:0] The system clock frequency FSYS follows the equation below according to CKDIV value. , while CKDIV = 00H, and × CKDIV , while CKDIV = 01H to FFH.

  • Page 158: Power Management

    MS51 6.2.1.5 System Clock Output The MS51 provides a CLO pin (P1.1) that outputs the system clock. Its frequency is the same as F The output enable bit is CLOEN (CKCON.1). CLO output stops when device is put in its Power-down mode because the system clock is turned off.
  • Page 159 MS51 6.2.2.2 Power-Down Mode Power-down mode is the lowest power state that the MS51 can enter. It remain the power consumption as A ”Μa” level by stopping the system clock source. Both of CPU and peripheral functions like Timers or UART are frozen. Flash memory is put into its stop mode. All activity is completely stopped and the power consumption is reduced to the lowest possible value.

  • Page 160: Power Monitoring And Reset

    MS51 6.2.3 Power Monitoring And Reset To prevent incorrect execution during power up and power drop, The MS51 provide three power monitor functions, power-on detection and brown-out detection. The MS51 has several options to place device in reset condition. It also offers the software flags to indicate the source, which causes a reset.

  • Page 161: External Reset And Hard Fault Reset

    MS51 BODCON0 – Brown-out Detection Control 0 Regiser Address Reset Value POR,CCCC_XC0Xb BODCON0 A3H, all pages,TA protected BOD, UUUU_XU1Xb Others,UUUU_XUUXb BODEN BOV[2:0] BORST BORF Name Description BORF Brown-out reset flag When the MCU is reset by brown-out event, this bit will be set via hardware. This flag is recommended to be cleared via software.

  • Page 162: Watchdog Timer Reset

    MS51 AUXR1 – Auxiliary Register 1 Regiser Address Reset Value POR 0000_0000b, Software 1U00_0000b AUXR1 A2H, all pages nRESET pin U100_0000b Others UUU0_0000b SWRF RSTPINF HardF HardFInt Name Description RSTPINF External reset flag When the MCU is reset by the external reset, this bit will be set via hardware. It is recommended that the flag be cleared via software.

  • Page 163: Software Reset

    MS51 WDCON – Watchdog Timer Control Regiser Address Reset Value POR 0000_0111b WDCON AAH, all pages, TA protected WDT 0000_1UUUb Others 0000_UUUUb WDTR WDCLR WDTF WIDPD WDTRF WDPS[2:0] Name Description WDTRF WDT reset flag When the CPU is reset by WDT time-out event, this bit will be set via hardware. This flag is recommended to be cleared via software after reset.

  • Page 164: Boot Select

    MS51 CHPCON – Chip Control Regiser Address Reset Value Software: 0000_00U0b CHPCON 9FH, all pages,TA protected Others 0000_00C0b SWRST IAPFF IAPEN Name Description SWRST Software reset To set this bit as logic 1 will cause a software reset. It will automatically be cleared via hardware after reset is finished.

  • Page 165: Reset State

    MS51 occurs and BS is 0, MCU will reboot from address 0000H of APROM. Else, the CPU will reboot from address 0000H of LDROM. Note that BS is loaded from the inverted value of CBS bit in CONFIG0.7 after all resets except software reset. Note: After the MCU is released from reset state, the hardware will always check the BS bit instead of the CBS bit to determine from which block that the device reboots.

  • Page 166: Enabling Interrupts

    MS51 The MS51 has a four-priority-level interrupt structure with 30 interrupt sources. Each of the interrupt sources has an individual priority setting bits, interrupt vector and enable bit. In addition, the interrupts can be globally enabled or disabled. When an interrupt occurs, the CPU is expected to service the interrupt.

  • Page 167: Interrupt Priorities

    MS51 6.2.13 Interrupt Priorities There are four priority levels for all interrupts. They are level highest, high, low, and lowest; and they are represented by level 3, level 2, level 1, and level 0. The interrupt sources can be individually set to one of four priority levels by setting their own priority bits.

  • Page 168: Interrupt Service

    MS51 Vector Natural Priority Control Power-Down Interrupt Source Interrupt Flag(S) Enable Bit Address Priority Bits Wake-Up Timer 1 001BH TF1[2] PT1, PT1H Serial port 0 0023H RI + TI PS, PSH Fault Brake event 0073h FBF (FBD.7) PFB, PFBH 004Bh SPIF (SPSR.7) + ESPI PSPI, PSPIH...

  • Page 169: Interrupt Latency

    MS51 completed. RET would leave the controller still thinking that the service routine is underway, making future interrupts impossible. 6.2.15 Interrupt Latency The response time for each interrupt source depends on several factors, such as the nature of the interrupt and the instruction underway. Each interrupt flags are polled and priority decoded each system clock cycle.
  • Page 170 MS51 IE – Interrupt Enable Regiser Address Reset Value A8H, all pages,Bit addressable 0000_0000b EADC EBOD Name Description Enable all interrupt This bit globally enables/disables all interrupts that are individually enabled. 0 = All interrupt sources Disabled. 1 = Each interrupt Enabled depending on its individual mask setting. Individual interrupts will occur if enabled.
  • Page 171 MS51 EIE – Extensive Interrupt Enable Regiser Address Reset Value 9BH, all pages 0000_0000b ESPI EWDT EPWM ECAP EI2C Name Description Enable Timer 2 interrupt 0 = Timer 2 interrupt Disabled. 1 = Interrupt generated by TF2 (T2CON.7) Enabled. Enable SPI interrupt ESPI 0 = SPI interrupt Disabled.
  • Page 172 MS51 EIE1 – Extensive Interrupt Enable 1 Regiser Address Reset Value EIE1 9CH, all pages 0000_0000b EWKT ES_1 Name Description Enable WKT interrupt EWKT 0 = WKT interrupt Disabled. 1 = Interrupt generated by WKTF (WKCON.4) Enabled. Enable Timer 3 interrupt 0 = Timer 3 interrupt Disabled.
  • Page 173 MS51 IP – Interrupt Priority Regiser Address Reset Value B8H, all pages, Bit addressable 0000_0000 b PADC PBOD Name Description PADC ADC interrupt priority low bit PBOD Brown-out detection interrupt priority low bit Serial port 0 interrupt priority low bit Timer 1 interrupt priority low bit External interrupt 1 priority low bit Timer 0 interrupt priority low bit...
  • Page 174 MS51 IPH – Interrupt Priority High Regiser Address Reset Value B7H, Page 0 0000_0000 b PADCH PBODH PT1H PX1H PT0H PX0H Name Description PADC ADC interrupt priority high bit PBOD Brown-out detection interrupt priority high bit Serial port 0 interrupt priority high bit PT1H Timer 1 interrupt priority high bit PX1H...
  • Page 175 MS51 EIP – Extensive Interrupt Priority Regiser Address Reset Value EFH, all pages 0000_0000b PSPI PWDT PPWM PCAP PI2C Name Description Timer 2 interrupt priority low bit PSPI SPI interrupt priority low bit Fault Brake interrupt priority low bit PWDT WDT interrupt priority low bit PPWM PWM interrupt priority low bit...
  • Page 176 MS51 EIPH – Extensive Interrupt Priority High Regiser Address Reset Value EIPH F7H, all page 0000_0000b PT2H PSPIH PFBH PWDTH PPWMH PCAPH PPIH PI2CH Name Description PT2H Timer 2 interrupt priority high bit PSPIH SPI interrupt priority high bit PFBH Fault Brake interrupt priority high bit PWDTH WDT interrupt priority high bit...
  • Page 177 MS51 EIP1 – Extensive Interrupt Priority 1 Regiser Address Reset Value EIP1 FEH, page 0 0000_0000b PWKT PS _ 1 Name Description PWKT WKT interrupt priority low bit Timer 3 interrupt priority low bit PS _ 1 Serial port 1 interrupt priority low bit Note: EIP1 is used in combination with the EIPH1 to determine the priority of each interrupt source.
  • Page 178 MS51 EIPH1 – Extensive Interrupt Priority High 1 Regiser Address Reset Value EIPH1 FFH, page 0 0000_0000b PWKTH PT3H PSH _ 1 Name Description PWKTH WKT interrupt priority high bit PT3H Timer 3 interrupt priority high bit PSH _ 1 Serial port 1 interrupt priority high bit Note: EIPH1 is used in combination with the EIP1 to determine the priority of each interrupt source.
  • Page 179 MS51 TCON – Timer 0 and 1 Control Regiser Address Reset Value TCON 88H, all pages, Bit-addressable 0000_0000b R (level) R (level) R/W (edge) R/W (edge) Name Description External interrupt 1 edge flag If IT1 = 1 (falling edge trigger), this flag will be set by hardware when a falling edge is detected. It remain set until cleared via software or cleared by hardware in the beginning of its interrupt service routine.
  • Page 180 MS51 Flash Memory Contorl 6.3.1 In-Application-Programming (IAP) Unlike RAM’s real-time operation, to update flash data often takes long time. Furthermore, it is a quite complex timing procedure to erase, program, or read flash data. The MS51 carried out the flash operation with convenient mechanism to help user re-programming the flash content by In-Application- Programming (IAP).

  • Page 181: Table 6.3-1 Iap Modes And Command Codes

    MS51 IAPCN IAPA[15:0] IAP Mode IAPFD[7:0] IAPB FCTRL {IAPAH, IAPAL} FOEN FCEN [1:0] [3:0] CONFIG byte-read 0000 CONFIG0: 0000H Data out CONFIG1: 0001H CONFIG2: 0002H CONFIG4: 0004H CONFIG6: 0005H Note: 1. “X” means “don’t care”. 2. Each page is 128 bytes size. Therefore, the address should be the address pointed to the target page Table 6.3-1 IAP Modes and Command Codes 6.3.1.2 Control register...
  • Page 182 MS51 Name Description IAPEN IAP enable 0 = IAP function Disabled. 1 = IAP function Enabled. Once enabling IAP function, the HIRC will be turned on for timing control. To clear IAPEN should always be the last instruction after IAP operation to stop internal oscillator if reducing power consumption is concerned.
  • Page 183 MS51 Name Description FCTRL[3:0] IAPAH – IAP Address High Byte Regiser Address Reset Value IAPAH A7H, all pages 0000_0000b IAPA[15:8] Name Description IAP address high byte IAPA[15:8] IAPAH contains address IAPA[15:8] for IAP operations. IAPAL – IAP Address Low Byte Regiser Address Reset Value...
  • Page 184 MS51 IAPTRG A4H, all pages,TA protected 0000_0000b IAPGO Name Description Reserved IAP go IAPGO IAP begins by setting this bit as logic 1. After this instruction, the CPU holds the Program Counter (PC) and the IAP hardware automation takes over to control the progress. After IAP action completed, the Program Counter continues to run the following instruction.
  • Page 185 MS51 ; Data Flash when user code is executed in APROM. ;****************************************************************************** PAGE_ERASE_AP 00100010b BYTE_PROGRAM_AP 00100001b 0000h TA,#0Aah ;CHPCON is TA protected TA,#55h CHPCON,#00000001b ;IAPEN = 1, enable IAP mode TA,#0Aah ;IAPUEN is TA protected TA,#55h IAPUEN,#00000001b ;APUEN = 1, enable APROM update IAPCN,#PAGE_ERASE_AP ;Erase page 200h~27Fh IAPAH,#02h...
  • Page 186 General speaking, an ISP is carried out by a communication between PC and MCU. PC transfers the new User Code to MCU through serial port. Then Boot Code receives it and re-programs into User Code through IAP commands. Nuvoton provides ISP firmware and PC application for MS51. It makes Dec. 17, 2019 Page 186 of 316 Rev 1.01...
  • Page 187 MS51 user quite easy perform ISP through UART port. Please visit Nuvoton 8-bit Microcontroller website: Nuvoton 80C51 Microcontroller Technical Support. A simple ISP demo code is given below. Assembly demo code: ;************************************************************************** ; This code illustrates how to do APROM and CONFIG IAP from LDROM.
  • Page 188 MS51 Enable_AP_Update: TA,#0Aah ;IAPUEN is TA protected TA,#55h IAPUEN,#00000001b ;APUEN = 1, enable APROM update Disable_AP_Update: TA,#0Aah TA,#55h IAPUEN,#11111110b ;APUEN = 0, disable APROM update Enable_CONFIG_Update: TA,#0Aah TA,#55h IAPUEN,#00000100b ;CFUEN = 1, enable CONFIG update Disable_CONFIG_Update: TA,#0Aah TA,#55h IAPUEN,#11111011b ;CFUEN = 0, disable CONFIG update Trigger_IAP: TA,#0Aah ;IAPTRG is TA protected...
  • Page 189 MS51 CALL Trigger_IAP DPTR IAPAL A,IAPAL CJNE A,#14,Program_AP_Loop Program_AP_Verify: IAPCN,#BYTE_READ_AP IAPAH,#00h IAPAL,#00h DPTR,#AP_code Program_AP_Verify_Loop: CALL Trigger_IAP MOVC A,@A+DPTR A,IAPFD CJNE A,B,Program_AP_Verify_Error DPTR IAPAL A,IAPAL CJNE A,#14,Program_AP_Verify_Loop Program_AP_Verify_Error: CALL Disable_IAP P0,#00h SJMP $ ;******************************************************************** IAP CONFIG Function ;******************************************************************** Erase_CONFIG: IAPCN,#ALL_ERASE_CONFIG IAPAH,#00h IAPAL,#00h IAPFD,#0FFh CALL Trigger_IAP...
  • Page 190 VDD and GND pins on the circuit board to make ICP possible. Nuvoton provides ICP tool for MS51, which enables user to easily perform ICP through Nuvoton ICP programmer. The ICP programmer developed by Nuvoton has been optimized according to the electric characteristics of MCU.
  • Page 191 MS51 programmed as 1, the OCD is activated. The OCD cannot operate if chip is locked. The OCD system uses a two-wire serial interface, OCDDA and OCDCK, to establish communication between the target device and the controlling debugger host. OCDDA is an input/output pin for debug data transfer and OCDCK is an input pin for synchronization with OCDDA data.
  • Page 192 MS51 Name Description OCDEN OCD enable 1 = OCD Disabled. 0 = OCD Enabled. Note: If MCU run in OCD debug mode and OCDEN = 0, hard fault reset will disable. Only HardF flag be asserted. 6.3.4 96-Bit Unique Code Before shipping out, each MS51 chip was factory pre-programmed with a 96-bit width serial number, which is guaranteed to be unique.

  • Page 193: Table 6.4-1 Configuration For Different I/O Modes

    MS51 General Purpose IO (GPIO) 6.4.1 GPIO Mode The MS51 has a maximum of 43 general purpose I/O pins which 40 bit-addressable general I/O pins grouped as 5 ports, P0 to P4, and 7 general I/O pins grouped as P5. Each port has its port control register (Px register).

  • Page 194: Figure 6.4-1 Quasi-Bidirectional Mode Structure

    MS51 2-CPU-clock Very Strong delay Weak Port Pin Port Latch Input Figure 6.4-1 Quasi-Bidirectional Mode Structure 6.4.1.2 Push-Pull Mode The push-pull mode has the same pull-low structure as the quasi-bidirectional mode, but provides a continuous strong pull-high when the port latch is written by logic 1. The push-pull mode is generally used as output pin when more source current is needed for an output driving.

  • Page 195: Figure 6.4-4 Open-Drain Mode Structure

    MS51 6.4.1.4 Open-Drain Mode The open-drain mode turns off all pull-high transistors and only drives the pull-low of the port pin when the port latch is given by logic 0. If the port latch is logic 1, it behaves as if in input-only mode. To be used as an output pin generally as I C lines, an open-drain pin should add an external pull-high, typically a resistor tied to V...
  • Page 196 MS51 Name Description P2.0 Port 2 bit 0 P2.0 is an input-only pin when RPD (CONFIG0.2) is programmed as 0. When leaving RPD un- programmed, P2.0 is always read as 0. Name Description Port 3 bit 0 P3.0 P3.0 is available only when the internal oscillator is used as the system clock. At this moment, P3.0 functions as a general purpose I/O.
  • Page 197 MS51 PnM2.7 PnM2.6 PnM2.5 PnM2.4 PnM2.3 PnM2.2 PnM2.1 PnM2.0 Name Description PnMn[7:0] Port 0 mode select 6.4.2.3 Input Type Select Each I/O pin can be configured individually as TTL input or Schmitt triggered input. Note that all of PxS registers are accessible by switching SFR page to Page 1. PnS –...
  • Page 198 MS51 Name Description Timer 1 output enable T1OE 0 = Timer 1 output Disabled. 1 = Timer 1 output Enabled from T1 pin. Note that Timer 1 output should be enabled only when operating in its “Timer” mode. Timer 0 output enable T0OE 0 = Timer 0 output Disabled.
  • Page 199 MS51 Increment. (INC direct) Decrement. (DEC direct) DJNZ Decrement and jump if not zero. (DJNZ direct, rel) bit, C Move carry to bit. (MOV bit, C) Clear bit. (CLR bit) SETB Set bit. (SETB bit) The last three seem not obviously “Read-Modify-Write” instructions but actually they are. They read the entire port latch value, modify the changed bit, and then write the new value back to the port latch.

  • Page 200: Figure 6.4-5 Pin Interface Block Diagram

    MS51 Figure 6.4-5 Pin Interface Block Diagram Pin interrupt is generally used to detect an edge transient from peripheral devices like keyboard or keypad. During idle state, the system prefers to enter Power-down mode to minimize power consumption and waits for event trigger. Pin interrupt can wake up the device from Power-down mode. Dec.
  • Page 201 MS51 PICON – Pin Interrupt Control Regiser Address Reset Value PICON E9H, all pages 0000_0000b PIT67 PIT45 PIT3 PIT2 PIT1 PIT0 PIPS[1:0] Name Description Pin interrupt channel 6 and 7 type select PIT67 This bit selects which type that pin interrupt channel 6 and 7 is triggered. 0 = Level triggered.
  • Page 202 MS51 PINEN – Pin Interrupt Negative Polarity Enable Regiser Address Reset Value PINEN EAH, all pages 0000_0000b PINEN7 PINEN6 PINEN5 PINEN4 PINEN3 PINEN2 PINEN1 PINEN0 Name Description PINENn Pin interrupt channel n negative polarity enable This bit enables low-level/falling edge triggering pin interrupt channel n. The level or edge triggered selection depends on each control bit PITn in PICON.
  • Page 203 MS51 PIPEN – Pin Interrupt Positive Polarity Enable Regiser Address Reset Value PIPEN EBH, all pages 0000_0000b PIPEN7 PIPEN6 PIPEN5 PIPEN4 PIPEN3 PIPEN2 PIPEN1 PIPEN0 Name Description PIPENn Pin interrupt channel n positive polarity enable This bit enables high-level/rising edge triggering pin interrupt channel n. The level or edge triggered selection depends on each control bit PITn in PICON.
  • Page 204 MS51 PIF – Pin Interrupt Flags Regiser Address Reset Value ECH, all pages 0000_0000b PIF7 PIF6 PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 R (level) R (level) R (level) R (level) R (level) R (level) R (level) R (level) R/W (edge) R/W (edge) R/W (edge) R/W (edge)

  • Page 205: Figure 6.5-1 Timer/Counters 0 And 1 In Mode 0

    MS51 Timer 6.5.1 Timer/Counter 0 And 1 Timer/Counter 0 and 1 on MS51 are two 16-bit Timers/Counters. Each of them has two 8-bit registers those form the 16-bit counting register. For Timer/Counter 0 they are TH0, the upper 8-bit register, and TL0, the lower 8-bit register.

  • Page 206: Figure 6.5-2 Timer/Counters 0 And 1 In Mode 1

    MS51 6.5.1.2 Mode 1 (16-Bit Timer) Mode 1 is similar to Mode 0 except that the counting registers are fully used as a 16-bit counter. Roll- over occurs when a count moves FFFFH to 0000H. The Timer overflow flag TF0 (TF1) of the relevant Timer/Counter is set and an interrupt will occurs if enabled.

  • Page 207: Figure 6.5-4 Timer/Counter 0 In Mode 3

    MS51 flag TF1 and the enable bit TR1. However Timer 1 can still be used as a Timer/Counter and retains ̅̅̅̅̅̅̅ pin and T1M. It can be used as a baud rate generator for the serial port or the use of GATE, INT1 other application not requiring an interrupt.
  • Page 208 MS51 TCON – Timer 0 and 1 Control Regiser Address Reset Value TCON 88H, all pages, Bit-addressable 0000_0000b R (level) R (level) R/W (edge) R/W (edge) Name Description Timer 1 overflow flag This bit is set when Timer 1 overflows. It is automatically cleared by hardware when the program executes the Timer 1 interrupt service routine.
  • Page 209 MS51 Name Description TL0[7:0] Timer 0 low byte The TL0 register is the low byte of the 16-bit counting register of Timer 0. TH0 – Timer 0 High Byte Regiser Address Reset Value 8CH, all pages 0000_0000b TH0[7:0] Name Description TH0[7:0] Timer 0 high byte The TH0 register is the high byte of the 16-bit counting register of Timer 0.
  • Page 210 MS51 CKCON – Clock Control Regiser Address Reset Value CKCON 8EH, all pages 0000_0000b FASTWK PWMCKS T1OE T0OE CLOEN Name Description Timer 1 output enable T1OE 0 = Timer 1 output Disabled. 1 = Timer 1 output Enabled from T1 pin. Note that Timer 1 output should be enabled only when operating in its “Timer”...

  • Page 211: Figure 6.5-5 Timer 2 Full Function Block Diagram

    MS51 P1.5/IC7 1000 CAPF0 CAPF0 0111 P0.5/IC6 [00] 0110 P0.3/IC5 0101 CAPF1 P0.1/IC4 CAP0 Noise Input Capture Interrupt P0.4/IC3 0100 [01] Filter P0.0/IC3 0011 P1.0/IC2 0010 CAPF2 CAP1 P1.1/IC1 0001 ENF0 [10] P1.2/IC0 0000 (CAPCON2.4) CAPEN0 CAP2 (CAPCON0.4) CAP0LS[1:0] (CAPCON1[1:0]) Input Capture 0 Module Input Capture 1 Module Input Capture 2 Module...

  • Page 212: Figure 6.5-6 Timer 2 Auto-Reload Mode Block Diagram

    MS51 CAPF0 P1.5/IC7 1000 CAPF0 [00] 0111 P0.5/IC6 CAPF1 0110 Input Capture Interrupt P0.3/IC5 Noise 0101 CAPF2 P0.1/IC4 CAP0 [01] P0.4/IC3 0100 Filter P0.0/IC3 0011 P1.0/IC2 0010 CAP1 ENF0 [10] P1.1/IC1 0001 (CAPCON2.4) CAPEN0 P1.2/IC0 0000 CAP2 (CAPCON0.4) CAP0LS[1:0] (CAPCON1[1:0]) Input Capture 0 Module Input Capture 1 Module Input Capture 2 Module...

  • Page 213: Figure 6.5-7 Timer 2 Compare Mode Block Diagram

    MS51 after a compare match has occurred. CAPF0 1000 P1.5/IC7 CAPF0 [00] 0111 P0.5/IC6 CAPF1 Input Capture Interrupt 0110 P0.3/IC5 Noise 0101 CAPF2 P0.1/IC4 CAP0 [01] P0.4/IC3 0100 Filter P0.0/IC3 0011 P1.0/IC2 0010 CAP1 ENF0 [10] P1.1/IC1 0001 (CAPCON2.4) CAPEN0 P1.2/IC0 0000 CAP2...
  • Page 214 MS51 T2CON – Timer 2 Control Regiser Address Reset Value T2CON C8H, all pages 0000_0000b ̅̅̅̅̅̅ CM/RL2 Name Description Timer 2 overflow flag This bit is set when Timer 2 overflows or a compare match occurs. If the Timer 2 interrupt and the global interrupt are enable, setting this bit will make CPU execute Timer 2 interrupt service routine.
  • Page 215 MS51 T2MOD – Timer 2 Mode Regiser Address Reset Value T2MOD C9H, all pages 0000_0000b LDEN T2DIV[2:0] CAPCR CMPCR LDTS[1:0] Name Description Enable auto-reload LDEN 0 = Reloading RCMP2H and RCMP2L to TH2 and TL2 Disabled. 1 = Reloading RCMP2H and RCMP2L to TH2 and TL2 Enabled. Timer 2 clock divider T2DIV[2:0] 000 = Timer 2 clock divider is 1/1.
  • Page 216 MS51 RCMP2L – Timer 2 Reload/Compare Low Byte Regiser Address Reset Value RCMP2L CAH, all pages 0000_0000b RCMP2L[7:0] Name Description RCMP2L[7:0] Timer 2 reload/compare low byte This register stores the low byte of compare value when Timer 2 is configured in compare mode.
  • Page 217 MS51 TL2 – Timer 2 Low Byte Regiser Address Reset Value CCH, all pages 0000_0000b TL2[7:0] Name Description TL2[7:0] Timer 2 low byte The TL2 register is the low byte of the 16-bit counting register of Timer 2. Dec. 17, 2019 Page 217 of 316 Rev 1.01...
  • Page 218 MS51 TH2 – Timer 2 High Byte Regiser Address Reset Value CDH, Page 0 0000_0000b TH2[7:0] Name Description TH2[7:0] Timer 2 high byte The TH2 register is the high byte of the 16-bit counting register of Timer 2. Note that the TH2 and TL2 are accessed separately. It is strongly recommended that user stops Timer 2 temporally by clearing TR2 bit before reading from or writing to TH2 and TL2.
  • Page 219 MS51 CAPCON0 – Input Capture Control 0 Regiser Address Reset Value CAPCON0 92H, all pages 0000_0000b CAPEN2 CAPEN1 CAPEN0 CAPF2 CAPF1 CAPF0 Name Description Reserved CAPEN2 Input capture 2 enable 0 = Input capture channel 2 Disabled. 1 = Input capture channel 2 Enabled. CAPEN1 Input capture 1 enable 0 = Input capture channel 1 Disabled.
  • Page 220 MS51 CAPCON1 – Input Capture Control 1 Regiser Address Reset Value CAPCON1 93H, all pages 0000_0000b CAP2LS[1:0] CAP1LS[1:0] CAP0LS[1:0] Name Description Reserved CAP2LS[1:0] Input capture 2 level select 00 = Falling edge. 01 = Rising edge. 10 = Either rising or falling edge. 11 = Reserved.
  • Page 221 MS51 CAPCON2 – Input Capture Control 2 Regiser Address Reset Value CAPCON2 94H, all pages 0000_0000b ENF2 ENF1 ENF0 Name Description Enable noise filer on input capture 2 ENF2 0 = Noise filter on input capture channel 2 Disabled. 1 = Noise filter on input capture channel 2 Enabled. Enable noise filer on input capture 1 ENF1 0 = Noise filter on input capture channel 1 Disabled.
  • Page 222 MS51 CnL – Capture n Low Byte Regiser Address Reset Value E4H, all pages 0000_0000b E6H, all pages 0000_0000b EDH, all pages 0000_0000b C0L[7:0] Name Description Input capture n result low byte CnL[7:0] The C0L register is the low byte of the 16-bit result captured by input capture 0. Dec.
  • Page 223 MS51 CnH – Capture n High Byte Regiser Address Reset Value E4H, all pages 0000_0000b E7H, all pages 0000_0000b EEH, all pages 0000_0000b C0H[7:0] Name Description CnH[7:0] Input capture n result high byte The C0H register is the high byte of the 16-bit result captured by input capture 0. Dec.
  • Page 224 MS51 CAPCON3 – Input Capture Control 3 Regiser Address Reset Value CAPCON3 F1H, all pages 0000_0000b CAP13 CAP12 CAP11 CAP10 CAP03 CAP02 CAP01 CAP00 Name Description Input capture channel 1 input pin select [7:4] CAP1[3:0] 0000 = P1.2/IC0 0001 = P1.1/IC1 0010 = P1.0/IC2 0011 = P0.0/IC3 0100 = P0.4/IC3...

  • Page 225: Figure 6.5-8 Timer 3 Block Diagram

    MS51 CAPCON4 – Input Capture Control 4 Regiser Address Reset Value CAPCON4 F2H, all pages 0000_0000b CAP23 CAP22 CAP21 CAP20 Name Description Input capture channel 2 input pin select [3:0] CAP2[3:0] 0000 = P1.2/IC0 0001 = P1.1/IC1 0010 = P1.0/IC2 0011 = P0.0/IC3 0100 = P0.4/IC3 0101 = P0.1/IC4...
  • Page 226 MS51 T3CON – Timer 3 Control Regiser Address Reset Value T3CON C4H, Page 0 0000_0000b SMOD_1 SMOD0_1 BRCK T3PS[2:0] Name Description Timer 3 overflow flag This bit is set when Timer 3 overflows. It is automatically cleared by hardware when the program executes the Timer 3 interrupt service routine.
  • Page 227 MS51 RL3 – Timer 3 Reload Low Byte Regiser Address Reset Value C5H, Page 0 0000_0000b RL3[7:0] Name Description RL3[7:0] Timer 3 reload low byte It holds the low byte of the reload value of Timer 3. RH3 – Timer 3 Reload High Byte Regiser Address Reset Value...

  • Page 228: Table 6.6-1 Watchdog Timer-Out Interval Under Different Pre-Scalars

    MS51 Watchdog Timer (WDT) The MS51 provides one Watchdog Timer (WDT). It can be configured as a time-out reset timer to reset whole device. Once the device runs in an abnormal status or hangs up by outward interference, a WDT reset recover the system. It provides a system monitor, which improves the reliability of the system.

  • Page 229: Figure 6.6-1 Wdt As A Time-Out Reset Timer

    MS51 down mode suggest use WKT function see Chapter 6.7 Self Wake-Up Timer (WKT). 6.6.1 Time-Out Reset Timer When the CONFIG bits WDTEN[3:0] (CONFIG4[7:4]) is not FH, the WDT is initialized as a time-out reset timer. If WDTEN[3:0] is not 5H, the WDT is allowed to continue running after the system enters Idle or Power-down mode.
  • Page 230 MS51 be set while the WDT completes the selected time interval. The software polls the WDTF flag to detect a time-out. An interrupt will occur if the individual interrupt EWDT (EIE0.4) and global interrupt enable EA is set. WDT will continue counting. User should clear WDTF and wait for the next overflow by polling WDTF flag or waiting for the interrupt occurrence.
  • Page 231 MS51 WDCON – Watchdog Timer Control Regiser Address Reset Value POR 0000_0111b WDCON AAH, all pages, TA protected WDT 0000_1UUUb Others 0000_UUUUb WDTR WDCLR WDTF WIDPD WDTRF WDPS[2:0] Name Description WDTR WDT run This bit is valid only when control bits in WDTEN[3:0] (CONFIG4[7:4]) are all 1. At this time, WDT works as a general purpose timer.

  • Page 232: Figure 6.7-1 Self Wake-Up Timer Block Diagram

    MS51 Self Wake-Up Timer (WKT) The MS51 has a dedicated Self Wake-up Timer (WKT), which serves for a periodic wake-up timer in low power mode or for general purpose timer. WKT remains counting in Idle or Power-down mode. When WKT is being used as a wake-up timer, a start of WKT can occur just prior to entering a power management mode.
  • Page 233 MS51 WKCON – Self Wake-up Timer Control Regiser Address Reset Value WKCON 8FH, all pages 0000_0000b WKTF WKTR WKPS[2:0] Name Description Reserved WKT overflow flag WKTF This bit is set when WKT overflows. If the WKT interrupt and the global interrupt are enabled, setting this bit will make CPU execute WKT interrupt service routine.
  • Page 234 MS51 RWK – Self Wake-up Timer Reload Byte Regiser Address Reset Value 86H, all pages 0000_0000b RWK[7:0] Name Description RWK[7:0] WKT reload byte It holds the 8-bit reload value of WKT. Note that RWK should not be FFH if the pre-scale is 1/1 for implement limitation.

  • Page 235: Figure 6.8-1 Serial Port Mode 0 Timing Diagram

    MS51 Serial Port (UART0 & UART1) The MS51 includes two enhanced full duplex serial ports enhanced with automatic address recognition and framing error detection. As control bits of these two serial ports are implemented the same. Generally speaking, in the following contents, there will not be any reference to serial port 1, but only to serial port 0.

  • Page 236: Figure 6.8-2 Serial Port Mode 1 Timing Diagram

    MS51 6.8.1.2 Mode 1 Mode 1 supports asynchronous, full duplex serial communication. The asynchronous mode is commonly used for communication with PCs, modems or other similar interfaces. In Mode 1, 10 bits are transmitted through TXD or received through RXD including a start bit (logic 0), 8 data bits (LSB first) and a stop bit (logic 1).

  • Page 237: Figure 6.8-3 Serial Port Mode 2 And 3 Timing Diagram

    MS51 Figure 6.8-3 Serial Port Mode 2 and 3 Timing Diagram Transmission is initiated by any writing instructions to SBUF. Transmission takes place on TXD pin. First the start bit comes out, the 8-bit data and bit TB8 (SCON.3) follows to be shifted out and then ends with a stop bit.

  • Page 238: Table 6.8-1 Serial Port Uart0 Mode / Baudrate Description

    MS51 Following shows all UART mode and baudrate fomula: Frame SM0 / SM1 SMOD Mode Baud Rate Bits (SCON[7:6]) (SCON[5]) (PCON[7]) FSYS divided by 12 FSYS divided by 2 Time1     TM1 CKCON[3] = 0 Time1  ...

  • Page 239: Table 6.8-2 Serial Port Uart1 Mode / Baudrate Description

    MS51 Frame SM0_1 / SM1_1 SMOD_1 Mode Baud Rate Bits (S1CON[7:6]) (T3CON[7]) FSYS divided by 12  Timer 3      scale 65536 (256 RL3)  Timer 3      scale 65536 (256 RL3) FSYS divided by 64 FSYS divided by 32 ...
  • Page 240 MS51 RH3 = value high byte RL3 = value low byte T3CON|= 0x08; Following list some popular baudrate value base on different Fsys and the deviation value: Fsys Value Baud Rate TH1 Value (Hex) RH3,RL3 Value (Hex) Baudrate Deviation 4800 FEC8 0.160256% (SMOD=0)
  • Page 241 MS51 The FE bit will be set 1 via hardware while a framing error occurs. FE can be checked in UART interrupt service routine if necessary. Note that SMOD0 should be 1 while reading or writing to FE. If FE is set, any following frames received without frame error will not clear the FE flag. The clearing has to be done via software.
  • Page 242 MS51 which bits are “don’t care”. The SADEN mask can be logically ANDed with the SADDR to create the “Given” address, which the master will use for addressing each of the slaves. Use of the “Given” address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme.
  • Page 243 MS51 necessary to make bit 2 = 1 to exclude slave 2. The “Broadcast” address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are treated as “don’t-cares”, e.g.: SADDR = 01010110b SADEN = 11111100b Broadcast = 1111111Xb...
  • Page 244 MS51 Name Description 9th transmitted bit This bit defines the state of the 9th transmission bit in serial port 0 Mode 2 or 3. It is not used in Mode 0 or 1. 9th received bit The bit identifies the logic level of the 9th received bit in serial port 0 Mode 2 or 3. In Mode 1, RB8 is the logic level of the received stop bit.
  • Page 245 MS51 SCON _ 1 – Serial Port 1 Control Regiser Address Reset Value SCON_1 F8H, all page, bit addressable 0000_0000b SM0_1/FE_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 Name Description Serial port 1 mode select SM0_1/FE_1 SMOD0_1 (T3CON.6) = 0: See Table 6.8-2 Serial Port UART1 Mode / baudrate Description for details.
  • Page 246 MS51 Dec. 17, 2019 Page 246 of 316 Rev 1.01...
  • Page 247 MS51 PCON – Power Control Regiser Address Reset Value POR, 0001_0000b PCON 87H, all pages Others,000U_0000b SMOD SMOD0 Name Description Serial port 0 double baud rate enable SMOD Setting this bit doubles the serial port baud rate when UART0 is in Mode 2 or when Timer 1 overflow is used as the baud rate source of UART0 Mode 1 or 3.
  • Page 248 MS51 T3CON – Timer 3 Control Regiser Address Reset Value T3CON C4H, Page 0 0000_0000b SMOD_1 SMOD0_1 BRCK T3PS[2:0] Name Description Serial port 1 double baud rate enable SMOD_1 Setting this bit doubles the serial port baud rate when UART1 is in Mode 2. See Table 6.8-1 Serial Port UART0 Mode / baudrate Description for details.
  • Page 249 MS51 SBUF – Serial Port 0 Data Buffer Regiser Address Reset Value SBUF 99H, all pages 0000_0000b SBUF[7:0] Name Description Serial port 0 data buffer SBUF[7:0] This byte actually consists two separate registers. One is the receiving resister, and the other is the transmitting buffer.
  • Page 250 MS51 SBUF_1 – Serial Port 1 Data Buffer Regiser Address Reset Value SBUF_1 9AH, all pages 0000_0000b SBUF1[7:0] Name Description SBUF1[7:0] Serial port 1 data buffer This byte actually consists two separate registers. One is the receiving resister, and the other is the transmitting buffer.
  • Page 251 MS51 IE – Interrupt Enable (Bit-addressable) Regiser Address Reset Value A8H, all pages, bit addressable 0000_0000b EADC EBOD Name Description Enable serial port 0 interrupt 0 = Serial port 0 interrupt Disabled. 1 = Interrupt generated by TI (SCON.1) or RI (SCON.0) Enabled. EIE1 –...
  • Page 252 MS51 SADDR – Slave 0 Address Regiser Address Reset Value SADDR A9H, all pages 0000_0000b SADDR[7:0] Name Description Slave 0 address SADDR[7:0] This byte specifies the microcontroller’s own slave address for UATR0 multi-processor communication. SADEN – Slave 0 Address Mask Regiser Address Reset Value...
  • Page 253 MS51 SADDR1 – Slave 1 Address Regiser Address Reset Value SADDR_1 BBH, all pages 0000_0000 b SADDR1[7:0] Name Description Slave 1 address SADDR1[7:0] This byte specifies the microcontroller’s own slave address for UART1 multi-processor communication. SADEN1 – Slave 1 Address Mask Regiser Address Reset Value...
  • Page 254 MS51 AUXR1 – Auxiliary Register 1 Regiser Address Reset Value POR 0000_0000b, Software 1U00_0000b AUXR1 A2H, all pages nRESET pin U100_0000b Others UUU0_0000b SWRF RSTPINF HardF SLOW UART0PX Name Description Serial port 0 pin exchange UART0PX 0 = Assign RXD to P0.7 and TXD to P0.6 by default. 1 = Exchange RXD to P0.6 and TXD to P0.7.

  • Page 255: Figure 6.9-1 Spi Block Diagram

    MS51 Serial Peripheral Interface (SPI) The MS51 provides two Serial Peripheral Interface (SPI) block to support high-speed serial communication. SPI is a full-duplex, high-speed, synchronous communication bus between microcontrollers or other peripheral devices such as serial EEPROM, LCD driver, or D/A converter. It provides either Master or Slave mode, high-speed rate up to , transfer complete and write collision flag.

  • Page 256: Figure 6.9-2 Spi Multi-Master, Multi-Slave Interconnection

    MS51 clock is used to synchronize the data movement both in and out of the devices through their MOSI and MISO pins. The shift clock is driven by the Master mode device for eight clock cycles. Eight clocks exchange one byte data on the serial lines. For the shift clock is always produced out of the Master device, the system should never exist more than one device in Master mode for avoiding device conflict.

  • Page 257: Table 6.9-1 Slave Select Pin Configurations

    MS51 data in from the Slave via MISO line. The two shift registers in the Master MCU and the Slave MCU can be considered as one 16-bit circular shift register. Therefore, while a transfer data pushed from Master into Slave, the data in Slave will also be pulled in Master device respectively. The transfer effectively exchanges the data, which was in the SPI shift registers of the two MCUs.

  • Page 258: Figure 6.9-4 Spi Clock Formats

    MS51 that CPOL and CPHA compose four different clock formats. The CPOL bit denotes the SPCLK line level in its idle state. The CPHA bit defines the edge on which the MOSI and MISO lines are sampled. The CPOL and CPHA should be identical for the Master and Slave devices on the same system. To Communicate in different data formats with one another will result undetermined result.

  • Page 259: Figure 6.9-5 Spi Clock And Data Format With Cpha = 0

    MS51 SPCLK Cycles SPCLK Cycles SPCLK (CPOL=0) SPCLK (CPOL=1) Transfer Progress (internal signal) MOSI MISO Input to Slave SS SS output of Master SPIF (Master) SPIF (Slave) Transfer progress starts by a writing SPDR of Master MCU. SS automatic output affects when MSTR = DISMODF = SSOE = 1. Figure 6.9-5 SPI Clock and Data Format with CPHA = 0 SPCLK Cycles SPCLK Cycles...
  • Page 260 MS51 6.9.3 Slave Select Pin Configuration ̅̅̅̅̅ The MS51 SPI gives a flexible SS pin feature for different system requirements. When the SPI ̅̅̅̅̅ ̅̅̅̅̅ operates as a Slave, SS pin always rules as Slave select input. When the Master mode is enabled, SS has three different functions according to DISMODF (SPInSR.3) and SSOE (SPInCR.7).

  • Page 261: Figure 6.9-7 Spi Overrun Waveform

    MS51 Data[n] Receiving Begins Data[n+1] Receiving Begins Data[n+2] Receiveing Begins Shift Register Shifting Data[n] in Shifting Data[n+1] in Shifting Data[n+2] in SPIF Read Data Buffer Data[n] Data[n] Data[n+2] SPIOVF When Data[n] is received, the SPIF will be set. If SPIF is not clear before Data[n+1] progress done, the SPIOVF will be set.
  • Page 262 MS51 Name Description Slave select output enable ̅̅̅̅ pin as This bit is used in combination with the DISMODF (SPSR.3) bit to determine the feature of SS shown in Table 6.9-1 Slave Select Pin Configurations. This bit takes effect only under MSTR = 1 and DISMODF = 1 condition.
  • Page 263 MS51 Name Description Reserved SPIS[1:0] SPI Interval time selection between adjacent bytes SPIS[1:0] and CPHA select eight grades of SPI interval time selection between adjacent bytes. As below table: CPHA SPIS1 SPIS0 SPI clock SPIS[1:0] are valid only under Master mode (MSTR = 1). SPSR –...
  • Page 264 MS51 Name Description TXBUF SPI writer data buffer status This bit indicates the SPI transmit buffer status. 0 = SPI writer data buffer is empty 1 = SPI writer data buffer is full. SPDR – Serial Peripheral Data Register Regiser Address Reset Value SPDR...

  • Page 265: Figure 6.10-1 I 2 C Bus Interconnection

    MS51 6.10 Inter-Integrated Circuit (I The MS51 provides two Inter-Integrated Circuit (I C) bus to serves as an serial interface between the microcontrollers and the I C devices such as EEPROM, LCD module, temperature sensor, and so on. The I C bus used two wires design (a serial data line I2C0_SDA and a serial clock line I2C0_SCL) to transfer information between devices.

  • Page 266: Figure 6.10-2 I 2 C Bus Protocol

    MS51 START STOP condition condition Figure 6.10-2 I C Bus Protocol 6.10.1.1 START and STOP Condition The protocol of the I C bus defines two states to begin and end a transfer, START (S) and STOP (P) conditions. A START condition is defined as a high-to-low transition on the I2C0_SDA line while I2C0_SCL line is high.

  • Page 267: Figure 6.10-4 Master Transmits Data To Slave By 7-Bit

    MS51 SLAVE ADDRESS DATA DATA data transfer ‘0’ : write (n bytes + acknowlegde) from master to slave A = acknowledge (SDA low) A = not acknowledge (SDA high) S = START condition from slave to master P = STOP condition Figure 6.10-4 Master Transmits Data to Slave by 7-bit Figure 6.10-5 shows a master read data from slave by 7-bit.

  • Page 268: Figure 6.10-7 Acknowledge Bit

    MS51 START condition. If a slave-receiver does acknowledge the slave address, it switches itself to not addressed slave mode and cannot receive any more data bytes. This slave leaves the I2C0_SDA line high. The master should generate a STOP or a repeated START condition. If a master-receiver is involved in a transfer, because the master controls the number of bytes in the transfer, it should signal the end of data to the slave-transmitter by not generating an acknowledge on the last byte.

  • Page 269: Figure 6.10-9 Control I

    MS51 Since control of the I C bus is decided solely on the address or master code and data sent by competing masters, there is no central master, nor any order of priority on the bus. Slaves are not involved in the arbitration procedure. 6.10.2 Operation Modes The on-chip I C ports support three operation modes, Master, Slave, and General Call Mode.

  • Page 270: Figure 6.10-10 Flow And Status Of Master Transmitter Mode

    MS51 ACK STATUS=0x18 ACK STATUS=0x28 STATUS=0x08 NAK STATUS=0x20 NAK STATUS=0x30 I2CnDAT ACK/ I2CnDAT ACK/ (SLA+W) (Data) I2CnDAT =SLA+W I2CnDAT =Data (STA,STO,SI,AA)=(1,0,1,x) (STA,STO,SI,AA)=(0,0,1,x) (STA,STO,SI,AA)=(0,0,1,x) STATUS=0x38 I2CnDAT ACK/ (Data) I2C_DAT=Data (STA,STO,SI,AA)=(0,0,1,x) STATUS=0x10 (STA,STO,SI,AA)=(1,0,1,x) STATUS=0xF8 (STA,STO,SI,AA)=(0,1,1,x) STATUS=0x08 (STA,STO,SI,AA)=(1,1,1,x) (Arbitration Lost) STATUS=0x38 C bus will be release; Not addressed SLV mode will be enterd I2CnDAT ACK/...

  • Page 271: Figure 6.10-11 Flow And Status Of Master Receiver Mode

    MS51 STATUS=0x08 STATUS=0x40 STATUS=0x50 I2CnDAT I2CnDAT (SLA+R) (Data) I2CnDAT=SLA+R (STA,STO,SI,AA)=(1,0,1,x) (STA,STO,SI,AA)=(0,0,1,1) (STA,STO,SI,AA)=(0,0,1,x) (Arbitration Lost) ACK STATUS=0x38 I2CnDAT (Data) (STA,STO,SI,AA)=(0,0,1,0) STATUS=0x58 I2CnDAT (Data) (STA,STO,SI,AA)=(0,0,1,0) STATUS=0x48 STATUS=0x08 (STA,STO,SI,AA)=(1,1,1,x) (Arbitration Lost) STATUS=0x38 STATUS=0xF8 I2CnDAT ACK/ (SLA+R) I2CnDAT=SLA+R (STA,STO,SI,AA)=(0,0,1,X) (STA,STO,SI,AA)=(0,1,1,x) (Arbitration Lost) ACK STATUS=0x10 STATUS= 0x68, 0x78, 0xB0 I2CnDAT (SLA+R)

  • Page 272: Figure 6.10-12 Flow And Status Of Slave Receiver Mode

    MS51 until it is addressed by its own address with the data direction bit “read” (SLA+R). The slave transmitter mode may also be entered if arbitration is lost. After the slave is addressed by SLA+R, it should clear its SI flag to transmit the data to the master receiver.

  • Page 273: Figure 6.10-13 Flow And Status Of General Call Mode

    MS51 6.10.2.5 General Call The General Call is a special condition of slave receiver mode by been addressed with all “0” data in slave address with data direction bit. Both GC (I2CnADDRx.0) bit and AA bit should be set as 1 to enable acknowledging General Calls.
  • Page 274 MS51 6.10.3 Miscellaneous States There are two I2CnSTAT status codes that do not correspond to the 25 defined states, The first status code F8H indicates that no relevant information is available during each transaction. Meanwhile, the SI flag is 0 and no I C interrupt is required.

  • Page 275: Figure 6.10-14 I 2 C Time-Out Counter

    MS51 There is a 14-bit time-out counter, which can be used to deal with the I C bus hang-up. If the time-out counter is enabled, the counter starts up counting until it overflows. Meanwhile I2TOF will be set by hardware and requests I C interrupt.

  • Page 276: Figure 6.10-15 Hold Time Extend Enable

    MS51 Name Description START flag When STA is set, the I2C generates a START condition if the bus is free. If the bus is busy, the I2C waits for a STOP condition and generates a START condition following. If STA is set while the I2C is already in the master mode and one or more bytes have been transmitted or received, the I2C generates a repeated START condition.
  • Page 277 MS51 I2STAT – I C Status Regiser Address Reset Value I2STAT BDH, all pages 1111_1000 b I2STAT[7:3] Name Description I2STAT[7:3] C status code The MSB five bits of I2STAT contains the status code. There are 27 possible status codes. When I2STAT is F8H, no relevant state information is available and SI flag keeps 0. All other 26 status codes correspond to the I C states.
  • Page 278 MS51 Regiser Address Reset Value I2ADDR C1H, all pages 0000_0000b I2ADDR[7:1] Name Description C device’s own slave address I2ADDR[7:1] In master mode: These bits have no effect. In slave mode: These 7 bits define the slave address of this I C device by user.
  • Page 279 MS51 Regiser Address Reset Value I2TOC BFH, all pages 0000_1001 b I2TOCEN I2TOF Name Description C time-out counter enable I2TOCEN 0 = I C time-out counter Disabled. 1 = I C time-out counter Enabled. Note: please always enable I C interrupt when enable I C time-out counter function C time-out counter clock divider 0 = The clock of I...
  • Page 280 MS51 case 0x20: /*20H, SLA+W transmitted, NACK received*/ STO = 1; //transmit STOP AA = 1; //ready for ACK own SLA+W/R or General Call break; case 0x28: /*28H, DATA transmitted, ACK received*/ if (Conti_TX_Data) //if continuing to send DATA I2DAT = NEXT_SEND_DATA2; else //if no DATA to be sent STO = 1;...
  • Page 281 MS51 case 0x70: /*70H, General Call received, ACK returned*/ AA = 1; break; case 0x78: /*78H, arbitration lost in SLA+W/R General Call received, ACK returned*/ AA = 0; STA = 1; break; case 0x80: /*80H, previous own SLA+W, DATA received, ACK returned*/ DATA_RECEIVED2 = I2DAT;...
  • Page 282 MS51 break; case 0Xb8: /*B8H, previous own SLA+R, DATA transmitted, ACK received*/ I2DAT = NEXT_SEND_DATA4; if (To_TX_Last_Data) //if last DATA will be transmitted AA = 0; else AA = 1; break; case 0Xc0: /*C0H, previous own SLA+R, DATA transmitted, NACK received, not addressed SLAVE mode entered*/ AA = 1;...
  • Page 283 MS51 6.11 Pulse Width Modulated (PWM) The PWM (Pulse Width Modulation) signal is a useful control solution in wide application field. It can used on motor driving, fan control, backlight brightness tuning, LED light dimming, or simulating as a simple digital to analog converter output through a low pass filter circuit. The MS51 PWM is especially designed for motor control by providing three pairs, maximum 16-bit resolution of PWM output with programmable period and duty.

  • Page 284: Figure 6.11-1 Pwm Block Diagram

    MS51 PWMP 0-to-1 (PWMnPH, PWMnPL) registers LOAD (PWMnCON0.6) PWMP buffer Counter Matching(edgealigned)/ underflow(venter aligned) PWMF PWM interrupt (PWMnCON0.5) PWMRUN 16-bit (PWMnCON0.7) clear counter up/down Interrupt CLRPWM INTSEL[1:0], INTTYP[1:0] counter select/type (PWMnCON0.4) (PWMnCON0[3:0]) Pre-scalar edge/center Timer 1 overflow PWMTYP PWMCKS PWMDIV0[2:0] PWMn_CH0 (PWMnCON1.4) (CKCON.6)

  • Page 285: Figure 6.11-2 Pwm And Fault Brake Output Control Block Diagram

    MS51 PWM and Fault Brake output control Dead Mask Brake mode time output control polarity select insertion PMEN0 PNP0 PG0_DT PMD0 FBD0 PWMn_CH0 PWM0/1 PWM0/1 dead mode time PG1_DT PMD1 FBD1 PWMn_CH1 PMEN1 PNP1 PMEN2 PG2_DT PNP2 PMD2 FBD2 PWM2/3 PWMn_CH2 PWM2/3 dead...

  • Page 286: Figure 6.11-3 Pwm Edge-Aligned Type Waveform

    MS51 6.11.2 PWM Types The PWM generator provides two PWM types: edge-aligned or center-aligned. PWM type is selected by PWMTYP (PWMnCON1.4). 6.11.2.1 Edge-Aligned Type In edge-aligned mode, the 16-bit counter uses single slop operation by counting up from 0000H to {PWMnPH, PWMnPL} and then starting from 0000H.

  • Page 287: Figure 6.11-4 Pwm Center-Aligned Type Waveform

    MS51 PWMP (2nd) PWMP (1st) 12-bit counter PWM01 (2nd) PWM01 (1st) PWM01 (2nd) duty valid PG01 output PWMP (2nd) period valid Load Load PWM01 (2nd) PWMP (2nd) Figure 6.11-4 PWM Center-aligned Type Waveform The output frequency and duty cycle for center-aligned PWM are given by following equations: PWM frequency = is the PWM clock source frequency divided by ...

  • Page 288: Figure 6.11-5 Pwm Complementary Mode With Dead-Time Insertion

    MS51 PG0_DT PG1_DT Figure 6.11-5 PWM Complementary Mode with Dead-time Insertion 6.11.3.3 Synchronous Mode Synchronous mode is enabled when PWMMOD[1:0] = [1:0]. In this mode, PG0/2/4 output PWM signals the same as the independent mode. PG1/3/5 output just the same in-phase PWM signals of PG02/4 correspondingly.

  • Page 289: Figure 6.11-7 Pwm Interrupt Type

    MS51 active level on all control fields implemented with positive logic. It means the power switch is ON when PWM outputs high level and OFF when low level. User can easily configure all setting with positive logic and then set PWMnNP bit to make PWM actually outputs according to the negative logic. 6.11.7 PWM Interrupt The PWM module has a flag PWMF (PWMnCON0.5) to indicate certain point of each complete PWM...
  • Page 290 MS51 Name Description PWM run enable PWMRUN 0 = PWM stays in idle. 1 = PWM starts running. PWM new period and duty load LOAD This bit is used to load period and duty control registers in their buffer if new period or duty value needs to be updated.
  • Page 291 MS51 Name Description PWM clock divider PWMDIV[2:0] This field decides the pre-scale of PWM clock source. 000 = 1/1. 001 = 1/2 010 = 1/4. 011 = 1/8. 100 = 1/16. 101 = 1/32. 110 = 1/64. 111 = 1/128. CKCON –...
  • Page 292 MS51 Name Description PWMP[15:8] PWM period high byte This byte with PWMPL controls the period of the PWM generator signal. PWMnH – PWM Channel 0~5 Duty High Byte n =0,1,2,3,4,5 Register SFR Address Description Reset Value PWM0H D2H, all pages PWM Channel 0 Duty High Byte 0000_0000 b PWM1H...
  • Page 293 MS51 Name Description PWMCn[7:0] PWMCn duty Low byte n=0,1,2,3,4,5 This byte with PWMnCxH controls the duty of the output signal PGx from PWM generator. PIOCON0 – PWM or I/O Select Regiser Address Reset Value PIOCON0 DEH, all pages 0000_0000b PIO05 PIO04 PIO03 PIO02...
  • Page 294 MS51 Name Description P0.5/PWM2 pin function select PIO12 0 = P0.5/PWM2 pin functions as P0.5. 1 = P0.5/PWM2 pin functions as PWM2 output. P1.4/PWM1 pin function select PIO11 0 = P1.4/PWM1 pin functions as P1.4. 1 = P1.4/PWM1 pin functions as PWM1 output. PDTEN –...
  • Page 295 MS51 Regiser Address Reset Value PMEN FBH, all page 0000_0000b PMEN5 PMEN4 PMEN3 PMEN2 PMEN1 PMEN0 Name Description PWMn mask enable PMENn 0 = PWMn signal outputs from its PWM generator. 1 = PWMn signal is masked by PMDn. PMD – PWM Mask Data Regiser Address Reset Value...
  • Page 296 MS51 Regiser Address Reset Value D6H, all pages 0000_0000b PNP5 PNP4 PNP3 PNP2 PNP1 PNP0 Name Description PWMn negative polarity output enable PNPn 0 = PWMn signal outputs directly on PWMn pin. 1 = PWMn signal outputs inversely on PWMn pin. PWMINTC –...

  • Page 297: Figure 6.12-112-Bit Adc Block Diagram

    MS51 6.12 12-Bit Analog-To-Digital Converter (ADC) The MS51 is embedded with a 12-bit SAR ADC. The ADC (analog-to-digital converter) allows conversion of an analog input signal to a 12-bit binary representation of that signal. The MS51 is selected as 8-channel inputs in single end mode. The internal band-gap voltage 0.814 V also can be the internal ADC input.
  • Page 298 MS51 6.12.1 ADC Operation Before ADC operation, the ADC circuit should be enabled by setting ADCEN (ADCCON1.0). This makes ADC circuit active. It consume extra power. Once ADC is not used, clearing ADCEN to turn off ADC circuit saves power. The ADC analog input pin should be specially considered.

  • Page 299: Figure 6.12-2 External Triggering Adc Circuit

    MS51 [00] PWM0_CH0 [01] PWM0_CH2 External ADCDLY PWM0_CH4 Trigger [10] STADC [11] PTRGSEL[1:0] (ADCCON0[5:4]) PTRGTYP[1:0] (ADCCON1[3:2]) Figure 6.12-2 External Triggering ADC Circuit 6.12.3 ADC Conversion Result Comparator The MS51 ADC has a digital comparator, which compares the A/D conversion result with a 12-bit constant value given in ACMPH and ACMPL registers.
  • Page 300 MS51 Formula as following For example: Read the 2 bytes value after the UID address, wherein the first byte value is 0x64, and the second byte value is 0x0E, merged as 0x64E = 1614. The conversion result is as follows: Band-gap as ADC input to calculate the V value: MS51 internal embedded band-gap voltage also can be the internal ADC input.
  • Page 301 MS51 Name Description A/D converting channel select ADCHS[3:0] This filed selects the activating analog input source of ADC. If ADCEN is 0, all inputs are disconnected. 0000 = ADC_CH0. 0001 = ADC_CH1. 0010 = ADC_CH2. 0011 = ADC_CH3. 0100 = ADC_CH4. 0101 = ADC_CH5.
  • Page 302 MS51 ADFBEN ADCMPOP ADCMPEN ADCMPO ADCAQT[2:0] ADCDLY.8 Name Description ADC compare result asserting Fault Brake enable ADFBEN 0 = ADC asserting Fault Brake Disabled. 1 = ADC asserting Fault Brake Enabled. Fault Brake is asserted once its compare result ADCMPO is 1. Meanwhile, PWM channels output Fault Brake data. PWMRUN (PWMCON0.7) will also be automatically cleared by hardware.
  • Page 303 MS51 ADCDLY – ADC Trigger Delay Counter Regiser Address Reset Value ADCDLY E3H, all pages 0000_0000b ADCDLY[7:0] Name Description ADCDLY[7:0] ADC external trigger delay counter low byte This 8-bit field combined with ADCCON2.0 forms a 9-bit counter. This counter inserts a delay after detecting the external trigger.
  • Page 304 MS51 ADCMPH – ADC Compare High Byte Regiser Address Reset Value ADCMPH CFH, page 0 0000_0000b ADCMP[11:4] Name Description ADCMP[11:4] ADC compare high byte The most significant 8 bits of the ADC compare value stores in this register. ADCMPL – ADC Compare Low Byte Regiser Address Reset Value...
  • Page 305 MS51 6.13 Auxiliary Features 6.13.1 Dual DPTRs The original 8051 contains one DPTR (data pointer) only. With single DPTR, it is difficult to move data form one address to another with wasting code size and low performance. The MS51 provides two data pointers.
  • Page 306 MS51 DPH[7:0] Name Description Data pointer high byte DPH[7:0] This is the high byte of 16-bit data pointer. DPH combined with DPL serve as a 16-bit data pointer DPTR to access indirect addressed RAM or Program Memory. DPS (AUXR1.0) bit decides which data pointer, DPTR or DPTR1, is activated.

  • Page 307: Figure 7.1-1 Tssop-20 Package Dimension

    MS51 PACKAGE DIMENSIONS TSSOP 20-pin (4.4 x 6.5 x 0.9 mm) Figure 7.1-1 TSSOP-20 Package Dimension Dec. 17, 2019 Page 307 of 316 Rev 1.01...
  • Page 308 MS51 Dec. 17, 2019 Page 308 of 316 Rev 1.01...

  • Page 309: Figure 7.2-1 Qfn-20 Package Dimension For Ms51Xb9Ae

    MS51 QFN 20-pin (3.0 x 3.0 x 0.8 mm) for MS51XB9AE Figure 7.2-1 QFN-20 Package Dimension for MS51XB9AE Dec. 17, 2019 Page 309 of 316 Rev 1.01...

  • Page 310: Figure 7.3-1 Qfn-20 Package Dimension For Ms51Xb9Be

    MS51 QFN 20-pin (3.0 x 3.0 x 0.6mm) for MS51XB9BE Figure 7.3-1 QFN-20 Package Dimension for MS51XB9BE Dec. 17, 2019 Page 310 of 316 Rev 1.01...

  • Page 311: Table 8.1-1 Instructions That Affect Flag Settings

    MS51 INSTRUCTION SET Instruction Set and Address Mode The MS51 executes all the instructions of the standard 80C51 family fully compatible with MCS-51. However, the timing of each instruction is different for it uses high performance 1T 8051 core. The architecture eliminates redundant bus states and implements parallel execution of fetching, decode, and execution phases.
  • Page 312 MS51 Instruction Set MS51 V.S. Tradition 80C51 Instruction OPCODE Bytes Clock Cycles Speed Ratio A, Rn 28~2F A, direct A, @Ri 26, 27 A, #data ADDC A, Rn 38~3F ADDC A, direct ADDC A, @Ri 36, 37 ADDC A, #data SUBB A, Rn 98~9F SUBB A, direct...
  • Page 313 MS51 MS51 V.S. Tradition 80C51 Instruction OPCODE Bytes Clock Cycles Speed Ratio SWAP A A, Rn E8~EF A, direct A, @Ri E6, E7 A, #data Rn, A F8~FF Rn, direct A8~AF Rn, #data 78~7F direct, A direct, Rn 88~8F direct, direct direct, @Ri 86, 87 direct, #data...

  • Page 314: Table 8.2-1 Instruction Set

    MS51 MS51 V.S. Tradition 80C51 Instruction OPCODE Bytes Clock Cycles Speed Ratio RETI AJMP addr11 01, 21, 41, 61, 81, A1, C1, E1[3] LJMP addr16 SJMP @A+DPTR bit, rel bit, rel bit, rel CJNE A, direct, rel CJNE A, #data, rel CJNE Rn, #data, rel B8~BF...
  • Page 315 MS51 REVISION HISTORY Date Revision Description 2019.01.22 1.00 Initial version. Section 4.1.2 Modified MS51XB9BE pin assignment. Section 6.5 Added SPROM description. 2019.12.17 1.01 Section 19.1.3 Added note in ADC result comparator function description. Section 7.2 Modified all ADC control register to SFR page 0. Dec.
  • Page 316 MS51 Important Notice Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”.

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