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Nuvoton NuMicro ML51 Series Technical Reference Manual

8-bit microcontroller
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ML51/ML54/ML56
1T 8051
8-bit Microcontroller
®
NuMicro
Family
ML51/ML54/ML56 Series
Technical Reference Manual
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
®
Nuvoton is providing this document only for reference purposes of NuMicro
microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
Sep. 01, 2020
Page 1 of 719
Rev 2.00

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Summary of Contents for Nuvoton NuMicro ML51 Series

  • Page 1 ML51/ML54/ML56 Series Technical Reference Manual The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. ® Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system design.

  • Page 2: Table Of Contents

    ML51/ML54/ML56 TABLE OF CONTENTS 1 GENERAL DESCRIPTION ................11 2 FEATURES ....................12 3 PART INFORMATION ................... 17 3.1 ML51/ML54/ML56 Series Package Type ..............17 3.2 ML51/ML54/ML56 Series Selection Guide .............. 18 3.2.1 ML51 Series ........................18 3.2.2 ML54 Series ........................21 3.2.3 ML56 Series ........................
  • Page 3 ML51/ML54/ML56 6.4.1 GPIO Mode ........................361 6.4.2 External Interrupt Pins ....................380 6.4.3 Pin Interrupt (PIT) ......................382 6.5 Timer ..........................389 6.5.1 Overview ........................389 6.5.2 Timer/Counter 0 and 1 ....................389 6.5.3 Timer 2 and Input Capture ..................401 6.5.4 Timer 3 ...........................
  • Page 4 ML51/ML54/ML56 6.11.5 Register Description ..................... 530 6.12 Inter-Integrated Circuit (I C) ................536 6.12.1 Overview ........................536 6.12.2 Features ......................... 536 6.12.3 Functional Description ....................536 6.12.4 I C Time-Out ........................547 6.12.5 I C Interrupt ........................550 6.12.6 Register Description ..................... 550 6.12.7 Typical Structure of I C Interrupt Service Routine ...........
  • Page 5 ML51/ML54/ML56 6.19 Touch Key (TK) ....................667 6.19.1 Overview ........................667 6.19.2 Features ......................... 667 6.19.3 Basic Configuration ...................... 667 6.19.4 Block Diagram ....................... 668 6.19.5 Functional Description ....................669 6.19.6 Register Description ..................... 674 6.20 Instruction Set ...................... 696 6.20.1 Instruction Set And Addressing Modes ..............
  • Page 6 ML51/ML54/ML56 List of Figures Figure 4.1-1 ML51SD1AE Pin Assignment ..................24 Figure 4.1-2 ML54SD1AE / ML56SD1AE Pin Assignment ............25 Figure 4.1-3 ML51LD1AE Pin Assignment ..................26 Figure 4.1-4 ML54LD1AE / ML56LD1AE Pin Assignment ............. 26 Figure 4.1-5 ML54MD1AE / ML56MD1AE Pin Assignment ............27 Figure 4.1-6 ML51TD1AE / ML51TC0AE / ML51TB9AE Pin Assignment ........
  • Page 7 ML51/ML54/ML56 Figure 6.1-4 Internal 256 Bytes RAM Addressing................. 85 Figure 6.1-5 CONFIG0 Any Reset Reloading ................87 Figure 6.1-6 CONFIG2 Power-On Reset Reloading ..............89 Figure 6.2-1 Clock System Block Diagram .................. 292 Figure 6.2-2 Brown-out Detection Block Diagram............... 306 Figure 6.2-3 Boot Selecting Diagram ..................
  • Page 8 ML51/ML54/ML56 Figure 6.10-2 SC Interface Connection ..................504 Figure 6.10-3 SC Data Character ....................506 Figure 6.10-4 Initial Character TS ....................507 Figure 6.10-5 SC Error Signal ..................... 507 Figure 6.10-6 Transmit Direction Block Guard Time Operation ..........508 Figure 6.10-7 Receive Direction Block Guard Time Operation ............ 508 Figure 6.10-8 Extra Guard Time Operation .................
  • Page 9 ML51/ML54/ML56 Figure 6.15-2 Comparator Hysteresis Function ................587 Figure 6.15-3 Comparator Reference Voltage Block Diagram ........... 588 Figure 6.15-4 Analog Comparator Interrupt Sources ..............588 Figure 6.16-1 PDMA Interface Diagram ..................595 Figure 6.16-2 PDMA Controller Block Diagram ................596 Figure 6.16-3 CRC-8 Block Diagram ...................
  • Page 10 ML51/ML54/ML56 List of Tables Table 6.1-1Special Function Register (SFR) Memory Map ............99 Table 6.1-2 SFR Definitions And Reset Values ................111 Table 6.2-1 Power Mode Table ....................301 Table 6.2-2 Entry setting of Power-down mode ................301 Table 6.2-3 BOF Reset Value ...................... 306 Table 6.2-4 Interrupt Vectors .......................

  • Page 11: General Description

    ML51/ML54/ML56 GENERAL DESCRIPTION The ML51/ML54/ML56 Series is a Flash embedded 1T 8051-based microcontroller. The instruction set of the ML51/ML54/ML56 Series is fully compatible with the standard 80C51 with performance enhanced. The ML51/ML54/ML56 Series runs up to 24 MHz. ML51 16KB and 32KB Flash series voltage range from 1.8V to 5.5V.

  • Page 12: Features

    ML51/ML54/ML56 FEATURES Core and System  Fully static design 8-bit high performance 1T 8051-based CMOS microcontroller.  Instruction set fully compatible with MCS-51. 8051  4-priority-level interrupts capability.  Dual Data Pointers (DPTRs).  POR with 1.55V threshold voltage level Power on Reset (POR) ...
  • Page 13 ML51/ML54/ML56 Clocks  4~24 MHz High-speed external crystal oscillator (HXT) for precise timing operation External Clock Source  32.768 kHz High-speed external crystal oscillator (LXT) for RTC operation  Default 24 MHz high-speed internal oscillator (HIRC) trimmed to ±1% (accuracy at 25 °C, 3.3 V), ±2% in -20~105°C. Internal Clock Source ...
  • Page 14 ML51/ML54/ML56  Supports trigger ADC on the following events  Supports real time counter and calendar counter for RTC time and calendar check.  Supports alarm time and calendar settings  Supports alarm time and calendar mask enable settings.  Selectable 12-hour or 24-hour time scale setting.
  • Page 15 ML51/ML54/ML56  2 sets of I C devices  Master/Slave mode  Bidirectional data transfer between masters and slaves  Multi-master bus (no central master)  7-bit addressing mode  Standard mode (100 kbps) and Fast mode (400 kbps).  Supports 8-bit time-out counter requesting the I C interrupt if the I...
  • Page 16 ML51/ML54/ML56  Support 1.8V to 5.5V LCD operating voltage  Supports up to 14 touch keys + reference pad + shielding electrode  Supports any TK pin as reference pad and any one of CLKO pin as shielding electrode.  Programmable sensitivity levels for each channel.

  • Page 17: Part Information

    ML51/ML54/ML56 PART INFORMATION 3.1 ML51/ML54/ML56 Series Package Type Package ML51 ML54 ML56 ML51xB ML51xC ML51xD ML54xD ML56xD MSOP10 ML51BB9AE TSSOP14 ML51DB9AE TSSOP20 ML51FB9AE SOP20 ML51OB9AE QFN20(3x3) ML51XB9AE TSSOP28 ML51EB9AE ML51EC0AE SOP28 ML51UB9AE ML51UC0AE LQFP32 ML51PB9AE ML51PC0AE QFN33(4x4) ML51TB9AE ML51TC0AE ML51TD1AE LQFP44 ML54MD1AE ML56MD1AE...

  • Page 18: Ml51/Ml54/Ml56 Series Selection Guide

    ML51/ML54/ML56 3.2 ML51/ML54/ML56 Series Selection Guide 3.2.1 ML51 Series ML51 16KB Flash Series ML51 Part Number BB9AE DB9AE FB9AE OB9AE XB9AE EB9AE UB9AE PB9AE Flash (KB) SRAM (KB) ISP ROM (KB) SPROM (bytes) System Frequency ( MHz) GPIO 16-bit Timer Analog Comparator Internal Voltage Reference PDMA...
  • Page 19 ML51/ML54/ML56 ML51 32KB Flash Series ML51 Part Number EC0AE UC0AE PC0AE TC0AE TC1AE LC1AE Flash (KB) SRAM (KB) ISP ROM (KB) SPROM (bytes) System Frequency ( MHz) GPIO 16-bit Timer Analog Comparator Internal Voltage Reference PDMA ISO 7816-3 UART 12-bit SAR ADC Package TSSOP28 SOP28...
  • Page 20 ML51/ML54/ML56 ML51 64KB Flash Series ML51 Part Number TD1AE LD1AE SD1AE Flash (KB) SRAM (KB) ISP ROM (KB) SPROM (bytes) System Frequency ( MHz) GPIO 16-bit Timer 6+2+2+2 6+2+2+2 6+2+2+2 Analog Comparator Internal Voltage Reference PDMA ISO 7816-3 UART 12-bit SAR ADC Package QFN33 LQFP48...

  • Page 21: Ml54 Series

    ML51/ML54/ML56 3.2.2 ML54 Series ML54 Part Number MD1AE LD1AE SD1AE Flash (KB) SRAM (KB) ISP ROM (KB) SPROM (bytes) System Frequency ( MHz) GPIO 16-bit Timer 6+2+2+2 6+2+2+2 6+2+2+2 Analog Comparator Internal Voltage Reference PDMA 8x17 8x18 8x28 6x19 6x20 6x30 4x21 4x22...

  • Page 22: Ml56 Series

    ML51/ML54/ML56 3.2.3 ML56 Series ML56 Part Number MD1AE LD1AE SD1AE Flash (KB) SRAM (KB) ISP ROM (KB) SPROM (bytes) System Frequency ( MHz) GPIO 16-bit Timer 6+2+2+2 6+2+2+2 6+2+2+2 Analog Comparator Internal Voltage Reference PDMA 8x17 8x18 8x28 6x19 6x20 6x30 4x21 4x22...

  • Page 23: Ml51/Ml54/Ml56 Series Selection Code

    ML51/ML54/ML56 3.3 ML51/ML54/ML56 Series Selection Code Core Line Package Flash SRAM Reserve Temperature 1T 8051 51: Base B: MSOP10 (3x3 mm) A: 8 KB 0: 2 KB E:-40 ~ 105°C Low power 54: LCD D: TSSOP14 (4.4x5.0 mm) B: 16 KB 1: 4 KB 56: Touch E: TSSOP28 (4.4x9.7 mm)

  • Page 24: Pin Configuration

    Users can find pin configuaration informations in chapter 4 or by using NuTool - PinConfigure. The ® NuTool - PinConfigure contains all Nuvoton NuMicro Family chip series with all part number, and helps users configure GPIO multi-function correctly and handily. 4.1.1 ML51/ML54/ML56 Series Pin Diagram 4.1.1.1...

  • Page 25: Figure 4.1-2 Ml54Sd1Ae / Ml56Sd1Ae Pin Assignment

    ML51/ML54/ML56 ML54SD1AE / ML56SD1AE nRESET P4.6 P5.6 P0.0 P4.7 P0.1 P3.3 P0.2 P3.2 P0.3 P3.1 P0.4 P3.0 P0.5 LQFP64 AVDD P3.6 VREF AVSS P6.7 P0.6 P6.6 P0.7 P6.5 P3.4 P6.4 P3.5 P2.7 P5.2 Figure 4.1-2 ML54SD1AE / ML56SD1AE Pin Assignment Sep.

  • Page 26: Figure 4.1-3 Ml51Ld1Ae Pin Assignment

    ML51/ML54/ML56 4.1.1.2 LQFP48 Package Corresponding Part Number: ML51LD1AE/ ML54LD1AE / ML56LD1AE ML51LD1AE nRESET P4.6 P5.6 P0.0 P4.7 P0.1 P3.3 P0.2 P3.2 P0.3 LQFP48 P3.1 P0.4 P3.0 P0.5 VREF P0.6 AVSS P0.7 P2.7 P5.2 P2.6 P5.3 Figure 4.1-3 ML51LD1AE Pin Assignment ML54LD1AE / ML56LD1AE nRESET P4.6...

  • Page 27: Figure 4.1-5 Ml54Md1Ae / Ml56Md1Ae Pin Assignment

    ML51/ML54/ML56 4.1.1.3 LQFP44 Package Corresponding Part Number: ML54MD1AE / ML56MD1AE ML54MD1AE / ML56MD1AE P5.0 P4.6 nRESET P0.0 P3.3 P0.1 P3.2 P0.2 LQFP44 P3.1 P0.3 P3.0 P0.6 VREF P0.7 AVSS P5.2 P2.7 P5.3 P2.6 P5.4 Figure 4.1-5 ML54MD1AE / ML56MD1AE Pin Assignment 4.1.1.4 QFN33 Package Corresponding Part Number: ML51TD1AE / ML51TC0AE / ML51TB9AE...

  • Page 28: Figure 4.1-7 Ml51Pc0Ae / Ml51Pb9Ae Pin Assignment

    ML51/ML54/ML56 4.1.1.5 LQFP32 Package Corresponding Part Number: ML51PC0AE / ML51PB9AE ML51PC0AE / ML51PB9AE nRESET P4.6 P5.6 P0.0 P3.3 P0.1 LQFP32 P3.2 P0.2 P3.1 P0.3 P3.0 P5.2 P5.3 Figure 4.1-7 ML51PC0AE / ML51PB9AE Pin Assignment 4.1.1.6 TSSOP28 Package Corresponding Part Number: ML51EC0AE / ML51EB9AE ML51EC0AE / ML51EB9AE P4.0 P1.4...

  • Page 29: Figure 4.1-9 Ml51Uc0Ae / Ml51Ub9Ae Pin Assignment

    ML51/ML54/ML56 4.1.1.7 SOP28 Package Corresponding Part Number: ML51UC0AE / ML51UB9AE ML51UC0AE / ML51UB9AE P4.0 P1.4 P4.1 P1.5 P5.1 P1.6 P5.0 P1.7 nRESET P0.0 P4.6 P0.1 P0.2 P3.2 P0.3 P3.1 P5.2 P3.0 P5.3 VREF P2.0 P2.5 P2.1 P2.4 P2.2 P2.3 Figure 4.1-9 ML51UC0AE / ML51UB9AE Pin Assignment 4.1.1.8 TSSOP20 Package Corresponding Part Number: ML51FB9AE...

  • Page 30: Figure 4.1-11 Ml51Ob9Ae Pin Assignment

    ML51/ML54/ML56 4.1.1.9 SOP20 Package Corresponding Part Number: ML51OB9AE ML51OB9AE P5.1 P4.6 P5.0 nRESET P3.2 P0.0 P3.1 P0.1 P3.0 P0.2 VREF P0.3 P2.5 P5.2 P2.4 P5.3 P2.3 P2.2 Figure 4.1-11 ML51OB9AE Pin Assignment 4.1.1.10 QFN20 Package Corresponding Part Number: ML51XB9AE ML51XB9AE 15 14 13 12 11 nRESET P0.0...

  • Page 31: Figure 4.1-13 Ml51Db9Ae Pin Assignment

    ML51/ML54/ML56 4.1.1.11 TSSOP14 Package Corresponding Part Number: ML51DB9AE ML51DB9AE P5.1 P4.6 P5.0 nRESET P3.1 P0.2 TSSOP14 P3.0 P0.3 P2.5 P5.2 P2.4 P5.3 Figure 4.1-13 ML51DB9AE Pin Assignment 4.1.1.12 MSOP10 Package Corresponding Part Number: ML51BB9AE ML51BB9AE P5.0 P5.1 nRESET MSOP10 P0.0 P4.6 P0.1 P2.0...

  • Page 32: Ml51/Ml54/Ml56 Series Multi Function Pin Diagram

    ML51/ML54/ML56 4.1.2 ML51/ML54/ML56 Series Multi Function Pin Diagram 4.1.2.1 LQFP64 Package Corresponding Part Number: ML51SD1AE / ML54SD1AE / ML56SD1AE ML51SD1AE Pin Function nRESET INT0 / CLKO / T0 / PWM0_CH0 / P4.6 P5.6 / PWM0_BRAKE / PWM0_CH1 / CLKO P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / PWM0_CH5 T1 / P4.7 P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / PWM0_CH4 PWM0_BRAKE / IC0 / PWM1_CH0 / SPI1_SS / P3.3...
  • Page 33 ML51/ML54/ML56 Pin ML51SD1AE Pin Function P2.2 / ADC_CH3 / ACMP1_N0 / I2C1_SDA / UART1_RXD / PWM0_CH3 P2.1 / ADC_CH4 / ACMP0_P2 / ACMP1_P2 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM3_CH0 / PWM0_BRAKE P2.0 / ADC_CH5 / ACMP0_N1 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM3_CH1 / PWM0_BRAKE P1.3 / IC0 P1.2 / UART3_TXD / IC1 P1.1 / UART3_RXD / UART1_TXD / IC2...
  • Page 34 ML51/ML54/ML56 Pin ML51SD1AE Pin Function P4.3 / PWM2_CH0 P4.2 / PWM2_CH1 P4.1 / UART2_TXD / I2C0_SCL / PWM3_CH0 / ACMP0_O P4.0 / UART2_RXD / I2C0_SDA / PWM3_CH1 / ACMP1_O / INT1 P6.3 / SPI0_SS / UART0_TXD P6.2 / UART3_TXD / SPI0_CLK / UART0_RXD P6.1 / UART3_RXD / SPI0_MISO P6.0 / SPI0_MOSI P1.4 / I2C1_SCL...

  • Page 35: Figure 4.1-16 Ml54Sd1Ae Multi-Function Pin Assignment

    ML51/ML54/ML56 ML54SD1AE Pin Function nRESET INT0 / CLKO / T0 / PWM0_CH0 / LCD_SEG17 / P4.6 P5.6 / PWM0_BRAKE / PWM0_CH1 / CLKO P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / PWM0_CH5 T1 / LCD_COM0 / LCD_SEG16 / P4.7 P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / PWM0_CH4 PWM0_BRAKE / IC0 / PWM1_CH0 / LCD_COM1 / SPI1_SS / LCD_SEG15 / P3.3 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3...
  • Page 36 ML51/ML54/ML56 Pin ML54SD1AE Pin Function P2.2 / ADC_CH3 / ACMP1_N0 / I2C1_SDA / LCD_COM3 / UART1_RXD / PWM0_CH3 P2.1 / ADC_CH4 / ACMP0_P2 / ACMP1_P2 / LCD_SEG5 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM3_CH0 / PWM0_BRAKE P2.0 / ADC_CH5 / ACMP0_N1 / LCD_SEG4 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM3_CH1 / PWM0_BRAKE P1.3 / IC0 P1.2 / LCD_DH2 / UART3_TXD / IC1...
  • Page 37 ML51/ML54/ML56 Pin ML54SD1AE Pin Function P4.4 / LCD_SEG30 / LCD_COM5 / UART2_RXD / I2C1_SDA / PWM1_CH1 P4.3 / LCD_SEG29 / LCD_COM6 / PWM2_CH0 P4.2 / LCD_SEG28 / LCD_COM7 / PWM2_CH1 P4.1 / LCD_SEG27 / LCD_COM2 / UART2_TXD / I2C0_SCL / PWM3_CH0 / ACMP0_O P4.0 / LCD_SEG26 / LCD_COM3 / UART2_RXD / I2C0_SDA / PWM3_CH1 / ACMP1_O / INT1 P6.3 / LCD_SEG25 / SPI0_SS / UART0_TXD P6.2 / LCD_SEG24 / UART3_TXD / SPI0_CLK / UART0_RXD...

  • Page 38: Figure 4.1-17 Ml56Sd1Ae Multi-Function Pin Assignment

    ML51/ML54/ML56 ML56SD1AE Pin Function nRESET INT0 / CLKO / T0 / PWM0_CH0 / LCD_SEG17 / P4.6 P5.6 / TK0 / PWM0_BRAKE / PWM0_CH1 / CLKO P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / TK1 / PWM0_CH5 T1 / LCD_COM0 / LCD_SEG16 / P4.7 P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / TK2 / PWM0_CH4 PWM0_BRAKE / IC0 / PWM1_CH0 / LCD_COM1 / SPI1_SS / LCD_SEG15 / P3.3 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / TK3 / PWM0_CH3...
  • Page 39 ML51/ML54/ML56 ML56SD1AE Pin Function P2.0/ADC_CH5/ACMP0_N1/LCD_SEG4/UART2_RXD/I2C1_SDA/PWM0_CH5/PWM3_CH1/PWM0_BRAKE P1.3/IC0 P1.2/LCD_DH2/UART3_TXD/IC1 P1.1/LCD_DH1/UART3_RXD/UART1_TXD/IC2 P1.0/UART1_RXD/IC0 VLCD P5.7/PWM0_BRAKE/PWM0_CH4/CLKO P5.5/UART2_RXD/PWM0_CH0/X32_IN/STADC P5.4/UART2_TXD/PWM0_CH1/X32_OUT P5.3/UART0_TXD/I2C0_SCL/XT1_IN P5.2/UART0_RXD/I2C0_SDA/XT1_OUT P3.5/LCD_SEG3/PWM2_CH0/T0 P3.4/LCD_SEG2/PWM2_CH1/T1 P0.7/LCD_SEG1/UART0_TXD/I2C1_SCL/PWM3_CH0/INT1 P0.6/LCD_SEG0/UART0_RXD/I2C1_SDA/PWM3_CH1/INT0 P3.6/TK7/PWM0_CH5/INT1 P0.5/UART0_TXD/I2C0_SCL/TK6/PWM0_CH0 P0.4/UART0_RXD/I2C0_SDA/TK5/PWM0_CH1 P0.3/SPI0_SS/SPI1_SS/UART1_TXD/I2C1_SCL/TK4/STADC/PWM0_CH2/CLKO P0.2/SPI0_CLK/SPI1_CLK/UART1_RXD/I2C1_SDA/TK3/PWM0_CH3 P0.1/SPI0_MISO/SPI1_MISO/UART2_RXD/UART0_TXD/TK2/PWM0_CH4 P0.0/SPI0_MOSI/SPI1_MOSI/UART2_TXD/UART0_RXD/TK1/PWM0_CH5 P5.6/TK0/PWM0_BRAKE/PWM0_CH1/CLKO nRESET P5.0/UART1_TXD/I2C1_SCL/UART0_TXD/ICE_DAT P5.1/UART1_RXD/I2C1_SDA/UART0_RXD/ICE_CLK P4.5/LCD_SEG31/LCD_COM4/UART2_TXD/I2C1_SCL/PWM1_CH0 P4.4/LCD_SEG30/LCD_COM5/UART2_RXD/I2C1_SDA/TK12/PWM1_CH1 P4.3/LCD_SEG29/LCD_COM6/TK13/PWM2_CH0 P4.2/LCD_SEG28/LCD_COM7/TK14/PWM2_CH1 P4.1/LCD_SEG27/LCD_COM2/UART2_TXD/I2C0_SCL/PWM3_CH0/ACMP0_O P4.0/LCD_SEG26/LCD_COM3/UART2_RXD/I2C0_SDA/PWM3_CH1/ACMP1_O/INT1 Sep. 01, 2020 Page 39 of 719 Rev 2.00...
  • Page 40 ML51/ML54/ML56 ML56SD1AE Pin Function P6.3/LCD_SEG25/SPI0_SS/UART0_TXD/TK8 P6.2/LCD_SEG24/UART3_TXD/SPI0_CLK/UART0_RXD/TK9 P6.1/LCD_SEG23/UART3_RXD/SPI0_MISO/TK10 P6.0/LCD_SEG22/SPI0_MOSI/TK11 P1.4/LCD_SEG21/I2C1_SCL/LCD_COM4 P1.5/LCD_SEG20/I2C1_SDA/LCD_COM5 P1.6/LCD_SEG19/UART0_TXD/LCD_COM6 P1.7/LCD_SEG18/UART0_RXD/LCD_COM7 P4.6/LCD_SEG17/PWM0_CH0/T0/CLKO/INT0 P4.7/LCD_SEG16/LCD_COM0/T1 P3.3/LCD_SEG15/SPI1_SS/LCD_COM1/PWM1_CH0/IC0/PWM0_BRAKE P3.2/ADC_CH7/ACMP1_N1/LCD_SEG14/SPI1_CLK/UART3_RXD/PWM1_CH1/IC1/CLKO P3.1/ADC_CH6/ACMP0_P3/ACMP1_P3/LCD_SEG13/SPI1_MISO/UART3_TXD/UART0_TXD/PWM2_CH0/IC2 P3.0/ADC_CH10/LCD_SEG12/SPI1_MOSI/UART0_RXD/PWM2_CH1/IC0 AVSS P6.7/ADC_CH11/LCD_SEG11/I2C1_SCL P6.6/ADC_CH12/LCD_SEG10/LCD_V1/I2C1_SDA P6.5/ADC_CH13/LCD_SEG9/LCD_V2/UART0_TXD P6.4/ADC_CH14/LCD_SEG8/LCD_V3/UART0_RXD P2.7/ADC_CH15/LCD_SEG7/UART1_TXD/PWM3_CH0/ACMP0_O Sep. 01, 2020 Page 40 of 719 Rev 2.00...

  • Page 41: Figure 4.1-18 Ml51Ld1Ae Multi-Function Pin Assignment

    ML51/ML54/ML56 4.1.2.2 LQFP48 Package Corresponding Part Number: ML51LD1AE ML51LD1AE Pin Function nRESET INT0 / CLKO / T0 / PWM0_CH0 / P4.6 P5.6 / PWM0_BRAKE / PWM0_CH1 / CLKO P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / PWM0_CH5 T1 / P4.7 P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / PWM0_CH4 PWM0_BRAKE / IC0 / PWM1_CH0 / SPI1_SS / P3.3 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3...
  • Page 42 ML51/ML54/ML56 Pin ML51LD1AE Pin Function P2.1 / ADC_CH4 / ACMP0_P2 / ACMP1_P2 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM3_CH0 / PWM0_BRAKE P2.0 / ADC_CH5 / ACMP0_N1 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM3_CH1 / PWM0_BRAKE P1.3 / IC0 P1.2 / UART3_TXD / IC1 P1.1 / UART3_RXD / UART1_TXD / IC2 P1.0 / UART1_RXD / IC0...
  • Page 43 ML51/ML54/ML56 Pin ML51LD1AE Pin Function P4.6 / PWM0_CH0 / T0 / CLKO / INT0 P4.7 / T1 P3.3 / SPI1_SS / PWM1_CH0 / IC0 / PWM0_BRAKE P3.2 / ADC_CH7 / ACMP1_N1 / SPI1_CLK / UART3_RXD / PWM1_CH1 / IC1 / CLKO P3.1 / ADC_CH6 / ACMP0_P3 / ACMP1_P3 / SPI1_MISO / UART3_TXD / UART0_TXD / PWM2_CH0 / P3.0 / ADC_CH10 / SPI1_MOSI / UART0_RXD / PWM2_CH1 / IC0 P2.7 / ADC_CH15 / UART1_TXD / PWM3_CH0 / ACMP0_O...

  • Page 44: Figure 4.1-19 Ml54Ld1Ae Multi-Function Pin Assignment

    ML51/ML54/ML56 ML54LD1AE Pin Function nRESET INT0 / CLKO / T0 / PWM0_CH0 / LCD_SEG17 / P4.6 P5.6 / PWM0_BRAKE / PWM0_CH1 / CLKO P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / PWM0_CH5 T1 / LCD_COM0 / LCD_SEG16 / P4.7 P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / PWM0_CH4 PWM0_BRAKE / IC0 / PWM1_CH0 / LCD_COM1 / SPI1_SS / LCD_SEG15 / P3.3 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3...
  • Page 45 ML51/ML54/ML56 Pin ML54LD1AE Pin Function P2.2 / ADC_CH3 / ACMP1_N0 / I2C1_SDA / LCD_COM3 / UART1_RXD / PWM0_CH3 P2.1 / ADC_CH4 / ACMP0_P2 / ACMP1_P2 / LCD_SEG5 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM3_CH0 / PWM0_BRAKE P2.0 / ADC_CH5 / ACMP0_N1 / LCD_SEG4 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM3_CH1 / PWM0_BRAKE P1.3 / IC0 P1.2 / LCD_DH2 / UART3_TXD / IC1...
  • Page 46 ML51/ML54/ML56 Pin ML54LD1AE Pin Function P1.6 / LCD_SEG19 / UART0_TXD / LCD_COM6 P1.7 / LCD_SEG18 / UART0_RXD / LCD_COM7 P4.6 / LCD_SEG17 / PWM0_CH0 / T0 / CLKO / INT0 P4.7 / LCD_SEG16 / LCD_COM0 / T1 P3.3 / LCD_SEG15 / SPI1_SS / LCD_COM1 / PWM1_CH0 / IC0 / PWM0_BRAKE P3.2 / ADC_CH7 / ACMP1_N1 / LCD_SEG14 / SPI1_CLK / UART3_RXD / PWM1_CH1 / IC1 / CLKO P3.1 / ADC_CH6 / ACMP0_P3 / ACMP1_P3 / LCD_SEG13 / SPI1_MISO / UART3_TXD / UART0_TXD / PWM2_CH0 / IC2...

  • Page 47: Figure 4.1-20 Ml56Ld1Ae Multi-Function Pin Assignment

    ML51/ML54/ML56 ML56LD1AE Pin Function nRESET INT0 / CLKO / T0 / PWM0_CH0 / LCD_SEG17 / P4.6 P5.6 / TK0 / PWM0_BRAKE / PWM0_CH1 / CLKO P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / TK1 / PWM0_CH5 T1 / LCD_COM0 / LCD_SEG16 / P4.7 P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / TK2 / PWM0_CH4 PWM0_BRAKE / IC0 / PWM1_CH0 / LCD_COM1 / SPI1_SS / LCD_SEG15 / P3.3 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / TK3 / PWM0_CH3...
  • Page 48 ML51/ML54/ML56 ML56LD1AE/ML56LC1AE Pin Function P2.0/ADC_CH5/ACMP0_N1/LCD_SEG4/UART2_RXD/I2C1_SDA/PWM0_CH5/PWM3_CH1/PWM0_BRAKE P1.3/IC0 P1.2/LCD_DH2/UART3_TXD/IC1 P1.1/LCD_DH1/UART3_RXD/UART1_TXD/IC2 VLCD P5.5/UART2_RXD/PWM0_CH0/X32_IN/STADC P5.4/UART2_TXD/PWM0_CH1/X32_OUT P5.3/UART0_TXD/I2C0_SCL/XT1_IN P5.2/UART0_RXD/I2C0_SDA/XT1_OUT P0.7/LCD_SEG1/UART0_TXD/I2C1_SCL/PWM3_CH0/INT1 P0.6/LCD_SEG0/UART0_RXD/I2C1_SDA/PWM3_CH1/INT0 P0.5/UART0_TXD/I2C0_SCL/TK6/PWM0_CH0 P0.4/UART0_RXD/I2C0_SDA/TK5/PWM0_CH1 P0.3/SPI0_SS/SPI1_SS/UART1_TXD/I2C1_SCL/TK4/STADC/PWM0_CH2/CLKO P0.2/SPI0_CLK/SPI1_CLK/UART1_RXD/I2C1_SDA/TK3/PWM0_CH3 P0.1/SPI0_MISO/SPI1_MISO/UART2_RXD/UART0_TXD/TK2/PWM0_CH4 P0.0/SPI0_MOSI/SPI1_MOSI/UART2_TXD/UART0_RXD/TK1/PWM0_CH5 P5.6/TK0/PWM0_BRAKE/PWM0_CH1/CLKO nRESET P5.0/UART1_TXD/I2C1_SCL/UART0_TXD/ICE_DAT P5.1/UART1_RXD/I2C1_SDA/UART0_RXD/ICE_CLK P4.5/LCD_SEG31/LCD_COM4/UART2_TXD/I2C1_SCL/PWM1_CH0 P4.4/LCD_SEG30/LCD_COM5/UART2_RXD/I2C1_SDA/TK12/PWM1_CH1 P4.3/LCD_SEG29/LCD_COM6/TK13/PWM2_CH0 P4.2/LCD_SEG28/LCD_COM7/TK14/PWM2_CH1 P4.1/LCD_SEG27/LCD_COM2/UART2_TXD/I2C0_SCL/PWM3_CH0/ACMP0_O P4.0/LCD_SEG26/LCD_COM3/UART2_RXD/I2C0_SDA/PWM3_CH1/ACMP1_O/INT1 P1.4/LCD_SEG21/I2C1_SCL/LCD_COM4 P1.5/LCD_SEG20/I2C1_SDA/LCD_COM5 P1.6/LCD_SEG19/UART0_TXD/LCD_COM6 P1.7/LCD_SEG18/UART0_RXD/LCD_COM7 P4.6/LCD_SEG17/PWM0_CH0/T0/CLKO/INT0 Sep. 01, 2020 Page 48 of 719 Rev 2.00...
  • Page 49 ML51/ML54/ML56 ML56LD1AE/ML56LC1AE Pin Function P4.7/LCD_SEG16/LCD_COM0/T1 P3.3/LCD_SEG15/SPI1_SS/LCD_COM1/PWM1_CH0/IC0/PWM0_BRAKE P3.2/ADC_CH7/ACMP1_N1/LCD_SEG14/SPI1_CLK/UART3_RXD/PWM1_CH1/IC1/CLKO P3.1/ADC_CH6/ACMP0_P3/ACMP1_P3/LCD_SEG13/SPI1_MISO/UART3_TXD/UART0_TXD/PWM2_CH0/IC2 P3.0/ADC_CH10/LCD_SEG12/SPI1_MOSI/UART0_RXD/PWM2_CH1/IC0 AVSS P2.7/ADC_CH15/LCD_SEG7/UART1_TXD/PWM3_CH0/ACMP0_O P2.6/LCD_SEG6/UART1_RXD/PWM3_CH1/ACMP1_O Sep. 01, 2020 Page 49 of 719 Rev 2.00...

  • Page 50: Figure 4.1-21 Ml54Md1Ae Multi-Function Pin Assignment

    ML51/ML54/ML56 4.1.2.3 LQFP44 Package ML54MD1AE Pin Function P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT INT0 / CLKO / T0 / PWM0_CH0 / LCD_SEG17 / P4.6 nRESET P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / TK1 / PWM0_CH5 PWM0_BRAKE / IC0 / PWM1_CH0 / LCD_COM1 / SPI1_SS / LCD_SEG15 / P3.3 P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / TK2 / PWM0_CH4 CLKO / IC1 / PWM1_CH1 / UART3_RXD / SPI1_CLK / LCD_SEG14 / ACMP1_N1 / ADC_CH7 / P3.2...
  • Page 51 ML51/ML54/ML56 Pin ML54MD1AE Pin Function P2.2 / ADC_CH3 / ACMP1_N0 / I2C1_SDA / LCD_COM3 / UART1_RXD / PWM0_CH3 P2.1 / ADC_CH4 / ACMP0_P2 / ACMP1_P2 / LCD_SEG5 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM3_CH0 / PWM0_BRAKE P2.0 / ADC_CH5 / ACMP0_N1 / LCD_SEG4 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM3_CH1 / PWM0_BRAKE P1.3 / IC0 P1.2 / LCD_DH2 / UART3_TXD / IC1...
  • Page 52 ML51/ML54/ML56 Pin ML54MD1AE Pin Function P4.6 / LCD_SEG17 / PWM0_CH0 / T0 / CLKO / INT0 P3.3 / LCD_SEG15 / SPI1_SS / LCD_COM1 / PWM1_CH0 / IC0 / PWM0_BRAKE P3.2 / ADC_CH7 / ACMP1_N1 / LCD_SEG14 / SPI1_CLK / UART3_RXD / PWM1_CH1 / IC1 / CLKO P3.1 / ADC_CH6 / ACMP0_P3 / ACMP1_P3 / LCD_SEG13 / SPI1_MISO / UART3_TXD / UART0_TXD / PWM2_CH0 / IC2 P3.0 / ADC_CH10 / LCD_SEG12 / SPI1_MOSI / UART0_RXD / PWM2_CH1 / IC0...

  • Page 53: Figure 4.1-22 Ml56Md1Ae Multi-Function Pin Assignment

    ML51/ML54/ML56 ML56MD1AE Pin Function P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT INT0 / CLKO / T0 / PWM0_CH0 / LCD_SEG17 / P4.6 nRESET P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / TK1 / PWM0_CH5 PWM0_BRAKE / IC0 / PWM1_CH0 / LCD_COM1 / SPI1_SS / LCD_SEG15 / P3.3 P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / TK2 / PWM0_CH4 CLKO / IC1 / PWM1_CH1 / UART3_RXD / SPI1_CLK / LCD_SEG14 / ACMP1_N1 / ADC_CH7 / P3.2 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / TK3 / PWM0_CH3...
  • Page 54 ML51/ML54/ML56 ML56MD1AE Pin Function P2.0/ADC_CH5/ACMP0_N1/LCD_SEG4/UART2_RXD/I2C1_SDA/PWM0_CH5/PWM3_CH1/PWM0_BRAKE P1.3/IC0 P1.2/LCD_DH2/UART3_TXD/IC1 P1.1/LCD_DH1/UART3_RXD/UART1_TXD/IC2 VLCD P5.5/UART2_RXD/PWM0_CH0/X32_IN/STADC P5.4/UART2_TXD/PWM0_CH1/X32_OUT P5.3/UART0_TXD/I2C0_SCL/XT1_IN P5.2/UART0_RXD/I2C0_SDA/XT1_OUT P0.7/LCD_SEG1/UART0_TXD/I2C1_SCL/PWM3_CH0/INT1 P0.6/LCD_SEG0/UART0_RXD/I2C1_SDA/PWM3_CH1/INT0 P0.3/SPI0_SS/SPI1_SS/UART1_TXD/I2C1_SCL/TK4/STADC/PWM0_CH2/CLKO P0.2/SPI0_CLK/SPI1_CLK/UART1_RXD/I2C1_SDA/TK3/PWM0_CH3 P0.1/SPI0_MISO/SPI1_MISO/UART2_RXD/UART0_TXD/TK2/PWM0_CH4 P0.0/SPI0_MOSI/SPI1_MOSI/UART2_TXD/UART0_RXD/TK1/PWM0_CH5 nRESET P5.0/UART1_TXD/I2C1_SCL/UART0_TXD/ICE_DAT P5.1/UART1_RXD/I2C1_SDA/UART0_RXD/ICE_CLK P4.5/LCD_SEG31/LCD_COM4/UART2_TXD/I2C1_SCL/PWM1_CH0 P4.4/LCD_SEG30/LCD_COM5/UART2_RXD/I2C1_SDA/TK12/PWM1_CH1 P4.3/LCD_SEG29/LCD_COM6/TK13/PWM2_CH0 P4.2/LCD_SEG28/LCD_COM7/TK14/PWM2_CH1 P4.1/LCD_SEG27/LCD_COM2/UART2_TXD/I2C0_SCL/PWM3_CH0/ACMP0_O P4.0/LCD_SEG26/LCD_COM3/UART2_RXD/I2C0_SDA/PWM3_CH1/ACMP1_O/INT1 P1.4/LCD_SEG21/I2C1_SCL/LCD_COM4 P1.5/LCD_SEG20/I2C1_SDA/LCD_COM5 P1.6/LCD_SEG19/UART0_TXD/LCD_COM6 P1.7/LCD_SEG18/UART0_RXD/LCD_COM7 P4.6/LCD_SEG17/PWM0_CH0/T0/CLKO/INT0 P3.3/LCD_SEG15/SPI1_SS/LCD_COM1/PWM1_CH0/IC0/PWM0_BRAKE P3.2/ADC_CH7/ACMP1_N1/LCD_SEG14/SPI1_CLK/UART3_RXD/PWM1_CH1/IC1/CLKO P3.1/ADC_CH6/ACMP0_P3/ACMP1_P3/LCD_SEG13/SPI1_MISO/UART3_TXD/UART0_TXD/PWM2_CH0/IC2 Sep. 01, 2020 Page 54 of 719 Rev 2.00...
  • Page 55 ML51/ML54/ML56 ML56MD1AE Pin Function P3.0/ADC_CH10/LCD_SEG12/SPI1_MOSI/UART0_RXD/PWM2_CH1/IC0 AVSS P2.7/ADC_CH15/LCD_SEG7/UART1_TXD/PWM3_CH0/ACMP0_O P2.6/LCD_SEG6/UART1_RXD/PWM3_CH1/ACMP1_O Sep. 01, 2020 Page 55 of 719 Rev 2.00...

  • Page 56: Figure 4.1-23 Ml51Td1Ae Multi-Function Pin Assignment

    ML51/ML54/ML56 4.1.2.4 QFN33 Package ML51TD1AE Pin Function nRESET Top transparent view INT0 / CLKO / T0 / PWM0_CH0 / P4.6 P5.6 / PWM0_BRAKE / PWM0_CH1 / CLKO P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / PWM0_CH5 PWM0_BRAKE / IC0 / PWM1_CH0 / SPI1_SS / P3.3 P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / PWM0_CH4 QFN33 CLKO / IC1 / PWM1_CH1 / UART3_RXD / SPI1_CLK / ACMP1_N1 / ADC_CH7 / P3.2...
  • Page 57 ML51/ML54/ML56 ML56TD1AE Pin Function P5.5/UART2_RXD/PWM0_CH0/X32_IN/STADC P5.4/UART2_TXD/PWM0_CH1/X32_OUT P5.3/UART0_TXD/I2C0_SCL/XT1_IN P5.2/UART0_RXD/I2C0_SDA/XT1_OUT P0.3/SPI0_SS/SPI1_SS/UART1_TXD/I2C1_SCL/TK4/STADC/PWM0_CH2/CLKO P0.2/SPI0_CLK/SPI1_CLK/UART1_RXD/I2C1_SDA/TK3/PWM0_CH3 P0.1/SPI0_MISO/SPI1_MISO/UART2_RXD/UART0_TXD/TK2/PWM0_CH4 P0.0/SPI0_MOSI/SPI1_MOSI/UART2_TXD/UART0_RXD/TK1/PWM0_CH5 P5.6/TK0/PWM0_BRAKE/PWM0_CH1/CLKO nRESET P5.0/UART1_TXD/I2C1_SCL/UART0_TXD/ICE_DAT P5.1/UART1_RXD/I2C1_SDA/UART0_RXD/ICE_CLK P4.1/LCD_SEG27/LCD_COM2/UART2_TXD/I2C0_SCL/PWM3_CH0/ACMP0_O P4.0/LCD_SEG26/LCD_COM3/UART2_RXD/I2C0_SDA/PWM3_CH1/ACMP1_O/INT1 P1.4/LCD_SEG21/I2C1_SCL/LCD_COM4 P1.5/LCD_SEG20/I2C1_SDA/LCD_COM5 P1.6/LCD_SEG19/UART0_TXD/LCD_COM6 P1.7/LCD_SEG18/UART0_RXD/LCD_COM7 P4.6/LCD_SEG17/PWM0_CH0/T0/CLKO/INT0 P3.3/LCD_SEG15/SPI1_SS/LCD_COM1/PWM1_CH0/IC0/PWM0_BRAKE P3.2/ADC_CH7/ACMP1_N1/LCD_SEG14/SPI1_CLK/UART3_RXD/PWM1_CH1/IC1/CLKO P3.1/ADC_CH6/ACMP0_P3/ACMP1_P3/LCD_SEG13/SPI1_MISO/UART3_TXD/UART0_TXD/PWM2_CH0/IC2 P3.0/ADC_CH10/LCD_SEG12/SPI1_MOSI/UART0_RXD/PWM2_CH1/IC0 Sep. 01, 2020 Page 57 of 719 Rev 2.00...

  • Page 58: Figure 4.1-24 Ml51Tc0Ae / Ml51Tb9Ae Multi-Function Pin Assignment

    ML51/ML54/ML56 ML51TC0AE / ML51TB9AE Pin Function nRESET Top transparent view INT0 / CLKO / T0 / PWM0_CH0 / P4.6 P5.6 / PWM0_BRAKE / PWM0_CH1 / CLKO P0.0 / SPI0_MOSI / SPI1_MOSI / UART0_RXD / PWM0_CH5 PWM0_BRAKE / IC0 / SPI1_SS / P3.3 P0.1 / SPI0_MISO / SPI1_MISO / UART0_TXD / PWM0_CH4 QFN33 CLKO / IC1 / SPI1_CLK / ACMP1_N1 / ADC_CH7 / P3.2...
  • Page 59 ML51/ML54/ML56 Pin ML51TC0AE / ML51TB9AE Pin Function P2.0 / ADC_CH5 / ACMP0_N1 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM0_BRAKE P5.5 / UART2_RXD / PWM0_CH0 / X32_IN / STADC P5.4 / UART2_TXD / PWM0_CH1 / X32_OUT P5.3 / UART0_TXD / I2C0_SCL / XT1_IN P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3...

  • Page 60: Figure 4.1-25 Ml51Pc0Ae / Ml51Pb9Ae Multi-Function Pin Assignment

    ML51/ML54/ML56 4.1.2.5 LQFP32 Package ML51PC0AE / ML51PB9AE Pin Function nRESET INT0 / CLKO / T0 / PWM0_CH0 / P4.6 P5.6 / PWM0_BRAKE / PWM0_CH1 / CLKO P0.0 / SPI0_MOSI / SPI1_MOSI / UART0_RXD / PWM0_CH5 PWM0_BRAKE / IC0 / SPI1_SS / P3.3 P0.1 / SPI0_MISO / SPI1_MISO / UART0_TXD / PWM0_CH4 LQFP32 CLKO / IC1 / SPI1_CLK / ACMP1_N1 / ADC_CH7 / P3.2...
  • Page 61 ML51/ML54/ML56 Pin ML51PC0AE Pin Function P2.1 / ADC_CH4 / ACMP0_P2 / ACMP1_P2 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM0_BRAKE P2.0 / ADC_CH5 / ACMP0_N1 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM0_BRAKE P5.5 / UART2_RXD / PWM0_CH0 / X32_IN / STADC P5.4 / UART2_TXD / PWM0_CH1 / X32_OUT P5.3 / UART0_TXD / I2C0_SCL / XT1_IN P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT...

  • Page 62: Figure 4.1-26 Ml51Ec0Ae / Ml51Eb9Ae Multi-Function Pin Assignment

    ML51/ML54/ML56 4.1.2.6 TSSOP28 Package ML51EC0AE / ML51EB9AE Pin Function I2C1_SCL / P1.4 P4.0 / UART2_RXD / I2C0_SDA / ACMP1_O / INT1 I2C1_SDA / P1.5 P4.1 / UART2_TXD / I2C0_SCL / ACMP0_O UART0_TXD / P1.6 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK UART0_RXD / P1.7 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT nRESET...
  • Page 63 ML51/ML54/ML56 Pin ML51EC0AE / ML51EB9AE Pin Function P0.1 / SPI0_MISO / SPI1_MISO / UART0_TXD / PWM0_CH4 P0.0 / SPI0_MOSI / SPI1_MOSI / UART0_RXD / PWM0_CH5 nRESET P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK P4.1 / UART2_TXD / I2C0_SCL / ACMP0_O P4.0 / UART2_RXD / I2C0_SDA / ACMP1_O / INT1 Sep.

  • Page 64: Figure 4.1-27 Ml51Uc0Ae / Ml51Ub9Ae Multi Function Pin Assignment

    ML51/ML54/ML56 4.1.2.7 SOP28 Package Corresponding Part Number: ML51UC0AE / ML51UB9AE I2C1_SCL / P1.4 P4.0 / UART2_RXD / I2C0_SDA / ACMP1_O / INT1 I2C1_SDA / P1.5 P4.1 / UART2_TXD / I2C0_SCL / ACMP0_O UART0_TXD / P1.6 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK UART0_RXD / P1.7 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT nRESET...
  • Page 65 ML51/ML54/ML56 Pin ML51UC0AE / ML51UB9AE Pin Function P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 P0.1 / SPI0_MISO / SPI1_MISO / UART0_TXD / PWM0_CH4 P0.0 / SPI0_MOSI / SPI1_MOSI / UART0_RXD / PWM0_CH5 nRESET P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK P4.1 / UART2_TXD / I2C0_SCL / ACMP0_O P4.0 / UART2_RXD / I2C0_SDA / ACMP1_O / INT1...

  • Page 66: Figure 4.1-28 Ml51Fb9Ae Multi Function Pin Assignment

    ML51/ML54/ML56 4.1.2.8 TSSOP20 Package ML51FB9AE Pin Function P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK INT0 / CLKO / T0 / PWM0_CH0 / P4.6 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT nRESET CLKO / IC1 / SPI1_CLK / ACMP1_N1 / ADC_CH7 / P3.2 P0.0 / SPI1_MOSI / UART0_RXD / PWM0_CH5 IC2 / UART0_TXD / SPI1_MISO / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1 P0.1 / SPI1_MISO / UART0_TXD / PWM0_CH4...

  • Page 67: Figure 4.1-29 Ml51Ob9Ae Multi Function Pin Assignment

    ML51/ML54/ML56 4.1.2.9 SOP20 Package ML51OB9AE Pin Function P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK INT0 / CLKO / T0 / PWM0_CH0 / P4.6 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT nRESET CLKO / IC1 / SPI1_CLK / ACMP1_N1 / ADC_CH7 / P3.2 P0.0 / SPI1_MOSI / UART0_RXD / PWM0_CH5 IC2 / UART0_TXD / SPI1_MISO / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1 P0.1 / SPI1_MISO / UART0_TXD / PWM0_CH4...

  • Page 68: Figure 4.1-30 Ml51Xb9Ae Multi Function Pin Assignment

    ML51/ML54/ML56 4.1.2.10 QFN20 Package ML51XB9AE Pin Function Top transparent view nRESET INT0 / CLKO / T0 / PWM0_CH0 / P4.6 P0.0 / SPI1_MOSI / UART0_RXD / PWM0_CH5 P0.1 / SPI1_MISO / UART0_TXD / PWM0_CH4 IC2 / UART0_TXD / SPI1_MISO / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1 P0.2 / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 IC0 / UART0_RXD / SPI1_MOSI / P3.0 P0.3 / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2...
  • Page 69 ML51/ML54/ML56 Pin ML51XB9AE Pin Function P0.0 / SPI1_MOSI / UART0_RXD / PWM0_CH5 nRESET P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK P4.1 / UART2_TXD / I2C0_SCL / ACMP0_O P4.0 / UART2_RXD / I2C0_SDA / ACMP1_O / INT1 P1.7 / UART0_RXD P4.6 / PWM0_CH0 / T0 / CLKO / INT0 P3.1 / ADC_CH6 / ACMP0_P3 / ACMP1_P3 / SPI1_MISO / UART0_TXD / IC2...

  • Page 70: Figure 4.1-31 Ml51Db9Ae Multi Function Pin Assignment

    ML51/ML54/ML56 4.1.2.11 TSSOP14 Package ML51DB9AE Pin Function P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK INT0 / CLKO / T0 / PWM0_CH0 / P4.6 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT nRESET IC2 / UART0_TXD / SPI1_MISO / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1 P0.2 / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 IC0 / UART0_RXD / SPI1_MOSI / P3.0 P0.3 / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2...

  • Page 71: Figure 4.1-32 Ml51Bb9Ae Pin Assignment

    ML51/ML54/ML56 4.1.2.12 MSOP10 Package ML51BB9AE Pin Function ICE_CLK / UART0_RXD / I2C1_SDA / UART1_RXD / P5.1 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT nRESET INT0 / CLKO / T0 / PWM0_CH0 / P4.6 P0.0 / SPI1_MOSI / UART0_RXD / PWM0_CH5 P0.1 / SPI1_MISO / UART0_TXD / PWM0_CH4 PWM0_BRAKE / PWM0_CH2 / UART1_TXD / I2C1_SCL / ADC_CH2 / P2.3 P2.0 / ADC_CH5 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM0_BRAKE...

  • Page 72: Pin Description

    ML51/ML54/ML56 4.2 Pin Description 4.2.1 ML51/ML54/ML56 Series Pin Mapping ML54/ML56 ML51 Pin Number 33/32 QFN20 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 P1.3 P1.2 P1.1 P1.0 VLCD P3.7 P5.7 P5.5 P5.4 P5.3 P5.2 P3.5 P3.4 P0.7 P0.6 P3.6 P0.5 P0.4 P0.3 P0.2 P0.1...
  • Page 73 ML51/ML54/ML56 ML54/ML56 ML51 Pin Number 33/32 QFN20 P5.0 P5.1 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 P6.3 P6.2 P6.1 P6.0 P1.4 P1.5 P1.6 P1.7 P4.6 P4.7 P3.3 P3.2 P3.1 P3.0 AVSS P6.7 P6.6 P6.5 P6.4 P2.7 Sep. 01, 2020 Page 73 of 719 Rev 2.00...

  • Page 74: Ml51/Ml54/Ml56 Series Pin Functional Description

    ML51/ML54/ML56 4.2.2 ML51/ML54/ML56 Series Pin Functional Description As default all GPIO type is defined as input mode. User should setting the GPIO Mode by PxMx register. A: Analog suggest disable digial function O: output, I: input, I/O: bi-direction (Quasi) Group Pin Name Type Description...
  • Page 75 ML51/ML54/ML56 Group Pin Name Type Description I2C0_SDA I2C0 data input/output pin. I2C1_SCL I2C1 clock pin. I2C1 I2C1_SDA I2C1 data input/output pin. Input Capture channel 0 Input Capture channel 1 Input Capture channel 2 Serial wired debugger clock pin. ICE_CLK Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin Serial wired debugger data pin.
  • Page 76 ML51/ML54/ML56 Group Pin Name Type Description LCD_SEG12 LCD segment 12 output LCD_SEG13 LCD segment 13 output LCD_SEG14 LCD segment 14 output LCD_SEG15 LCD segment 15 output LCD_SEG16 LCD segment 16 output LCD_SEG17 LCD segment 17 output LCD_SEG18 LCD segment 18 output LCD_SEG19 LCD segment 19 output LCD_SEG20...
  • Page 77 ML51/ML54/ML56 Group Pin Name Type Description PWM2_CH0 PWM2 channel 0 output/capture input. PWM2 PWM2_CH1 PWM2 channel 1 output/capture input. PWM3_CH0 PWM3 channel 0 output/capture input. PWM3 PWM3_CH1 PWM3 channel 1 output/capture input. SPI0_CLK SPI0 serial clock pin. SPI0_MISO SPI0 MISO (Master In, Slave Out) pin. SPI0 SPI0_MOSI SPI0 MOSI (Master Out, Slave In) pin.
  • Page 78 ML51/ML54/ML56 Group Pin Name Type Description UART2_TXD UART2 data transmitter output pin. UART3_RXD UART3 data receiver input pin. UART3 UART3_TXD UART3 data transmitter output pin. ADC reference voltage input. Note: This pin needs to be connected with a 1uF capacitor when use internal voltage reference output.

  • Page 79: Block Diagram

    ML51/ML54/ML56 BLOCK DIAGRAM 5.1 ML51/ML54/ML56 Series Full Function Block Power 1T High POR / LVR / BOD Performance Management 8051 Core Memory Max. 64KB Timer 0/1 APROM Flash Access Timer 2 with ICAP0~2 Max. 4KB Input Capture LDROM Flash Timer 3 Digital Max.

  • Page 80: Functional Description

    ML51/ML54/ML56 FUNCTIONAL DESCRIPTION 6.1 Memory Organization A standard 80C51 based microcontroller divides the memory into two different sections, Program Memory and Data Memory. The Program Memory is used to store the instruction codes, whereas the Data Memory is used to store data or variations during the program execution. The Data Memory occupies a separate address space from Program Memory.

  • Page 81: Figure 6.1-1 Ml51/Ml54/Ml56 Series Program Memory Map

    ML51/ML54/ML56 CONFIG1 LDSIZE[2:0] Factory default value: 1111 1111b Name Description [2:0] LDSIZE[2:0] LDROM Size Select Flash size is 64KB: 111 = No LDROM. APROM is 64 Kbytes. 110 = LDROM is 1 Kbytes. APROM is 63 Kbytes. 101 = LDROM is 2 Kbytes. APROM is 62 Kbytes. 100 = LDROM is 3 Kbytes.

  • Page 82: Security Protection Memory (Sprom)

    ML51/ML54/ML56 6.1.2 Security Protection Memory (SPROM) The security protection memory (SPROM) is used to store instructions for security application. The SPROM includes 128 bytes at location address FF80H ~ FFFFH and doesn’t support “whole chip erase command”. Figure 6.1-2 SPROM Memory Mapping And SPROM Security Mode shows that the last byte of SPROM (address: FFFFH) is used to identify the SPROM code is non-secured or secured mode.

  • Page 83: 96-Bit Unique Code (Uid)

    ML51/ML54/ML56 6.1.3 96-Bit Unique Code (UID) Before shipping out, each ML51/ML54/ML56 Series chip was factory pre-programmed with a 96-bit width serial number, which is guaranteed to be unique for each piece of ML51/ML54/ML56 Series. The serial number is called Unique Code or UID. The user can read the Unique Code only by IAP command.

  • Page 84: Data Memory

    ML51/ML54/ML56 6.1.5 Data Memory 6.1.5.1 Internal data memory 0FFFH Upper 128 Bytes 07FFH internal RAM 03FFH (direct addressing) (indirect addressing) Lower 128 Bytes internal RAM 4 KByte XRAM (direct or indirect (MOVX addressing) addressing) 0000H Figure 6.1-3 Data Memory Map Figure 6.1-3 Data Memory Map shows the internal Data Memory spaces available on ML51/ML54/ML56 Series.

  • Page 85: Figure 6.1-4 Internal 256 Bytes Ram Addressing

    ML51/ML54/ML56 Indirect Accessing RAM Direct or Indirect Accessing RAM Bit-addressable Register Bank 3 Register Bank 2 General Purpose General Purpose Registers Registers Register Bank 1 Register Bank 0 Figure 6.1-4 Internal 256 Bytes RAM Addressing 6.1.5.2 On-Chip XRAM The ML51/ML54/ML56 Series provides additional on-chip 4 Kbytes auxiliary RAM called XRAM to enlarge the RAM space.

  • Page 86: Config Bytes

    ML51/ML54/ML56 MOV DPTR,#0023H ;read from XRAM with address @0023H MOVX A,@DPTR C51: unsigned char temp; //define data variable unsigned char xdata xtemp _at_ 0x23; //define variable at xdata 0x23; xtemp = 0x5B; //write #5BH to XRAM with address @0023H xtemp++; temp = xtemp;...

  • Page 87: Figure 6.1-5 Config0 Any Reset Reloading

    ML51/ML54/ML56 CONFIG0 FSYS OCDPWM OCDEN LOCK Factory default value: 1111 1111b Name Description CONFIG Boot Select This bit defines from which block that MCU re-boots after resets except software reset. 1 = MCU will re-boot from APROM after resets except software reset. 0 = MCU will re-boot from LDROM after resets except software reset.
  • Page 88 ML51/ML54/ML56 CONFIG1 LDSIZE[2:0] Factory default value: 1111 1111b Name Description LDSIZE[2:0] LDROM Size Select [2:0] Flash size is 64KB: 111 = No LDROM. APROM is 64 Kbytes. 110 = LDROM is 1 Kbytes. APROM is 63 Kbytes. 101 = LDROM is 2 Kbytes. APROM is 62 Kbytes. 100 = LDROM is 3 Kbytes.

  • Page 89: Figure 6.1-6 Config2 Power-On Reset Reloading

    ML51/ML54/ML56 CONFIG2 CBODEN CBOV[2:0] BOIAP CBORST Factory default value: 1111 1111b Name Description CBODEN CONFIG Brown-Out Detect Enable 1 = Brown-out detection circuit OFF. 0 = Brown-out detection circuit ON. [6:4] CBOV[2:0] CONFIG Brown-Out Voltage Select 111 = V is 1.8V. 110 = V is 1.8V.
  • Page 90 ML51/ML54/ML56 CONFIG4 WDTEN[3:0] Factory default value: 1111 1111b Name Description WDTEN[3:0] WDT Enable [7:4] This field configures the WDT behavior after MCU execution. 1111 = WDT is Disabled. WDT can be used as a general purpose timer via software control. 0101 = WDT is Enabled as a time-out reset timer and it stops running during Idle or Power-down mode.

  • Page 91: Special Function Register (Sfr)

    ML51/ML54/ML56 6.1.7 Special Function Register (SFR) The ML51/ML54/ML56 Series uses Special Function Registers (SFR) to control and monitor peripherals and their modes. The SFR reside in the register locations 80 to FFH and are accessed by direct addressing only. SFR those end their addresses as 0H or 8H are bit-addressable. It is very useful in cases where user would like to modify a particular bit directly without changing other bits via bit-field instructions.
  • Page 92 ML51/ML54/ML56 SFRS – SFR Page Selection Register SFR Address Reset Value SFRS 91H, All pages 0000_0000b SFRPAGE[1:0] Name Description [1:0] SFRPAGE[1:0] SFR Page Select 00 = Instructions access SFR Page 0. 01 = Instructions access SFR Page 1. 10 = Instructions access SFR page 2. 11 = Instructions access SFR page 3.
  • Page 93 ML51/ML54/ML56 TA – Timed Access Register SFR Address Reset Value C7H, All pages 0000_0000 b TA[7:0] Name Description [7:0] TA[7:0] Timed Access The timed access register controls the access to protected SFR. To access protected bits, user should first write AAH to the TA and immediately followed by a write of 55H to TA. After these two steps, a writing permission window is opened for 4 clock cycles during this period that user may write to protected SFR.
  • Page 94 ML51/ML54/ML56 Example 3, MOV TA,#0AAH ;3 clock cycles MOV TA,#55H ;3 clock cycles MOV WDCON,#data1 ;3 clock cycles ORL BODCON0,#data2 ;4 clock cycles Example 4, MOV TA,#0AAH ;3 clock cycles ;1 clock cycle MOV TA,#55H ;3 clock cycles ANL BODCON0,#data ;4 clock cycles In the first example, the writing to the protected bits is done before the 3-clock-cycle window closes.
  • Page 95 ML51/ML54/ML56 DPL – Data Pointer Low Byte Register SFR Address Reset Value 82H, All pages 0000_0000b DPTR[7:0] Name Description [7:0] DPTR[7:0] Data Pointer Low Byte This is the low byte of 16-bit data pointer. DPL combined with DPH serve as a 16-bit data pointer DPTR to access indirect addressed RAM or Program Memory.
  • Page 96 ML51/ML54/ML56 DPH – Data Pointer High Byte Register SFR Address Reset Value 83H, All pages 0000_0000b DPTR[15:8] Name Description [7:0] DPTR[15:8] Data Pointer High Byte This is the high byte of 16-bit data pointer. DPH combined with DPL serve as a 16-bit data pointer DPTR to access indirect addressed RAM or Program Memory.
  • Page 97 ML51/ML54/ML56 AUXR0 – Auxiliary Register 0 Register SFR Address Reset Value POR: 0000 0000b, Software reset: 1U00 0000b, AUXR0 A2H, Page 0 nRESET pin: U100 0000b, Hard fault: UU10 0000b Others: UUU0 0000b SWRF RSTPINF HardF HardFInt Name Description General Purpose Flag 2 The general purpose flag that can be set or cleared by the user via software.
  • Page 98 ML51/ML54/ML56 6.1.7.4 SFR Memory Map SPI1CR0 SPI1CR1 SPI1SR SPI1DR DMA1BAH EIP1 EIPH1 PWM0DTEN PWM0DTCNT PWM0MEN PWM0MD LVRFLTEN LVRDIS S1CON P0MF10 P0MF32 P0MF54 P0MF76 P1MF10 P1MF32 P1MF54 LCDCON LCDCLK LCDPTR LCDDAT LCDPWR LCDBL LCDMODE DMA1TSR MTM1DA SPI0CR0 SPI0SR SPI0DR DMA0BAH EIPH0 SPI0CR1 P1MF76 P2MF10...

  • Page 99: Table 6.1-1Special Function Register (Sfr) Memory Map

    ML51/ML54/ML56 LIRCTRIM XLTCON CWKL P6M1 P6M2 PWM1PH Table 6.1-1Special Function Register (SFR) Memory Map Sep. 01, 2020 Page 99 of 719 Rev 2.00...
  • Page 100 ML51/ML54/ML56 6.1.7.5 SFR Definitions And Reset Values Bits marked in “-“ are reserved for future use. They must be kept in their own initial states. Accessing these bits may cause an unpredictable effect. Reset Register Definition Value Extensive Interrupt EIPH1 PSPI1H PDMA1H PDMA0H...
  • Page 101 ML51/ML54/ML56 Reset Register Definition Value Pump Counter Value SPI0DR Spi0 Data SPDR[7:0] 00000000b P2.7 And P2.6 P2MF76 Multi Function P2MF7[3:0] P2MF6[3:0] 00000000b Select LCD Pump Counter Alarm LCDCPALCT0 LCDCPOVCT[7:0] 00000000b Y Setting Value Low Byte SPI0SR Spi0 Status SPIF WCOL SPIOVF MODF DISMODF...
  • Page 102 ML51/ML54/ML56 Reset Register Definition Value Level/Rising Edge Enable P4.1 And P4.0 P4MF10 Multi Function P4MF1[3:0] P4MF0[3:0] 00000000b Select Memory To Memory MTM0DA MDAL[7:0] 00000000b Destination Address Low Byte Pin Interrupt Low PINEN Level/Falling Edge PINEN7 PINEN6 PINEN5 PINEN4 PINEN3 PINEN2 PINEN1 PINEN0 00000000b...
  • Page 103 ML51/ML54/ML56 Reset Register Definition Value P5.3 And P5.2 P5MF32 Multi Function P5MF3[3:0] P5MF2[3:0] 00000000b Select Accumulator ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 00000000b Sc0 Transfer SC0TSR TXEMPTY TXOV RXEMPTY RXOV 00001010b Status Register PWMMOD_ PWMMOD_ PWM0CON1 Pwm Control 1 PWMTYP FBINEN PWMDIV_2 PWMDIV_1 PWMDIV_0...
  • Page 104 ML51/ML54/ML56 Reset Register Definition Value Analog ACMPSR Comparator Status ACMP1O ACMP1IF ACMP0O ACMP0IF 00000000b Register Pwm0 Channel 2 PWM0C2H PWM0C3[15:8] 00000000b Duty High Byte PWM3CON0 Pwm3 Control 0 2 PWM3RUN LOAD PWMF CLRPWM 00000000b Analog ACMPCR1 Comparator 0 POSSEL_1 POSSEL_0 NEGSEL_1 NEGSEL_0 WKEN HYSEN ACMPIE...
  • Page 105 ML51/ML54/ML56 Reset Register Definition Value T2MOD Timer2 Mode LDEN T2DIV_2 T2DIV_1 T2DIV_0 CAPCR CMPCR LDTS_1 LDTS_0 00000000b Auxiliary Register AUXR1 UART3PX UART2PX UART1PX UART0PX 00000000b Pwm Period High PWM3PH PWM3P[15:8] 00000000b Byte T2CON Timer2 Control CM_RL2 00000000b Time Access TA[7:0] 00000000b Protection Timer3 Reload...
  • Page 106 ML51/ML54/ML56 Reset Register Definition Value I2C0DAT I2c0 Data I2C0DAT[7:0] 00000000b Port4 Slew Rate P4SR P4SR.7 P4SR.6 P4SR.5 P4SR.4 P4SR.3 P4SR.2 P4SR.1 P4SR.0 00000000b Control PWM2MD Pwm Mask Data PMD1 PMD0 00000000b RTCLEAPYEA Rtc Leap Year LEAPYEAR 00000000b Indicator Register SADDR1 Slave1 Address SADDR1[7:0] 00000000b...
  • Page 107 ML51/ML54/ML56 Reset Register Definition Value Minute Register Outputlatch, 00000000b Port 5 P5.7 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0 Input, XXXXXXXXb P0M1 P0 Mode Select 1 P0M1_7 P0M1_6 P0M1_5 P0M1_4 P0M1_3 P0M1_2 P0M1_1 P0M1_0 11111111b PDMA1 N DMA2TSR Transfer Status HDONE FDONE 00000000b...
  • Page 108 ML51/ML54/ML56 Reset Register Definition Value Iap Address High IAPAH IAPA[15:8] 00000000b Byte Pin Interrupt PIPS6 PSEL_2 PSEL_1 PSEL_0 BSEL_2 BSEL_1 BSEL_0 00000000b Control 6 Outputlatch, 00000000b Port6 P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0 Input, XXXXXXXXb Rtc Interrupt RTCINTSTS TICKIF ALMIF 00000000b...
  • Page 109 ML51/ML54/ML56 Reset Register Definition Value Control Reset Flag LVRF PORF HFRF RSTPINF BORF WDTRF SWRF 11010000b Register Port2 Schmitt P2S.7 P2S.6 P2S.5 P2S.4 P2S.3 P2S.2 P2S.1 P2S.0 00000000b Triggered Input PWMMOD_ PWMMOD_ PWM1CON1 Pwm1 Control 1 PWMTYP FBINEN PWMDIV_2 PWMDIV_1 PWMDIV_0 00000000b DMA3SEED PDMA1 Crc Seed...
  • Page 110 ML51/ML54/ML56 Reset Register Definition Value Select PDMA1 Crc DMA1CRC CRC[7:0] 00000000b Checksum PDMA1 0 Control DMA0CR0 PSSEL_3 PSSEL_2 PSSEL_1 PSSEL_0 00000000b Register Port0 Pull P0UP P0UP.7 P0UP.6 P0UP.5 P0UP.4 P0UP.3 P0UP.2 P0UP.1 P0UP.0 00000000b Upresister Control P6.1 And P6.0 P6MF10 Multi Function P6MF1[3:0] P6MF0[3:0]...

  • Page 111: Table 6.1-2 Sfr Definitions And Reset Values

    ML51/ML54/ML56 Reset Register Definition Value Port6 Mode Select P6M2 P6M2.7 P6M2.6 P6M2.5 P6M2.4 P6M2.3 P6M2.2 P6M2.1 P6M2.0 00000000b Internal Rc Trim RCTRIM0 HIRCTRIM[8:1] XXXXXXXXb Y Value High Byte LIRCTRIM Lirc Trim Value LIRCTRIM[7:0] XXXXXXXXb Port6 Mode Select P6M1 P6M1.7 P6M1.6 P6M1.5 P6M1.4 P6M1.3...
  • Page 112 ML51/ML54/ML56 6.1.7.6 All SFR Description Note: the reset value show as following means U-unchanged; C-initialized by CONFIG; X- base on real chip status. Sep. 01, 2020 Page 112 of 719 Rev 2.00...
  • Page 113 ML51/ML54/ML56 Pn – Port Register SFR Address Reset Value 80H, All pages, Bit-addressable 1111_1111 b 90H, All pages, Bit-addressable 1111_1111 b A0H, All pages, Bit-addressable 1111_1111 b B0H, All pages, Bit-addressable 1111_1111 b D8H, All pages, Bit-addressable 1111_1111 b B1H, Page 0 1111_1111 b A7H, Page 2 1111_1111 b...
  • Page 114 ML51/ML54/ML56 SP – Stack Pointer Register SFR Address Reset Value 81H, All pages 0000_0111b SP[7:0] Name Description SP[7:0] Stack Pointer [7:0] The Stack Pointer stores the scratch-pad RAM address where the stack begins. It is incremented before data is stored during PUSH or CALL instructions. Note that the default value of SP is 07H.
  • Page 115 ML51/ML54/ML56 DPL – Data Pointer Low Byte Register SFR Address Reset Value 82H, All pages 0000_0000b DPTR[7:0] Name Description DPTR[7:0] Data Pointer Low Byte [7:0] This is the low byte of 16-bit data pointer. DPL combined with DPH serve as a 16-bit data pointer DPTR to access indirect addressed RAM or Program Memory.
  • Page 116 ML51/ML54/ML56 DPH – Data Pointer High Byte Register SFR Address Reset Value 83H, All pages 0000_0000b DPTR[15:8] Name Description DPTR[15:8] Data Pointer High Byte [7:0] This is the high byte of 16-bit data pointer. DPH combined with DPL serve as a 16-bit data pointer DPTR to access indirect addressed RAM or Program Memory.
  • Page 117 ML51/ML54/ML56 RCTRIM0 – High Speed Internal Oscillator Trim 0 (TA Protected) Register SFR Address Reset Value RCTRIM0 84H, Page 0, TA protected XXXX_XXXXb HIRCTRIM[8:1] Name Description HIRCTRIM[8:1] High Speed Internal Oscillator Trim Value High Byte [7:0] Sep. 01, 2020 Page 117 of 719 Rev 2.00...
  • Page 118 ML51/ML54/ML56 RCTRIM1 – High Speed Internal Oscillator Trim 1 (TA Protected) Register SFR Address Reset Value RCTRIM1 85H, Page 0, TA protected XXXX_XXXXb HIRCTRIM[0] Name Description HIRCTRIM[0] High Speed Internal Oscillator Trim Value lowest bit Sep. 01, 2020 Page 118 of 719 Rev 2.00...
  • Page 119 ML51/ML54/ML56 LIRCTRIM – Low Speed Internal Oscillator Trim (TA Protected) Register SFR Address Reset Value LIRCTRIM 84H, Page 1 XXXX_XXXXb LIRCTRIM[7:0] Name Description [7:0] LIRCTRIM[7:0] Low Speed Internal Oscillator Trim Value Sep. 01, 2020 Page 119 of 719 Rev 2.00...
  • Page 120 ML51/ML54/ML56 XLTCON – XLT Clock Control (TA Protected) Register SFR Address Reset Value XLTCON 85H, Page 1, TA protected 0111_0111b HSCH HXSG[2:0] LXSG[1:0] Name Description HSCH HXT Schmitt Trigger Select 0 = disable 1 = enable [6:4] HXSG[2:0] HXT Gain Value Select 000 = L0 mode (smallest value) 001 = L1 mode 010 = L2 mode...
  • Page 121 ML51/ML54/ML56 RWKL – Self Wake-up Timer Reload Low Byte Register SFR Address Reset Value RWKL 86H, Page 0 0000_0000b RWK[7:0] Name Description RWK[7:0] WKT Reload Byte [7:0] It holds the 16-bit reload value of WKT. Note that RWK should not be FFFFH if the pre-scale is 1/1 for implement limitation.
  • Page 122 ML51/ML54/ML56 CWKL – Self Wake-up Timer Current Count Value Low Byte Register SFR Address Reset Value CWKL 86H, Page 1 0000_0000b CWK[7:0] Name Description CWK[7:0] WKT Current Count Value Low Byte [7:0] It is store value of WKT current count. Sep.
  • Page 123 ML51/ML54/ML56 PCON – Power Control Register SFR Address Reset Value POR: 0001_0000b PCON 87H, All pages Others: 000U _0000b SMOD SMOD0 Name Description SMOD Serial Port 0 Double Baud Rate Enable Setting this bit doubles the serial port baud rate when UART0 is in Mode 2 or when Timer 1 overflow is used as the baud rate source of UART0 Mode 1 or 3.
  • Page 124 ML51/ML54/ML56 Name Description Idle Mode Setting this bit puts CPU into Idle mode. Under this mode, the CPU clock stops and Program Counter (PC) suspends but all peripherals keep activated. After CPU is woken up from Idle, this bit will be automatically cleared via hardware and the program continue executing the ISR of the very interrupt source that woke the system up before.
  • Page 125 ML51/ML54/ML56 TCON – Timer 0 and 1 Control Register SFR Address Reset Value TCON 88H, All pages, Bit-addressable 0000_0000b R (level) R (level) R/W (edge) R/W (edge) Name Description Timer 1 Overflow Flag This bit is set when Timer 1 overflows. It is automatically cleared by hardware when the program executes the Timer 1 interrupt service routine.
  • Page 126 ML51/ML54/ML56 Name Description External Interrupt 0 Type Select This bit selects by which type that INT0 is triggered. 0 = INT0 is low level triggered. 1 = INT0 is falling edge triggered. Sep. 01, 2020 Page 126 of 719 Rev 2.00...
  • Page 127 ML51/ML54/ML56 TMOD – Timer 0 and 1 Mode Register SFR Address Reset Value TMOD 89H, All pages 0000_0000b GATE GATE Name Description GATE Timer 1 Gate Control 0 = Timer 1 will clock when TR1 is 1 regardless of INT1 logic level. 1 = Timer 1 will clock only when TR1 is 1 and INT1 is logic 1.
  • Page 128 ML51/ML54/ML56 TL0 – Timer 0 Low Byte Register SFR Address Reset Value 8AH, Page 0 0000_0000b TL0[7:0] Name Description TL0[7:0] Timer 0 Low Byte [7:0] The TL0 register is the low byte of the 16-bit counting register of Timer 0. Sep.
  • Page 129 ML51/ML54/ML56 PnDW – Port n Pull-down Resister Control Register SFR Address Reset Value P0DW 8AH, Page 1 0000_0000 b P1DW 8BH, Page 1 0000_0000 b P2DW 8CH, Page 1 0000_0000 b P3DW 8DH, Page 1 0000_0000 b P4DW 8EH, Page 1 0000_0000 b P5DW 8FH, Page 1...
  • Page 130 ML51/ML54/ML56 TL1 – Timer 1 Low Byte Register SFR Address Reset Value 8BH, Page 0 0000_0000b TL1[7:0] Name Description TL1[7:0] Timer 1 Low Byte [7:0] The TL1 register is the low byte of the 16-bit counting register of Timer 1. Sep.
  • Page 131 ML51/ML54/ML56 TH0 – Timer 0 High Byte Register SFR Address Reset Value 8CH, Page 0 0000_0000b TH0[7:0] Name Description TH0[7:0] Timer 0 High Byte [7:0] The TH0 register is the high byte of the 16-bit counting register of Timer 0. Sep.
  • Page 132 ML51/ML54/ML56 TH1 – Timer 1 High Byte Register SFR Address Reset Value 8DH, Page 0 0000_0000b TH1[7:0] Name Description TH1[7:0] Timer 1 High Byte [7:0] The TH1 register is the high byte of the 16-bit counting register of Timer 1. Sep.
  • Page 133 ML51/ML54/ML56 CKCON – Clock Control Register SFR Address Reset Value CKCON 8EH, Page 0 1000_0000b FASTWK PWMCKS T1OE T0OE CLOEN Name Description FASTWK Fast Wakeup Enable 0 = Faster Wakeup Disabled, when system wakeup from Power-down mode, HIRC clock stable time is about 10us. 1 = Faster Wakeup Enabled, when system wakeup from Power-down mode, HIRC clock stable time is about 3us.
  • Page 134 ML51/ML54/ML56 WKCON – Self Wake-up Timer Control Register SFR Address Reset Value WKCON 8FH, Page 0 0000_0000b WKTCK WKTF WKTR WKPS[2:0] Name Description [7:6] Reserved WKTCK WKT Clock Source This bit is set WKT clock source select bit. 0 = LIRC 1 = LXT WKTF WKT Overflow Flag...
  • Page 135 ML51/ML54/ML56 SFRS – SFR Page Selection Register SFR Address Reset Value SFRS 91H, All pages 0000_0000b SFRPAGE[1:0] Name Description SFRPAGE[1:0] SFR Page Select [1:0] 00 = Instructions access SFR Page 0. 01 = Instructions access SFR Page 1. 10 = Instructions access SFR page 2. 11 = Instructions access SFR page 3.
  • Page 136 ML51/ML54/ML56 DMAnCR – PDMAn Control Register Register SFR Address Reset Value DMA0CR0 92H, Page 0 0000_0000 b DMA1CR0 EBH, Page 0 0000_0000 b DMA2CR0 B3H, Page 2 0000_0000 b DMA3CR0 ABH, Page 2 0000_0000 b PSSEL[3:0] Name Description [7:4] PSSEL[3:0] Peripheral Source Select 0000 = XRAM to XRAM 0001 = SPI0 RX...
  • Page 137 ML51/ML54/ML56 PnUP – Port n Pull-up Resister Control Register SFR Address Reset Value P0UP 92H, Page 1 0000_0000 b P1UP 93H, Page 1 0000_0000 b P2UP 94H, Page 1 0000_0000 b P3UP 95H, Page 1 0000_0000 b P4UP 96H, Page 1 0000_0000 b P5UP 97H, Page 1...
  • Page 138 ML51/ML54/ML56 DMAnMA – PDMA XRAM Base Address Low Byte Register SFR Address Reset Value DMA0MAL 93H, Page 0 0000_0000 b DMA1MAL ECH, Page 0 0000_0000 b DMA2MAL B4H, Page 2 0000_0000 b DMA3MAL ACH, Page 2 0000_0000 b MAL[7:0] Name Description [7:0] MAL[7:0]...
  • Page 139 ML51/ML54/ML56 DMAnCNT – PDMA Transfer Count Register SFR Address Reset Value DMA0CNT 94H, Page 0 0000_0000 b DMA1CNT EDH, Page 0 0000_0000 b DMA2CNT B5H, Page 2 0000_0000 b DMA3CNT ADH, Page 2 0000_0000 b DMAnCNT[7:0] Name Description [7:0] DMAnCNT[7:0] PDMA Transfer Count The total transfer count for PDMA request operation.
  • Page 140 ML51/ML54/ML56 DMAnCCNT – PDMA Current Transfer Count Register SFR Address Reset Value DMA0CCNT 95H, Page 0 0000_0000 b DMA1CCNT EEH, Page 0 0000_0000 b DMA2CCNT B6H, Page 2 0000_0000 b DMA3CCNT AEH, Page 2 0000_0000 b DMAnCCNT[7:0] Name Description [7:0] DMAnCCNT[7:0] PDMA Current Transfer Count The current transfer count for PDMA request operation.
  • Page 141 ML51/ML54/ML56 CKSWT – Clock Switch (TA Protected) Register SFR Address Reset Value CKSWT 96H, PAGE 0, TA protected 0011 _0000 b HXTST LXTST HIRCST LIRCST ECLKST OSC[2:0] Name Description HXTST High Speed External Crystal/Resonator 4 MHz to 24 MHz Status 0 = High speed external crystal/resonator is not stable or is disabled.
  • Page 142 ML51/ML54/ML56 CKEN – Clock Enable Register SFR Address Reset Value CKEN 97H, PAGE 0, TA protected 0011_0100 b EHXTEN ELXTEN HIRCEN LIRCEN ECLKEN CKSWTF Name Description EHXTEN External High-Speed Crystal/Resonator Enable 1 = High-speed external crystal/resonator 4 MHz to 24 MHz Enabled. 0 = High-speed external crystal/resonator 4 MHz to 24 MHz Disabled, P5.2 and P5.3 work as general purpose I/O or other functions if ECLKEN set to 0.
  • Page 143 ML51/ML54/ML56 SCON – Serial Port Control Register SFR Address Reset Value SCON 98H, All pages, Bit addressable 0000_0000 b SM0/FE Name Description SM0/FE Serial Port Mode Select SMOD0 (PCON.6) = 0: See Table 6.9-1 Serial Port 0 Mode / baud rate Description for details. SMOD0 (PCON.6) = 1: SM0/FE bit is used as frame error (FE) status flag.
  • Page 144 ML51/ML54/ML56 Name Description 9th Received Bit The bit identifies the logic level of the 9th received bit in serial port 0 Mode 2 or 3. In Mode 1, RB8 is the logic level of the received stop bit. SM2 bit as logic 1 has restriction for exception. RB8 is not used in Mode 0.
  • Page 145 ML51/ML54/ML56 SBUF – Serial Port 0 Data Buffer Register SFR Address Reset Value SBUF 99H, Page 0 0000_0000 b SBUF[7:0] Name Description SBUF[7:0] Serial Port 0 Data Buffer [7:0] This byte actually consists two separate registers. One is the receiving resister, and the other is the transmitting buffer.
  • Page 146 ML51/ML54/ML56 PnS – Port n Schmitt Triggered Input Register SFR Address Reset Value 99H, Page 1 0000_0000 b 9BH, Page 1 0000_0000 b 9DH, Page 1 0000_0000 b ACH, Page 1 0000_0000 b BBH, Page 1 0000_0000 b BFH, Page 1 0000_0000 b 96H, Page 2 0000_0000 b...
  • Page 147 ML51/ML54/ML56 WDCON – Watchdog Timer Control (TA Protected) Register SFR Address Reset Value POR 0000_0001 b WDT 0000_000U b WDCON AAH, Page 0, TA protected Others 0000_000U b WDPS[3] Name Description [7:1] Reserved WDPS[3] WDT Clock Pre-Scalar Select These bits determine the pre-scale of WDT clock from 1/1 through 1/2048. SeeTable 6.6-1 Watchdog Timer-out Interval Under Different Pre-scalars The default is the maximum pre-scale value.
  • Page 148 ML51/ML54/ML56 SBUF1 – Serial Port 1 Data Buffer Register SFR Address Reset Value SBUF1 9AH, Page 0 0000 _0000 b SBUF1[7:0] Name Description SBUF1[7:0] Serial Port 1 Data Buffer [7:0] This byte actually consists two separate registers. One is the receiving resister, and the other is the transmitting buffer.
  • Page 149 ML51/ML54/ML56 PnSR –Port n Slew Rate Control Register SFR Address Reset Value P0SR 9AH, Page 1 0000_0000 b P1SR 9CH, Page 1 0000_0000 b P2SR 9EH, Page 1 0000_0000 b P3SR ADH, Page 1 0000_0000 b P4SR BCH, Page 1 0000_0000 b P5SR AEH, Page 1...
  • Page 150 ML51/ML54/ML56 EIE0 – Extensive Interrupt Enable Register SFR Address Reset Value EIE0 9BH, Page 0 0000 _0000 b ESPI0 EFB0 EWDT EPWM0 ECAP EI2C0 Name Description Enable Timer 2 Interrupt 0 = Timer 2 interrupt Disabled. 1 = Timer 2 interrupt Enable. When interrupt generated, TF2 (T2CON.7) set 1 ESPI0 Enable SPI Interrupt 0 = SPI interrupt Disabled.
  • Page 151 ML51/ML54/ML56 EIE1 – Extensive Interrupt Enable 1 Register SFR Address Reset Value EIE1 9CH, Page 0 0000 _0000 b EPWM123 EI2C1 ESPI1 EHFI EWKT Name Description EPWM123 Enable PWM123 Interrupt 0 = PWM1/2/3 interrupt Disabled. 1 = PWM1/2/3 interrupt Enable. When interrupt generated PWMF (PWM1CON0.5) set 1. EI2C1 Enable I2C1 Interrupt 0 = I 2 C1 interrupt Disabled.
  • Page 152 ML51/ML54/ML56 RSR – Reset Flag Register Register SFR Address Reset Value 9DH, Page 0 1101_0000 b LVRF PORF HFRF RSTPINF BORF WDTRF SWRF Name Description LVRF LVR Reset Flag 1: LVR Reset Flag is active 0: LVR Reset Flag is inactive Write 0 to clear this bit PORF POR Reset Flag...
  • Page 153 ML51/ML54/ML56 CHPCON – Chip Control (TA Protected) Register SFR Address Reset Value Software 0000_00U0 b CHPCON 9FH, Page 0, TA protected Others 0000_00C0 b SWRST IAPFF IAPEN Name Description SWRST Software Reset To set this bit as logic 1 will cause a software reset. It will automatically be cleared via hardware after reset is finished.
  • Page 154 ML51/ML54/ML56 ADCCON0 – ADC Control Register 0 Register SFR Address Reset Value ADCCON0 A1H, Page 0 0000_0000b ADCF ADCS ETGSEL1 ETGSEL0 ADCHS3 ADCHS2 ADCHS1 ADCHS0 Name Description ADCF ADC Flag This flag is set when an A/D conversion is completed in single sampling mode, final sampling complete in continue sampling mode or comparing hit if result comparator is enabled.
  • Page 155 ML51/ML54/ML56 Name Description [3:0] ADCHS[3:0] A/D Converting Channel Select This filed selects the activating analog input source of ADC. If ADCEN is 0, all inputs are disconnected. 0000 = ADC_CH0. 0001 = ADC_CH1. 0010 = ADC_CH2. 0011 = ADC_CH3. 0100 = ADC_CH4. 0101 = ADC_CH5.
  • Page 156 ML51/ML54/ML56 PIPSn – Pin Interrupt Control Register SFR Address Reset Value PIPS0 A1H, Page 1 0000_0000 b PIPS1 A2H, Page 1 0000_0000 b PIPS2 A3H, Page 1 0000_0000 b PIPS3 A4H, Page 1 0000_0000 b PIPS4 A5H, Page 1 0000_0000 b PIPS5 A6H, Page 1 0000_0000 b...
  • Page 157 ML51/ML54/ML56 AUXR0 – Auxiliary Register 0 Register SFR Address Reset Value POR: 0000 0000b, Software reset: 1U00 0000b, AUXR0 A2H, Page 0 nRESET pin: U100 0000b, Hard fault: UU10 0000b Others: UUU0 0000b SWRF RSTPINF HFRF HFIF Name Description SWRF Software Reset Flag When the MCU is reset via software reset, this bit will be set via hardware.
  • Page 158 ML51/ML54/ML56 BODCON0 – Brown-out Detection Control 0 (TA Protected) Register SFR Address Reset Value POR,CCCC XC0X b BOD, UUUU XU1X b BODCON0 A3H, Page 0, TA protected Others,UUUU XUUX b BODEN BOV[2:0] BORST BORF Name Description BODEN Brown-Out Detection Enable 0 = Brown-out detection circuit ON.
  • Page 159 ML51/ML54/ML56 Name Description Brown-Out Status This bit indicates the V voltage level comparing with VBOD while BOD circuit is enabled. It keeps 0 if BOD is not enabled. 0 = V voltage level is higher than VBOD or BOD is disabled. 1 = V voltage level is lower than VBOD.
  • Page 160 ML51/ML54/ML56 IAPTRG – IAP Trigger (TA Protected) Register SFR Address Reset Value IAPTRG A4H, Page 0, TA protected 0000 _0000 b IAPGO Name Description [7:1] Reserved IAPGO IAP Go IAP begins by setting this bit as logic 1. After this instruction, the CPU holds the Program Counter (PC) and the IAP hardware automation takes over to control the progress.
  • Page 161 ML51/ML54/ML56 IAPUEN – IAP Updating Enable (TA Protected) Register SFR Address Reset Value IAPUEN A5H, Page 0, TA protected 0000 _0000 b SPMEN SPUEN CFUEN LDUEN APUEN R/WFV Name Description [7:5] Reserved SPMEN SPROM Memory Space Mapping Enable 0 = CPU memory address 0xff80~0xffff is mapping to APROM memory 1 = CPU memory address 0xff80~0xffff is mapping to SPROM memory SPUEN SPROM Memory Space Updated Enable(TA Protected)
  • Page 162 ML51/ML54/ML56 IAPAL – IAP Address Low Byte Register SFR Address Reset Value IAPAL A6H, Page 0 0000 _0000 b IAPA[7:0] Name Description IAPA[7:0] IAP Address Low Byte [7:0] IAPAL contains address IAPA[7:0] for IAP operations. Sep. 01, 2020 Page 162 of 719 Rev 2.00...
  • Page 163 ML51/ML54/ML56 IAPAH – IAP Address High Byte Register SFR Address Reset Value IAPAH A7H, Page 0 0000 _0000 b IAPA[15:8] Name Description IAPA[15:8] IAP Address High Byte [7:0] IAPAH contains address IAPA[15:8] for IAP operations. Sep. 01, 2020 Page 163 of 719 Rev 2.00...
  • Page 164 ML51/ML54/ML56 IE – Interrupt Enable Register SFR Address Reset Value A8H, All pages, Bit addressable 0000 _0000 b EADC EBOD Name Description Enable All Interrupt This bit globally enables/disables all interrupts that are individually enabled. 0 = All interrupt sources Disabled. 1 = Each interrupt Enabled depending on its individual mask setting.
  • Page 165 ML51/ML54/ML56 SADDRn – UART Slave Address Register SFR Address Reset Value SADDR0 A9H, Page 0 0000 _0000 b SADDR1 BBH, Page 0 0000 _0000 b SADDRn[7:0] Name Description [7:0] SADDRn[7:0] Slave n Address This byte specifies the microcontroller’s own slave address for UATR0 multi-processor communication.
  • Page 166 ML51/ML54/ML56 VRFCON – Internal V Control (TA Protected) Register SFR Address Reset Value VRFCON A9H,Page 1, TA protected 0000 _0000 b VRFSEL[2:0] ENLOAD ENVRF Name Description Reserved [6:4] VRFSEL[2:0] Internal V Output Voltage Select This field selects V output voltage. 000 = 1.538V , when V >...
  • Page 167 ML51/ML54/ML56 WDCON – Watchdog Timer Control (TA Protected) Register SFR Address Reset Value POR 0000_0111 b WDT 0000_1UUU b WDCON AAH, Page 0, TA protected Others 0000_UUUU b WDTR WDCLR WDTF WIDPD WDTRF WDPS[2:0] Name Description WDTR WDT Run This bit is valid only when control bits in WDTEN[3:0] (CONFIG4[7:4]) are all 1. At this time, WDT works as a general purpose timer.
  • Page 168 ML51/ML54/ML56 Name Description Note: WDTRF will be cleared after power-on reset, be set after WDT reset, and remains unchanged after any other resets WDPS[3:0] are all set after power-on reset and keep unchanged after any reset other than power-on reset. Sep.
  • Page 169 ML51/ML54/ML56 VRFTRIM – Internal V Trim Select (TA Protected) Register SFR Address Reset Value VRFTRIM AAH, Page 1, TA protected 0100_0000b VRFTRIM[6:0] Address: AAH, Page 1 Reset value: 0100 0000b Name Description Reserved [6:0] VRFTRIM[6:0] Internal V Trim Select default=7’b1000000 Output MAX=7’b1111110;...
  • Page 170 ML51/ML54/ML56 BODCON1 – Brown-out Detection Control Byte 1 (TA Protected) Register SFR Address Reset Value POR 0000 0001 b BODCON1 ABH, Page 0, TA protected Others 0000 0UUU b LPBOD[1:0] BODFLT Name Description [7:3] Reserved [2:1] LPBOD[1:0] Low Power BOD Enable 00 = BOD normal mode.
  • Page 171 ML51/ML54/ML56 ACMPCR2 – Analog Comparator Control Register 2 Register SFR Address Reset Value ACMPCR2 ABH, Page 1 0000 _0000 b SPEED1 POE1 POE0 SPEED0 CRVSSEL CRVEN Name Description SPEED1 Analog Comparator 1 Speed Control [7:6] 00 = slow speed, propagation delay : 4.5us, 1.2uA (typ.) 01 = slow+ speed, propagation delay : 2.0us, 3uA (typ.) 10 = fast speed, propagation delay : 0.6us, 10uA (typ.) 11 = fast+ speed, propagation delay : 0.2us, 75uA (typ.)
  • Page 172 ML51/ML54/ML56 EIP2 – Extensive Interrupt Priority 2 Register SFR Address Reset Value EIP2 ACH, Page 0 0000_0000 b PDMA3 PDMA2 SMC1 PPWM1 PI2C1 PACMP Name Description RTC interrupt priority low bit PDMA3 PDMA3 interrupt priority low bit PDMA2 PDMA2 interrupt priority low bit SMC1 SMC1 interrupt priority low bit Touch Key interrupt priority low bit...
  • Page 173 ML51/ML54/ML56 EIPH2 – Extensive Interrupt Priority High 2 Register SFR Address Reset Value EIPH2 ADH, Page 0 0000_0000 b RTCH PDMA3H PDMA2H SMC1H PPWM1H PI2C1H PACMPH Name Description RTCH RTCH interrupt priority high bit PDMA3H PDMA3H interrupt priority high bit PDMA2H PDMA2H interrupt priority high bit SMC1H...
  • Page 174 ML51/ML54/ML56 IAPFD – IAP Flash Data Register SFR Address Reset Value IAPFD AEH, Page 0 0000 _0000 b IAPFD[7:0] Name Description IAPFD[7:0] IAP Flash Data [7:0] This byte contains Flash data, which is read from or is going to be written to the Flash Memory.
  • Page 175 ML51/ML54/ML56 IAPCN – IAP Control Register SFR Address Reset Value IAPCN AFH, Page 0 0011_0000 b IAPB[1:0] FOEN FCEN FCTRL[3:0] Name Description IAPB[1:0] IAP Control [7:6] This byte is used for IAP command. For details, see Figure 6.3-1 IAP Modes and Command Codes.
  • Page 176 ML51/ML54/ML56 PnM1 – Port n Mode Select 1 Register SFR Address Reset Value P0M1 B1H, Page 1 1111_1111 b P1M1 B3H, Page 1 1111_1111 b P2M1 B5H, Page 1 1111_1111 b P3M1 C2H, Page 1 1111_1111 b P4M1 B9H, Page 1 1111_1111 b P5M1 BDH, Page 1...
  • Page 177 ML51/ML54/ML56 PnM2 – Port n Mode Select 2 Register SFR Address Reset Value P0M2 B2H, Page 1 0000_0000 b P1M2 B4H, Page 1 0000_0000 b P2M2 B6H, Page 1 0000_0000 b P3M2 C3H, Page 1 0000_0000 b P4M2 BAH, Page 1 0000_0000 b P5M2 BEH, Page 1...
  • Page 178 ML51/ML54/ML56 I2C1DAT – I2C1 Data Register SFR Address Reset Value I2C1DAT B3H, Page 0 0000_0000 b I2C1DAT[7:0] Name Description I2C1DAT[7:0] I2C1 Data [7:0] I2CnDAT contains a byte of the I C data to be transmitted or a byte, which has just received.
  • Page 179 ML51/ML54/ML56 PWMnINTC – PWM Interrupt Control Register SFR Address Reset Value PWM0INTC B7H, Page 1 0000_0000 b PWM1INTC 9EH, Page 2 0000_0000 b PWM2INTC C6H, Page 2 0000_0000 b PWM3INTC D6H, Page 2 0000_0000 b INTTYP1 INTTYP0 INTSEL2 INTSEL1 INTSEL0 Name Description [7:6]...
  • Page 180 ML51/ML54/ML56 IP – Interrupt Priority Register SFR Address Reset Value B8H, All pages, Bit addressable 0000_0000 b PADC PBOD Name Description Reserved PADC ADC interrupt priority low bit PBOD Brown-out detection interrupt priority low bit Serial port 0 interrupt priority low bit Timer 1 interrupt priority low bit External interrupt 1 priority low bit Timer 0 interrupt priority low bit...
  • Page 181 ML51/ML54/ML56 SADENn – UART Slave n Address Mask Register SFR Address Reset Value SADEN0 B9H, Page 0 0000_0000 b SADEN1 BAH, Page 0 0000_0000 b SADENn[7:0] Name Description [7:0] SADENn[7:0] Slave n Address Mask This byte is a mask byte of UART0 that contains “don’t-care” bits (defined by zeros) to form the device’s “Given”...
  • Page 182 ML51/ML54/ML56 I2CnDAT – I C Data Register SFR Address Reset Value I2C0DAT BCH, Page 0 0000_0000 b I2C1DAT B3H, Page 0 0000_0000 b I2CnDAT[7:0] Name Description I 2 Cn Data [7:0] I2CnDAT[7:0] I2CnDAT contains a byte of the I C data to be transmitted or a byte, which has just received.
  • Page 183 ML51/ML54/ML56 I2CnSTAT – I C Status Register SFR Address Reset Value I2C0STAT BDH, Page 0 1111_1000 b I2C1STAT B4H, Page 0 1111_1000 b I2CnSTAT[7:3] Name Description I 2 Cn Status Code [7:3] I2CnSTAT[7:3] The MSB five bits of I2CnSTAT contains the status code. There are 27 possible status codes.
  • Page 184 ML51/ML54/ML56 I2CnCLK – I C Clock Register SFR Address Reset Value I2C0CLK BEH, Page 0 0000_1001 b I2C1CLK B5H, Page 0 0000_1001 b I2CnCLK[7:0] Address: BEH, Page 0 Reset value: 0000 1001b Name Description [7:0] I2CnCLK[7:0] I 2 Cn Clock Setting In master mode: This register determines the clock rate of I C bus when the device is in a master mode.
  • Page 185 ML51/ML54/ML56 AUXR3 – Auxiliary Register 3 Register SFR Address Reset Value AUXR3 CFH, Page 3 0000_0000 b UART3DG UART2DG UART1DG UART0DG Name Description [7:4] Reserved UART3DG UART3 RX Deglitch Control 1: Deglitch is Enabled 0: Deglitch is Disabled UART2DG UART2 RX Deglitch Control 1: Deglitch is Enabled 0: Deglitch is Disabled UART1DG...
  • Page 186 ML51/ML54/ML56 I2CnTOC – I2Cn Time-out Counter Register SFR Address Reset Value I2C0TOC BFH, Page 0 0000_0000b I2C1TOC B6H, Page 0 0000_0000b I2TOCEN I2TOF Name Description [7:3] Reserved I 2 Cn Time-Out Counter Enable I2TOCEN 0 = I C time-out counter Disabled. 1 = I C time-out counter Enabled.
  • Page 187 ML51/ML54/ML56 CWKH – Self Wake-up Timer Current Count Value High Byte Register SFR Address Reset Value CWKH BEH, Page 2 0000_0000 b CWK[15:8] Name Description CWK[15:8] WKT Current Count Value Low Byte High Byte [7:0] It is store value of WKT current count. Sep.
  • Page 188 ML51/ML54/ML56 RWKH – Self Wake-up Timer Reload High Byte Register SFR Address Reset Value RWKH BFH, Page 2 0000 0000b RWK[15:8] Name Description RWK[15:8] WKT Reload High Byte [7:0] It holds the 16-bit reload value of WKT. Note that RWK should not be FFFFH if the pre-scale is 1/1 for implement limitation.
  • Page 189 ML51/ML54/ML56 I2CnCON – I C Control Register SFR Address Reset Value I2C0CON C0H, All pages, Bit-addressable 0000_0000 b I2C1CON E8H, All pages 0000_0000 b I2CEN Name Description I 2 Cn Hold Time Extend Enable 0 = I C DATA to SCL hold time extend disabled 1 = I C DATA to SCL hold time extend enabled, extend 8 system clock I2CEN...
  • Page 190 ML51/ML54/ML56 Name Description I 2 C0 Interrupt Flag SI flag is set by hardware when one of 26 possible I C status (besides F8H status) is entered. After SI is set, the software should read I2CnSTAT register to determine which step has been passed and take actions for next step.
  • Page 191 ML51/ML54/ML56 I2CnADDRx – I2Cn Own Slave Address Register SFR Address Reset Value I2C0ADDR0 C1H, Page 0 0000_0000 b I2C0ADDR1 A1H, Page 2 0000_0000 b I2C0ADDR2 A2H, Page 2 0000_0000 b I2C0ADDR3 A3H, Page 2 0000_0000 b I2C1ADDR0 B2H, Page 0 0000_0000 b I2C1ADDR1 A4H, Page 2...
  • Page 192 ML51/ML54/ML56 CKDIV – Clock Divider Register SFR Address Reset Value CKDIV C1H, Page 1 0000_0000b CKDIV[7:0] Name Description CKDIV[7:0] Clock Divider [7:0] The system clock frequency F follows the equation below according to CKDIV value.  , while CKDIV = 00H, ...
  • Page 193 ML51/ML54/ML56 ADCRL – ADC Result Low Byte Register SFR Address Reset Value ADCRL C2H, Page 0 0000_0000 b ADCR[3:0] Name Description [7:4] Reserved [3:0] ADCR[3:0] ADC Result Low Byte The least significant 4 bits of the ADC result stored in this register. Sep.
  • Page 194 ML51/ML54/ML56 PWMnCxH – PWM0/1/2/3 Channel 0~5 Duty High Byte n=0,1,2,3; x=0,1,2,3,4,5 Register SFR Address Reset Value PWM0C0H D2H, Page 1 0000_0000 b PWM0C1H D3H, Page 1 0000_0000 b PWM0C2H D4H, Page 1 0000_0000 b PWM0C3H D5H, Page 1 0000_0000 b PWM0C4H C4H, Page 1 0000_0000 b...
  • Page 195 ML51/ML54/ML56 ADCRH – ADC Result High Byte Register SFR Address Reset Value ADCRH C3H, Page 0 0000_0000 b ADCR[11:4] Name Description ADCR[11:4] ADC Result High Byte [7:0] The most significant 8 bits of the ADC result stored in this register. Sep.
  • Page 196 ML51/ML54/ML56 T3CON – Timer 3 Control Register SFR Address Reset Value T3CON C4H, Page 0 0000_0000 b SMOD_1 SMOD0_1 BRCK T3PS[2:0] Name Description SMOD_1 Serial Port 1 Double Baud Rate Enable Setting this bit doubles the serial port baud rate when UART1 is in Mode 2.see Table 6.9-2 Serial Port 1 Mode / baud rate Description for details.
  • Page 197 ML51/ML54/ML56 RL3 – Timer 3 Reload Low Byte Register SFR Address Reset Value C5H, Page 0 0000_0000 b RL3[7:0] Name Description RL3[7:0] Timer 3 Reload Low Byte [7:0] It holds the low byte of the reload value of Timer 3. Sep.
  • Page 198 ML51/ML54/ML56 RH3 – Timer 3 Reload High Byte Register SFR Address Reset Value C6H, Page 0 0000_0000 b RH3[15:8] Name Description [7:0] RH3[15:8] Timer 3 Reload High Byte It holds the high byte of the reload value of Time 3. Sep.
  • Page 199 ML51/ML54/ML56 PORDIS – POR Disable (TA Protected) Register SFR Address Reset Value PORDIS C6H, Page 1, TA protected 0000_0000 b PORDIS[7:0] Name Description PORDIS[7:0] POR Disable [7:0] To first writing 5AH to the PORDIS and immediately followed by a writing of A5H will disable all of PORs (POR50 and POR15).
  • Page 200 ML51/ML54/ML56 TA – Timed Access Register SFR Address Reset Value C7H, All pages 0000_0000 b TA[7:0] Name Description TA[7:0] Timed Access [7:0] The timed access register controls the access to protected SFR. To access protected bits, user should first write AAH to the TA and immediately followed by a write of 55H to TA. After these two steps, a writing permission window is opened for 4 clock cycles during this period that user may write to protected SFR.
  • Page 201 ML51/ML54/ML56 T2CON – Timer 2 Control Register SFR Address Reset Value T2CON C8H, All pages, Bit addressable 0000_0000 b CM_RL2 Name Description Timer 2 Overflow Flag This bit is set when Timer 2 overflows or a compare match occurs. If the Timer 2 interrupt and the global interrupt are enable, setting this bit will make CPU execute Timer 2 interrupt service routine.
  • Page 202 ML51/ML54/ML56 T2MOD – Timer 2 Mode Register SFR Address Reset Value T2MOD C9H, Page 0 0000_0000 b LDEN T2DIV[2:0] CAPCR CMPCR LDTS[1:0] Name Description LDEN Enable Auto-Reload 0 = Reloading RCMP2H and RCMP2L to TH2 and TL2 Disabled. 1 = Reloading RCMP2H and RCMP2L to TH2 and TL2 Enabled. [6:4] T2DIV[2:0] Timer 2 Clock Divider...
  • Page 203 ML51/ML54/ML56 AUXR1 – Auxiliary Register 1 Register SFR Address Reset Value AUXR1 C9H, Page 1 0000_0000 b UART3PX UART2PX UART1PX UART0PX Name Description [7:4] Reserved UART3PX Serial Port 3 RX (SMC1 DATA) /TX (SMC1 CLK) Pin Exchange 0 = Assign UART3 RXD (SMC1 DATA) to multiple I/O pin RXD UART3 TXD (SMC CLK) to multiple I/O pin TXD 1 = Assign UART3 RXD (SMC1 DATA) to multiple I/O pin TXD UART3 TXD (SMC CLK) to multiple I/O pin RXD...
  • Page 204 ML51/ML54/ML56 Name Description UART0PX Serial Port 0 RX/TX Pin Exchange 0 = Assign UART0 RXD to multiple I/O pin RXD UART0 TXD to multiple I/O pin TXD 1 = Assign UART0 RXD to multiple I/O pin TXD UART0 TXD to multiple I/O pin RXD Note: that Pin direction is controlled by I/O type of relative pin.
  • Page 205 ML51/ML54/ML56 PIF – Pin Interrupt Flags Register SFR Address Reset Value CAH, Page 0 0000_0000 b PIF7 PIF6 PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 R (level) R (level) R (level) R (level) R (level) R (level) R (level) R (level) R/W (edge) R/W (edge) R/W (edge)
  • Page 206 ML51/ML54/ML56 RCMP2L– Timer 2 Reload/Compare Low Byte Register SFR Address Reset Value RCMP2L CAH, Page 1 0000_0000 b RCMP2[7:0] Name Description RCMP2[7:0] Timer 2 Reload/Compare Low Byte [7:0] This register stores the low byte of compare value when Timer 2 is configured in compare mode.
  • Page 207 ML51/ML54/ML56 ADCBAL – ADC RAM Base Address Low Byte Register SFR Address Reset Value ADCBAL CBH, Page 0 0000_0000 b ADCBAL[7:0] Name Description ADCBAL[7:0] ADC RAM Base Address (Low Byte) [7:0] The least significant 8 bits of RAM base address to store ADC continue sampling data. RAM base address ADCBA[11:0] = { ADCBAH[3:0], ADCBAL[7:0]} Sep.
  • Page 208 ML51/ML54/ML56 RCMP2H – Timer 2 Reload/Compare High Byte Register SFR Address Reset Value RCMP2H CBH, Page 1 0000_0000 b RCMP2[15:8] Name Description RCMP2[15:8] Timer 2 Reload/Compare High Byte [7:0] This register stores the high byte of compare value when Timer 2 is configured in compare mode.
  • Page 209 ML51/ML54/ML56 TL2 – Timer 2 Low Byte Register SFR Address Reset Value CCH, Page 0 0000_0000 b T2[7:0] Name Description T2[7:0] Timer 2 Low Byte [7:0] The TL2 register is the low byte of the 16-bit counting register of Timer 2. Sep.
  • Page 210 ML51/ML54/ML56 TH2 – Timer 2 High Byte Register SFR Address Reset Value CDH, Page 0 0000_0000 b T2[15:8] Name Description T2[15:8] Timer 2 High Byte [7:0] The TH2 register is the high byte of the 16-bit counting register of Timer 2. Sep.
  • Page 211 ML51/ML54/ML56 ADCMPL – ADC Compare Low Byte Register SFR Address Reset Value ADCMPL CEH, Page 0 0000_0000 b ADCMP[3:0] Name Description [7:4] Reserved [3:0] ADCMP[3:0] ADC Compare Low Byte The least significant 4 bits of the ADC compare value stores in this register. Sep.
  • Page 212 ML51/ML54/ML56 AINDIDS0 – ADC Channel Digital Input Disconnect Register SFR Address Reset Value AINDIDS0 CEH, Page 1 0000_0000 b AIN7DIDS AIN6DIDS AIN5DIDS AIN4DIDS AIN3DIDS AIN2DIDS AIN1DIDS AIN0DIDS Name Description AINnDIDS ADC Channel Digital Input Disable [7:0] 0 = Enabled digital input at ADC channel n. 1 = Disabled digital input at ADC channel n .
  • Page 213 ML51/ML54/ML56 AINDIDS1 – ADC Channel Digital Input Disconnect Register SFR Address Reset Value AINDIDS1 CEH, Page 2 0000_0000 b AIN15DIDS AIN14DIDS AIN13DIDS AIN12DIDS AIN11DIDS AIN10DIDS Name Description AINnDIDS ADC Channel Digital Input Disable [7:0] 0 = Enabled digital input at ADC channel n. 1 = Disabled digital input at ADC channel n .
  • Page 214 ML51/ML54/ML56 PWM0FBS – PWM Brake Source Select Register SFR Address Reset Value PWM0FBS CEH, Page 3 0000_0000 b PWM0FBS Name Description PWM0FBS PWM Brake Source Select [1:0] 00 = GPIO ( depended on Multi-function register select). 01 = Reserved 10 = ACMP0 11 = ACMP1 Sep.
  • Page 215 ML51/ML54/ML56 ADCMPH – ADC Compare High Byte Register SFR Address Reset Value ADCMPH CFH, Page 0 0000_0000 b ADCMP[11:4] Name Description ADCMP[11:4] ADC Compare High Byte [7:0] The most significant 8 bits of the ADC compare value stores in this register. Sep.
  • Page 216 ML51/ML54/ML56 I2CnADDRM – I2Cn Address Mask Register SFR Address Reset Value I2C0ADDRM CFH, Page 2 0000_0000 b I2C1ADDRM D7H, Page 2 0000_0000 b Mask Bit 7 Mask Bit 6 Mask Bit 5 Mask Bit 4 Mask Bit 3 Mask Bit 2 Mask Bit 1 Mask Bit 0 Name...
  • Page 217 ML51/ML54/ML56 PSW – Program Status Word Register SFR Address Reset Value D0H, All pages, Bit addressable 0000_0000 b Name Description Carry Flag For a adding or subtracting operation, CY will be set when the previous operation resulted in a carry-out from or a borrow-in to the Most Significant bit, otherwise cleared. If the previous operation is MUL or DIV, CY is always 0.
  • Page 218 ML51/ML54/ML56 Name Description User Flag 1 The general purpose flag that can be set or cleared by user via software. Parity Flag Set to 1 to indicate an odd number of ones in the accumulator. Cleared for an even number of ones.
  • Page 219 ML51/ML54/ML56 PWM0CON0 – PWM Control Register0 Register SFR Address Reset Value PWM0CON0 D1H, Page 0 0000_0000 b PWM0RUN LOAD PWMF CLRPWM Name Description PWM0RUN PWM0 Run Enable 0 = PWM0 stays in idle. 1 = PWM0 starts running. LOAD PWM New Period and Duty Load This bit is used to load period and duty Register Description in their buffer if new period or duty value needs to be updated.
  • Page 220 ML51/ML54/ML56 PWMnCON0 – PWM Control Register0 Register SFR Address Reset Value PWM1CON0 9CH, Page 2 0000_0000 b PWM2CON0 C4H, Page 2 0000_0000 b PWM3CON0 D4H, Page 2 0000_0000 b PWMnRUN LOAD PWMF CLRPWM Name Description PWMnRUN PWMn Run Enable 0 = PWM stays in idle. 1 = PWM starts running.
  • Page 221 ML51/ML54/ML56 PWMnPH – PWM Period High Byte Register SFR Address Reset Value PWM0PH D1H, Page 1 0000_0000 b PWM1PH 86H, Page 2 0000_0000 b PWM2PH B9H, Page 2 0000_0000 b PWM3PH C9H, Page 2 0000_0000 b PWMnP[15:8] Name Description [7:0] PWMnP[15:8] PWM Period High Byte This byte with PWMnPL controls the period of the PWM generator signal.
  • Page 222 ML51/ML54/ML56 ACMPCR0 – Analog Comparator Control Register 0 Register SFR Address Reset Value ACMPCR0 D2H, Page 0 0000_0000 b POSSEL NEGSEL WKEN HYSEN ACMPIE ACMPEN Name Description POSSEL Comparator 0 Positive Input Selection [7:6] 00 = ACMP0_P0 (P2.5) pin. 01 = ACMP0_P1 (P2.3) pin. 10 = ACMP0_P2 (P2.1) pin.
  • Page 223 ML51/ML54/ML56 ACMPCR1 – Analog Comparator Control Register 1 Register SFR Address Reset Value ACMPCR1 D3H, Page 0 0000_0000 b POSSEL NEGSEL WKEN HYSEN ACMPIE ACMPEN Name Description POSSEL Comparator 1 Positive Input Selection [7:6] 00 = ACMP1_P0 (P2.5) pin. 01 = ACMP1_P1 (P2.3) pin. 10 = ACMP1_P2 (P2.1) pin.
  • Page 224 ML51/ML54/ML56 ACMPSR – Analog Comparator Status Register Register SFR Address Reset Value ACMPSR D4H, Page 0 0000_0000 b ACMP1O ACMP1IF ACMP0O ACMP0IF Name Description [7:4] Reserved ACMP1O Comparator 1 Output Synchronized to the PCLK to allow reading by software. Cleared when the comparator 1 is disabled, i.e.
  • Page 225 ML51/ML54/ML56 – ACMP Reference Voltage Control Register ACMPV Register SFR Address Reset Value ACMPV D5H, Page 0 0000_0000 b CRV1CTL[2:0] CRV0CTL[2:0] Name Description Reserved [6:4] CRV1CTL[2:0] Comparator 1 Reference Voltage Setting CRV1 = CRV source voltage * (2/12+CRV1CTL/12). Reserved [2:0] CRV0CTL[2:0] Comparator 0 Reference Voltage Setting CRV0 = CRV source voltage * (2/12+CRV0CTL/12).
  • Page 226 ML51/ML54/ML56 SCnCR0 – SC Control Register Register SFR Address Reset Value SC0CR0 D6H, Page 0 0000_0000 b SC1CR0 E6H, Page 2 0000_0000 b RXBGTEN CONSEL AUTOCEN TXOFF RXOFF SCEN Name Description Stop Bit Length This field indicates the length of stop bit. 0 = The stop bit length is 2 ETU.
  • Page 227 ML51/ML54/ML56 Name Description AUTOCEN Auto Convention Enable Bit 0 = Auto-convention Disabled. 1 = Auto-convention Enabled. When hardware receives TS in answer to reset state and the TS is direct convention, CONSEL(SCnCR0[4]) will be set to 0 automatically, otherwise if the TS is inverse convention, and CONSEL (SCnCR0[4]) will be set to 1.
  • Page 228 ML51/ML54/ML56 PWM0NP – PWM Negative Polarity Register SFR Address Reset Value PWM0NP D6H, Page 1 0000_0000 b PNP5 PNP4 PNP3 PNP2 PNP1 PNP0 Name Description PNPn PWMn Negative Polarity Output Enable [5:0] 0 = PWMn signal outputs directly on PWMn pin. 1 = PWMn signal outputs inversely on PWMn pin.
  • Page 229 ML51/ML54/ML56 SCnCR1 – SC Control Register Register SFR Address Reset Value SC0CR1 D7H, Page 0 0000_0000 b SC1CR1 E7H, Page 2 0000_0000 b PBOFF WLS[1:0] TXDMAEN RXDMAEN CLKKEEP UARTEN Name Description Odd Parity Enable Bit 0 = Even number of logic 1’s are transmitted or check the data word and parity bits in receiving mode.
  • Page 230 ML51/ML54/ML56 Name Description UARTEN UART Mode Enable Bit 0 = Smart Card mode. 1 = UART mode. Note 1:When operating in UART mode, user must set CONSEL (SCnCR0[4]) = 0 and AUTOCEN(SCnCR0[3]) = 0. Note 2:When operating in Smart Card mode, user must set UARTEN(SCnCR1 [0]) = 0. Note 3:When UART is enabled, hardware will generate a reset to reset FIFO and internal state machine.
  • Page 231 ML51/ML54/ML56 PWM0FBD – PWM Fault Brake Data Register SFR Address Reset Value PWM0FBD D7H, Page 1 0000_0000 b FBINLS FBD5 FBD4 FBD3 FBD2 FBD1 FBD0 Name Description Fault Brake Flag This flag is set when FBINEN is set as 1 and FB pin detects an edge, which matches FBINLS (PWM0FBD.6) selection.
  • Page 232 ML51/ML54/ML56 SCnDR – SC Data Register Register SFR Address Reset Value SC0DR D9H, Page 0 0000_0000 b SC1DR D9H, Page 2 0000_0000 b SCnDR[7:0] Name Description [7:0] SCnDR[7:0] SC / UART Buffer Data This byte is used for transmitting or receiving data on SC / UART bus. A write of this byte is a write to the shift register.
  • Page 233 ML51/ML54/ML56 PWMnPL – PWM Period Low Byte Register SFR Address Reset Value PWM0PL D9H, Page 1 0000_0000 b PWM1PL 99H, Page 2 0000_0000 b PWM2PL C1H, Page 2 0000_0000 b PWM3PL D1H, Page 2 0000_0000 b PWMnP[7:0] Name Description [7:0] PWMnP[7:0] PWMn Period Low Byte This byte with PWMnPH controls the period of the PWM generator signal.
  • Page 234 ML51/ML54/ML56 SCnEGT – SC Extra Guard Time Register Register SFR Address Reset Value SC0EGT DAH, Page 0 0000_0000 b SC1EGT DAH, Page 2 0000_0000 b SCnEGT[7:0] Name Description [7:0] SCnEGT[7:0] SC Extra Guard Time This field indicates the extra guard timer value. Note: The counter is ETU base .
  • Page 235 ML51/ML54/ML56 PWMnCxL – PWM0/1/2/3 Channel 0~5 Duty Low Byte n=0,1,2,3; x=0,1,2,3,4,5 Register SFR Address Reset Value PWM0C0L DAH, Page 1 0000_0000 b PWM0C1L DBH, Page 1 0000_0000 b PWM0C2L DCH, Page 1 0000_0000 b PWM0C3L DDH, Page 1 0000_0000 b PWM0C4L CCH, Page 1 0000_0000 b...
  • Page 236 ML51/ML54/ML56 SCnETURD0 – SCn ETU Rate Divider Register Register SFR Address Reset Value SC0ETURD0 DBH, Page 0 0111_0011 b SC1ETURD0 DBH, Page 2 0111_0011 b ETURDIV[7:0] Name Description [7:0] ETURDIV[7:0] LSB Bits of ETU Rate Divider The field indicates the LSB of clock rate divider. The real ETU is ETURDIV[11:0] + 1.
  • Page 237 ML51/ML54/ML56 SCnETURD1 –SC ETU Rate Divider Register Register SFR Address Reset Value SC0ETURD1 DCH, Page 0 0011_0001 b SC1ETURD1 DCH, Page 2 0011_0001 b SCDIV[2:0] ETURDIV[11:8] Name Description Reserved [6:4] SCDIV[2:0] SC Clock Divider 000 = F is F 001 = F is F 010 = F is F...
  • Page 238 ML51/ML54/ML56 ScnIE – SC Interrupt Enable Control Register Register SFR Address Reset Value SC0IE DDH, Page 0 0000_0000 b SC1IE DDH, Page 2 0000_0000 b ACERRIEN BGTIEN TERRIEN TBEIEN RDAIEN Name Description [7:5] Reserved ACERRIEN Auto Convention Error Interrupt Enable Bit This field is used to enable auto-convention error interrupt.
  • Page 239 ML51/ML54/ML56 ScnIS – SC Interrupt Status Register Register SFR Address Reset Value SC0IS DEH, Page 0 0000_0010 b SC1IS DEH, Page 2 0000_0010 b Tx_Er ACERRIF BGTIF TERRIF TBEIF RDAIF Name Description [7:6] Reserved. Tx_Er TX transmit error flag ACERRIF Auto Convention Error Interrupt Status Flag (Read Only) This field indicates auto convention sequence error.
  • Page 240 ML51/ML54/ML56 SCnTSR – SC Transfer Status Register Register SFR Address Reset Value SC0TSR DFH, Page 0 0000_1010 b SC1TSR DFH, Page 2 0000_1010 b TXEMPTY TXOV RXEMPTY RXOV Name Description Transmit /Receive in Active Status Flag (Read Only) 0 = This bit is cleare automatically when TX/RX transfer is finished 1 = This bit is set by hardware when TX/RX transfer is in active.
  • Page 241 ML51/ML54/ML56 Name Description RXOV RX Overflow Error Status Flag (Read Only) This bit is set when RX buffer overflow. Note: This bit is read only, but it can be cleared by writing 0 to it. Sep. 01, 2020 Page 241 of 719 Rev 2.00...
  • Page 242 ML51/ML54/ML56 PWMnCON1 – PWM Control 1 Register SFR Address Reset Value PWM0CON1 DFH, Page 1 0000_0000 b PWM1CON1 9DH, Page 2 0000_0000 b PWM2CON1 C5H, Page 2 0000_0000 b PWM3CON1 D5H, Page 2 0000_0000 b PWMMOD[1:0] PWMTYP FBINEN PWMDIV[2:0] Name Description [7:6] PWMMOD[1:0]...
  • Page 243 ML51/ML54/ML56 Name Description [2:0] PWMDIV[2:0] PWM Clock Divider This field decides the pre-scale of PWM clock source. 000 = 1/1. 001 = 1/2 010 = 1/4. 011 = 1/8. 100 = 1/16. 101 = 1/32. 110 = 1/64. 111 = 1/128. Sep.
  • Page 244 ML51/ML54/ML56 A or ACC – Accumulator (Bit-addressable) Register SFR Address Reset Value E0H, All pages, Bit addressable 0000_0000 b ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 Name Description ACC[7:0] Accumulator [7:0] The A or ACC register is the standard 80C51 accumulator for arithmetic operation. Sep.
  • Page 245 ML51/ML54/ML56 ADCCON1 – ADC Control 1 Register SFR Address Reset Value ADCCON1 E1H, Page 0 0000_0000 b CONT ETGTYP[1:0] ADCEX ADCEN Name Description [7:6] Reserved ADC Half Done Interrupt Enable 0 = ADC interrupt is not set while half of A/D conversions are complete in continue mode 1 = ADC interrupt is set while half of A/D conversions are complete in continue mode CONT ADC Continue Sampling Select...
  • Page 246 ML51/ML54/ML56 CAPCON0 – Input Capture Control 0 Register SFR Address Reset Value CAPCON0 E1H, Page 1 0000_0000b CAPEN2 CAPEN1 CAPEN0 CAPF2 CAPF1 CAPF0 Name Description Reserved CAPEN2 Input Capture 2 Enable 0 = Input capture channel 2 Disabled. 1 = Input capture channel 2 Enabled. CAPEN1 Input Capture 1 Enable 0 = Input capture channel 1 Disabled.
  • Page 247 ML51/ML54/ML56 ADCCON2 – ADC Control 2 Register SFR Address Reset Value ADCCON2 E2H, Page 0 0000_0000 b ADFBEN ADCMPOP ADCMPEN ADCMPO ADCAQT[2:0] ADCDLY.8 Name Description ADFBEN ADC Compare Result Asserting Fault Brake Enable 0 = ADC asserting Fault Brake Disabled. 1 = ADC asserting Fault Brake Enabled.
  • Page 248 ML51/ML54/ML56 CAPCON1 – Input Capture Control 1 Register SFR Address Reset Value CAPCON1 E2H, Page 1 0000_0000b CAP2LS[1:0] CAP1LS[1:0] CAP0LS[1:0] Name Description [7:6] Reserved CAP2LS[1:0] Input Capture 2 Level Select [5:4] 00 = Falling edge. 01 = Rising edge. 10 = Either rising or falling edge. 11 = Reserved.
  • Page 249 ML51/ML54/ML56 ADCDLY – ADC Trigger Delay Counter Register SFR Address Reset Value ADCDLY E3H, Page 0 0000_0000 b ADCDLY[7:0] Name Description ADCDLY[7:0] ADC External Trigger Delay Counter Low Byte [7:0] This 8-bit field combined with ADCCON2.0 forms a 9-bit counter. This counter inserts a delay after detecting the external trigger.
  • Page 250 ML51/ML54/ML56 CAPCON2 – Input Capture Control 2 Register SFR Address Reset Value CAPCON2 E3H, Page 1 0000_0000b ENF2 ENF1 ENF0 Name Description Reserved ENF2 Enable Noise Filer on Input Capture 2 0 = Noise filter on input capture channel 2 Disabled. 1 = Noise filter on input capture channel 2 Enabled.
  • Page 251 ML51/ML54/ML56 ADCBAH – ADC RAM Base Address High Byte Register SFR Address Reset Value ADCBAH E4H, Page 0 0000_0000 b ADCBA[11:8] Name Description [7:4] Reserved [3:0] ADCBA[11:8] ADC RAM Base Address (High Byte) The most significant 4 bits of RAM base address to store ADC continue sampling data. RAM base address ADCBA[11:0] = {ADCBAH[3:0], ADCBAL[7:0]} Sep.
  • Page 252 ML51/ML54/ML56 CnL – Capture Low Byte, n = 0,1,2 Register SFR Address Reset Value E4H, Page 1 0000_0000 b E6H, Page 1 0000_0000 b EDH, Page 1 0000_0000 b CnL[7:0] Name Description [7:0] CnL[7:0] Input Capture 0 Result Low Byte The C0L register is the low byte of the 16-bit result captured by input capture 0.
  • Page 253 ML51/ML54/ML56 ADCSN – ADC Sampling Number Register SFR Address Reset Value ADCSN E5H, Page 0 0000_0000 b ADCSN[7:0] Name Description ADCSN[7:0] ADC Sampling Number [7:0] The total sampling numbers for ADC continue sampling select. Total sampling number= ADCSN[7:0] + 1 Sep.
  • Page 254 ML51/ML54/ML56 CnH – Capture n High Byte, n = 1,2,3 Register SFR Address Reset Value E5H, Page 1 0000_0000 b E7H, Page 1 0000_0000 b EEH, Page 1 0000_0000 b CnH[7:0] Name Description [7:0] CnH[7:0] Input Capture n Result High Byte The CnH register is the high byte of the 16-bit result captured by input capture n.
  • Page 255 ML51/ML54/ML56 ADCCN – ADC Current Sampling Number Register SFR Address Reset Value ADCCN E6H, Page 0 0000_0000 b ADCCN[7:0] Name Description [7:0] ADCCN[7:0] ADC Current Sampling Number The current sampling numbers for ADC continue sampling select. The current sampling number= ADCCN[7:0] + 1 Sep.
  • Page 256 ML51/ML54/ML56 ADCSR – ADC Status Register Register SFR Address Reset Value ADCSR E7H, Page 0 0000_0000 b SLOW ADCDIV[2:0] CMPHIT HDONE FDONE Name Description SLOW ADC Slow Speed Selection This bit is used to select ADC low speed. 0 = high speed 500 R/W 1 = low speed 200 R/W [6:4] ADCDIV[2:0]...
  • Page 257 ML51/ML54/ML56 DMAnTSR – PDMAn Transfer Status Register Register SFR Address Reset Value DMA0TSR E9H, Page 0 0000_0000 b DMA1TSR F1H, Page 0 0000_0000 b DMA2TSR B1H, Page 2 0000_0000 b DMA3TSR A9H, Page 2 0000_0000 b HDONE FDONE Name Description [7:3] Reserved PDMA in Active Status Flag (Read Only)
  • Page 258 ML51/ML54/ML56 PICON – Pin Interrupt Control Register SFR Address Reset Value PICON E9H, Page 1 0000 _0000 b PIT7 PIT6 PIT5 PIT4 PIT3 PIT2 PIT1 PIT0 Name Description PIT7 Pin Interrupt Channel 7 Type Select This bit selects which type that pin interrupt channel 7 is triggered. 0 = Level triggered.
  • Page 259 ML51/ML54/ML56 Name Description PIT0 Pin Interrupt Channel 0 Type Select This bit selects which type that pin interrupt channel 0 is triggered. 0 = Level triggered. 1 = Edge triggered. Sep. 01, 2020 Page 259 of 719 Rev 2.00...
  • Page 260 ML51/ML54/ML56 MTMnDA – Memory to Memory Destination Address Low Byte Register SFR Address Reset Value MTM0DA EAH, Page 0 0000_0000 b MTM1DA F2H, Page 0 0000_0000 b MTM2DA B7H, Page 2 0000_0000 b MTM3DA AFH, Page 2 0000_0000 b MTMnDA[7:0] Name Description [7:0]...
  • Page 261 ML51/ML54/ML56 PINEN – Pin Interrupt Negative Polarity Enable. Register SFR Address Reset Value PINEN EAH, Page 1 0000_0000 b PINEN7 PINEN6 PINEN5 PINEN4 PINEN3 PINEN2 PINEN1 PINEN0 Name Description PINENn Pin Interrupt Channel n Negative Polarity Enable [7:0] This bit enables low-level/falling edge triggering pin interrupt channel n. The level or edge triggered selection depends on each control bit PITn in PICON.
  • Page 262 ML51/ML54/ML56 Sep. 01, 2020 Page 262 of 719 Rev 2.00...
  • Page 263 ML51/ML54/ML56 PIPEN – Pin Interrupt Positive Polarity Enable. Register SFR Address Reset Value PIPEN EBH, Page 1 0000_0000 b PIPEN7 PIPEN6 PIPEN5 PIPEN4 PIPEN3 PIPEN2 PIPEN1 PIPEN0 Name Description PIPENn Pin Interrupt Channel n Positive Polarity Enable [7:0] This bit enables high-level/rising edge triggering pin interrupt channel n. The level or edge triggered selection depends on each control bit PITn in PICON.
  • Page 264 ML51/ML54/ML56 EIP0 – Extensive Interrupt Priority Register SFR Address Reset Value EIP0 EFH, Page 0 0000_0000 b PSPI0 PWDT PPWM0 PCAP PI2C0 Name Description Timer 2 interrupt priority low bit PSPI0 SPI0 interrupt priority low bit Fault Brake interrupt priority low bit PWDT WDT interrupt priority low bit PPWM0...
  • Page 265 ML51/ML54/ML56 B – B Register (Bit-addressable) Register SFR Address Reset Value F0H, All pages, Bit addressable 0000_0000 b Name Description B[7:0] B Register [7:0] The B register is the other accumulator of the standard 80C51 .It is used mainly for MUL and DIV instructions.
  • Page 266 ML51/ML54/ML56 LCDCPUMP – LCD Charge Pump Voltage Set Register SFR Address Reset Value LCDCPUMP F1H, Page 3 0000_0000 b VCP_SEL[5:0] Address: F1H, Page 3 Reset value: 0000 0000b Name Description [7:6] Reserved [5:0] VCP_SEL[5:0] Charge Pump Voltage Set 000000 = 5.2V 000101 = 5.0V 001010 = 4.8V 010000 = 4.6V...
  • Page 267 ML51/ML54/ML56 SPInCR0 – Serial Peripheral Control Register0 Register SFR Address Reset Value SPI0CR0 F3H, Page 0 0000_0000 b SPI1CR0 F9H, Page 0 0000_0000 b SSOE SPIEN LSBFE MSTR CPOL CPHA SPR1 SPR0 Name Description SSOE Slave Select Output Enable This bit is used in combination with the DISMODF (SPInSR.3) bit to determine the feature of ̅̅̅̅...
  • Page 268 ML51/ML54/ML56 Name Description [1:0] SPR[1:0] SPI Clock Rate Select These two bits select four grades of SPI clock divider. The clock rates below are illustrated under F = 24 R/W condition. SPR3 SPR2 SPR1 SPR0 Divider SPI clock rate 12M bit/s 6M bit/s 3M bit/s 1.5M bit/s...
  • Page 269 ML51/ML54/ML56 SPInCR1 – Serial Peripheral Control Register1 Register SFR Address Reset Value SPI0CR1 F3H, Page 1 0000_0000 b SPI1CR1 FAH, Page 0 0000_0000 b SPR3 SPR2 TXDMAEN RXDMAEN SPIS1 SPIS0 Name Description [7:6] Reserved. [5:4] SPR[3:2] SPI Clock Rate Select These two bits select four grades of SPI clock divider.
  • Page 270 ML51/ML54/ML56 Name Description TXDMAEN SPI TX DMA Enable This bit enables the SPI TX operating by through PDMA transfer, TX data needs to be ready in XRAM before SPI TX starting. 0 = SPI TX DMA Disabled 1 = SPI TX DMA Enabled RXDMAEN SPI RX DMA Enable This bit enables the SPI RX operating by through PDMA transfer, RX data are saved in XRAM...
  • Page 271 ML51/ML54/ML56 SPInSR – Serial Peripheral Status Register Register SFR Address Reset Value SPI0SR F4H, Page 0 0000_0000 b SPI1SR FBH, Page 0 0000_0000 b SPIF WCOL SPIOVF MODF DISMODF DISSPIF TXBFF Name Description SPIF SPI Complete Flag This bit is set to logic 1 via hardware while an SPI data transfer is complete or an receiving data has been moved into the SPI read buffer.
  • Page 272 ML51/ML54/ML56 SPInDR – Serial Peripheral Data Register Register SFR Address Reset Value SPI0DR F5H, Page 0 0000_0000 b SPI1DR FCH, Page 0 0000_0000 b SPInDR[7:0] Name Description SPInDR[7:0] Serial Peripheral Data [7:0] This byte is used for transmitting or receiving data on SPI bus. A write of this byte is a write to the shift register.
  • Page 273 ML51/ML54/ML56 DMAnBAH – PDMAn XRAM Base Address High Byte Register SFR Address Reset Value DMA0BAH F6H, Page 0 0000_0000 b DMA1BAH FDH, Page 0 0000_0000 b DMA2BAH B2H, Page 2 0000_0000 b DMA3BAH AAH, Page 2 0000_0000 b MTMDA[7:4] XRAMA[7:4] Name Description [7:4]...
  • Page 274 ML51/ML54/ML56 EIPH0 – Extensive Interrupt Priority High Register SFR Address Reset Value EIPH0 F7H, Page 0 0000_0000 b PT2H PSPI0H PFBH PWDTH PPWM0H PCAPH PPIH PI2C0H Name Description PT2H Timer 2 interrupt priority high bit PSPI0H SPI0 interrupt priority high bit PFBH Fault Brake interrupt priority high bit PWDTH...
  • Page 275 ML51/ML54/ML56 S1CON – Serial Port 1 Control Register SFR Address Reset Value S1CON F8H, All pages, Bit addressable 0000_0000 b SM0_1/FE_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 Name Description SM0_1/FE_1 Serial Port 1 Mode Select SMOD0 _ 1 (T3CON.6) = 0: See Table 6.9-2 Serial Port 1 Mode / baud rate Description for details.
  • Page 276 ML51/ML54/ML56 Name Description RB8_1 Received Bit The bit identifies the logic level of the 9 received bit in serial port 1 Mode 2 or 3. In Mode 1, RB8 _ 1 is the logic level of the received stop bit. SM2 _ 1 bit as logic 1 has restriction for exception.
  • Page 277 ML51/ML54/ML56 PWM0DTEN – PWM Dead-time Enable (TA Protected) Register SFR Address Reset Value PWM0DTEN F9H, Page 1, TA protected 0000_0000 b PWMnDTCNT.8 PDT45EN PDT23EN PDT01EN Name Description [7:5] Reserved PWMnDTCNT.8 PWM Dead-Time Counter Bit 8 See PWMnDTCNT register. Reserved PDT45EN PWM4/5 Pair Dead-Time Insertion Enable This bit is valid only when PWM4/5 is under complementary mode.
  • Page 278 ML51/ML54/ML56 LCDCON – LCD Control Register SFR Address Reset Value LCDCON F9H, Page 3 0000_0000 b LCDEN TYPE BIAS[1:0] DUTY[1:0] LCD_IE Name Description LCDEN LCD Enable 0 = LCD circuit OFF. Each COM and SEG pin functions as general purpose I/O and its multi-functions other than LCD.
  • Page 279 ML51/ML54/ML56 PWM0DTCNT – PWM Dead-time Counter (TA Protected) Register SFR Address Reset Value PWM0DTCNT FAH, Page 1, TA protected 0000_0000 b PWM0DTCNT[7:0] Name Description PWM0DTCNT[7:0] PWM Dead-Time Counter Low Byte [7:0] This 8-bit field combined with PWMnDTEN .4 forms a 9-bit PWM dead-time counter PWM0DTCNT.
  • Page 280 ML51/ML54/ML56 LCDCLK – LCD Clock Control Register SFR Address Reset Value LCDCLK FAH, Page 3 0000_0000 b LCDCKS DISP LCDDIV[2:0] Name Description [7:5] Reserved LCDCKS LCD Clock Source Select 0 = LIRC/2 1 = LXT/2 DISP DISP The LCD display keeps display on or display off during chip power-down mode. If LXT is used as the LCD clock source, user should turn on LXT first by software.
  • Page 281 ML51/ML54/ML56 PWMxMEN – PWMnCx Mask Enable, n=0,1,2,3;x=0,1,2,3,4,5 Register SFR Address Reset Value PWM0MEN FBH, Page 1 0000_0000 b PWM1MEN 8DH, Page 2 0000_0000 b PWM2MEN BDH, Page 2 0000_0000 b PWM3MEN CDH, Page 2 0000_0000 b PMEN5 PMEN4 PMEN3 PMEN2 PMEN1 PMEN0 Name...
  • Page 282 ML51/ML54/ML56 LCDPTR – LCD Data Pointer Register SFR Address Reset Value LCDPTR FBH, Page 3 0000_0000 b LCDPTR[4:0] Name Description [7:5] Reserved [4:0] LCDPTR[4:0] LCD Data Pointer This field determines which LCD display data register is accessed by LCDDAT. User should fill the target pointer value in LCDPTR before accessing LCDDAT.
  • Page 283 ML51/ML54/ML56 PWMnMD – PWM Mask Data Register SFR Address Reset Value PWM0MD FCH, Page 1 0000_0000 b PWM1MD 8CH, Page 2 0000_0000 b PWM2MD BCH, Page 2 0000_0000 b PWM3MD CCH, Page 2 0000_0000 b PMD5 PMD4 PMD3 PMD2 PMD1 PMD0 Name Description...
  • Page 284 ML51/ML54/ML56 LCDDAT – LCD Data Register SFR Address Reset Value LCDDAT FCH, Page 3 0000_0000 b LCDDAT[7:0] Name Description LCDDAT[7:0] LCD Data [7:0] The value written into this register will be displayed to the corresponding LCD SEG and COM pins pointed by LCDPTR. 0 = LCD pixel is cleared.
  • Page 285 ML51/ML54/ML56 LVRFLTEN – LVR Filter Enable (TA Protected) Register SFR Address Reset Value LVRFLTEN FDH, Page 1, TA protected 0000_0000 b LVRFLTEN[7:0] Address: FDH, Page 1 reset value: 0000 0000b Name Description LVRFLTEN[7:0] LVR18 Filter Enable [7:0] To first writing 5AH to the LVRFLTEN and immediately followed by a writing of A5H. Others = Disabled.
  • Page 286 ML51/ML54/ML56 LCDPWR – LCD Power Saving Mode Register SFR Address Reset Value LCDPWR FDH, Page 3 0000_0000 b PWR_SAVING[1:0] Name Description [7:2] Reserved [1:0] PWR_SAVING[1:0] LCD_PWR_SAVING LCD driving cycle select, turn on timing decide the driving current. 00 = always ON. No power saving 01 = Turns on 1/4 cycle 10 = Turns on 2/4 cycle 11 = Turns on 3/4 cycle...
  • Page 287 ML51/ML54/ML56 EIP1 – Extensive Interrupt Priority 1 Register SFR Address Reset Value EIP1 FEH, Page 0 0000_0000 b PSPI1 PDMA1 PDMA0 PSMC PWKT Name Description PSPI1 SPI1 interrupt priority low bit PDMA1 PDMA1 interrupt priority low bit PDMA0 PDMA0 interrupt priority low bit PSMC SMC interrupt priority low bit Hard fault interrupt priority low bit...
  • Page 288 ML51/ML54/ML56 LCDBL – LCD Blink Register SFR Address Reset Value LCDBL FEH, Page 3 0000_0000 b BLINK BLF[2:0] Name Description [7:4] Reserved BLINK LCD BLINK 0 = LCD always on 1 = LCD blink [2:0] BLF[2:0] BLINK Frequency LCDCKS[1:0] = 00 FBLINK = FLXT/2(14+ BL_Time[2:0]) LCDCKS[1:0] = 01 FBLINK = FLIRC/2(14+ BL_Time[2:0])
  • Page 289 ML51/ML54/ML56 EIPH1 – Extensive Interrupt Priority High 1 Register SFR Address Reset Value EIPH1 FFH, Page 0 0000_0000 b PSPI1H PDMA1H PDMA0H PSMCH PHFH PWKTH PT3H PS1H Name Description PSPI1H SPI1 interrupt priority high bit PDMA1H PDMA1 interrupt priority high bit PDMA0H PDMA0 interrupt priority high bit PSMCH...
  • Page 290 ML51/ML54/ML56 LVRDIS – LVR Disable (TA Protected) Register SFR Address Reset Value LVRDIS FFH, Page 0, TA protected 0000_0000 b LVRDIS[7:0] Name Description LVRDIS[7:0] LVR Disable [7:0] To first writing 5AH to the LVRDIS and immediately followed by a writing of A5H will disable LVR.
  • Page 291 ML51/ML54/ML56 LCDMODE – LCD Resister Mode Register SFR Address Reset Value LCDMODE FFH, Page 3 0000_0000 b R_MODE BUF_EN VLCD_MODE[1:0] Name Description R_MODE Resister Mode 0 = LCD none resister mode 1 = LCD resister mode BUF_EN Buffer Enable 0 = buffer off 1 = buffer on [5:2] Reserved...

  • Page 292: System Manager

    ML51/ML54/ML56 6.2 System Manager 6.2.1 Clock System The ML51/ML54/ML56 Series has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. The ML51/ML54/ML56 Series provides five options of the system clock sources including internal oscillator, crystal/resonator, or external clock from X pin via software.
  • Page 293 ML51/ML54/ML56 OSC[2:0] as [1,0,x], LIRC will be selected as the system clock. Note that after the ML51/ML54/ML56 Series is powered, HIRC and LIRC will be both enabled and HIRC is default selected as the system clock source. While using internal oscillators, X , X32 and X32 automatically switch as one...
  • Page 294 ML51/ML54/ML56 XLTCON – XLT Clock Control (TA Protected) Register SFR Address Reset Value XLTCON 85H, Page 1, TA protected 0111_0111b HSCH HXSG[6:4] LXSG[1:0] Name Description HSCH HXT Schmitt Trigger Select 0 = disable 1 = enable [6:4] HXSG[6:4] HXT Gain Value Select 000 = L0 mode (smallest value) 001 = L1 mode 010 = L2 mode...
  • Page 295 ML51/ML54/ML56 is concerned. Note that if not following the steps above, the hardware will take certain actions to deal with such illegal operations as follows. 1. If user tries to disable the current clock source by changing CKEN value, the device will ignore this action.
  • Page 296 ML51/ML54/ML56 CKSWT – Clock Switch (TA Protected) Register SFR Address Reset Value CKSWT 96H, PAGE 0, TA protected 0011 _0000 b HXTST LXTST HIRCST LIRCST ECLKST OSC[2:0] Address: 96H, PAGE 0 Reset value: 0011 0000b Name Description HXTST High Speed External Crystal/Resonator 4 R/W to 24 R/W Status 0 = High speed external crystal/resonator is not stable or is disabled.
  • Page 297 ML51/ML54/ML56 CKEN – Clock Enable (TA Protected) Register SFR Address Reset Value CKEN 97H, PAGE 0, TA protected 0011_0100 b EHXTEN ELXTEN HIRCEN LIRCEN ECLKEN CKSWTF Address: 97H, Page 0 Reset value: 0011 0100b Name Description EHXTEN External High-Speed Crystal/Resonator Enable 1 = High-speed external crystal/resonator 4 R/W to 24 R/W Enabled.
  • Page 298 ML51/ML54/ML56 6.2.1.5 System Clock Divider The oscillator frequency (F ) can be divided down, by an integer, up to 1/510 by configuring a dividing register, CKDIV, to provide the system clock (F ). This feature makes it possible to temporarily run the MCU at a lower rate, reducing power consumption. By dividing the clock, the MCU can retain the ability to respond to events other than those that can cause interrupts (i.e.
  • Page 299 ML51/ML54/ML56 CKDIV – Clock Divider Register SFR Address Reset Value CKDIV C1H, Page 1 0000_0000b CKDIV[7:0] Name Description CKDIV[7:0] Clock Divider [7:0] The system clock frequency FSYS follows the equation below according to CKDIV value. , while CKDIV = 00H, and ×...
  • Page 300 ML51/ML54/ML56 CKCON – Clock Control Register SFR Address Reset Value CKCON 8EH, Page 0 1000_0000b FASTWK PWMCKS T1OE T0OE CLOEN Address: 8EH, Page 0 Reset value: 1000 0000b Name Description CLOEN System Clock Output Enable 0 = System clock output Disabled. 1 = System clock output Enabled from CLO pin.

  • Page 301: Power Management

    ML51/ML54/ML56 6.2.2 Power Management The ML51/ML54/ML56 Series has several features that help user to control the power consumption of the device. Table 6.2-1 Table 6.2-1 Power Mode Tablelists all power mode at ML51/ML54/ML56 Series to save the power consumption. For a stable current consumption, the state and mode of each pin should be taken care of.
  • Page 302 ML51/ML54/ML56 PCON – Power Control Register SFR Address Reset Value POR: 0001_0000b PCON 87H, All pages Others: 000U _0000b SMOD SMOD0 Address: 87H, All pagess POR reset value: 0001 000b, other reset value: 000U 0000b Name Description Low Power Run Mode 0 = disable 1 = enable Note: If PD = 1 and LPR = 1 at the same time, LPR is invalid, CPU will enter Power-down...
  • Page 303 ML51/ML54/ML56 6.2.2.2 Low Power Run Mode The CPU and the selected peripherals are running with a low speed oscillator (LXT or LIRC). At first system clock should be switch to LXT or LIRC. And then put the device into Low power run mode by writing 1 to the bit LPR (PCON.5) .

  • Page 304: Power Monitering And Reset

    ML51/ML54/ML56 6.2.3 Power Monitering and Reset The ML51/ML54/ML56 Series has several options to place device in reset condition. It also offers the software flags to indicate the source, which causes a reset. In general, most SFR go to their Reset value irrespective of the reset condition, but there are several reset source indicating flags whose state depends on the source of reset.
  • Page 305 ML51/ML54/ML56 PCON – Power Control Register SFR Address Reset Value POR: 0001_0000b PCON 87H, All pages Others: 000U _0000b SMOD SMOD0 Address: 87H, All pagess POR reset value: 0001 000b, other reset value: 000U 0000b Name Description Power-on Reset Flag This bit will be set as 1 after a power-on reset.

  • Page 306: Figure 6.2-2 Brown-Out Detection Block Diagram

    ML51/ML54/ML56 6.2.3.2 Brown-Out Reset (BOR) The other power monitoring function brown-out detection (BOD) circuit is used for monitoring the V level during execution. There are eight CONFIG selectable brown-out trigger levels available for wide voltage applications. These eight nominal levels are 1.8V, 2.0V, 2.4V, 2.7V, 3.0V, 3.7V and 4.4V selected via setting CBOV[2:0] (CONFIG2[6:4]).
  • Page 307 ML51/ML54/ML56 CONFIG2 CBODEN CBOV[2:0] BOIAP CBORST Factory default value: 1111 1111b Name Description CBODEN CONFIG Brown-Out Detect Enable 1 = Brown-out detection circuit OFF. 0 = Brown-out detection circuit ON. [6:4] CBOV[2:0] CONFIG Brown-Out Voltage Select 111 = V is 1.8V. 110 = V is 1.8V.
  • Page 308 ML51/ML54/ML56 BODCON0 – Brown-out Detection Control 0 (TA Protected) Register SFR Address Reset Value POR,CCCC XC0X b BOD, UUUU XU1X b BODCON0 A3H, Page 0, TA protected Others,UUUU XUUX b BODEN BOV[2:0] BORST BORF Name Description BODEN Brown-Out Detection Enable 0 = Brown-out detection circuit ON.
  • Page 309 ML51/ML54/ML56 Name Description Note: 1.BODEN, BOV[2:0], and BORST are initialized by being directly loaded from CONFIG2 bit 7, [6:4], and 2 after all resets. 2. BOF reset value depends on different setting of CONFIG2 and V voltage level. Sep. 01, 2020 Page 309 of 719 Rev 2.00...
  • Page 310 ML51/ML54/ML56 BODCON1 – Brown-out Detection Control Byte 1 (TA Protected) Register SFR Address Reset Value POR 0000 0001 b BODCON1 ABH, Page 0, TA protected Others 0000 0UUU b LPBOD[1:0] BODFLT Address: ABH, Page 0 Reset value: POR: 0000 0001b / Others:0000 0UUUb Name Description [7:3]...
  • Page 311 ML51/ML54/ML56 6.2.3.3 External Reset and Hard Fault Reset ̅̅̅̅̅̅ is an input with a Schmitt trigger. An external reset is accomplished by The external reset pin RST ̅̅̅̅̅̅ pin low for at least 24 system clock cycles to ensure detection of a valid hardware holding the RST reset signal.
  • Page 312 ML51/ML54/ML56 AUXR0 – Auxiliary Register 0 Register SFR Address Reset Value POR: 0000 0000b, Software reset: 1U00 0000b, AUXR0 A2H, Page 0 nRESET pin: U100 0000b, Hard fault: UU10 0000b Others: UUU0 0000b SWRF RSTPINF HardF HardFInt Name Description RSTPINF External Reset Flag When the MCU is reset by the external reset, this bit will be set via hardware.
  • Page 313 ML51/ML54/ML56 6.2.3.4 Watchdog Timer Reset The WDT is a free running timer with programmable time-out intervals and a dedicated internal clock source. User can clear the WDT at any time, causing it to restart the counter. When the selected time- out occurs but no software response taking place for a while, the WDT will reset the system directly and CPU will begin execution from 0000H.
  • Page 314 ML51/ML54/ML56 WDCON – Watchdog Timer Control (TA Protected) Register SFR Address Reset Value POR 0000_0111 b WDCON AAH, Page 0, TA protected WDT 0000_1UUU b Others 0000_UUUU b WDTR WDCLR WDTF WIDPD WDTRF WDPS[2:0] Address: AAH, Page 0 Reset value: POR: 0000 0111b / WDT: 0000 1UUUb / Others: 0000 UUUUb Name Description WDTRF...
  • Page 315 ML51/ML54/ML56 6.2.3.5 Software Reset The ML51/ML54/ML56 Series provides a software reset, which allows the software to reset the whole system just similar to an external reset, initializing the MCU as it reset state. The software reset is quite useful in the end of an ISP progress. For example, if an ISP of Boot Code updating User Code finishes, a software reset can be asserted to re-boot CPU to execute new User Code immediately.
  • Page 316 ML51/ML54/ML56 CHPCON – Chip Control (TA Protected) Register SFR Address Reset Value Software 0000_00U0 b CHPCON 9FH, Page 0, TA protected Others 0000_00C0 b SWRST IAPFF IAPEN Name Description SWRST Software Reset To set this bit as logic 1 will cause a software reset. It will automatically be cleared via hardware after reset is finished.
  • Page 317 ML51/ML54/ML56 AUXR0 – Auxiliary Register 0 Register SFR Address Reset Value POR: 0000 0000b, Software reset: 1U00 0000b, AUXR0 A2H, Page 0 nRESET pin: U100 0000b, Hard fault: UU10 0000b Others: UUU0 0000b SWRF RSTPINF HardF HardFInt Name Description SWRF Software Reset Flag When the MCU is reset via software reset, this bit will be set via hardware.

  • Page 318: Figure 6.2-3 Boot Selecting Diagram

    ML51/ML54/ML56 6.2.3.6 Boot Select CONFIG0.7 CHPCON.1 Load Power-on reset Low voltage reset Reset and boot from APROM Watchdog timer reset BS = 0 Brown-out reset Hard fault reset BS = 1 RST pin reset Reset and boot from LDROM Software reset Figure 6.2-3 Boot Selecting Diagram The ML51/ML54/ML56 Series provides user a flexible boot selection for variant application.
  • Page 319 ML51/ML54/ML56 CONFIG0 FSYS OCDPWM OCDEN LOCK Factory default value: 1111 1111b Name Description CONFIG Boot Select This bit defines from which block that MCU re-boots after resets except software reset. 1 = MCU will re-boot from APROM after resets except software reset. 0 = MCU will re-boot from LDROM after resets except software reset.
  • Page 320 ML51/ML54/ML56 CHPCON – Chip Control (TA Protected) Register SFR Address Reset Value Software 0000_00U0 b CHPCON 9FH, Page 0, TA protected Others 0000_00C0 b SWRST IAPFF IAPEN Address: 9FH, Page 0 Reset value: Software: 0000 00U0b / others: 0000 00C0b Name Description Boot Select...

  • Page 321: Interrupt System

    ML51/ML54/ML56 6.2.4 Interrupt System 6.2.4.1 Interrupt Overview The purpose of the interrupt is to make the software deal with unscheduled or asynchronous events. The ML51/ML54/ML56 Series has a four-priority-level interrupt structure with 31 interrupt sources. Each of the interrupt sources has an individual priority setting bits, interrupt vector and enable bit. In addition, the interrupts can be globally enabled or disabled.
  • Page 322 ML51/ML54/ML56 interrupt enable bit in the IE and EIE0 SFR. There is also a global enable bit EA bit (I.E.7), which can be cleared to disable all the interrupts at once. It is set to enable all individually enabled interrupts. Setting the EA bit to logic 0 disables all interrupt sources regardless of the individual interrupt-enable settings.
  • Page 323 ML51/ML54/ML56 IE – Interrupt Enable Register SFR Address Reset Value A8H, All pages, Bit addressable 0000 _0000 b EADC EBOD Name Description Enable All Interrupt This bit globally enables/disables all interrupts that are individually enabled. 0 = All interrupt sources Disabled. 1 = Each interrupt Enabled depending on its individual mask setting.
  • Page 324 ML51/ML54/ML56 EIE0 – Extensive Interrupt Enable Register SFR Address Reset Value EIE0 9BH, Page 0 0000 _0000 b ESPI0 EFB0 EWDT EPWM0 ECAP EI2C0 Name Description Enable Timer 2 Interrupt 0 = Timer 2 interrupt Disabled. 1 = Timer 2 interrupt Enable. When interrupt generated, TF2 (T2CON.7) set 1 ESPI0 Enable SPI Interrupt 0 = SPI interrupt Disabled.
  • Page 325 ML51/ML54/ML56 EIE1 – Extensive Interrupt Enable 1 Register SFR Address Reset Value EIE1 9CH, Page 0 0000 _0000 b EPWM123 EI2C1 ESPI1 EHFI EWKT Name Description Reserved EPWM123 Enable PWM123 Interrupt 0 = PWM1/2/3 interrupt Disabled. 1 = PWM1/2/3 interrupt Enable. When interrupt generated PWMF (PWM1CON0.5) set 1. EI2C1 Enable R/W1 Interrupt 0 = R/W1 interrupt Disabled.
  • Page 326 ML51/ML54/ML56 ScnIE – SC Interrupt Enable Control Register Register SFR Address Reset Value SC0IE DDH, Page 0 0000_0000 b SC1IE DDH, Page 2 0000_0000 b ACERRIEN BGTIEN TERRIEN TBEIEN RDAIEN Name Description [7:5] Reserved ACERRIEN Auto Convention Error Interrupt Enable Bit This field is used to enable auto-convention error interrupt.
  • Page 327 ML51/ML54/ML56 DMAnCR – PDMAn Control Register Register SFR Address Reset Value DMA0CR0 92H, Page 0 0000_0000 b DMA1CR0 EBH, Page 0 0000_0000 b DMA2CR0 B3H, Page 2 0000_0000 b DMA3CR0 ABH, Page 2 0000_0000 b PSSEL[3:0] Name Description [7:4] PSSEL[3:0] Peripheral Source Select 0000 = XRAM to XRAM 0001 = SPI0 RX...

  • Page 328: Table 6.2-5 Interrupt Priority Level Setting

    ML51/ML54/ML56 6.2.4.3 Interrupt Priorities There are four priority levels for all interrupts. They are level highest, high, low, and lowest; and they are represented by level 3, level 2, level 1, and level 0. The interrupt sources can be individually set to one of four priority levels by setting their own priority bits.
  • Page 329 ML51/ML54/ML56 Vector Natural Priority Control Interrupt Source Interrupt Flag Enable Bit Address Priority Bits Wake-Up 005BH ADCF (ADCCON0.7) EADC (I.E.6) PADC, PADCH External interrupt 1 0013H IE1 (TCON.3) EX1 (I.E.2) PX1, PX1H Pin interrupt 003BH PIF0 (PIF.0) EPI (EIE0.1) PPI, PPIH PIF1 (PIF.1) PIF2 (PIF.2) PIF3 (PIF.3)

  • Page 330: Table 6.2-6 Characteristics Of Each Interrupt Source

    ML51/ML54/ML56 Vector Natural Priority Control Interrupt Source Interrupt Flag Enable Bit Address Priority Bits Wake-Up PWM123 interrupt PWMF(PWM1CON0.5) EPWM123 (EIE1.6) PPWM1, PPWM1H PWMF(PWM2CON0.5) 00CBH PWMF(PWM3CON0.5) Touch_Key 00D3H TKSCIF (TKSTA0.1) TKSCTHIE (TKINTEN.0) TK, TKH TKIF (TKSTA0.2) TKSCIE (TKINTEN.1) TKIF_ALL (TKSTA0.3) TKIF0 (TKSTA1.0) TKIF1 (TKSTA1.1) TKIF2 (TKSTA1.2) TKIF3 (TKSTA1.3)
  • Page 331 ML51/ML54/ML56 IP – Interrupt Priority Register SFR Address Reset Value B8H, All pages, Bit addressable 0000_0000 b PADC PBOD Name Description Reserved PADC ADC interrupt priority low bit PBOD Brown-out detection interrupt priority low bit Serial port 0 interrupt priority low bit Timer 1 interrupt priority low bit External interrupt 1 priority low bit Timer 0 interrupt priority low bit...
  • Page 332 ML51/ML54/ML56 IPH – Interrupt Priority High Register SFR Address Reset Value B7H, Page 0 0000_0000 b PADCH PBODH PT1H PX1H PT0H PX0H Name Description PADCH ADC interrupt priority high bit PBODH Brown-out detection interrupt priority high bit Serial port 0 interrupt priority high bit PT1H Timer 1 interrupt priority high bit PX1H...
  • Page 333 ML51/ML54/ML56 EIP0 – Extensive Interrupt Priority Register SFR Address Reset Value EIP0 EFH, Page 0 0000_0000 b PSPI0 PWDT PPWM0 PCAP PI2C0 Name Description Timer 2 interrupt priority low bit PSPI0 SPI0 interrupt priority low bit Fault Brake interrupt priority low bit PWDT WDT interrupt priority low bit PPWM0...
  • Page 334 ML51/ML54/ML56 EIPH0 – Extensive Interrupt Priority High Register SFR Address Reset Value EIPH0 F7H, Page 0 0000_0000 b PT2H PSPI0H PFBH PWDTH PPWM0H PCAPH PPIH PI2C0H Name Description PT2H Timer 2 interrupt priority high bit PSPI0H SPI0 interrupt priority high bit PFBH Fault Brake interrupt priority high bit PWDTH...
  • Page 335 ML51/ML54/ML56 EIP1 – Extensive Interrupt Priority 1 Register SFR Address Reset Value EIP1 FEH, Page 0 0000_0000 b PSPI1 PDMA1 PDMA0 PSMC PWKT Name Description PSPI1 SPI1 interrupt priority low bit PDMA1 PDMA1 interrupt priority low bit PDMA0 PDMA0 interrupt priority low bit PSMC SMC interrupt priority low bit Hard fault interrupt priority low bit...
  • Page 336 ML51/ML54/ML56 EIPH1 – Extensive Interrupt Priority High 1 Register SFR Address Reset Value EIPH1 FFH, Page 0 0000_0000 b PSPI1H PDMA1H PDMA0H PSMCH PHFH PWKTH PT3H PS1H Name Description PSPI1H SPI1 interrupt priority high bit PDMA1H PDMA1 interrupt priority high bit PDMA0H PDMA0 interrupt priority high bit PSMCH...
  • Page 337 ML51/ML54/ML56 EIP2 – Extensive Interrupt Priority 2 Register SFR Address Reset Value EIP2 ACH, Page 0 0000_0000 b PDMA3 PDMA2 SMC1 PPWM1 PI2C1 PACMP Name Description RTC interrupt priority low bit PDMA3 PDMA3 interrupt priority low bit PDMA2 PDMA2 interrupt priority low bit SMC1 SMC1 interrupt priority low bit Touch Key interrupt priority low bit...
  • Page 338 ML51/ML54/ML56 EIPH2 – Extensive Interrupt Priority High 2 Register SFR Address Reset Value EIPH2 ADH, Page 0 0000_0000 b RTCH PDMA3H PDMA2H SMC1H PPWM1H PI2C1H PACMPH Name Description RTCH RTCH interrupt priority high bit PDMA3H PDMA3H interrupt priority high bit PDMA2H PDMA2H interrupt priority high bit SMC1H...
  • Page 339 ML51/ML54/ML56 AUXR0 – Auxiliary Register 0 Register SFR Address Reset Value POR: 0000 0000b, Software reset: 1U00 0000b, AUXR0 A2H, Page 0 nRESET pin: U100 0000b, Hard fault: UU10 0000b Others: UUU0 0000b SWRF RSTPINF HFRF HFIF Name Description SWRF Software Reset Flag When the MCU is reset via software reset, this bit will be set via hardware.
  • Page 340 ML51/ML54/ML56 6.2.4.4 Interrupt Service The interrupt flags are sampled every system clock cycle. In the same cycle, the sampled interrupts are polled and their priority is resolved. If certain conditions are met then the hardware will execute an internally generated LCALL instruction, which will vector the process to the appropriate interrupt vector address.

  • Page 341: Flash Memory Control

    ML51/ML54/ML56 6.3 Flash Memory Control 6.3.1 In-application-programming (IAP) Unlike RAM’s real-time operation, to update Flash data often takes long time. Furthermore, it is a quite complex timing procedure to erase, program, or read Flash data. The ML51/ML54/ML56 Series carried out the Flash operation with convenient mechanism to help user re-programming the Flash content by In-Application-Programming (IAP).
  • Page 342 ML51/ML54/ML56 CHPCON – Chip Control (TA Protected) Register SFR Address Reset Value Software 0000_00U0 b CHPCON 9FH, Page 0, TA protected Others 0000_00C0 b SWRST IAPFF IAPEN Name Description IAPFF IAP Fault Flag The hardware will set this bit after IAPGO (IAPTRG.0) is set if any of the following condition is met: (1) The accessing address is oversize.
  • Page 343 ML51/ML54/ML56 IAPUEN – IAP Updating Enable (TA Protected) Register SFR Address Reset Value IAPUEN A5H, Page 0, TA protected 0000 _0000 b SPMEN SPUEN CFUEN LDUEN APUEN Name Description [7:5] Reserved SPMEN SPROM Memory Space Mapping Enable 0 = CPU memory address 0xff80~0xffff is mapping to APROM memory 1 = CPU memory address 0xff80~0xffff is mapping to SPROM memory SPUEN SPROM Memory Space Updated Enable(TA Protected)
  • Page 344 ML51/ML54/ML56 IAPCN – IAP Control Register SFR Address Reset Value IAPCN AFH, Page 0 0011_0000 b IAPB[1:0] FOEN FCEN FCTRL[3:0] Name Description IAPB[1:0] IAP Control [7:6] This byte is used for IAP command. For details, see Figure 6.3-1 IAP Modes and Command Codes.
  • Page 345 ML51/ML54/ML56 IAPAH – IAP Address High Byte Register SFR Address Reset Value IAPAH A7H, Page 0 0000 _0000 b IAPA[15:8] Name Description IAPA[15:8] IAP Address High Byte [7:0] IAPAH contains address IAPA[15:8] for IAP operations. Sep. 01, 2020 Page 345 of 719 Rev 2.00...
  • Page 346 ML51/ML54/ML56 IAPAL – IAP Address Low Byte Register SFR Address Reset Value IAPAL A6H, Page 0 0000 _0000 b IAPA[7:0] Name Description IAPA[7:0] IAP Address Low Byte [7:0] IAPAL contains address IAPA[7:0] for IAP operations. Sep. 01, 2020 Page 346 of 719 Rev 2.00...
  • Page 347 ML51/ML54/ML56 IAPFD – IAP Flash Data Register SFR Address Reset Value IAPFD AEH, Page 0 0000 _0000 b IAPFD[7:0] Name Description IAPFD[7:0] IAP Flash Data [7:0] This byte contains Flash data, which is read from or is going to be written to the Flash Memory.
  • Page 348 ML51/ML54/ML56 IAPTRG – IAP Trigger (TA Protected) Register SFR Address Reset Value IAPTRG A4H, Page 0, TA protected 0000 _0000 b IAPGO Name Description [7:1] Reserved IAPGO IAP Go IAP begins by setting this bit as logic 1. After this instruction, the CPU holds the Program Counter (PC) and the IAP hardware automation takes over to control the progress.
  • Page 349 ML51/ML54/ML56 6.3.1.1 IAP Commands The ML51/ML54/ML56 Series provides a wide range of applications to perform IAP to APROM, LDROM, or CONFIG bytes. The IAP action mode and the destination of the Flash block are defined by IAP control register IAPCN. IAPCN IAPA[15:0] IAP Mode...

  • Page 350: Figure 6.3-1 Iap Modes And Command Codes

    ML51/ML54/ML56 IAPCN IAPA[15:0] IAP Mode IAPFD[7:0] FCTRL IAPB {IAPAH, IAPAL} FOEN FCEN [1:0] [3:0] All CONFIG bytes erase 0010 0000H CONFIG byte-program 0001 CONFIG0: 0000H Data in CONFIG1: 0001H CONFIG2: 0002H CONFIG4: 0004H CONFIG6: 0005H CONFIG byte-read 0000 CONFIG0: 0000H Data out CONFIG1: 0001H CONFIG2: 0002H...

  • Page 351: Figure 6.3-2. Crc-8 Block Diagram

    ML51/ML54/ML56 6.3.1.2 CRC-8 for Flash check Flash CRC-8 Checksum Data_in[7:0] CRC-8: X + X + 1 Seed[7:0]=0x00 CRC_active CRC[7:0] Figure 6.3-2. CRC-8 Block Diagram 6.3.1.3 IAP User Guide IAP facilitates the updating Flash contents in a convenient way; however, user should follow some restricted laws in order that the IAP operates correctly.
  • Page 352 ML51/ML54/ML56 BYTE_PROGRAM_AP 00100001b 0000h TA,#0Aah ;CHPCON is TA protected TA,#55h CHPCON,#00000001b ;IAPEN = 1, enable IAP mode TA,#0Aah ;IAPUEN is TA protected TA,#55h IAPUEN,#00000001b ;APUEN = 1, enable APROM update IAPCN,#PAGE_ERASE_AP ;Erase page 200h~27Fh IAPAH,#02h IAPAL,#00h IAPFD,#0FFh TA,#0Aah ;IAPTRG is TA protected TA,#55h IAPTRG,#00000001b ;write ‘1’...
  • Page 353 ML51/ML54/ML56 volatile unsigned char code Data_Flash[128] _at_ 0x0200; Main (void) TA = 0Xaa; //CHPCON is TA protected TA = 0x55; CHPCON |= 0x01; //IAPEN = 1, enable IAP mode TA = 0Xaa; //IAPUEN is TA protected TA = 0x55; IAPUEN |= 0x01; //APUEN = 1, enable APROM update IAPCN = PAGE_ERASE_AP;...
  • Page 354 User Code to MCU through serial port. Then Boot Code receives it and re-programs into User Code through IAP commands. Nuvoton provides ISP firmware and PC application for ML51/ML54/ML56 Series. It makes user quite easy perform ISP through UART port. Please visit...
  • Page 355 ML51/ML54/ML56 TA,#0Aah ;CHPCON is TA protected TA,#55h CHPCON,#00000001b ;IAPEN = 1, enable IAP mode Disable_IAP: TA,#0Aah TA,#55h CHPCON,#11111110b ;IAPEN = 0, disable IAP mode Enable_AP_Update: TA,#0Aah ;IAPUEN is TA protected TA,#55h IAPUEN,#00000001b ;APUEN = 1, enable APROM update Disable_AP_Update: TA,#0Aah TA,#55h IAPUEN,#11111110b ;APUEN = 0, disable APROM update...
  • Page 356 ML51/ML54/ML56 IAPAL,#80h CALL Trigger_IAP CJNE R0,#44h,Erase_AP_Loop Program_AP: IAPCN,#BYTE_PROGRAM_AP IAPAH,#00h IAPAL,#00h DPTR,#AP_code Program_AP_Loop: MOVC A,@A+DPTR IAPFD,A CALL Trigger_IAP DPTR IAPAL A,IAPAL CJNE A,#14,Program_AP_Loop Program_AP_Verify: IAPCN,#BYTE_READ_AP IAPAH,#00h IAPAL,#00h DPTR,#AP_code Program_AP_Verify_Loop: CALL Trigger_IAP MOVC A,@A+DPTR A,IAPFD CJNE A,B,Program_AP_Verify_Error DPTR IAPAL A,IAPAL CJNE A,#14,Program_AP_Verify_Loop Program_AP_Verify_Error: CALL Disable_IAP P0,#00h...

  • Page 357: In-Circuit-Programming (Icp)

    ML51/ML54/ML56 IAPFD,#0FFh CALL Trigger_IAP Read_CONFIG: IAPCN,#BYTE_READ_CONFIG IAPAH,#00h IAPAL,#02h CALL Trigger_IAP R7,IAPFD Program_CONFIG: IAPCN,#BYTE_PROGRAM_CONFIG IAPAH,#00h IAPAL,#02h A,R7 A,#11111011b IAPFD,A ;disable BOD reset R6,A ;temp data CALL Trigger_IAP Program_CONFIG_Verify: IAPCN,#BYTE_READ_CONFIG IAPAH,#00h IAPAL,#02h CALL Trigger_IAP B,R6 A,IAPFD CJNE A,B,Program_CONFIG_Verify_Error Program_CONFIG_Verify_Error: CALL Disable_IAP P0,#00h SJMP $ ;******************************************************************** APROM code...

  • Page 358: On-Chip-Debugger (Ice)

    V and GND pins on the circuit board to make ICP possible. Nuvoton provides ICP tool for ML51/ML54/ML56 Series, which enables user to easily perform ICP through Nuvoton ICP programmer. The ICP programmer developed by Nuvoton has been optimized according to the electric characteristics of MCU.
  • Page 359 ML51/ML54/ML56 5. HIRC cannot be turned off because OCD uses this clock to monitor its internal status. The instruction that turns off HIRC affects nothing if executing under debug mode. When CPU enters its Power-down mode under debug mode, HIRC keeps turning on. The ML51/ML54/ML56 Series OCD system has another limitation that non-intrusive commands cannot be executed at any time while the user’s program is running.
  • Page 360 ML51/ML54/ML56 CONFIG0 FSYS OCDPWM OCDEN LOCK Factory default value: 1111 1111b Name Description OCDPWM PWM Output State Under OCD Halt This bit decides the output state of PWM when OCD halts CPU. 1 = Tri-state pins those are used as PWM outputs. 0 = PWM continues.

  • Page 361: Gpio Port Structure And Operation

    ML51/ML54/ML56 6.4 GPIO Port Structure and Operation 6.4.1 GPIO Mode The ML51/ML54/ML56 Series has a maximum of 56 general purpose I/O pins which 40 bit- addressable general I/O pins grouped as 5 ports, P0 to P4, and 16 general I/O pins grouped as P5 and P6.

  • Page 362: Figure 6.4-1 Quasi-Bidirectional Mode Structure

    ML51/ML54/ML56 2-CPU-clock Very delay Strong Weak Port Pin Port Latch Input Figure 6.4-1 Quasi-Bidirectional Mode Structure Push-Pull Mode The push-pull mode has the same pull-low structure as the quasi-bidirectional mode, but provides a continuous strong pull-high when the port latch is written by logic 1. The push-pull mode is generally used as output pin when more source current is needed for an output driving.

  • Page 363: Figure 6.4-3 Input-Only Mode Structure

    ML51/ML54/ML56 Input Port Pin Figure 6.4-3 Input-Only Mode Structure Open-Drain Mode The open-drain mode turns off all pull-high transistors and only drives the pull-low of the port pin when the port latch is given by logic 0. If the port latch is logic 1, it behaves as if in input-only mode. To be used as an output pin generally as R/W lines, an open-drain pin should add an external pull-high, typically a resistor tied to V .
  • Page 364 ML51/ML54/ML56 6.4.1.2 Input and Output Data Control These registers are I/O input and output data buffers. Reading gets the I/O input data. Writing forces the data output. All of these registers are bit-addressable. Sep. 01, 2020 Page 364 of 719 Rev 2.00...
  • Page 365 ML51/ML54/ML56 Pn – Port Register SFR Address Reset Value 80H, All pages, Bit-addressable 1111_1111 b 90H, All pages, Bit-addressable 1111_1111 b A0H, All pages, Bit-addressable 1111_1111 b B0H, All pages, Bit-addressable 1111_1111 b D8H, All pages, Bit-addressable 1111_1111 b B1H, Page 0 1111_1111 b A7H, Page 2 1111_1111 b...
  • Page 366 ML51/ML54/ML56 6.4.1.3 GPIO Mode Control These registers control GPIO mode, which is configurable among four modes: input-only, quasi- bidirectional, push-pull, or open-drain. Each pin can be configured individually. As default after reset all GPIO setting as input only mode. Sep. 01, 2020 Page 366 of 719 Rev 2.00...
  • Page 367 ML51/ML54/ML56 PnM1 – Port n Mode Select 1 Register SFR Address Reset Value P0M1 B1H, Page 1 1111_1111 b P1M1 B3H, Page 1 1111_1111 b P2M1 85H, Page 1 1111_1111 b P3M1 C2H, Page 1 1111_1111 b P4M1 B9H, Page 1 1111_1111 b P5M1 BDH, Page 1...
  • Page 368 ML51/ML54/ML56 PnM2 – Port n Mode Select 2 Register SFR Address Reset Value P0M2 B2H, Page 1 0000_0000 b P1M2 B4H, Page 1 0000_0000 b P2M2 B6H, Page 1 0000_0000 b P3M2 C3H, Page 1 0000_0000 b P4M2 BAH, Page 1 0000_0000 b P5M2 BEH, Page 1...
  • Page 369 ML51/ML54/ML56 6.4.1.4 GPIO Multi-Function Select PnMF10 – Pn.1 and Pn.0 Multi-function Select Register SFR Address Reset Value P0MF10 F9H, Page 2 0000_0000 b P1MF10 FDH, Page 2 0000_0000 b P2MF10 F2H, Page 2 0000_0000 b P3MF10 F6H, Page 2 0000_0000 b P4MF10 EBH, Page 2 0000_0000 b...
  • Page 370 ML51/ML54/ML56 PnMF32 – Pn.3 and Pn.2 Multi-function Select Register SFR Address Reset Value P0MF32 FAH, Page 2 0000_0000 b P1MF32 FEH, Page 2 0000_0000 b P2MF32 F3H, Page 2 0000_0000 b P3MF32 F7H, Page 2 0000_0000 b P4MF32 ECH, Page 2 0000_0000 b P5MF32 E1H, Page 2...
  • Page 371 ML51/ML54/ML56 PnMF54 – Pn.5 and Pn.4 Multi-function Select Register SFR Address Reset Value P0MF54 FBH, Page 2 0000_0000 b P1MF54 FFH, Page 2 0000_0000 b P2MF54 F4H, Page 2 0000_0000 b P3MF54 E9H, Page 2 0000_0000 b P4MF54 EDH, Page 2 0000_0000 b P5MF54 E2H, Page 2...
  • Page 372 ML51/ML54/ML56 PnMF76 – Pn.7 and Pn.6 Multi-function Select Register SFR Address Reset Value P0MF76 FCH, Page 2 0000_0000 b P1MF76 F1H, Page 2 0000_0000 b P2MF76 F5H, Page 2 0000_0000 b P3MF76 EAH, Page 2 0000_0000 b P4MF76 EEH, Page 2 0000_0000 b P5MF76 E3H, Page 2...
  • Page 373 ML51/ML54/ML56 6.4.1.5 Input Type Each I/O pin can be configured individually as TTL input or Schmitt triggered input. Note that all of PxS registers are accessible by switching SFR page to Page 1. Sep. 01, 2020 Page 373 of 719 Rev 2.00...
  • Page 374 ML51/ML54/ML56 PnS – Port n Schmitt Triggered Input Register SFR Address Reset Value 99H, Page 1 0000_0000 b 9BH, Page 1 0000_0000 b 9DH, Page 1 0000_0000 b ACH, Page 1 0000_0000 b BBH, Page 1 0000_0000 b BFH, Page 1 0000_0000 b PnS.7 PnS.6...
  • Page 375 ML51/ML54/ML56 6.4.1.6 Output Slew Rate Control Slew rate for each I/O pin is configurable individually. By default, each pin is in normal slew rate mode. User can set each control register bit to enable high-speed slew rate for the corresponding I/O pin. Note that all PxSR registers are accessible by switching SFR page to Page 1.
  • Page 376 ML51/ML54/ML56 PnSR –Port n Slew Rate Control Register SFR Address Reset Value P0SR 9AH, Page 1 0000_0000 b P1SR 9CH, Page 1 0000_0000 b P2SR 9EH, Page 1 0000_0000 b P3SR ADH, Page 1 0000_0000 b P4SR BCH, Page 1 0000_0000 b P5SR AEH, Page 1...
  • Page 377 ML51/ML54/ML56 PnUP – Port n Pull-up Resister Control Register SFR Address Reset Value P0UP 92H, Page 1 0000_0000 b P1UP 93H, Page 1 0000_0000 b P2UP 94H, Page 1 0000_0000 b P3UP 95H, Page 1 0000_0000 b P4UP 96H, Page 1 0000_0000 b P5UP 97H, Page 1...
  • Page 378 ML51/ML54/ML56 6.4.1.8 Pull-Down Resister Control Pull down resister for each I/O pin is configurable individually. Even enabled the pull down resister only effect when GPIO setting as input mode. By default, after reset each pin pull high resister is disabled. Sep.
  • Page 379 ML51/ML54/ML56 PnDW – Port n Pull-down Resister Control Register SFR Address Reset Value P0DW 8AH, Page 1 0000_0000 b P1DW 8BH, Page 1 0000_0000 b P2DW 8CH, Page 1 0000_0000 b P3DW 8DH, Page 1 0000_0000 b P4DW 8EH, Page 1 0000_0000 b P5DW 8FH, Page 1...

  • Page 380: External Interrupt Pins

    ML51/ML54/ML56 6.4.2 External Interrupt Pins Following is the MFP define ofr extneral interrupt pins. Group Pin Name GPIO Type Description P2.5 MFP15 INT0 INT0 P0.6 MFP15 External interrupt 0 input pin. P4.6 MFP15 P2.4 MFP15 P0.7 MFP15 INT1 INT1 External interrupt 1 input pin. P3.6 MFP15 P4.0...
  • Page 381 ML51/ML54/ML56 TCON – Timer 0 and 1 Control (Bit-addressable) Register SFR Address Reset Value TCON 88H, All pages, Bit-addressable 0000_0000b R (level) R (level) R/W (edge) R/W (edge) Name Description External Interrupt 1 Edge Flag If IT1 = 1 (falling edge trigger), this flag will be set by hardware when a falling edge is detected. It remain set until cleared via software or cleared by hardware in the beginning of its interrupt service routine.

  • Page 382: Pin Interrupt (Pit)

    ML51/ML54/ML56 6.4.3 Pin Interrupt (PIT) The ML51/ML54/ML56 Series provides pin interrupt input for each I/O pin to detect pin state if button or keypad set is used. A maximum 8-channel pin interrupt detection can be assigned by I/O port sharing. The pin interrupt is generated when any key is pressed on a keyboard or keypad, which produces an edge or level triggering event.
  • Page 383 ML51/ML54/ML56 PICON – Pin Interrupt Control Register SFR Address Reset Value PICON E9H, Page 1 0011 _0100 b PIT7 PIT6 PIT5 PIT4 PIT3 PIT2 PIT1 PIT0 Name Description PIT7 Pin Interrupt Channel 7 Type Select This bit selects which type that pin interrupt channel 7 is triggered. 0 = Level triggered.
  • Page 384 ML51/ML54/ML56 Name Description PIT0 Pin Interrupt Channel 0 Type Select This bit selects which type that pin interrupt channel 0 is triggered. 0 = Level triggered. 1 = Edge triggered. Sep. 01, 2020 Page 384 of 719 Rev 2.00...
  • Page 385 ML51/ML54/ML56 PINEN – Pin Interrupt Negative Polarity Enable Register SFR Address Reset Value PINEN EAH, Page 1 0000_0000 b PINEN7 PINEN6 PINEN5 PINEN4 PINEN3 PINEN2 PINEN1 PINEN0 Name Description PINENn Pin Interrupt Channel n Negative Polarity Enable [7:0] This bit enables low-level/falling edge triggering pin interrupt channel n. The level or edge triggered selection depends on each control bit PITn in PICON.
  • Page 386 ML51/ML54/ML56 PIPEN – Pin Interrupt Positive Polarity Enable Register SFR Address Reset Value PIPEN EBH, Page 1 0000_0000 b PIPEN7 PIPEN6 PIPEN5 PIPEN4 PIPEN3 PIPEN2 PIPEN1 PIPEN0 Name Description PIPENn Pin Interrupt Channel n Positive Polarity Enable [7:0] This bit enables high-level/rising edge triggering pin interrupt channel n. The level or edge triggered selection depends on each control bit PITn in PICON.
  • Page 387 ML51/ML54/ML56 PIF – Pin Interrupt Flags Register SFR Address Reset Value CAH, Page 0 0000_0000 b PIF7 PIF6 PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 R (level) R (level) R (level) R (level) R (level) R (level) R (level) R (level) R/W (edge) R/W (edge) R/W (edge)
  • Page 388 ML51/ML54/ML56 PIPSn – Pin Interrupt Control Register SFR Address Reset Value PIPS0 A1H, Page 1 0000_0000 b PIPS1 A2H, Page 1 0000_0000 b PIPS2 A3H, Page 1 0000_0000 b PIPS3 A4H, Page 1 0000_0000 b PIPS4 A5H, Page 1 0000_0000 b PIPS5 A6H, Page 1 0000_0000 b...

  • Page 389: Timer

    ML51/ML54/ML56 6.5 Timer 6.5.1 Overview ML51/ML54/ML56 Series provides following 16-bit Timer. Two 16-bit Timers/Counters 0 and 1 compatible with standard 8051. One 16-bit Timer 2 with three-channel input capture module and 9 input pin can be selected. One 16-bit auto-reload Timer 3, which can be the baud rate clock source of UARTs.

  • Page 390: Figure 6.5-1 Timer/Counters 0 And 1 In Mode 0

    ML51/ML54/ML56 (T1M) 1/12 TL0 (TL1) T0 (T1) pin Timer Interrupt (TF1) TR0 (TR1) TH0 (TH1) T0 (T1) pin GATE T0OE (T1OE) INT0 (INT1) pin Figure 6.5-1 Timer/Counters 0 and 1 in Mode 0 6.5.2.2 Mode 1 (16-Bit Timer) Mode 1 is similar to Mode 0 except that the counting registers are fully used as a 16-bit counter. Roll- over occurs when a count moves FFFFH to 0000H.

  • Page 391: Figure 6.5-3 Timer/Counters 0 And 1 In Mode 2

    ML51/ML54/ML56 (T1M) 1/12 TL0 (TL1) T0 (T1) pin Timer Interrupt (TF1) T0 (T1) pin T0OE TR0 (TR1) (T1OE) GATE TH0 (TH1) INT0 (INT1) pin Figure 6.5-3 Timer/Counters 0 and 1 in Mode 2 6.5.2.4 Mode 3 (Two Separate 8-Bit Timers) Mode 3 has different operating methods for Timer 0 and Timer 1.
  • Page 392 ML51/ML54/ML56 6.5.2.5 Register Description Sep. 01, 2020 Page 392 of 719 Rev 2.00...
  • Page 393 ML51/ML54/ML56 TMOD – Timer 0 and 1 Mode Register SFR Address Reset Value TMOD 89H, All pages 0000_0000b ̅ ̅ GATE GATE Name Description GATE Timer 1 Gate Control 0 = Timer 1 will clock when TR1 is 1 regardless of INT1 logic level. 1 = Timer 1 will clock only when TR1 is 1 and INT1 is logic 1.
  • Page 394 ML51/ML54/ML56 TCON – Timer 0 and 1 Control (Bit-addressable) Register SFR Address Reset Value TCON 88H, All pages, Bit-addressable 0000_0000b R (level) R (level) R/W (edge) R/W (edge) Name Description Timer 1 Overflow Flag This bit is set when Timer 1 overflows. It is automatically cleared by hardware when the program executes the Timer 1 interrupt service routine.
  • Page 395 ML51/ML54/ML56 Name Description External Interrupt 0 Type Select This bit selects by which type that INT0 is triggered. 0 = INT0 is low level triggered. 1 = INT0 is falling edge triggered. Sep. 01, 2020 Page 395 of 719 Rev 2.00...
  • Page 396 ML51/ML54/ML56 TL0 – Timer 0 Low Byte Register SFR Address Reset Value 8AH, Page 0 0000_0000b TL0[7:0] Name Description TL0[7:0] Timer 0 Low Byte [7:0] The TL0 register is the low byte of the 16-bit counting register of Timer 0. Sep.
  • Page 397 ML51/ML54/ML56 TH0 – Timer 0 High Byte Register SFR Address Reset Value 8CH, Page 0 0000_0000b TH0[7:0] Name Description TH0[7:0] Timer 0 High Byte [7:0] The TH0 register is the high byte of the 16-bit counting register of Timer 0. Sep.
  • Page 398 ML51/ML54/ML56 TL1 – Timer 1 Low Byte Register SFR Address Reset Value 8BH, Page 0 0000_0000b TL1[7:0] Name Description TL1[7:0] Timer 1 Low Byte [7:0] The TL1 register is the low byte of the 16-bit counting register of Timer 1. Sep.
  • Page 399 ML51/ML54/ML56 TH1 – Timer 1 High Byte Register SFR Address Reset Value 8DH, Page 0 0000_0000b TH1[7:0] Name Description TH1[7:0] Timer 1 High Byte [7:0] The TH1 register is the high byte of the 16-bit counting register of Timer 1. Sep.
  • Page 400 ML51/ML54/ML56 CKCON – Clock Control Register SFR Address Reset Value CKCON 8EH, Page 0 1000_0000b FASTWK PWMCKS T1OE T0OE CLOEN Name Description T1OE Timer 1 Output Enable 0 = Timer 1 output Disabled. 1 = Timer 1 output Enabled from T1 pin. Note that Timer 1 output should be enabled only when operating in its “Timer”...

  • Page 401: Timer 2 And Input Capture

    ML51/ML54/ML56 6.5.3 Timer 2 and Input Capture Timer 2 is a 16-bit up counter cascaded with TH2, the upper 8 bits register, and TL2, the lower 8 bit register. Equipped with RCMP2H and RCMP2L, Timer 2 can operate under compare mode and auto- ̅̅̅̅̅̅...

  • Page 402: Figure 6.5-6 Timer 2 Auto-Reload Mode And Input Capture Module Functional Block Diagram

    ML51/ML54/ML56 Note that the TH2 and TL2 are accessed separately. It is strongly recommended that user stops Timer 2 temporally by clearing TR2 bit before reading from or writing to TH2 and TL2. The free-running reading or writing may cause unpredictable result. 6.5.3.2 Auto-Reload Mode ̅̅̅̅̅̅...

  • Page 403: Figure 6.5-7 Timer 2 Compare Mode And Input Capture Module Functional Block Diagram

    ML51/ML54/ML56 CAPF0 CAPF0 [00] CAPF1 Input Capture Interrupt Noise CAPF2 CAP0 [01] Filter CAP1 ENF0 [10] (CAPCON2.4) CAPEN0 CAP2 (CAPCON0.4) CAP0LS[1:0] (CAPCON1[1:0]) Input Capture 0 Module Input Capture 1 Module Input Capture 2 Module CMPCR (T2MOD.2) Clear Timer 2 Pre-scalar T2DIV[2:0] (T2MOD[6:4]) (T2CON.2)
  • Page 404 ML51/ML54/ML56 6.5.3.5 Register Description Sep. 01, 2020 Page 404 of 719 Rev 2.00...
  • Page 405 ML51/ML54/ML56 CAPCON0 – Input Capture Control 0 Register SFR Address Reset Value CAPCON0 E1H, Page 1 0000_0000b CAPEN2 CAPEN1 CAPEN0 CAPF2 CAPF1 CAPF0 Name Description Reserved CAPEN2 Input Capture 2 Enable 0 = Input capture channel 2 Disabled. 1 = Input capture channel 2 Enabled. CAPEN1 Input Capture 1 Enable 0 = Input capture channel 1 Disabled.
  • Page 406 ML51/ML54/ML56 CAPCON1 – Input Capture Control 1 Register SFR Address Reset Value CAPCON1 E2H, Page 1 0000_0000b CAP2LS[1:0] CAP1LS[1:0] CAP0LS[1:0] Address: E2H, Page 1 Reset value: 0000 0000b Name Description [7:6] Reserved [5:4] CAP2LS[1:0] Input Capture 2 Level Select 00 = Falling edge. 01 = Rising edge.
  • Page 407 ML51/ML54/ML56 CAPCON2 – Input Capture Control 2 Register SFR Address Reset Value CAPCON2 E3H, Page 1 0000_0000b ENF2 ENF1 ENF0 Name Description ENF2 Enable Noise Filer on Input Capture 2 0 = Noise filter on input capture channel 2 Disabled. 1 = Noise filter on input capture channel 2 Enabled.
  • Page 408 ML51/ML54/ML56 CnL – Capture Low Byte, n = 0,1,2 Register SFR Address Reset Value E4H, Page 1 0000_0000 b E6H, Page 1 0000_0000 b EDH, Page 1 0000_0000 b CnL[7:0] Name Description CnL[7:0] Input Capture n Result Low Byte [7:0] The CnL register is the low byte of the 16-bit result captured by input capture n.
  • Page 409 ML51/ML54/ML56 CnH – Capture n High Byte, n = 1,2,3 Register SFR Address Reset Value E5H, Page 1 0000_0000 b E7H, Page 1 0000_0000 b EEH, Page 1 0000_0000 b CnH[7:0] Name Description [7:0] CnH[7:0] Input Capture n Result High Byte The CnH register is the high byte of the 16-bit result captured by input capture n.

  • Page 410: Timer 3

    ML51/ML54/ML56 6.5.4 Timer 3 Timer 3 is implemented simply as a 16-bit auto-reload, up-counting timer. The user can select the pre- scale with T3PS[2:0] (T3CON[2:0]) and fill the reload value into RH3 and RL3 registers to determine its overflow rate. User then can set TR3 (T3CON.3) to start counting. When the counter rolls over FFFFH, TF3 (T3CON.4) is set as 1 and a reload is generated and causes the contents of the RH3 and RL3 registers to be reloaded into the internal 16-bit counter.
  • Page 411 ML51/ML54/ML56 T3CON – Timer 3 Control Register SFR Address Reset Value T3CON C4H, Page 0 0000_0000 b SMOD_1 SMOD0_1 BRCK T3PS[2:0] Name Description Timer 3 Overflow Flag This bit is set when Timer 3 overflows. It is automatically cleared by hardware when the program executes the Timer 3 interrupt service routine.
  • Page 412 ML51/ML54/ML56 RL3 – Timer 3 Reload Low Byte Register SFR Address Reset Value C5H, Page 0 0000_0000 b RL3[7:0] Name Description RL3[7:0] Timer 3 Reload Low Byte [7:0] It holds the low byte of the reload value of Timer 3. Sep.
  • Page 413 ML51/ML54/ML56 RH3 – Timer 3 Reload High Byte Register SFR Address Reset Value C6H, Page 0 0000_0000 b RH3[7:0] Name Description RH3[7:0] Timer 3 Reload High Byte [7:0] It holds the high byte of the reload value of Time 3. Sep.

  • Page 414: Watchdog Timer (Wdt)

    ML51/ML54/ML56 6.6 Watchdog Timer (WDT) The ML51/ML54/ML56 Series provides one Watchdog Timer (WDT). It can be configured as a time- out reset timer to reset whole device. Once the device runs in an abnormal status or hangs up by outward interference, a WDT reset recover the system. It provides a system monitor, which improves the reliability of the system.

  • Page 415: General Purpose Timer

    ML51/ML54/ML56 38.4 kHz 512-clock Pre-scalar WDT counter overflow LIRC WDT Reset Internal WDTRF Delay (1/1~1/256) (6-bit) Oscillator clear clear WDPS[2:0] WDCLR WDTF WDT Interrupt Figure 6.6-1 WDT as A Time-Out Reset Timer After the device is powered and it starts to execute software code, the WDT starts counting simultaneously.

  • Page 416: Register Description

    ML51/ML54/ML56 6.6.3 Register Description Sep. 01, 2020 Page 416 of 719 Rev 2.00...
  • Page 417 ML51/ML54/ML56 CONFIG4 WDTEN[3:0] Factory default value: 1111 1111b Name Description [7:4] WDTEN[3:0] WDT Enable This field configures the WDT behavior after MCU execution. 1111 = WDT is Disabled. WDT can be used as a general purpose timer via software control. 0101 = WDT is Enabled as a time-out reset timer and it stops running during Idle or Power- down mode.
  • Page 418 ML51/ML54/ML56 WDCON – Watchdog Timer Control (TA Protected) Register SFR Address Reset Value POR 0000_0111 b WDT 0000_1UUU b WDCON AAH, Page 0, TA protected Others 0000_UUUU b WDTR WDCLR WDTF WIDPD WDTRF WDPS[2:0] Name Description WDTR WDT Run This bit is valid only when control bits in WDTEN[3:0] (CONFIG4[7:4]) are all 1. At this time, WDT works as a general purpose timer.

  • Page 419: Typical Structure Of Wdt Service Routine

    ML51/ML54/ML56 Name Description Note: 1. WDTRF will be cleared after power-on reset, be set after WDT reset, and remains unchanged after any other resets. 2. WDPS[3:0] are all set after power-on reset and keep unchanged after any reset other than power-on reset. 6.6.4 Typical Structure of WDT Service Routine In some application of low power consumption, the CPU usually stays in Idle mode when nothing...
  • Page 420 ML51/ML54/ML56 LOOP: PCON,#02H LJMP LOOP Sep. 01, 2020 Page 420 of 719 Rev 2.00...

  • Page 421: Self Wake-Up Timer (Wkt)

    ML51/ML54/ML56 6.7 Self Wake-up Timer (WKT) 6.7.1 Overview The ML51/ML54/ML56 Series has a dedicated Self Wake-up Timer (WKT), which serves for a periodic wake-up timer in low power mode or for general purpose timer. WKT remains counting in Idle or Power-down mode.

  • Page 422: Control Register

    ML51/ML54/ML56 6.7.3 Control Register Sep. 01, 2020 Page 422 of 719 Rev 2.00...
  • Page 423 ML51/ML54/ML56 WKCON – Self Wake-up Timer Control Register SFR Address Reset Value WKCON 8FH, Page 0 0000_0000b WKTCK WKTF WKTR WKPS[2:0] Name Description [7:6] Reserved WKTCK WKT Clock Source This bit is set WKT clock source select bit. 0 = LIRC 1 = LXT WKTF WKT Overflow Flag...
  • Page 424 ML51/ML54/ML56 RWKH – Self Wake-up Timer Reload High Byte Register SFR Address Reset Value RWKH BFH, Page 2 0000 0000b RWK[15:8] Name Description RWK[15:8] WKT Reload High Byte [7:0] It holds the 16-bit reload value of WKT. Note that RWK should not be FFFFH if the pre-scale is 1/1 for implement limitation.
  • Page 425 ML51/ML54/ML56 RWKL – Self Wake-up Timer Reload Low Byte Register SFR Address Reset Value RWKL 86H, Page 0 0000 0000b RWK[7:0] Name Description RWK[7:0] WKT Reload Low Byte [7:0] It holds the 16-bit reload value of WKT. Note that RWK should not be FFFFH if the pre-scale is 1/1 for implement limitation.
  • Page 426 ML51/ML54/ML56 CWKH – Self Wake-up Timer Current Count Value High Byte Register SFR Address Reset Value CWKH BEH, Page 2 0000 0000b CWK[15:8] Name Description [7:0] CWK[15:8] WKT Current Count Value Low Byte High Byte It is store value of WKT current count. Sep.
  • Page 427 ML51/ML54/ML56 CWKL – Self Wake-up Timer Current Count Value Low Byte Register SFR Address Reset Value CWKL 86H, Page 1 0000 0000b CWK[7:0] Name Description [7:0] CWK[7:0] WKT Current Count Value Low Byte Low Byte It is store value of WKT current count. Sep.

  • Page 428: Pulse Width Modulated (Pwm)

    ML51/ML54/ML56 6.8 Pulse Width Modulated (PWM) 6.8.1 Overview The PWM (Pulse Width Modulation) signal is a useful control solution in wide application field. It can used on motor driving, fan control, backlight brightness tuning, LED light dimming, or simulating as a simple digital to analog converter output through a low pass filter circuit.

  • Page 429: Block Diagram

    ML51/ML54/ML56 6.8.3 Block Diagram 6.8.3.1 PWM0 Block Diagram PWM0P 0-to-1 (PWM0PH, PWM0PL) registers LOAD (PWM0CON0.6) PWM0P buffer Counter Matching(edgealigned)/ underflow(venter aligned) PWMF PWM0 interrupt (PWM0CON0.5) PWMRUN 16-bit (PWM0CON0.7) clear counter up/down Interrupt INTSEL[1:0], CLRPWM INTTYP[1:0] counter select/type (PWMnCON0.4) Pre-scalar (PWMnCON0[3:0]) edge/center Timer 1 overflow PWMTYP...

  • Page 430: Figure 6.8-2 Pwm1/ Pwm2 / Pwm3 Block Diagram

    ML51/ML54/ML56 6.8.3.2 PWM1/ PWM2 / PWM3 Block Diagram 0-to-1 PWMnP (PWMnPH, PWMnPL) registers LOAD (PWMnCON0.6) PWMnP buffer Counter Matching(edgealigned)/ underflow(venter aligned) PWMF PWMn interrupt (PWMnCON0.5) PWMRUNn 16-bit clear counter up/down Interrupt CLRPWM INTSEL[1:0], INTTYP[1:0] counter select/type (PWMnCON0.4) (PWMnCON0[3:0]) Pre-scalar edge/center Timer 1 overflow PnG0 PWMTYP...

  • Page 431: Functional Description

    ML51/ML54/ML56 6.8.4 Functional Description 6.8.4.1 PWM Generator The PWM generator is clocked by the system clock or Timer 1 overflow divided by a PWM clock pre- scalar selectable from 1/1~1/128. The PWM0/1/2/3 period is defined by effective 16-bit period registers, {PWMnPH, PWMnPL}. The period is the same for all PWM0/1/2/3 channels for they share the same 16-bit period counter.

  • Page 432: Figure 6.8-3 Pwm0 And Fault Brake Output Control Block Diagram

    ML51/ML54/ML56 PWM0 and Fault Brake output control Dead Mask Brake mode time output control polarity select insertion PMEN0 PNP0 P0G0_DT P0G0 PMD0 FBD0 PWM0_CH0 PWM0C PWM0C dead mode P0G1 time P0G1_DT PMD1 FBD1 PWM0_CH1 PMEN1 PNP1 PMEN2 P0G2_DT PNP2 P0G2 PMD2 PWM0C FBD2...

  • Page 433: Figure 6.8-4 Pwm1/2/3 Control Block Diagram

    ML51/ML54/ML56 PWM1/2/3 output control Mask mode output select PWMnMEN0 PnG0 PWMn_CH0 PWMnMD0 PWMnC0/1 mode PnG1 PWMn_CH1 PWMnMD1 PWMnMEN1 PWMnMOD[1:0] PWMnMEN, (PWMnCON1[7:6]) PWMnMD Figure 6.8-4 PWM1/2/3 Control Block Diagram Note: A loading of new period and duty by setting LOAD should be ensured complete by monitoring it and waiting for a hardware automatic clearing LOAD bit.
  • Page 434 ML51/ML54/ML56 PWM0CON0 – PWM Control Register0 Register SFR Address Reset Value PWM0CON0 D1H, Page 0 0000_0000 b PWM0RUN LOAD PWMF CLRPWM Name Description PWM0RUN PWM0 Run Enable 0 = PWM0 stays in idle. 1 = PWM0 starts running. LOAD PWM New Period and Duty Load This bit is used to load period and duty Register Description in their buffer if new period or duty value needs to be updated.
  • Page 435 ML51/ML54/ML56 PWMnCON0 – PWM Control Register0 Register SFR Address Reset Value PWM1CON0 9CH, Page 2 0000_0000 b PWM2CON0 C4H, Page 2 0000_0000 b PWM3CON0 D4H, Page 2 0000_0000 b PWMnRUN LOAD PWMF CLRPWM Name Description PWMnRUN PWMn Run Enable 0 = PWM stays in idle. 1 = PWM starts running.
  • Page 436 ML51/ML54/ML56 PWMnCON1 – PWM Control 1 Register SFR Address Reset Value PWM0CON1 DFH, Page 1 0000_0000 b PWM1CON1 9DH, Page 2 0000_0000 b PWM2CON1 C5H, Page 2 0000_0000 b PWM3CON1 D5H, Page 2 0000_0000 b PWMMOD[1:0] PWMTYP FBINEN PWMDIV[2:0] Name Description PWMDIV[2:0] PWM Clock Divider...
  • Page 437 ML51/ML54/ML56 CKCON – Clock Control Register SFR Address Reset Value CKCON 8EH, Page 0 0000_0000b FASTWK PWMCKS T1OE T0OE CLOEN Name Description PWMCKS PWM Clock Source Select 0 = The clock source of PWM is the system clock FSYS. 1 = The clock source of PWM is the overflow of Timer 1. Sep.
  • Page 438 ML51/ML54/ML56 PWMnPL – PWM Period Low Byte Register SFR Address Reset Value PWM0PL D9H, Page 1 0000_0000 b PWM1PL 99H, Page 2 0000_0000 b PWM2PL C1H, Page 2 0000_0000 b PWM3PL D1H, Page 2 0000_0000 b PWMnP[7:0] Name Description [7:0] PWMnP[7:0] PWMn Period Low Byte This byte with PWMnPH controls the period of the PWM generator signal.
  • Page 439 ML51/ML54/ML56 PWMnPH – PWM Period High Byte Register SFR Address Reset Value PWM0PH D1H, Page 1 0000_0000 b PWM1PH 86H, Page 2 0000_0000 b PWM2PH B9H, Page 2 0000_0000 b PWM3PH C9H, Page 2 0000_0000 b PWMnP[15:8] Name Description [7:0] PWMnP[15:8] PWM Period High Byte This byte with PWMnPL controls the period of the PWM generator signal.
  • Page 440 ML51/ML54/ML56 PWMnCxH – PWM0/1/2/3 Channel 0~5 Duty High Byte n=0,1,2,3; x=0,1,2,3,4,5 Register SFR Address Reset Value PWM0C0H D2H, Page 1 0000_0000 b PWM0C1H D3H, Page 1 0000_0000 b PWM0C2H D4H, Page 1 0000_0000 b PWM0C3H D5H, Page 1 0000_0000 b PWM0C4H C4H, Page 1 0000_0000 b...
  • Page 441 ML51/ML54/ML56 PWMnCxL – PWM0/1/2/3 Channel 0~5 Duty Low Byte n=0,1,2,3; x=0,1,2,3,4,5 Register SFR Address Reset Value PWM0C0L DAH, Page 1 0000_0000 b PWM0C1L DBH, Page 1 0000_0000 b PWM0C2L DCH, Page 1 0000_0000 b PWM0C3L DDH, Page 1 0000_0000 b PWM0C4L CCH, Page 1 0000_0000 b...
  • Page 442 ML51/ML54/ML56 6.8.4.2 PWM Types The PWM generator provides two PWM types: edge-aligned or center-aligned. PWM type is selected by PWMTYP (PWMnCON1.4). Sep. 01, 2020 Page 442 of 719 Rev 2.00...
  • Page 443 ML51/ML54/ML56 PWMnCON1 – PWM Control 1 Register SFR Address Reset Value PWM0CON1 DFH, Page 1 0000_0000 b PWM1CON1 9DH, Page 2 0000_0000 b PWM2CON1 C5H, Page 2 0000_0000 b PWM3CON1 D5H, Page 2 0000_0000 b PWMMOD[1:0] PWMTYP FBINEN PWMDIV[2:0] Name Description PWMTYP PWM Type Select...

  • Page 444: Figure 6.8-5 Pwm Edge-Aligned Type Waveform

    ML51/ML54/ML56 6.8.4.3 Edge-Aligned Type In edge-aligned mode, the 16-bit counter uses single slop operation by counting up from 0000H to {PWMnPH, PWMnPL} and then starting from 0000H. The PWM generator signal (PGn before PWM and Fault Brake output control) is cleared on the compare match of 16-bit counter and the duty register {PWMnH, PWMnL} and set at the 16-bit counter is 0000H.

  • Page 445: Figure 6.8-6 Pwm Center-Aligned Type Waveform

    ML51/ML54/ML56 PWMP (2nd) PWMP (1st) 12-bit counter PWM01 (2nd) PWM01 (1st) PWM01 (2nd) duty valid PG01 output PWMP (2nd) period valid Load Load PWM01 (2nd) PWMP (2nd) Figure 6.8-6 PWM Center-aligned Type Waveform The output frequency and duty cycle for center-aligned PWM are given by following equations: PWM frequency = is the PWM clock source frequency divided by ...
  • Page 446 ML51/ML54/ML56 PWMnCON1 – PWM Control 1 Register SFR Address Reset Value PWM0CON1 DFH, Page 1 0000_0000 b PWM1CON1 9DH, Page 2 0000_0000 b PWM2CON1 C5H, Page 2 0000_0000 b PWM3CON1 D5H, Page 2 0000_0000 b PWMMOD[1:0] PWMTYP FBINEN PWMDIV[2:0] Name Description [7:6] PWMMOD[1:0]...

  • Page 447: Figure 6.8-7 Pwm Complementary Mode With Dead-Time Insertion

    ML51/ML54/ML56 PG0_DT PG1_DT Figure 6.8-7 PWM Complementary Mode with Dead-time Insertion Sep. 01, 2020 Page 447 of 719 Rev 2.00...
  • Page 448 ML51/ML54/ML56 PWM0DTEN – PWM Dead-time Enable (TA Protected) Register SFR Address Reset Value PWM0DTEN F9H, Page 1 0000_0000 b PWMnDTCNT.8 PDT45EN PDT23EN PDT01EN Name Description [7:5] Reserved PWMnDTCNT.8 PWM Dead-Time Counter Bit 8 See PWMnDTCNT register. Reserved PDT45EN PWM4/5 Pair Dead-Time Insertion Enable This bit is valid only when PWM4/5 is under complementary mode.
  • Page 449 ML51/ML54/ML56 PWM0DTCNT – PWM Dead-time Counter (TA Protected) Register SFR Address Reset Value PWM0DTCNT FAH, Page 1, TA protected 0000_0000 b PWM0DTCNT[7:0] Name Description [7:0] PWM0DTCNT[7:0] PWM Dead-Time Counter Low Byte This 8-bit field combined with PWMnDTEN .4 forms a 9-bit PWM dead-time counter PWM0DTCNT.
  • Page 450 ML51/ML54/ML56 6.8.4.6 Mask Output Control Each PWM signal can be software masked by driving a specified level of PWM signal. The PWM mask output function is quite useful when controlling Electrical Commutation Motor like a BLDC. PWMnMEN contains six bits, those determine which channel of PWM signal will be masked. PWMnMD set the individual mask level of each PWM channel.
  • Page 451 ML51/ML54/ML56 PWMxMEN – PWMnCx Mask Enable, n=0,1,2,3;x=0,1,2,3,4,5 Register SFR Address Reset Value PWM0MEN FBH, Page 1 0000_0000 b PWM1MEN 8DH, Page 2 0000_0000 b PWM2MEN BDH, Page 2 0000_0000 b PWM3MEN CDH, Page 2 0000_0000 b PMEN5 PMEN4 PMEN3 PMEN2 PMEN1 PMEN0 Name...
  • Page 452 ML51/ML54/ML56 PWMnMD – PWM Mask Data Register SFR Address Reset Value PWM0MD FCH, Page 1 0000_0000 b PWM1MD 8CH, Page 2 0000_0000 b PWM2MD BCH, Page 2 0000_0000 b PWM3MD CCH, Page 2 0000_0000 b PMD5 PMD4 PMD3 PMD2 PMD1 PMD0 Name Description...

  • Page 453: Figure 6.8-8 Fault Brake Function Block Diagram

    ML51/ML54/ML56 De-bounce FBINLS FBINEN Fault Brake event Fault Brake interrupt ADC comparator ADC compare event Figure 6.8-8 Fault Brake Function Block Diagram Sep. 01, 2020 Page 453 of 719 Rev 2.00...
  • Page 454 ML51/ML54/ML56 PWMnCON1 – PWM Control 1 Register SFR Address Reset Value PWM0CON1 DFH, Page 1 0000_0000 b PWM1CON1 9DH, Page 2 0000_0000 b PWM2CON1 C5H, Page 2 0000_0000 b PWM3CON1 D5H, Page 2 0000_0000 b PWMMOD[1:0] PWMTYP FBINEN PWMDIV[2:0] Name Description FBINEN FB Pin Input Enable...
  • Page 455 ML51/ML54/ML56 PWMnFBD – PWM Fault Brake Data Register SFR Address Reset Value PWM0FBD D7H, Page 1 0000_0000 b FBINLS FBD5 FBD4 FBD3 FBD2 FBD1 FBD0 Name Description Fault Brake Flag This flag is set when FBINEN is set as 1 and FB pin detects an edge, which matches FBINLS (PWM0FBD.6) selection.

  • Page 456: Pwm Interrupt

    ML51/ML54/ML56 PWM0NP – PWM Negative Polarity Register SFR Address Reset Value PWM0NP D6H, Page 1 0000_0000 b PNP5 PNP4 PNP3 PNP2 PNP1 PNP0 Name Description [5:0] PNPn PWMn Negative Polarity Output Enable 0 = PWMn signal outputs directly on PWMn pin. 1 = PWMn signal outputs inversely on PWMn pin.
  • Page 457 ML51/ML54/ML56 PWMnINTC – PWM Interrupt Control Register SFR Address Reset Value PWM0INTC B7H, Page 1 0000_0000 b PWM1INTC 9EH, Page 2 0000_0000 b PWM2INTC C6H, Page 2 0000_0000 b PWM3INTC D6H, Page 2 0000_0000 b INTTYP1 INTTYP0 INTSEL2 INTSEL1 INTSEL0 Name Description [7:6]...

  • Page 458: Figure 6.8-9 Pwm Interrupt Type

    ML51/ML54/ML56 The PWM interrupt related with PWM waveform is shown as figure below. Edge-aligned PWM Center-aligned PWM Central point 12-bit PWM counter End point Dead time PWM channel 0/2/4 pin output PWMF (falling edge) Software (INTTYP[1:0] = [0:0]) clear PWMF (rising edge) (INTTYP[1:0] = [0:1]) PWMF (central point) Reserved...

  • Page 459: Register Description

    ML51/ML54/ML56 6.8.6 Register Description Sep. 01, 2020 Page 459 of 719 Rev 2.00...
  • Page 460 ML51/ML54/ML56 PWM0CON0 – PWM Control Register0 Register SFR Address Reset Value PWM0CON0 D1H, Page 0 0000_0000 b PWM0RUN LOAD PWMF CLRPWM Name Description PWM0RUN PWM0 Run Enable 0 = PWM0 stays in idle. 1 = PWM0 starts running. LOAD PWM New Period and Duty Load This bit is used to load period and duty Register Description in their buffer if new period or duty value needs to be updated.
  • Page 461 ML51/ML54/ML56 PWMnCON0 – PWM Control Register0 Register SFR Address Reset Value PWM1CON0 9CH, Page 2 0000_0000 b PWM2CON0 C4H, Page 2 0000_0000 b PWM3CON0 D4H, Page 2 0000_0000 b PWMnRUN LOAD PWMF CLRPWM Name Description PWMnRUN PWMn Run Enable 0 = PWM stays in idle. 1 = PWM starts running.
  • Page 462 ML51/ML54/ML56 PWMnCON1 – PWM Control 1 Register SFR Address Reset Value PWM0CON1 DFH, Page 1 0000_0000 b PWM1CON1 9DH, Page 2 0000_0000 b PWM2CON1 C5H, Page 2 0000_0000 b PWM3CON1 D5H, Page 2 0000_0000 b PWMMOD[1:0] PWMTYP FBINEN PWMDIV[2:0] Name Description PWMMOD[1:0] PWM Mode Select...
  • Page 463 ML51/ML54/ML56 Name Description [2:0] PWMDIV[2:0] PWM Clock Divider This field decides the pre-scale of PWM clock source. 000 = 1/1. 001 = 1/2 010 = 1/4. 011 = 1/8. 100 = 1/16. 101 = 1/32. 110 = 1/64. 111 = 1/128. Sep.
  • Page 464 ML51/ML54/ML56 PWMnPL – PWM Period Low Byte Register SFR Address Reset Value PWM0PL D9H, Page 1 0000_0000 b PWM1PL 99H, Page 2 0000_0000 b PWM2PL C1H, Page 2 0000_0000 b PWM3PL D1H, Page 2 0000_0000 b PWMnP[7:0] Name Description [7:0] PWMnP[7:0] PWMn Period Low Byte This byte with PWMnPH controls the period of the PWM generator signal.
  • Page 465 ML51/ML54/ML56 PWMnPH – PWM Period High Byte Register SFR Address Reset Value PWM0PH D1H, Page 1 0000_0000 b PWM1PH 86H, Page 2 0000_0000 b PWM2PH B9H, Page 2 0000_0000 b PWM3PH C9H, Page 2 0000_0000 b PWMnP[15:8] Name Description [7:0] PWMnP[15:8] PWM Period High Byte This byte with PWMnPL controls the period of the PWM generator signal.
  • Page 466 ML51/ML54/ML56 PWMnCxH – PWM0/1/2/3 Channel 0~5 Duty High Byte n=0,1,2,3; x=0,1,2,3,4,5 Register SFR Address Reset Value PWM0C0H D2H, Page 1 0000_0000 b PWM0C1H D3H, Page 1 0000_0000 b PWM0C2H D4H, Page 1 0000_0000 b PWM0C3H D5H, Page 1 0000_0000 b PWM0C4H C4H, Page 1 0000_0000 b...
  • Page 467 ML51/ML54/ML56 PWMnCxL – PWM0/1/2/3 Channel 0~5 Duty Low Byte n=0,1,2,3; x=0,1,2,3,4,5 Register SFR Address Reset Value PWM0C0L DAH, Page 1 0000_0000 b PWM0C1L DBH, Page 1 0000_0000 b PWM0C2L DCH, Page 1 0000_0000 b PWM0C3L DDH, Page 1 0000_0000 b PWM0C4L CCH, Page 1 0000_0000 b...
  • Page 468 ML51/ML54/ML56 PWM0DTEN – PWM Dead-time Enable (TA Protected) Register SFR Address Reset Value PWM0DTEN F9H, Page 1 0000_0000 b PWMnDTCNT.8 PDT45EN PDT23EN PDT01EN Name Description [7:5] Reserved PWMnDTCNT.8 PWM Dead-Time Counter Bit 8 See PWMnDTCNT register. Reserved PDT45EN PWM4/5 Pair Dead-Time Insertion Enable This bit is valid only when PWM4/5 is under complementary mode.
  • Page 469 ML51/ML54/ML56 PWM0DTCNT – PWM Dead-time Counter (TA Protected) Register SFR Address Reset Value PWM0DTCNT FAH, Page 1, TA protected 0000_0000 b PWM0DTCNT[7:0] Name Description [7:0] PWM0DTCNT[7:0] PWM Dead-Time Counter Low Byte This 8-bit field combined with PWMnDTEN .4 forms a 9-bit PWM dead-time counter PWM0DTCNT.
  • Page 470 ML51/ML54/ML56 PWMxMEN – PWMnCx Mask Enable, n=0,1,2,3;x=0,1,2,3,4,5 Register SFR Address Reset Value PWM0MEN FBH, Page 1 0000_0000 b PWM1MEN 8DH, Page 2 0000_0000 b PWM2MEN BDH, Page 2 0000_0000 b PWM3MEN CDH, Page 2 0000_0000 b PMEN5 PMEN4 PMEN3 PMEN2 PMEN1 PMEN0 Name...
  • Page 471 ML51/ML54/ML56 PWMnMD – PWM Mask Data Register SFR Address Reset Value PWM0MD FCH, Page 1 0000_0000 b PWM1MD 8CH, Page 2 0000_0000 b PWM2MD BCH, Page 2 0000_0000 b PWM3MD CCH, Page 2 0000_0000 b PMD5 PMD4 PMD3 PMD2 PMD1 PMD0 Name Description...
  • Page 472 ML51/ML54/ML56 PWMnFBD – PWM Fault Brake Data Register SFR Address Reset Value PWM0FBD D7H, Page 1 0000_0000 b FBINLS FBD5 FBD4 FBD3 FBD2 FBD1 FBD0 Name Description Fault Brake Flag This flag is set when FBINEN is set as 1 and FB pin detects an edge, which matches FBINLS (PWM0FBD.6) selection.
  • Page 473 ML51/ML54/ML56 PWM0NP – PWM Negative Polarity Register SFR Address Reset Value PWM0NP D6H, Page 1 0000_0000 b PNP5 PNP4 PNP3 PNP2 PNP1 PNP0 Name Description [5:0] PNPn PWMn Negative Polarity Output Enable 0 = PWMn signal outputs directly on PWMn pin. 1 = PWMn signal outputs inversely on PWMn pin.
  • Page 474 ML51/ML54/ML56 PWMnINTC – PWM Interrupt Control Register SFR Address Reset Value PWM0INTC B7H, Page 1 0000_0000 b PWM1INTC 9EH, Page 2 0000_0000 b PWM2INTC C6H, Page 2 0000_0000 b PWM3INTC D6H, Page 2 0000_0000 b INTTYP1 INTTYP0 INTSEL2 INTSEL1 INTSEL0 Name Description [7:6]...

  • Page 475: Serial Port (Uart0 & Uart1)

    ML51/ML54/ML56 6.9 Serial Port (UART0 & UART1) 6.9.1 Overview The ML51/ML54/ML56 Series includes two enhanced full duplex serial ports enhanced with automatic address recognition and framing error detection. As control bits of these two serial ports are implemented the same. Generally speaking, in the following contents, there will not be any reference to serial port 1, but only to serial port 0.

  • Page 476: Functional Description

    ML51/ML54/ML56 6.9.3 Functional Description 6.9.3.1 Operation Mode Mode 0 Mode 0 provides synchronous communication with external devices. Serial data centers and exits through RXD pin. TXD outputs the shift clocks. 8-bit frame of data are transmitted or received. Mode 0 therefore provides half-duplex communication because the transmitting or receiving data is via the same data line RXD.

  • Page 477: Figure 6.9-2 Serial Port Mode 1 Timing Diagram

    ML51/ML54/ML56 Figure 6.9-2 Serial Port Mode 1 Timing Diagram Transmission is initiated by any writing instructions to SBUF. Transmission takes place on TXD pin. First the start bit comes out, the 8-bit data follows to be shifted out and then ends with a stop bit. After the stop bit appears, TI (SCON.1) will be set to indicate one byte transmission complete.

  • Page 478: Figure 6.9-3 Serial Port Mode 2 And 3 Timing Diagram

    ML51/ML54/ML56 Figure 6.9-3 Serial Port Mode 2 and 3 Timing Diagram Transmission is initiated by any writing instructions to SBUF. Transmission takes place on TXD pin. First the start bit comes out, the 8-bit data and bit TB8 (SCON.3) follows to be shifted out and then ends with a stop bit.

  • Page 479: Table 6.9-1 Serial Port 0 Mode / Baud Rate Description

    ML51/ML54/ML56 auto-reload mode (Mode 2). If using Timer 3 as the baud rate generator, its interrupt should also be disabled. Following shows all UART mode and baudrate fomula: SM0 / SM1 SMOD Frame Mode Baud Rate (SCON[7:6]) (SCON[5]) (PCON[7]) Bits FSYS divided by 12 FSYS divided by 2 Time1...

  • Page 480: Table 6.9-2 Serial Port 1 Mode / Baud Rate Description

    ML51/ML54/ML56 SM0_1 / SM1_1 SMOD_1 Mode Frame Bits Baud Rate (S1CON[7:6]) (T3CON[7]) divided by 12    Timer 3    scale 65536 (256 RL3)  Timer 3      scale 65536 (256 RL3) divided by 64 divided by 32 ...
  • Page 481 ML51/ML54/ML56 RL3 = value low byte T3CON|= 0x08; //Trigger Timer3 Serial port (UART1) Timer baudrate generator: Fomula       scale 65536 (256 RL3) SCON_1 = 0x52; //UART1 Mode1,REN_1=1,TI_1=1 T3CON = 0xF8; //T3PS2=0,T3PS1=0,T3PS0=0(Prescale=1), RH3 = value high byte RL3 = value low byte T3CON|= 0x08;...
  • Page 482 ML51/ML54/ML56 Fsys Value Baud Rate TH1 Value (Hex) RH3,RL3 Value (Hex) Baudrate Deviation 276480 FFFB 0.000000% 345600 FFFC 0.000000% 460800 FFFD 0.000000% 691200 FFFE 0.000000% 1382400 FFFF 0.000000% 4800 FF28 0.067515% 9600 FF94 0.067515% 19200 FFCA 0.067515% 16600000 38400 FFE5 0.067515% 57600 FFEE...
  • Page 483 ML51/ML54/ML56 6.9.3.3 Framing Error Detection Framing error detection is provided for asynchronous modes. (Mode 1, 2, or 3.) The framing error occurs when a valid stop bit is not detected due to the bus noise or contention. The UART can detect a framing error and notify the software.
  • Page 484 ML51/ML54/ML56 If desired, user may enable the automatic address recognition feature in Mode 1. In this configuration, the stop bit takes the place of the ninth data bit. RI is set only when the received command frame address matches the device’s address and is terminated by a valid stop bit. Using the automatic address recognition feature allows a master to selectively communicate with one or more slaves by invoking the “Given”...
  • Page 485 ML51/ML54/ML56 Example 3, slave 2: SADDR = 11000000b SADEN = 11111100b Given = 110000XXb In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 11100110b. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 11100101b.

  • Page 486: Register Description

    ML51/ML54/ML56 6.9.4 Register Description Sep. 01, 2020 Page 486 of 719 Rev 2.00...
  • Page 487 ML51/ML54/ML56 SCON – Serial Port Control Register SFR Address Reset Value SCON 98H, All pages, Bit addressable 0000_0000 b SM0/FE Name Description SM0/FE Serial Port Mode Select SMOD0 (PCON.6) = 0: See Table 6.9-1 Serial Port 0 Mode / baud rate Description for details. SMOD0 (PCON.6) = 1: SM0/FE bit is used as frame error (FE) status flag.
  • Page 488 ML51/ML54/ML56 Name Description 9th Received Bit The bit identifies the logic level of the 9th received bit in serial port 0 Mode 2 or 3. In Mode 1, RB8 is the logic level of the received stop bit. SM2 bit as logic 1 has restriction for exception. RB8 is not used in Mode 0.
  • Page 489 ML51/ML54/ML56 S1CON – Serial Port 1 Control Register SFR Address Reset Value S1CON F8H, All pages, Bit addressable 0000_0000 b SM0_1/FE_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 Name Description SM0_1/FE_1 Serial Port 1 Mode Select SMOD0 _ 1 (T3CON.6) = 0: See Table 6.9-2 Serial Port 1 Mode / baud rate Description for details.
  • Page 490 ML51/ML54/ML56 Name Description RB8_1 Received Bit The bit identifies the logic level of the 9 received bit in serial port 1 Mode 2 or 3. In Mode 1, RB8 _ 1 is the logic level of the received stop bit. SM2 _ 1 bit as logic 1 has restriction for exception.
  • Page 491 ML51/ML54/ML56 PCON – Power Control Register SFR Address Reset Value POR: 0001_0000b PCON 87H, All pages Others: 000U _0000b SMOD SMOD0 Name Description SMOD Serial Port 0 Double Baud Rate Enable Setting this bit doubles the serial port baud rate when UART0 is in Mode 2 or when Timer 1 overflow is used as the baud rate source of UART0 Mode 1 or 3.
  • Page 492 ML51/ML54/ML56 T3CON – Timer 3 Control Register SFR Address Reset Value T3CON C4H, Page 0 0000_0000 b SMOD_1 SMOD0_1 BRCK T3PS[2:0] Name Description SMOD_1 Serial Port 1 Double Baud Rate Enable Setting this bit doubles the serial port baud rate when UART1 is in Mode 2. See Table 6.9-2 Serial Port 1 Mode / baud rate Description for details.
  • Page 493 ML51/ML54/ML56 SBUF – Serial Port 0 Data Buffer Register SFR Address Reset Value SBUF 99H, Page 0 0000_0000 b SBUF[7:0] Name Description SBUF[7:0] Serial Port 0 Data Buffer [7:0] This byte actually consists two separate registers. One is the receiving resister, and the other is the transmitting buffer.
  • Page 494 ML51/ML54/ML56 SBUF1 – Serial Port 1 Data Buffer Register SFR Address Reset Value SBUF1 9AH, Page 0 0000 _0000 b SBUF1[7:0] Name Description [7:0] SBUF1[7:0] Serial Port 1 Data Buffer This byte actually consists two separate registers. One is the receiving resister, and the other is the transmitting buffer.
  • Page 495 ML51/ML54/ML56 IE – Interrupt Enable (Bit-addressable) Register SFR Address Reset Value A8H, All pages, Bit addressable 0000 _0000 b EADC EBOD Name Description Enable Serial Port 0 Interrupt 0 = Serial port 0 interrupt Disabled. 1 = Interrupt generated by TI (SCON.1) or RI (SCON.0) Enabled. Sep.
  • Page 496 ML51/ML54/ML56 EIE1 – Extensive Interrupt Enable 1 Register SFR Address Reset Value EIE1 9CH, Page 0 0000 _0000 b EPWM123 EI2C1 ESPI1 EHFI EWKT Name Description Enable Serial Port 1 Interrupt 0 = Serial port 1 interrupt Disabled. 1 = Serial port 1Interrupt Enable. When interrupt generated TI_1 (S1CON.1) or RI_1 (S1CON.0) set 1.
  • Page 497 ML51/ML54/ML56 SADDR0 – Slave 0 Address Register SFR Address Reset Value SADDR0 A9H, Page 0 0000 _0000 b SADDR0[7:0] Name Description SADDR0[7:0] Slave 0 Address [7:0] This byte specifies the microcontroller’s own slave address for UATR0 multi-processor communication. Sep. 01, 2020 Page 497 of 719 Rev 2.00...
  • Page 498 ML51/ML54/ML56 SADEN0 – Slave 0 Address Mask Register SFR Address Reset Value SADEN0 B9H, Page 0 0000_0000 b SADEN0[7:0] Name Description [7:0] SADEN0[7:0] Slave 0 Address Mask This byte is a mask byte of UART0 that contains “don’t-care” bits (defined by zeros) to form the device’s “Given”...
  • Page 499 ML51/ML54/ML56 SADDR1 – Slave 1 Address Register SFR Address Reset Value SADDR1 BBH, Page 0 0000_0000 b SADDR1[7:0] Name Description [7:0] SADDR1[7:0] Slave 1 Address This byte specifies the microcontroller’s own slave address for UART1 multi-processor communication. Sep. 01, 2020 Page 499 of 719 Rev 2.00...
  • Page 500 ML51/ML54/ML56 SADEN1 – Slave 1 Address Mask Register SFR Address Reset Value SADEN1 BAH, Page 0 0000_0000 b SADEN1[7:0] Name Description SADEN1[7:0] Slave 1 Address Mask [7:0] This byte is a mask byte of UART1 that contains “don’t-care” bits (defined by zeros) to form the device’s “Given”...
  • Page 501 ML51/ML54/ML56 AUXR1 – Auxiliary Register 1 Register SFR Address Reset Value AUXR1 C9H, Page 1 0000_0000 b UART3PX UART2PX UART1PX UART0PX Name Description [7:4] Reserved UART3PX Serial Port 3 RX (SMC1 DATA) /TX (SMC1 CLK) Pin Exchange 0 = Assign UART3 RXD (SMC1 DATA) to multiple I/O pin RXD UART3 TXD (SMC CLK) to multiple I/O pin TXD 1 = Assign UART3 RXD (SMC1 DATA) to multiple I/O pin TXD UART3 TXD (SMC CLK) to multiple I/O pin RXD...
  • Page 502 ML51/ML54/ML56 Name Description UART0PX Serial Port 0 RX/TX Pin Exchange 0 = Assign UART0 RXD to multiple I/O pin RXD UART0 TXD to multiple I/O pin TXD 1 = Assign UART0 RXD to multiple I/O pin TXD UART0 TXD to multiple I/O pin RXD Note: that Pin direction is controlled by I/O type of relative pin.

  • Page 503: Smart Card Interface (Sc)

    ML51/ML54/ML56 6.10 Smart Card Interface (SC) 6.10.1 Overview The ML51/ML54/ML56 Series provides Smart Card Interface controller (SC controller) with asynchronous protocal based on ISO/IEC 7816-3 standard. Software controls GPIO pins as the smartcard reset function and card detection function. This controller also provides UART emulation for high precision baud rate communication.

  • Page 504: Operating Modes

    ML51/ML54/ML56 6.10.4 Operating Modes 6.10.4.1 Smart Card Mode The Smart Card Interface controller supports activation, cold reset, warm reset and deactivation sequence by software control. The activation, cold reset, warm reset and deactivation and sequence are shown as follows. SC Interface Connection The SC interface connection is shown in Figure 15.3-1 1.

  • Page 505: Table 6.10-1 Sc Activation And Cold Reset Sequence

    ML51/ML54/ML56 SC_PWR SC_CLK SC_RST Undefined SC_DAT Suggestion timing (Unit SC Clock) 400 <= T3 <= 40000 Comment Time 83.5 SC_PWR to SC_CLK Start SC_CLK Start to SC_RST Assert SC_RST Start to ATR Appear 42060 Note : The values are measured by chip I / O pin and the real value will depend on system design Table 6.10-1 SC Activation and Cold Reset Sequence Warm Reset The warm reset sequence is showed in Figure 15.3-3...

  • Page 506: Smart Card Data Transfer

    ML51/ML54/ML56 2. Stop SC_CLK by programming CLKKEEP (SCCR2[1]) to ‘0’ period of timing T8. 3. Set SC_DAT to low by software programming to ‘0’ period of timing T8. 4. Deactivate SC_PWR by software programming to ‘0’ period of timing T9. SC_PWR SC_CLK SC_RST...

  • Page 507: Figure 6.10-4 Initial Character Ts

    ML51/ML54/ML56 Character TS. If the TS pattern is 1100_0000, it is inverse convention. When decoded by inverse convention, the conveyed byte is equal to 0x3F. If the TS pattern is 1101_1100, it is direct convention. When decoded by direct convention, the conveyed byte is equal to 0x3B.Software can set AUTOCEN (SCnCR1[3]) and then the operating convention will be decided by hardware.

  • Page 508: Figure 6.10-6 Transmit Direction Block Guard Time Operation

    ML51/ML54/ML56 block guard time. According to ISO7816-3, in T = 0 mode, software must fill T bit = 0 (real block guard time = 16.5) to this field; in T = 1 mode, software must fill T bit = 1 (real block guard time = 22.5) to it. In transmit direction, the smart card sends data to smart card host controller, first.

  • Page 509: Register Description

    ML51/ML54/ML56 6.10.6 Register Description Sep. 01, 2020 Page 509 of 719 Rev 2.00...
  • Page 510 ML51/ML54/ML56 SCnCR0 – SC Control Register 0 Register SFR Address Reset Value SC0CR0 D6H, Page 0 0000_0000 b SC1CR0 E6H, Page 2 0000_0000 b RXBGTEN CONSEL AUTOCEN TXOFF RXOFF SCEN Name Description Stop Bit Length This field indicates the length of stop bit. 0 = The stop bit length is 2 ETU.
  • Page 511 ML51/ML54/ML56 Name Description AUTOCEN Auto Convention Enable Bit 0 = Auto-convention Disabled. 1 = Auto-convention Enabled. When hardware receives TS in answer to reset state and the TS is direct convention, CONSEL(SCnCR0[4]) will be set to 0 automatically, otherwise if the TS is inverse convention, and CONSEL (SCnCR0[4]) will be set to 1.
  • Page 512 ML51/ML54/ML56 SCnCR1 – SC Control Register Register SFR Address Reset Value SC0CR1 D7H, Page 0 0000_0000 b SC1CR1 E7H, Page 2 0000_0000 b PBOFF WLS[1:0] TXDMAEN RXDMAEN CLKKEEP UARTEN Name Description Odd Parity Enable Bit 0 = Even number of logic 1’s are transmitted or check the data word and parity bits in receiving mode.
  • Page 513 ML51/ML54/ML56 Name Description UARTEN UART Mode Enable Bit 0 = Smart Card mode. 1 = UART mode. Note 1:When operating in UART mode, user must set CONSEL (SCnCR0[4]) = 0 and AUTOCEN(SCnCR0[3]) = 0. Note 2:When operating in Smart Card mode, user must set UARTEN(SCnCR1 [0]) = 0. Note 3:When UART is enabled, hardware will generate a reset to reset FIFO and internal state machine.
  • Page 514 ML51/ML54/ML56 SCnDR – SC Data Register Register SFR Address Reset Value SC0DR D9H, Page 0 0000_0000 b SC1DR D9H, Page 2 0000_0000 b SCnDR[7:0] Name Description [7:0] SCnDR[7:0] SC / UART Buffer Data This byte is used for transmitting or receiving data on SC / UART bus. A write of this byte is a write to the shift register.
  • Page 515 ML51/ML54/ML56 SCnEGT – SC0~1 Extra Guard Time Register Register SFR Address Reset Value SC0EGT DAH, Page 0 0000_0000 b SC1EGT DAH, Page 2 0000_0000 b SCnEGT[7:0] Name Description [7:0] SCnEGT[7:0] SC Extra Guard Time This field indicates the extra guard timer value. Note: The counter is ETU base .
  • Page 516 ML51/ML54/ML56 SCnETURD0 – SCn ETU Rate Divider Register Register SFR Address Reset Value SC0ETURD0 DBH, Page 0 0111_0011 b SC1ETURD0 DBH, Page 2 0111_0011 b ETURDIV[7:0] Name Description [7:0] ETURDIV[7:0] LSB Bits of ETU Rate Divider The field indicates the LSB of clock rate divider. The real ETU is ETURDIV[11:0] + 1.
  • Page 517 ML51/ML54/ML56 SCnETURD1 –SC ETU Rate Divider Register Register SFR Address Reset Value SC0ETURD1 DCH, Page 0 0011_0001 b SC1ETURD1 DCH, Page 2 0011_0001 b SCDIV[2:0] ETURDIV[11:8] Name Description Reserved SCDIV[2:0] SC Clock Divider [6:4] 000 = F is F 001 = F is F 010 = F is F...
  • Page 518 ML51/ML54/ML56 ScnIE – SC Interrupt Enable Control Register Register SFR Address Reset Value SC0IE DDH, Page 0 0000_0000 b SC1IE DDH, Page 2 0000_0000 b ACERRIEN BGTIEN TERRIEN TBEIEN RDAIEN Name Description [7:5] Reserved ACERRIEN Auto Convention Error Interrupt Enable Bit This field is used to enable auto-convention error interrupt.
  • Page 519 ML51/ML54/ML56 SCnIS – SC Interrupt Status Register Register SFR Address Reset Value SC0IS DEH, Page 0 0000_0010 b SC1IS DEH, Page 2 0000_0010 b Tx_Er ACERRIF BGTIF TERRIF TBEIF RDAIF Name Description [7:6] Reserved. Tx_Er TX transmit error flag ACERRIF Auto Convention Error Interrupt Status Flag (Read Only) This field indicates auto convention sequence error.
  • Page 520 ML51/ML54/ML56 SCnTSR – SC Transfer Status Register Register SFR Address Reset Value SC0TSR DFH, Page 0 0000_1010 b SC1TSR DFH, Page 2 0000_1010 b TXEMPTY TXOV RXEMPTY RXOV Name Description Transmit /Receive in Active Status Flag (Read Only) 0 = This bit is cleared automatically when TX/RX transfer is finished 1 = This bit is set by hardware when TX/RX transfer is in active.
  • Page 521 ML51/ML54/ML56 Name Description RXOV RX Overflow Error Status Flag (Read Only) This bit is set when RX buffer overflow. Note: This bit is read only, but it can be cleared by writing 0 to it. Sep. 01, 2020 Page 521 of 719 Rev 2.00...

  • Page 522: Serial Peripheral Interface (Spi)

    ML51/ML54/ML56 6.11 Serial Peripheral Interface (SPI) 6.11.1 Overview The ML51/ML54/ML56 Series provides two Serial Peripheral Interface (SPI) block to support high- speed serial communication. SPI is a full-duplex, high-speed, synchronous communication bus between microcontrollers or other peripheral devices such as serial EEPROM, LCD driver, or D/A converter.

  • Page 523: Block Diagram

    ML51/ML54/ML56 6.11.3 Block Diagram MISO Divider Write Data Buffer MOSI 8-bit Shift Register Read Data Buffer Select CLOCK Clock Logic SPCLK MSTR SPIEN SPI Status Control Logic SPI Status Register SPI Control Register Internal SPI Interrupt Data Bus Figure 6.11-1 SPI Block Diagram Sep.

  • Page 524: Functional Description

    ML51/ML54/ML56 6.11.4 Functional Description SPI block diagram provides an overview of SPI architecture in this device. The main blocks of SPI are the SPI control register logic, SPI status logic, clock rate control logic, and pin control logic. For a serial data transfer or receiving, The SPI block exists a shift register and a read data buffer.

  • Page 525: Figure 6.11-3 Spi Single-Master / Single-Slave Interconnection

    ML51/ML54/ML56 MOSI MOSI SPI shift register SPI shift register MISO MISO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 SPCLK SPCLK SPI clock generator Master MCU Slave MCU * SS configuration follows DISMODF and SSOE bits. Figure 6.11-3 SPI Single-Master / Single-Slave Interconnection Figure 6.11-3 SPI Single-Master / Single-Slave Interconnection shows the simplest SPI system...

  • Page 526: Figure 6.11-4 Spi Clock Formats

    ML51/ML54/ML56 6.11.4.2 Clock Formats and Data Transfer To accommodate a wide variety of synchronous serial peripherals, the SPI has a clock polarity bit CPOL (SPInCR.3) and a clock phase bit CPHA (SPInCR.2). Figure 6.11-4 SPI Clock Formats shows that CPOL and CPHA compose four different clock formats. The CPOL bit denotes the SPCLK line level in its idle state.

  • Page 527: Figure 6.11-5 Spi Clock And Data Format With Cpha = 0

    ML51/ML54/ML56 SPCLK Cycles SPCLK Cycles SPCLK (CPOL=0) SPCLK (CPOL=1) Transfer Progress (internal signal) MOSI MISO Input to Slave SS SS output of Master SPIF (Master) SPIF (Slave) Transfer progress starts by a writing SPDR of Master MCU. SS automatic output affects when MSTR = DISMODF = SSOE = 1. Figure 6.11-5 SPI Clock and Data Format with CPHA = 0 SPCLK Cycles SPCLK Cycles...

  • Page 528: Table 6.11-1 Slave Select Pin Configurations

    ML51/ML54/ML56 6.11.4.3 Slave Select Pin Configuration ̅̅̅̅̅ The ML51/ML54/ML56 Series SPI gives a flexible SS pin feature for different system requirements. ̅̅̅̅̅ When the SPI operates as a Slave, SS pin always rules as Slave select input. When the Master mode ̅̅̅̅̅...

  • Page 529: Figure 6.11-7 Spi Overrun Waveform

    ML51/ML54/ML56 Data[n] Receiving Begins Data[n+1] Receiving Begins Data[n+2] Receiveing Begins Shift Register Shifting Data[n] in Shifting Data[n+1] in Shifting Data[n+2] in SPIF Read Data Buffer Data[n] Data[n] Data[n+2] SPIOVF When Data[n] is received, the SPIF will be set. If SPIF is not clear before Data[n+1] progress done, the SPIOVF will be set.

  • Page 530: Register Description

    ML51/ML54/ML56 6.11.5 Register Description SPInCR0 – Serial Peripheral Control Register0 Register SFR Address Reset Value SPI0CR0 F3H, Page 0 0000_0000 b SPI1CR0 F9H, Page 0 0000_0000 b SSOE SPIEN LSBFE MSTR CPOL CPHA SPR1 SPR0 Name Description SSOE Slave Select Output Enable This bit is used in combination with the DISMODF (SPInSR.3) bit to determine the feature of ̅̅̅̅...
  • Page 531 ML51/ML54/ML56 Name Description [1:0] SPR[1:0] SPI Clock Rate Select These two bits select four grades of SPI clock divider. The clock rates below are illustrated under F = 24 MHz condition. SPR3 SPR2 SPR1 SPR0 Divider SPI clock rate 12M bit/s 6M bit/s 3M bit/s 1.5M bit/s...
  • Page 532 ML51/ML54/ML56 SPInCR1 – Serial Peripheral Control Register1 Register SFR Address Reset Value SPI0CR1 F3H, Page 1 0000_0000 b SPI1CR1 FAH, Page 0 0000_0000 b SPR3 SPR2 TXDMAEN RXDMAEN SPIS1 SPIS0 Name Description [7:6] Reserved. [5:4] SPR[3:2] SPI Clock Rate Select These two bits select four grades of SPI clock divider.
  • Page 533 ML51/ML54/ML56 Name Description TXDMAEN SPI TX DMA Enable This bit enables the SPI TX operating by through PDMA transfer, TX data needs to be ready in XRAM before SPI TX starting. 0 = SPI TX DMA Disabled 1 = SPI TX DMA Enabled RXDMAEN SPI RX DMA Enable This bit enables the SPI RX operating by through PDMA transfer, RX data are saved in...
  • Page 534 ML51/ML54/ML56 SPInSR – Serial Peripheral Status Register Register SFR Address Reset Value SPI0SR F4H, Page 0 0000_0000 b SPI1SR FBH, Page 0 0000_0000 b SPIF WCOL SPIOVF MODF DISMODF DISSPIF TXBFF Name Description SPIF SPI Complete Flag This bit is set to logic 1 via hardware while an SPI data transfer is complete or an receiving data has been moved into the SPI read buffer.
  • Page 535 ML51/ML54/ML56 SPInDR – Serial Peripheral Data Register Register SFR Address Reset Value SPI0DR F5H, Page 0 0000_0000 b SPI1DR FCH, Page 0 0000_0000 b SPInDR[7:0] Name Description [7:0] SPInDR[7:0] Serial Peripheral Data This byte is used for transmitting or receiving data on SPI bus. A write of this byte is a write to the shift register.

  • Page 536: Inter-Integrated Circuit (I 2 C)

    ML51/ML54/ML56 6.12 Inter-Integrated Circuit (I 6.12.1 Overview The ML51/ML54/ML56 Series provides two Inter-Integrated Circuit (I C) bus to serves as an serial interface between the microcontrollers and the I C devices such as EEPROM, LCD module, temperature sensor, and so on. The I C bus used two wires design (a serial data line SDA and a serial clock line SCL) to transfer information between devices.

  • Page 537: Figure 6.12-2 I C Bus Protocol

    ML51/ML54/ML56 The I C is considered free when both lines are high. Meanwhile, any device, which can operate as a master can occupy the bus and generate one transfer after generating a START condition. The bus now is considered busy before the transfer ends by sending a STOP condition. The master generates all of the serial clock pulses and the START and STOP condition.

  • Page 538: Figure 6.12-4 Master Transmits Data To Slave By 7-Bit

    ML51/ML54/ML56 6.12.3.2 7-Bit Address with Data Format Following the START condition is generated, one byte of special data should be transmitted by the master. It includes a 7-bit long slave address (SLA) following by an 8 bit, which is a data direction bit (R/W), to address the target slave device and determine the direction of data flow.

  • Page 539: Figure 6.12-6 Data Format Of One I

    ML51/ML54/ML56 ADDRESS DATA DATA Figure 6.12-6 Data Format of One I C Transfer During the data transaction period, the data on the SDA line should be stable during the high period of the clock, and the data line can only change when SCL is low. 6.12.3.3 Acknowledge SCL pulse for any transferred byte is dedicated as an Acknowledge (ACK).

  • Page 540: Figure 6.12-8 Arbitration Procedure Of Two Masters

    ML51/ML54/ML56 by the winning master. It also releases SDA line to high level for not affecting the data transfer continued by the winning master. However, the arbitration lost master continues generating clock pulses on SCL line until the end of the byte in which it loses the arbitration. Arbitration is carried out by all masters continuously monitoring the SDA line after outputting data.
  • Page 541 ML51/ML54/ML56 Updated Status Last Status STATUS=0x18 STATUS=0x08 I2C_DAT (SLA+W) Register Control I2C_DAT=SLA+W Master to Slave (STA,STO,SI,AA)=(0,0,1,x) Slave to Master Figure 6.12-9 Control I C Bus according to the Current I C Status Master Transmitter Mode In the master transmitter mode, several bytes of data are transmitted to a slave receiver. The master should prepare by setting desired clock rate in I2CnCLK.

  • Page 542: Figure 6.12-10 Flow And Status Of Master Transmitter Mode

    ML51/ML54/ML56 ACK STATUS=0x18 ACK STATUS=0x28 STATUS=0x08 NAK STATUS=0x20 NAK STATUS=0x30 I2CnDAT ACK/ I2CnDAT ACK/ (SLA+W) (Data) I2CnDAT =SLA+W I2CnDAT =Data (STA,STO,SI,AA)=(1,0,1,x) (STA,STO,SI,AA)=(0,0,1,x) (STA,STO,SI,AA)=(0,0,1,x) STATUS=0x38 I2CnDAT ACK/ (Data) I2C_DAT=Data (STA,STO,SI,AA)=(0,0,1,x) STATUS=0x10 (STA,STO,SI,AA)=(1,0,1,x) STATUS=0xF8 (STA,STO,SI,AA)=(0,1,1,x) STATUS=0x08 (STA,STO,SI,AA)=(1,1,1,x) (Arbitration Lost) STATUS=0x38 C bus will be release; Not addressed SLV mode will be enterd I2CnDAT ACK/...

  • Page 543: Figure 6.12-11 Flow And Status Of Master Receiver Mode

    ML51/ML54/ML56 Master Receiver Mode In the master receiver mode, several bytes of data are received from a slave transmitter. The transaction is initialized just as the master transmitter mode. Following the START condition, I2CnDAT should be loaded with the target slave address and the data direction bit “read” (SLA+R). After the SLA+R byte is transmitted and an acknowledge bit has been returned, the SI flag is set again and I2CnSTAT is read as 40H.
  • Page 544 ML51/ML54/ML56 Slave Receiver In the slave receiver mode, several bytes of data are received form a master transmitter. Before a transmission is commenced, I2CnADDRx should be loaded with the address to which the device will respond when addressed by a master. I2CnCLK does not affect in slave mode. The AA bit should be set to enable acknowledging its own slave address.

  • Page 545: Figure 6.12-12 Flow And Status Of Slave Receiver Mode

    ML51/ML54/ML56 Switch to not addressed mode STATUS=0x60 STATUS=0x80 Own SLA will be recognized I2CnDAT I2CnDAT (Data) (SLA+W) STATUS=0x88 (STA,STO,SI,AA)=(0,0,1,1) (STA,STO,SI,AA)=(0,0,1,1) (Arbitration Lost) STATUS=0x68 I2CnDAT I2CnDAT (Data) (SLA+W) (STA,STO,SI,AA)=(0,0,1,0) STATUS=0xA8 STATUS=0xA0 I2CnDAT (SLA+R) (STA,STO,SI,AA)=(0,0,1,X) (Arbitration Lost) STATUS=0xA0 STATUS=0xB0 I2CnDAT (SLA+R) (STA,STO,SI,AA)=(0,0,1,1) (STA,STO,SI,AA)=(0,0,1,X) STATUS=0xB8 Switch to not addressed mode...

  • Page 546: Figure 6.12-13 Flow And Status Of General Call Mode

    ML51/ML54/ML56 6.12.3.6 General Call The General Call is a special condition of slave receiver mode by been addressed with all “0” data in slave address with data direction bit. Both GC (I2CnADDRx.0) bit and AA bit should be set as 1 to enable acknowledging General Calls.

  • Page 547: C Time-Out

    ML51/ML54/ML56 occurred during a transaction. A bus error is caused by a START or STOP condition appearing temporally at an illegal position such as the second through eighth bits of an address or a data byte, and the acknowledge bit. When a bus error occurs, the SI flag is set immediately. When a bus error is detected on the I C bus, the operating device immediately switches to the not addressed salve mode, releases SDA and SCL lines, sets the SI flag, and loads I2CnSTAT as 00H.

  • Page 548: Figure 6.12-15 I C Time-Out Counter

    ML51/ML54/ML56 not set for a period. The 14-bit time-out counter will overflow and require the interrupt service. 14-bit I C Time-out Counter I2TOF Clear Counter I2CEN I2TOCEN Figure 6.12-15 I C Time-Out Counter Sep. 01, 2020 Page 548 of 719 Rev 2.00...
  • Page 549 ML51/ML54/ML56 I2CnTOC – I C Time-out Counter Register SFR Address Reset Value I2C0TOC BFH, Page 0 0000_0000 b I2C1TOC B6H, Page 0 0000_0000 b I2TOCEN I2TOF Name Description [7:3] Reserved I2TOCEN I 2 C0 Time-Out Counter Enable 0 = I C time-out counter Disabled.

  • Page 550: C Interrupt

    ML51/ML54/ML56 6.12.5 I C Interrupt There are two I C flags, SI and I2TOF. Both of them can generate an I C event interrupt requests. If C interrupt mask is enabled via setting EI2C and EA as 1, CPU will execute the I C interrupt service routine once any of these two flags is set.
  • Page 551 ML51/ML54/ML56 I2CnCON – I C Control (Bit-addressable) Register SFR Address Reset Value I2C0CON C0H, All pages 0000_0000 b I2C1CON E8H, All p Pages ages 0000_0000 b I2CEN Name Description I 2 Cn Hold Time Extend Enable 0 = I C DATA to SCL hold time extend disabled 1 = I C DATA to SCL hold time extend enabled, extend 8 system clock I2CEN...
  • Page 552 ML51/ML54/ML56 Name Description I 2 Cn Interrupt Flag SI flag is set by hardware when one of 26 possible I C status (besides F8H status) is entered. After SI is set, the software should read I2CnSTAT register to determine which step has been passed and take actions for next step.
  • Page 553 ML51/ML54/ML56 I2CnSTAT – I C Status Register SFR Address Reset Value I2C0STAT BDH, Page 0 1111_1000 b I2C1STAT B4H, Page 0 1111_1000 b I2CnSTAT[7:3] Name Description I 2 Cn Status Code [7:3] I2CnSTAT[7:3] The MSB five bits of I2CnSTAT contains the status code. There are 27 possible status codes.
  • Page 554 ML51/ML54/ML56 I2CnDAT – I C Data Register SFR Address Reset Value I2C0DAT BCH, Page 0 0000_0000 b I2C1DAT B3H, Page 0 0000_0000 b I2CnDAT[7:0] Name Description I 2 Cn Data [7:0] I2CnDAT[7:0] I2CnDAT contains a byte of the I C data to be transmitted or a byte, which has just received.
  • Page 555 ML51/ML54/ML56 I2CnADDRx – I2Cn Own Slave Address Register SFR Address Reset Value I2C0ADDR0 C1H, Page 0 0000_0000 b I2C0ADDR1 A1H, Page 2 0000_0000 b I2C0ADDR2 A2H, Page 2 0000_0000 b I2C0ADDR3 A3H, Page 2 0000_0000 b I2C1ADDR0 B2H, Page 0 0000_0000 b I2C1ADDR1 A4H, Page 2...
  • Page 556 ML51/ML54/ML56 I2CnCLK – I C Clock Register SFR Address Reset Value I2C0CLK BEH, Page 0 0000_1001 b I2C1CLK B5H, Page 0 0000_1001 b I2CnCLK[7:0] Name Description I2CnCLK[7:0] I2Cn Clock Setting [7:0] In master mode: This register determines the clock rate of I C bus when the device is in a master mode.

  • Page 557: Typical Structure Of I C Interrupt Service Routine

    ML51/ML54/ML56 6.12.7 Typical Structure of I C Interrupt Service Routine The following software example in C language for KEIL C51 compiler shows the typical structure of the I C interrupt service routine including the 26 state service routines and may be used as a base for user applications.
  • Page 558 ML51/ML54/ML56 //=========== case 0x38: /*38H, arbitration lost*/ STA = 1; //retry to transmit START if bus free break; //==================== //Master Receiver Mode //==================== case 0x40: /*40H, SLA+R transmitted, ACK received*/ AA = 1; //ACK next received DATA break; case 0x48: /*48H, SLA+R transmitted, NACK received*/ STO = 1;...
  • Page 559 ML51/ML54/ML56 break; case 0x88: /*88H, previous own SLA+W, DATA received, NACK returned, not addressed SLAVE mode entered*/ DATA_RECEIVED_LAST2 = I2DAT; AA = 1; //wait for ACK next Master addressing break; case 0x90: /*90H, previous General Call, DATA received, ACK returned*/ DATA_RECEIVED3 = I2DAT;...
  • Page 560 ML51/ML54/ML56 AA = 1; break; case 0Xc8: /*C8H, previous own SLA+R, last DATA trans- mitted, ACK received, not addressed SLAVE AA = 1; mode entered*/ break; }//end of switch (I2STAT) SI = 0; //SI should be the last command of I C ISR while(STO);...

  • Page 561: 12-Bit Analog-To-Digital Converter (Adc)

    ML51/ML54/ML56 6.13 12-bit Analog-to-digital Converter (ADC) 6.13.1 Overview The ML51/ML54/ML56 Series is embedded with a 12-bit SAR ADC. The ADC (analog-to-digital converter) allows conversion of an analog input signal to a 12-bit binary representation of that signal. The ML51/ML54/ML56 Series is selected as 8-channel inputs in single end mode. The internal band- gap voltage 0.814 V also can be the internal ADC input.

  • Page 562: Block Diagram

    ML51/ML54/ML56 6.13.2 Block Diagram ADCEN ADC_CH0 0000 ADC_CH1 0001 ADC_CH2 0010 ADC Interrupt ADCF ADC_CH3 0011 ADC_CH4 1 2- bit SAR 0100 ADC_CH5 0101 ADC_CH6 ADC flag 0110 ADC_CH7 0111 1000 ADCRH ADCRL VTEMP 1001 1010 ADC_CH10 ADC XRAM Control ADC_CH11 1011 ADC_CH12...

  • Page 563: Functional Description

    ML51/ML54/ML56 6.13.3 Functional Description 6.13.3.1 ADC Operation Before ADC operation, the ADC circuit should be enabled by setting ADCEN (ADCCON1.0). This makes ADC circuit active. It consume extra power. Once ADC is not used, clearing ADCEN to turn off ADC circuit saves power. The ADC analog input pin should be specially considered.

  • Page 564: Figure 6.13-2 External Triggering Adc Circuit

    ML51/ML54/ML56 [00] PWM0CH0 [01] PWM0CH2 External ADCDLY PWM0CH4 Trigger [10] STADC [11] PTRGSEL[1:0] (ADCCON0[5:4]) PTRGTYP[1:0] (ADCCON1[3:2]) Figure 6.13-2 External Triggering ADC Circuit 6.13.3.3 ADC Conversion Result Comparator The ML51/ML54/ML56 Series ADC has a digital comparator, which compares the A/D conversion result with a 12-bit constant value given in ACMPH and ACMPL registers.

  • Page 565: Figure 6.13-4 Adc Continues Mode With Dma

    ML51/ML54/ML56 ADC Continues Conversion schedule {ADCRH[7:0],ADCRL[3:0]} ADCR[11:4] ADCR[3:0] ADCR[11:4] ADCR[3:0] ADC conversion result length (ADCCN[7:0] + 1) ADCR[11:4] ADCR[3:0] XRAM ADDR XRAM {ADCBAH[3:0],ADCBAL[7:0]} ADCR[11:4] ADCBA[11:0] ADCR[11:4] ADCBA[11:0] + 1 ADCR[11:4] ADCBA[11:0] + N ADCR[3:0] ADCR[3:0] ADCBA[11:0] + N + 1 ADCR[3:0] ADCR[3:0] ADCBA[11:0] + N + 2...

  • Page 566: Register Description

    ML51/ML54/ML56 6.13.4 Register Description Sep. 01, 2020 Page 566 of 719 Rev 2.00...
  • Page 567 ML51/ML54/ML56 ADCCON0 – ADC Control 0 Register SFR Address Reset Value ADCCON0 A1H, Page 0 0000_0000b ADCF ADCS ETGSEL1 ETGSEL0 ADCHS3 ADCHS2 ADCHS1 ADCHS0 Name Description ADCF ADC Flag This flag is set when an A/D conversion is completed in single sampling mode, final sampling complete in continue sampling mode or comparing hit if result comparator is enabled.
  • Page 568 ML51/ML54/ML56 [3:0] ADCHS[3:0] A/D Converting Channel Select This filed selects the activating analog input source of ADC. If ADCEN is 0, all inputs are disconnected. 0000 = ADC_CH0 0001 = ADC_CH1. 0010 = ADC_CH2. 0011 = ADC_CH3. 0100 = ADC_CH4. 0101 = ADC_CH5.
  • Page 569 ML51/ML54/ML56 ADCCON1 – ADC Control 1 Register SFR Address Reset Value ADCCON1 E1H, Page 0 0000_0000 b CONT ETGTYP[1:0] ADCEX ADCEN Name Description [7:6] Reserved ADC Half Done Interrupt Enable 0 = ADC interrupt is not set while half of A/D conversions are complete in continue mode 1 = ADC interrupt is set while half of A/D conversions are complete in continue mode CONT ADC Continue Sampling Select...
  • Page 570 ML51/ML54/ML56 ADCCON2 – ADC Control 2 Register SFR Address Reset Value ADCCON2 E2H, Page 0 0000_0000 b ADFBEN ADCMPOP ADCMPEN ADCMPO ADCAQT[2:0] ADCDLY.8 Name Description ADFBEN ADC Compare Result Asserting Fault Brake Enable 0 = ADC asserting Fault Brake Disabled. 1 = ADC asserting Fault Brake Enabled.
  • Page 571 ML51/ML54/ML56 ADCDLY – ADC Trigger Delay Counter Register SFR Address Reset Value ADCDLY E3H, Page 0 0000_0000 b ADCDLY[7:0] Name Description ADCDLY[7:0] ADC External Trigger Delay Counter Low Byte [7:0] This 8-bit field combined with ADCCON2.0 forms a 9-bit counter. This counter inserts a delay after detecting the external trigger.
  • Page 572 ML51/ML54/ML56 AINDIDS0 – ADC Channel Digital Input Disconnect Register SFR Address Reset Value AINDIDS0 CEH, Page 1 0000_0000 b AIN7DIDS AIN6DIDS AIN5DIDS AIN4DIDS AIN3DIDS AIN2DIDS AIN1DIDS AIN0DIDS Name Description AINnDIDS ADC Channel Digital Input Disable [7:0] 0 = Enabled digital input at ADC channel n. 1 = Disabled digital input at ADC channel n .
  • Page 573 ML51/ML54/ML56 AINDIDS1 – ADC Channel Digital Input Disconnect Register SFR Address Reset Value AINDIDS1 CEH, Page 2 0000_0000 b AIN15DIDS AIN14DIDS AIN13DIDS AIN12DIDS AIN11DIDS AIN10DIDS Name Description AINnDIDS ADC Channel Digital Input Disable [7:0] 0 = Enabled digital input at ADC channel n. 1 = Disabled digital input at ADC channel n .
  • Page 574 ML51/ML54/ML56 ADCRH – ADC Result High Byte Register SFR Address Reset Value ADCRH C3H, Page 0 0000_0000 b ADCR[11:4] Name Description ADCR[11:4] ADC Result High Byte [7:0] The most significant 8 bits of the ADC result stored in this register. Sep.
  • Page 575 ML51/ML54/ML56 ADCRL – ADC Result Low Byte Register SFR Address Reset Value ADCRL C2H, Page 0 0000_0000 b ADCR[3:0] Name Description [7:4] Reserved [3:0] ADCR[3:0] ADC Result Low Byte The least significant 4 bits of the ADC result stored in this register. Sep.
  • Page 576 ML51/ML54/ML56 ADCMPH – ADC Compare High Byte Register SFR Address Reset Value ADCMPH CFH, Page 0 0000_0000 b ADCMP[11:4] Name Description ADCMP[11:4] ADC Compare High Byte [7:0] The most significant 8 bits of the ADC compare value stores in this register. Sep.
  • Page 577 ML51/ML54/ML56 ADCMPL – ADC Compare Low Byte Register SFR Address Reset Value ADCMPL CEH, Page 0 0000_0000 b ADCMP[3:0] Name Description [7:4] Reserved [3:0] ADCMP[3:0] ADC Compare Low Byte The least significant 4 bits of the ADC compare value stores in this register. Sep.
  • Page 578 ML51/ML54/ML56 ADCBAH – ADC RAM Base Address High Byte Register SFR Address Reset Value ADCBAH E4H, Page 0 0000_0000 b ADCBA[3:0] Name Description [7:4] Reserved [3:0] ADCBA[3:0] ADC RAM Base Address (High Byte) The most significant 4 bits of RAM base address to store ADC continue sampling data. RAM base address ADCBA[11:0] = {ADCBAH[3:0], ADCBAL[7:0]} Sep.
  • Page 579 ML51/ML54/ML56 ADCBAL – ADC RAM Base Address Low Byte Register SFR Address Reset Value ADCBAL CBH, Page 0 0000_0000 b ADCBA[7:0] Address: CBH, Page:0 Reset value: 0000 0000b Name Description ADCBA[7:0] ADC RAM Base Address (Low Byte) [7:0] The least significant 8 bits of RAM base address to store ADC continue sampling data. RAM base address ADCBA[11:0] = { ADCBAH[3:0], ADCBAL[7:0]} Sep.
  • Page 580 ML51/ML54/ML56 ADCSN – ADC Sampling Number Register SFR Address Reset Value ADCSN E5H, Page 0 0000_0000 b ADCSN[7:0] Name Description ADCSN[7:0] ADC Sampling Number [7:0] The total sampling numbers for ADC continue sampling select. Total sampling number= ADCSN[7:0] + 1 Sep.
  • Page 581 ML51/ML54/ML56 ADCCN – ADC Current Sampling Number Register SFR Address Reset Value ADCCN E6H, Page 0 0000_0000 b ADCCN[7:0] Name Description ADCCN[7:0] ADC Current Sampling Number [7:0] The current sampling numbers for ADC continue sampling select. The current sampling number= ADCCN[7:0] + 1 Sep.
  • Page 582 ML51/ML54/ML56 ADCSR – ADC Status Register Register SFR Address Reset Value ADCSR E7H, Page 0 0000_0000 b SLOW ADCDIV[2:0] CMPHIT HDONE FDONE Name Description SLOW ADC Slow Speed Selection This bit is used to select ADC low speed. 0 = high speed 500 ksps 1 = low speed 200 ksps [6:4] ADCDIV[2:0]...

  • Page 583: Voltage Reference

    ML51/ML54/ML56 6.14 Voltage Reference (V The V pin is for analog multiplexer, such as ADC, ACMP. It default be used as an external source(set ENVRF = 0). It also could be configurable as on-chip reference voltage generator (V REF_IN by setting ENVRF = 1 (seeFigure 6.14-1 VREF Block Diagram). The output voltage is selectable by setting VRFSEL[2:0].
  • Page 584 ML51/ML54/ML56 VRFCON – Internal V Control (TA Protected) Register SFR Address Reset Value VRFCON A9H,Page 1, TA protected 0000_0000 b VRFSEL[2:0] ENLOAD ENVRF Name Description Reserved [6:4] VRFSEL[2:0] Internal V Output Voltage Select This field selects V output voltage. 000 = 1.538V , when V >...

  • Page 585: Analog Comparator Controller (Acmp)

    ML51/ML54/ML56 6.15 Analog Comparator Controller (ACMP) 6.15.1 Overview The ML51/ML54/ML56 Series contains two comparators. The comparator output is logic 1 when positive input is greater than negative input; otherwise, the output is 0. The comparator can be configured to generate an interrupt when the comparator output value changes. 6.15.2 Feature ...

  • Page 586: Block Diagram

    ML51/ML54/ML56 6.15.3 Block Diagram ACMP_P0 (P2.5) CRVSSEL ACMP_P1 (P2.3) (ACMPCR2[1]) ACMP_P2 (P2.1) ACMP_P3 (P3.1) VDDA VREF CRVEN POSSEL (ACMPCR2[0] (ACMPCR0[7:6]) ACMPEN (ACMPCR0[0]) SPEED0 (ACMPCR2[6]) ACMP0_N0 (P2.4) ACMP0O (ACMPSR[1]) ACMP0_O CRV0 output ACMP0 (P4.1) AO0PEN (ACMPCR2[4]) HYSEN ACMP0_N1 (P2.0) (ACMPCR0[2]) CRV0CTL[2:0] (ACMPVREF[2:0]) ACMPIE NEGSEL...

  • Page 587: Functional Description

    ML51/ML54/ML56 6.15.4 Functional Description 6.15.4.1 Hysteresis Function The analog comparator provides the hysteresis function to make the comparator to have a stable output transition. If comparator output is 0, it will not be changed to 1 until the positive input voltage exceeds the negative input voltage by a high threshold voltage.

  • Page 588: Figure 6.15-3 Comparator Reference Voltage Block Diagram

    ML51/ML54/ML56 VREF CRVSSEL (ACMPCR2[1]) CRVEN (ACMPCR2[0]) CRV0 CRV1 Band-gap CRVEN (ACMPCR2[0]) CRV1CTL[2:0] CRV0CTL[2:0] (ACMPVREF[6:4]) (ACMPVREF[2:0]) Figure 6.15-3 Comparator Reference Voltage Block Diagram Note that If CRVEN = 0, CRV0 is equal to 0 and CRV1 is equal to Band-gap. 6.15.4.3 Interrupt Sources The comparator generates an output ACMPnO (ACMPSR).

  • Page 589: Register Description

    ML51/ML54/ML56 6.15.5 Register Description Sep. 01, 2020 Page 589 of 719 Rev 2.00...
  • Page 590 ML51/ML54/ML56 ACMPCR0 – Analog Comparator Control Register 0 Register SFR Address Reset Value ACMPCR0 D2H, Page 0 0000_0000 b POSSEL NEGSEL WKEN HYSEN ACMPIE ACMPEN Name Description [7:6] POSSEL Comparator 0 Positive Input Selection 00 = ACMP0_P0 (P2.5) pin. 01 = ACMP0_P1 (P2.3) pin. 10 = ACMP0_P2 (P2.1) pin.
  • Page 591 ML51/ML54/ML56 ACMPCR1 – Analog Comparator Control Register 1 Register SFR Address Reset Value ACMPCR1 D3H, Page 0 0000_0000 b POSSEL NEGSEL WKEN HYSEN ACMPIE ACMPEN Name Description POSSEL Comparator 1 Positive Input Selection [7:6] 00 = ACMP1_P0 (P2.5) pin. 01 = ACMP1_P1 (P2.3) pin. 10 = ACMP1_P2 (P2.1) pin.
  • Page 592 ML51/ML54/ML56 ACMPCR2 – Analog Comparator Control Register 2 Register SFR Address Reset Value ACMPCR2 ABH, Page 1 0000_0000 b SPEED1 POE1 POE0 SPEED0 CRVSSEL CRVEN Name Description SPEED1 Analog Comparator 1 Speed Control [7:6] 00 = slow speed, propagation delay : 4.5us, 1.2uA (typ.) 01 = slow+ speed, propagation delay : 2.0us, 3uA (typ.) 10 = fast speed, propagation delay : 0.6us, 10uA (typ.) 11 = fast+ speed, propagation delay : 0.2us, 75uA (typ.)
  • Page 593 ML51/ML54/ML56 ACMPSR – Analog Comparator Status Register Register SFR Address Reset Value ACMPSR D4H, Page 0 0000_0000 b ACMP1O ACMP1IF ACMP0O ACMP0IF Name Description [7:4] Reserved ACMP1O Comparator 1 Output Synchronized to the PCLK to allow reading by software. Cleared when the comparator 1 is disabled, i.e.
  • Page 594 ML51/ML54/ML56 – ACMP Reference Voltage Control Register ACMPV Register SFR Address Reset Value ACMPV D5H, Page 0 0000_0000 b CRV1CTL[2:0] CRV0CTL[2:0] Name Description Reserved [6:4] CRV1CTL[2:0] Comparator 1 Reference Voltage Setting CRV1 = CRV source voltage * (2/12+CRV1CTL/12). Reserved [2:0] CRV0CTL[2:0] Comparator 0 Reference Voltage Setting CRV0 = CRV source voltage * (2/12+CRV0CTL/12).

  • Page 595: Pdma Controller (Pdma)

    ML51/ML54/ML56 6.16 PDMA Controller (PDMA) 6.16.1 Overview The ML51/ML54/ML56 Series provides peripheral direct memory access (PDMA) controller. The PDMA controller is used to provide high-speed data transfer between memory and peripherals or between memory and memory. The PDMA controller can transfer data from one address to another without CPU intervention.

  • Page 596: Functional Description

    ML51/ML54/ML56 6.16.4 Functional Description PDMA_INT XRAM Address XRAM Data PDMA Controller PDMA_CCNT[7:0] PDMA_CRC PDMA_TSR Done MOSI MISO SPCLK PDMA_CNT[7:0] PDMA_MA[7:0],0x0 Data Buffer SIO/RX SMC/UART SCLK/TX M2MSA[7:0], 0x0 PSSEL[2:0] (PDMA_CR[2]) (PDMA_CR[1]) (PDMA_CR[0]) (PDMA_CR[6:4]) Figure 6.16-2 PDMA Controller Block Diagram 6.16.4.1 Operating Modes Each PDMA channel behavior is not pre-defined, user must configure the channel service settings of PSSEL[3:0] registers before starting the related PDMA channel operation.
  • Page 597 ML51/ML54/ML56 sets EN DMAnCR[0] bit and RUN DMAnCR[1] bit to start operation again. SMC/UART peripheral to XRAM memory 1. Configure DMAnCR register to set EN DMAnCR[0] bit to enable PDMA channel. 2. Set PSSEL[3:0] = 0010 SMC/UART RX ( or 0110 SMC/UART TX) (DMAnCR (n-1~2)) register to configure the channel service setting.

  • Page 598: Figure 6.16-3 Crc-8 Block Diagram

    ML51/ML54/ML56 6.16.4.2 CRC-8 Function for PDMA Data_in[7:0] REFIN Bit order Revise CRC-8: X + X + 1 Seed[7:0] CRC_active REFOUT Bit order Revise CRC[7:0] Figure 6.16-3 CRC-8 Block Diagram Sep. 01, 2020 Page 598 of 719 Rev 2.00...

  • Page 599: Register Description

    ML51/ML54/ML56 6.16.5 Register Description Sep. 01, 2020 Page 599 of 719 Rev 2.00...
  • Page 600 ML51/ML54/ML56 DMAnCR – PDMAn Control Register Register SFR Address Reset Value DMA0CR0 92H, Page 0 0000_0000 b DMA1CR0 EBH, Page 0 0000_0000 b DMA2CR0 B3H, Page 2 0000_0000 b DMA3CR0 ABH, Page 2 0000_0000 b PSSEL[3:0] Name Description [7:4] PSSEL[3:0] Peripheral Source Select 0000 = XRAM to XRAM 0001 = SPI0 RX...
  • Page 601 ML51/ML54/ML56 DMAnMAL – PDMA XRAM Base Address Low Byte Register SFR Address Reset Value DMA0MAL 93H, Page 0 0000_0000 b DMA1MAL ECH, Page 0 0000_0000 b DMA2MAL B4H, Page 2 0000_0000 b DMA3MAL ACH, Page 2 0000_0000 b MAL[7:0] Name Description [7:0] MAL[7:0]...
  • Page 602 ML51/ML54/ML56 DMAnBAH – PDMAn XRAM Base Address and Memory to Memory Destination Address High Byte Register SFR Address Reset Value DMA0BAH F6H, Page 0 0000_0000 b DMA1BAH FDH, Page 0 0000_0000 b DMA2BAH B2H, Page 2 0000_0000 b DMA3BAH AAH, Page 2 0000_0000 b MTMDA[7:4] XRAMA[7:4]...
  • Page 603 ML51/ML54/ML56 DMAnCNT – PDMA Transfer Count Register SFR Address Reset Value DMA0CNT 94H, Page 0 0000_0000 b DMA1CNT EDH, Page 0 0000_0000 b DMA2CNT B5H, Page 2 0000_0000 b DMA3CNT ADH, Page 2 0000_0000 b DMAnCNT[7:0] Name Description [7:0] DMAnCNT[7:0] PDMA Transfer Count The total transfer count for PDMA request operation.
  • Page 604 ML51/ML54/ML56 DMAnCCNT – PDMA Current Transfer Count Register SFR Address Reset Value DMA0CCNT 95H, Page 0 0000_0000 b DMA1CCNT EEH, Page 0 0000_0000 b DMA2CCNT B6H, Page 2 0000_0000 b DMA3CCNT AEH, Page 2 0000_0000 b DMAnCCNT[7:0] Name Description [7:0] DMAnCCNT[7:0] PDMA Current Transfer Count The current transfer count for PDMA request operation.
  • Page 605 ML51/ML54/ML56 DMAnTSR – PDMAn Transfer Status Register Register SFR Address Reset Value DMA0TSR E9H, Page 0 0000_0000 b DMA1TSR F1H, Page 0 0000_0000 b DMA2TSR B1H, Page 2 0000_0000 b DMA3TSR A9H, Page 2 0000_0000 b HDONE FDONE Name Description [7:3] Reserved PDMA in Active Status Flag (Read Only)
  • Page 606 ML51/ML54/ML56 MTMnDA – Memory to Memory Destination Address Low Byte Register SFR Address Reset Value MTM0DA EAH, Page 0 0000_0000 b MTM1DA F2H, Page 0 0000_0000 b MTM2DA B7H, Page 2 0000_0000 b MTM3DA AFH, Page 2 0000_0000 b MTMnDA[7:0] Name Description [7:0]...
  • Page 607 ML51/ML54/ML56 DMAnCR1 – PDMAn Control 1 Register Register SFR Address Reset Value DMA0CR1 8AH, Page 3 0000_0000 b DMA1CR1 8BH, Page 3 0000_0000 b DMA2CR1 8CH, Page 3 0000_0000 b DMA3CR1 8DH, Page 3 0000_0000 b XOROUT REFOUT REFIN CRCEN Name Description [7:4]...
  • Page 608 ML51/ML54/ML56 DMAnCRC – PDMA CRC Checksum Register SFR Address Reset Value DMA0CRC 92H, Page 3 0000_0000 b DMA1CRC 93H, Page 3 0000_0000 b DMA2CRC 94H, Page 3 0000_0000 b DMA3CRC 95H, Page 3 0000_0000 b CRC[7:0] Name Description [7:0] CRC[7:0] PDMA CRC Checksum The checksum of the Cyclic Redundancy Check (CRC-8) calculation The CRC-8 polynomial is below...
  • Page 609 ML51/ML54/ML56 DMAnSEED – PDMA CRC SEED Register SFR Address Reset Value DMA0SEED 9AH, Page 3 0000_0000 b DMA1SEED 9BH, Page 3 0000_0000 b DMA2SEED 9CH, Page 3 0000_0000 b DMA3SEED 9DH, Page 3 0000_0000 b SEED[7:0] Name Description [7:0] SEED[7:0] PDMA CRC SEED The seed of the Cyclic Redundancy Check (CRC-8) calculation The CRC-8 polynomial is below...

  • Page 610: Lcd Driver

    ML51/ML54/ML56 6.17 LCD Driver 6.17.1 Overview The Liquid Crystal Displays (LCD) panel is widely used to meet the display need in applications. The ML54/ML56 series is equipped with LCD driver that can directly drive the LCD panel with 4 COM x 32 SEG , 6 COM x 30 SEG or 8 COM x 28 SEG.

  • Page 611: Block Diagram

    ML51/ML54/ML56 6.17.3 Block Diagram LCDCPCT1[1:0], CPCNT[9:0] D LCDCPCT0[7:0] Charge Pump Active Counter Latch Counter LCDCPCT > LCDCPALIF LCDCPACLT (LCDIF[0]) LCD_DIS = 0 LCD_INT LCDCPALCT1[1:0], LCD_IE(LCDCO LCDCPALCT0[7:0] LCDCPOVIF LCD_DIS(LCDCON1[3]) LCD _CTRL N1[2]) LCDIF2] _REG LCDCPCT = 0x3FF LCD_DIS = 1 LCDCPIF LCDCPCT <...

  • Page 612: Functional Description

    ML51/ML54/ML56 6.17.4 Functional Description 6.17.4.1 Control Logic Setting LCDEN (LCDCON.7) as 1 turns on the LCD circuit. If LCDEN is enabled, COM pins and SEG pins driver signals and display the LCD panel according to the registers. The duty and bias can be setting by DUTY[1:0] (LCDCON[3:2]) and BIAS[1:0] (LCDCON[5:4]) bits individually.

  • Page 613: Figure 6.17-2. Lcd Register Map Example

    ML51/ML54/ML56 Display Off Display On If COM1 and SEG15 is the same pin, MFP defined this pin as COM1 DUTY[1:0] = 00 (4COM) DUTY[1:0] = 10 (8COM) DUTY[1:0] = 10 (8COM) LCDPTR = 0x0A ~ 0x11 LCDPTR = 0x0A ~ 0x11 LCDPTR = 0x0A ~ 0x11 LCDDAT = 0xFF LCDDAT = 0xB7...

  • Page 614: Figure 6.17-4. Example Of Type A And Type B 8 Com And Seg Driving Signals Of 1/3 Bias

    ML51/ML54/ML56 COM0 COM1 LCDDAT (bit) (7) (6) (5) (4) (3) (2) (1) (0) 1 SEG0 LCDPTR =0H 0 SEG1 LCDPTR =1H COM2 COM7 SEG0 SEG1 A TYPE B TYPE Frame Frame Frame Odd Frame Even Frame 2/3V 2/3V COM0 COM0 1/3V 1/3V 2/3V...

  • Page 615: Figure 6.17-5. Example Of Type A And Type B 8 Com And Seg Driving Signals Of 1/4 Bias

    ML51/ML54/ML56 COM0 COM1 LCDDAT (bit) (7) (6) (5) (4) (3) (2) (1) (0) 1 SEG0 LCDPTR =0H COM2 0 SEG1 LCDPTR =1H COM7 SEG0 SEG1 A TYPE B TYPE Frame Frame Frame Odd Frame Even Frame 3/4V 3/4V COM0 2/4V COM0 2/4V 1/4V...

  • Page 616: Table 6.17-1 Vlcd Source Selection Table

    ML51/ML54/ML56 6.17.4.2 LCD Driving Voltage Select Followoing table shows the three types of LCD voltage source and how to select. VLCD_MODE[1:0] Range VLCD / LCD_DH1 / LCD_DH2 pin Note (LCDMODE[1:0]) External 1.8 ~ 5.5 V VLCD pin connect with external voltage is acceptable VLCD LCD_DH1 and LCD_DH2 can be used as...
  • Page 617 ML51/ML54/ML56 6.17.4.4 LCD Interrupt There are Three LCD flags, LCDCPIF , LCDCPOVIF and LCDCPALIF. ALL of them can generate an LCD event interrupt requests. If LCD interrupt Enable bit LCDIE and interrupt source select pin LCDIS is select. After EA as 1, CPU will execute the LCD interrupt service routine once any of these three flags is set.

  • Page 618: Register Description

    ML51/ML54/ML56 6.17.5 Register Description Sep. 01, 2020 Page 618 of 719 Rev 2.00...
  • Page 619 ML51/ML54/ML56 LCDCON – LCD Control Register SFR Address Reset Value LCDCON F9H, Page 3 0000_0000 b LCDEN TYPE BIAS[1:0] DUTY[1:0] Name Description LCDEN LCD Enable 0 = LCD circuit OFF. Each COM and SEG pin functions as general purpose I/O and its multi-functions other than LCD.
  • Page 620 ML51/ML54/ML56 LCDCLK – LCD Clock Control Register SFR Address Reset Value LCDCLK FAH, Page 3 0000_0000 b LCDCKS DISP LCDDIV[2:0] Name Description [7:5] Reserved LCDCKS LCD Clock Source Select 0 = LIRC/2 1 = LXT/2 DISP DISP The LCD display keeps display on or display off during chip power-down mode. If LXT is used as the LCD clock source, user should turn on LXT first by software.
  • Page 621 ML51/ML54/ML56 LCDDPTR – LCD Data Pointer Register SFR Address Reset Value LCDPTR FBH, Page 3 0000_0000 b LCDPTR[4:0] Name Description [7:5] Reserved [4:0] LCDPTR[4:0] LCD Data Pointer This field determines which LCD display data register is accessed by LCDDAT. It’s also means the LCD segment address.the value is from 0 ~31.
  • Page 622 ML51/ML54/ML56 LCDDAT – LCD Data Register SFR Address Reset Value LCDDAT FCH, Page 3 0000_0000 b LCDDAT[7:0] Name Description [7:0] LCDDAT[7:0] LCD Data This byte is defined which COM pin should be enabled. Bit 0 means COM 0 and bit 7 means COM 7.
  • Page 623 ML51/ML54/ML56 LCDPWR – LCD Power Saving Mode Register SFR Address Reset Value LCDPWR FDH, Page 3 0000_0000 b PWR_SAVE[1:0] Name Description [7:2] Reserved [1:0] PWR_SAVE[1:0] LCD Power Save Mode Select LCD driving cycle select, turn on timing decide the driving current. 00 = always ON.
  • Page 624 ML51/ML54/ML56 LCDBL – LCD Blink Register SFR Address Reset Value LCDBL FEH, Page 3 0000_0000 b BLINK BLF[2:0] Address: FEH, Page 3 Reset value: 0000 0000b Name Description [7:4] Reserved BLINK LCD BLINK 0 = LCD always on 1 = LCD blinking. The blinking frequency is based on BLF[2:0] define. [2:0] BLF[2:0] BLINK Frequency...
  • Page 625 ML51/ML54/ML56 LCDMODE – LCD Mode Register SFR Address Reset Value LCDMODE FFH, Page 3 0000_0000 b R_MODE BUF_MODE VLCD_MODE[1:0] Name Description R_MODE Resister Mode Enable This bit going to define LCD driver as Resistor Mode or Resistor Enhance Mode About R_MODE, RE_MODE and BUF_MODE define and the LCD driving current please reference Table 6.17-2 LCD Driving Mode .
  • Page 626 ML51/ML54/ML56 LCDCPUMP – LCD Charge Pump Voltage Set Value Register SFR Address Reset Value LCDCPUMP F1H, Page 3 0000_0000 b VCP_SEL[5:0] Address: F1H, Page 3 Reset value: 0000 0000b Name Description [7:6] Reserved [5:0] VCP_SEL[5:0] Charge Pump Voltage Set Value 000000 = 5.4V 000101 = 5.2V 001010 = 5.0V...
  • Page 627 ML51/ML54/ML56 LCDCON1– LCD Control Register 1 (TA Protected) Register SFR Address Reset Value LCDCON1 F4H, Page 3, TA protected 0000_0000 b LCDIS LCDIE RE_MODE Name Description [7:4] Reserved LCDIS LCD Interrupt Source Select 0 = LCD charge pump counter alarm interrupt When LCDIE is enabled and this bit is 0, only when LCD charge pump counter value over LCDCPALCT0 and LCDCPALCT1 defined value, the LCD will go intot LCD interrupt.The LCDCPALIF(LCDIF[0]) will be set to 1.
  • Page 628 ML51/ML54/ML56 LCDCPALCT0 – LCD Charge Pump Alarm Counter Value Low Byte (TA Protected) Register SFR Address Reset Value LCDCPALCT0 F5H, Page 3, TA protected 0000_0000 b LCDCPOVCT[7:0] Name Description LCDCPOVCT[7:0] LCD Chage Pump Counter Alarm Value for Trig Interrupt Value . [7:0] Low byte of Trig LCD interrupt alarm counter value for user setting.
  • Page 629 ML51/ML54/ML56 LCDCPALCT1 – LCD Charge Pump Alarm Counter Value High Byte (TA Protected) Register SFR Address Reset Value LCDCPALCT1 E9H, Page 3, TA protected 0000_0000 b LCDCPOVCT [9:8] Name Description Reserved. [7:2] [1:0] LCDCPOVCT [9:8] LCD Chage Pump Counter Overflow Trig Interrupt Value . High byte of Trig LCD interrupt alarm counter value for user setting.
  • Page 630 ML51/ML54/ML56 LCDCPCT0 – LCD Charge Pump Counter Value Low Byte Register SFR Address Reset Value LCDCPCT0 F6H, page3 0000_0000 b LCDCPCT[7:0] Name Description [7:0] LCDCPCT[7:0] LCD Current Frame Chage Pump Counter Value Low Byte Each time after interrupt this byte reload LCD current frame charge pump value low byte. This byte is read only.
  • Page 631 ML51/ML54/ML56 LCDCPCT1 – LCD Charge Pump Counter Value High Byte Register SFR Address Reset Value LCDCPCT1 EAH, page3 0000_0000 b LCDCPCT[9:8] Name Description [7:2] Reserved. LCDCPCT [9:8] LCD Current Frame Chage Pump Counter Value High Byte [1:0] Each time after interrupt this byte reload LCD current frame charge pump value low byte. This byte is read only.
  • Page 632 ML51/ML54/ML56 LCDIF – LCD Interrupt Flag Register SFR Address Reset Value LCDIF F7H, Page 3 0000_0000 b LCDCPOVIF LCDCPIF LCDCPALIF Name Description [7:3] LCDCPOVIF LCD Charge Pump Counter Value Overflow Flag This Flag check LCDCPCT0 and LCDCPCT1 counter value. When LCDIS (LCDCON1.3) = 1 and LCDIE (LCDCON1.2) = 1. When LCD module charge pump value is match the maximum 0x3FF this bit will be set to 1 and the LCD interrupt happen.

  • Page 633: Lcd Program Flow

    ML51/ML54/ML56 6.17.6 LCD Program Flow Before LCD driver is enabled, the I/O state shared with used COM and SEG pins should be carefully considered. All used COM and SEG pins generate analog output waveforms. First, user needs to determine the VLCD, duty, and bias selections according to the target LCD panel. A suitable frame rate, normally 30 Hz to 100 Hz, is also important and needs to carefully give the LCDCLK register a proper value.

  • Page 634: Real Time Clock (Rtc)

    ML51/ML54/ML56 6.18 Real Time Clock (RTC) 6.18.1 Overview The Real Time Clock (RTC) controller provides the real time and calendar message. The RTC offers programmable time tick and alarm match interrupts. The data format of time and calendar messages are expressed in BCD format. A digital frequency compensation feature is available to compensate external crystal oscillator frequency accuracy.

  • Page 635: Block Diagram

    ML51/ML54/ML56 6.18.3 Block Diagram The RTC block diagram is shown below. Time Alarm Calendar Alarm Register Register (RTCTALMHR) (RTCCALMYEAR) Time Alarm Mask Calendar Alarm Mask (RTCTALMMIN) (RTCCALMMON) Register Register (RTCTALMSEC) (RTCCALMDAY) (RTCTAMSK) (RTCCAMSK) Time Loading Calendar Loading Register Register ALMIEN (RTCINTEN[0]) (RTCTIMEHR) (RTCCALYEAR) (RTCTIMEMIN)

  • Page 636: Functional Description

    ML51/ML54/ML56 6.18.4 Functional Description 6.18.4.1 RTC Initiation When a RTC block is powered on, RTC is at reset state. User has to write a number 0x57 to RTC initial register INIT(RTCINIT[7:0]) to make RTC leave reset state. Once the INIT(RTCINIT[7:0]) register is written as 0x57, the RTC will be in normal active state permanently.

  • Page 637: Table 6.18-1 Rtc Read/Write Enable

    ML51/ML54/ML56 Register INIR = 0 RWENF = 1 RWENF = 0 RTCCAMSK Not available Table 6.18-1 RTC Read/Write Enable 6.18.4.3 Frequency Compensation The RTCFREQADJ0 and RTCFREQADJ1 registers allow user to make digital compensation to a clock input. Please follow the example and formula below to write the actual frequency of 32k crystal to RTCFREQADJ0 and RTCFREQADJ1 registers.

  • Page 638: Table 6.18-212/24 Hour Time Scale Selection

    ML51/ML54/ML56 Note: The Hour Value Write Into RTCTIMEHR[5:0], Messages Are Expressed In BCD Format. 24-Hour Time Scale 12-Hour Time Scale (PM Time + 0x20) (24HEN = 1) (24HEN = 0) (PM Time + 0x20) 0x06 (AM06) 0x18 (PM06) 0x06 (AM06) 0x26 (PM06) 0x07 (AM07) 0x19 (PM07)

  • Page 639: Table 6.18-3 Registers Value After Powered On

    ML51/ML54/ML56 (RTCTIMEHR[3:0]) is 0x2. MIN: RTCTIMEMIN[6:0]: 0x59 combined by TENMIN (RTCTIME[6:4]) is 0x5, MIN (RTCTIMEMIN[3:0]) is 0x9. SEC: RTCTIMESEC[6:0]: 0x30 combined by TENSEC (RTCTIMESEC[6:4]) is 0x3, SEC (RTCTIMESEC[3:0]) is 0x0. 5. The below table shows registers value after both core power and battery power are first powered on.

  • Page 640: Register Description

    ML51/ML54/ML56 6.18.5 Register Description Sep. 01, 2020 Page 640 of 719 Rev 2.00...
  • Page 641 ML51/ML54/ML56 RTCINIT – RTC Initiation Register (TA Protected) Register SFR Address Reset Value RTCINIT A1H, Page 3, TA protected 0000_0000 b INIT[7:2] INIT[1]/HOL INIT/[0]ACTIVE Name Description RTC Initiation (Write Only) When RTC block is powered on, RTC is at reset state. User has to write a number (0x 57) to INIT to make RTC leave reset state.
  • Page 642 ML51/ML54/ML56 RTCRWEN – RTC Access Enable Register Register SFR Address Reset Value RTCRWEN A2H, Page 3 0000_0001 b FADJTG RWENF Name Description [7:2] Reserved. RTC Counter Update (Read and Write) FADJTG Set this bit = 1 by software. It will update to RTC counter from RTCFREQADJ1/0. After RTC counter updated, this bit will auto recover to 0 by hardware.
  • Page 643 ML51/ML54/ML56 RTCCLKSEL – RTC Clock Select Register Register SFR Address Reset Value RTCCLKSEL A3H, Page 3 0000_0000 b C32KS Name Description [7:1] Reserved. Clock 32K Source Selection: C32KS 0 = Internal 32K clock is from 32.786 kHz crystal . 1 = Internal 32K clock is from LIRC38.4 kHz. Sep.
  • Page 644 ML51/ML54/ML56 RTCFREQADJ0 – RTC Frequency Compensation 0 Register Register SFR Address Reset Value RTCFREQADJ0 A4H, Page 3 0000_0000 b FRACTION Name Description [7:6] Reserved. Fraction Part [5:0] FRACTION Formula: FRACTION = (fraction part of detected value) X 64. Note: Digit in FCR must be expressed as hexadecimal number. Note: FREQADJ’s counter will be reset for start to Compensatie when write RTCFREQADJ0/1 , RTCTIME, RTCCAL, RTCWEEKDAY.
  • Page 645 ML51/ML54/ML56 RTCFREQADJ1 – RTC Frequency Compensation 1 Register Register SFR Address Reset Value RTCFREQADJ1 A5H, Page 3 0001_0000 b INTEGER Name Description [7:5] Reserved. Integer Part 00000 = Integer part of detected value is 32752. 00001 = Integer part of detected value is 32753. 00010 = Integer part of detected value is 32754.
  • Page 646 ML51/ML54/ML56 Name Description Note:FREQADJ’s counter will be reset for start to Compensatie when write RTCFREQADJ0/1 , RTCTIME, RTCCAL, RTCWEEKDAY. Imply RTC Time will be restart . Sep. 01, 2020 Page 646 of 719 Rev 2.00...
  • Page 647 ML51/ML54/ML56 RTCINTEN – RTC Interrupt Enable Register Register SFR Address Reset Value RTCINTEN A6H, Page 3 0000_0000 b TICKIEN ALMIEN Name Description [7:2] Reserved. Time Tick Interrupt Enable Bit Set TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated.
  • Page 648 ML51/ML54/ML56 RTCINTSTS – RTC Interrupt Status Register Register SFR Address Reset Value RTCINTSTS A7H, Page 3 0000_0000 b TICKIF ALMIF Name Description [7:2] Reserved. RTC Time Tick Interrupt Flag TICKIF 0 = Tick condition does not occur. 1 = Tick condition occur. RTC Alarm Interrupt Flag ALMIF 0 = Alarm condition is not matched.
  • Page 649 ML51/ML54/ML56 RTCTIMESEC – RTC Time-second Loading Register Register SFR Address Reset Value RTCTIMESEC A9H, Page 3 0000_0000 b TENSEC[2:0] SEC[3:0] Name Description Reserved. [6:4] TENSEC[2:0] 10-Sec Time Digit (0~5) [3:0] SEC[3:0] 1-Sec Time Digit (0~9) Note: 1. RTCTIMESEC is a BCD digit counter and RTC will not check loaded data. 2.
  • Page 650 ML51/ML54/ML56 RTCTIMEMIN – RTC Time-minute Loading Register Register SFR Address Reset Value RTCTIMEMIN AAH, Page 3 0000_0000 b TENMIN[2:0] MIN[3:0] Name Description Reserved. [6:4] TENMIN[2:0] 10-Min Time Digit (0~5) [3:0] MIN[3:0] 1-Min Time Digit (0~9) Note: 1. RTCTIMEMIN is a BCD digit counter and RTC will not check loaded data. 2.
  • Page 651 ML51/ML54/ML56 RTCTIMEHR – RTC Time-hour Loading Register Register SFR Address Reset Value RTCTIMEHR ABH, Page 3 0000_0000 b TENHR[1:0] HR[3:0] Name Description [7:6] Reserved. 10-Hour Time Digit (0~2) TENHR[1:0] [5:4] When RTC runs as 12-hour time scale mode, RTCTIMEHR[5] (the high bit of TENHR[1:0]) means AM/PM indication (If RTCTIMEHR[5] is 1, it indicates PM time message.) [3:0] HR[3:0]...
  • Page 652 ML51/ML54/ML56 RTCCALDAY – RTC Calendar-day Loading Register Register SFR Address Reset Value RTCCALDAY ADH, Page 3 0000_1000 b TENDAY Name Description [7:6] Reserved. [5:4] TENDAY 10-Day Calendar Digit (0~3) [3:0] 1-Day Calendar Digit (0~9) Note: 1. RTCCALDAY is a BCD digit counter and RTC will not check loaded data. 2.
  • Page 653 ML51/ML54/ML56 RTCCALMON – RTC Calendar-month Loading Register Register SFR Address Reset Value RTCCALMON AEH, Page 3 0000_1000 b TENMON MON[3:0] Name Description [7:5] Reserved. TENMON 10-Month Calendar Digit (0~1) MON[3:0] [3:0] 1-Month Calendar Digit (0~9) Note: 1. RTCCALMON is a BCD digit counter and RTC will not check loaded data. 2.
  • Page 654 ML51/ML54/ML56 RTCCALYEAR – RTC Calendar-year Loading Register Register SFR Address Reset Value RTCCALYEAR AFH, Page 3 0001_0101 b TENYEAR YEAR Name Description TENYEAR [7:4] 10-Year Calendar Digit (0~9) [3:0] YEAR 1-Year Calendar Digit (0~9) Note: 1. RTCCALYEAR is a BCD digit counter and RTC will not check loaded data. 2.
  • Page 655 ML51/ML54/ML56 RTCTALMSEC – RTC Time Alarm-second Register Register SFR Address Reset Value RTCTALMSEC B1H, Page 3 0000_0000 b TENSEC[2:0] SEC[3:0] Name Description Reserved. [6:4] TENSEC[2:0] 10-Sec Time Digit of Alarm Setting (0~5) SEC[3:0] [3:0] 1-Sec Time Digit of Alarm Setting (0~9) Note: 1.
  • Page 656 ML51/ML54/ML56 RTCTALMMIN – RTC Time Alarm-minute Register Register SFR Address Reset Value RTCTALMMIN B2H, Page 3 0000_0000 b TENMIN[2:0] MIN[3:0] Name Description Reserved. [6:4] TENMIN[2:0] 10-Min Time Digit of Alarm Setting (0~5) MIN[3:0] [3:0] 1-Min Time Digit of Alarm Setting (0~9) Note: 1.
  • Page 657 ML51/ML54/ML56 RTCTALMHR – RTC Time Alarm-hour Register Register SFR Address Reset Value RTCTALMHR B3H, Page 3 0000_0000 b TENHR[1:0] HR[3:0] Name Description [7:6] Reserved. 10-Hour Time Digit of Alarm Setting (0~2) TENHR[1:0] When RTC runs as 12-hour time scale mode, RTCTIMEHR[5] (the high bit of TENHR[1:0]) [5:4] means AM/PM indication (If RTCTIMEHR[5] is 1, it indicates PM time message.) [3:0]...
  • Page 658 ML51/ML54/ML56 RTCCALMDAY – RTC Calendar Alarm-day Register Register SFR Address Reset Value RTCCALMDAY B5H, Page 3 0000_0000 b TENDAY[1:0] DAY[3:0] Name Description [7:6] Reserved. [5:4] TENDAY[1:0] 10-Day Calendar Digit of Alarm Setting (0~3) [3:0] DAY[3:0] 1-Day Calendar Digit of Alarm Setting (0~9) Note: 1.
  • Page 659 ML51/ML54/ML56 RTCCALMMON – RTC Calendar Alarm-month Register Register SFR Address Reset Value RTCCALMMON B6H, Page 3 0000_0000 b TENMON MON[3:0] Name Description [7:5] Reserved. TENMON 10-Month Calendar Digit of Alarm Setting (0~1) MON[3:0] [3:0] 1-Month Calendar Digit of Alarm Setting (0~9) Note: 1.
  • Page 660 ML51/ML54/ML56 RTCWEEKDAY – RTC Calendar Alarm-year Register Register SFR Address Reset Value RTCCALMYEAR B7H, Page 3 0000_0000 b TENYEAR[3:0] YEAR[3:0] Name Description [7:4] TENYEAR[3:0] 10-Year Calendar Digit of Alarm Setting (0~9) [3:0] YEAR[3:0] 1-Year Calendar Digit of Alarm Setting (0~9) Note: 1.
  • Page 661 ML51/ML54/ML56 RTCCLKFMT – RTC Time Scale Selection Register Register SFR Address Reset Value RTCCLKFMT B9H, Page 3 0000_0001 b 24HEN Name Description [7:1] Reserved. 24-Hour / 12-Hour Time Scale Selection Indicates that RTCTIMEHR and RTCTALMHR are in 24-hour time scale or 12-hour time scale 24HEN 0 = 12-hour time scale with AM and PM indication selected.
  • Page 662 ML51/ML54/ML56 RTCWEEKDAY – RTC Day of the Week Register Register SFR Address Reset Value RTCWEEKDAY BBH, Page 3 0000_0110 b WEEKDAY Name Description [7:3] Reserved. Day of the Week Register 000 = Sunday. 001 = Monday. 010 = Tuesday. [2:0] WEEKDAY 011 = Wednesday.
  • Page 663 ML51/ML54/ML56 RTCLEAPYEAR – RTC Leap Year Indication Register Register SFR Address Reset Value RTCLEAPYEAR BCH, Page 3 0000_0000 b LEAPYEAR Name Description [7:1] Reserved. Leap Year Indication Register (Read Only) LEAPYEAR 0 = This year is not a leap year. 1 = This year is leap year.
  • Page 664 ML51/ML54/ML56 RTCTICK – RTC Time Tick Register Register SFR Address Reset Value RTCTICK BDH, Page 3 0000_0000 b TICK[2:0] Name Description [7:3] Reserved. Time Tick Register These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. 000 = Time tick is 1 second.
  • Page 665 ML51/ML54/ML56 RTCTAMSK – RTC Time Alarm MASK Register Register SFR Address Reset Value RTCTAMSK BEH, Page 3 0000_0000 b MTENHR MTENMIN MMIN MTENSEC MSEC Name Description [7:6] Reserved. MTENHR Mask 10-Hour Time Digit of Alarm Setting (0~2) Mask 1-Hour Time Digit of Alarm Setting (0~9) MTENMIN Mask 10-Min Time Digit of Alarm Setting (0~5) MMIN...
  • Page 666 ML51/ML54/ML56 RTCCAMSK – RTC Calendar Alarm MASK Register Register SFR Address Reset Value RTCCAMSK BFH, Page 3 0000_0000 b MTENYEAR MYEAR MTENMON MMON MTENDAY MDAY Name Description [7:6] Reserved. MTENYEAR Mask 10-Year Calendar Digit of Alarm Setting (0~9) MYEAR Mask 1-Year Calendar Digit of Alarm Setting (0~9) MTENMON Mask 10-Month Calendar Digit of Alarm Setting (0~1) MMON...

  • Page 667: Table 6.19-1 All Touch Key Pins Select Source List

    ML51/ML54/ML56 6.19 Touch Key (TK) 6.19.1 Overview The capacitive touch key sensing controller supports several programmable sensitivity levels for different applications to detect the finger touched or near the electrode covered by dielectric. It supports total 14 keys with single scan or programmable periodic key scans, and system can be waked up by any key for low power applications.

  • Page 668: Figure 6.19-1Touch Key Block Diagram

    ML51/ML54/ML56 6.19.4 Block Diagram The block diagram of Touch Key controller is depicted as following: TKx Control TK14 TK13 Reference Reference Capacitor Bank Polarity Select TK12 TK11 Shielding Shielding TK10 Capacitor Bank for Reference Touch Key 1 Touch Key 1 Analog Interface counter...
  • Page 669 ML51/ML54/ML56 6.19.5 Functional Description When a finger touches on a key pad, capacitance of the key pad sensed by Touch Key controller will be bigger than it is not touched. The capacitance is measured by Touch Key controller analog front end circuit, user can read the sensed capacitance value to distinguish if a finger touch event occurs or not.

  • Page 670: Figure 6.19-2 Touch Key Sensing Method

    ML51/ML54/ML56 No Finger Touch Finger Touch Capacitor Bank Capacitor Bank Polarity Select Polarity Select Complement Complement Capacitor Bank Capacitor Bank Capacitor Bank Capacitor Bank for for Reference for Reference for Touch Key Touch Key Touch Key Touch Key CMPX_IN CMPX_IN counter counter Reference Pad...

  • Page 671: Figure 6.19-3 Finger Touch Detection Method

    ML51/ML54/ML56 Touch key controller will ’ increase C to C Capacitor Bank Polarity Select Complement Capacitor Bank Capacitor Bank for Reference for Touch Key Touch Key Touch Key CMPX_IN counter Reference Pad Reference Pad CMPX_IP Touch Key Scan Touch Key Scan Enabled Cycle Enabled Cycle Voltage...
  • Page 672 ML51/ML54/ML56 6.19.5.2 Touch Key Scan Mode Single Scan Mode In this mode, user must set TK_EN (TKCON0[2]) and SCAN (TKCON0[0]) to high and other bits of TKSENx~TKRENx must be set according to application requirements for sensitivity setting. Those channels enabled by corresponding bits of TKSENx register will be scanned successively when scan initiate.

  • Page 673: Figure 6.19-4 Touch Key Controller Interrupt Modes For Threshold Control

    ML51/ML54/ML56 threshold control for each channel can be pre-determined in TKHTHx registers, x denotes adjacent channels’ number, for example, TKHTH0. TKIFx is set if TKDATx is greater than TKHTHx. TKDATx greater than TKHTHx means a potential key touch occurs. As shown in Figure 6.19-4 Touch Key Controller Interrupt Modes For Threshold Control. TKHTHx scan TKIFx...
  • Page 674 ML51/ML54/ML56 6.19.6 Register Description Sep. 01, 2020 Page 674 of 719 Rev 2.00...
  • Page 675 ML51/ML54/ML56 TKCON0 – Touch Key Control 0 Register Register Memory Address Reset Value TKCON0 8000H 0111_000 b SCAN_ALL TK_EN TMRTRG_EN SCAN Name Description H Voltage Select 0000 = 2/32 V 0001 = 4/32 V 0010 = 6/32 V 0011 = 8/32 V 0100 = 10/32 V 0101 = 12/32 V 0110 = 14/32 V...
  • Page 676 ML51/ML54/ML56 TKCON1 – Touch Key Control 1 Register Register Memory Address Reset Value TKCON1 8001H 0000_0000 b PULSET SENSET Name Description Reserved. Touch Key Sensing Pulse Width Time Control 000 = 500ns. 001 = 1us. 010 = 2us. [6:4] PULSET 011 = 4us.
  • Page 677 ML51/ML54/ML56 TKCON2 – Touch Key Control 2 Register Register Memory Address Reset Value TKCON2 8002H 0000_0001 b POL_INIT POL_CAP Name Description [7:3] Reserved. Touch Key Sensing Initial Potential Control POL_INIT 0 = Key pad is connected to Gnd before sensing. 1 = Key pad is connected to AV H before sensing.
  • Page 678 ML51/ML54/ML56 TKSEN0 – Touch Key Scan Enable 0 Register Register Memory Address Reset Value TKSEN0 8003H 0000_0000 b TK7SEN TK6SEN TK5SEN TK4SEN TK3SEN TK2SEN TK1SEN TK0SEN Name Description TK7 Scan Enable This bit is ignored if TK7REN (TKREN0[7]) is “1”. TK7SEN 0 = TKDAT7 is invalid.
  • Page 679 ML51/ML54/ML56 TKSEN1 – Touch Key Scan Enable 1 Register Register Memory Address Reset Value TKSEN1 8004H 0000_0000 b TK14SEN TK13SEN TK12SEN TK11SEN TK10SEN TK9SEN TK8SEN Name Description Reserved. TK14 Scan Enable This bit is ignored if TK14REN (TKREN1[6]) is “1”. TK14SEN 0 = TKDAT14 is invalid.
  • Page 680 ML51/ML54/ML56 TKREN0 – Touch Key Reference Enable 0 Register Register Memory Address Reset Value TKREN0 8005H 0000_0000 b TK7REN TK6REN TK5REN TK4REN TK3REN TK2REN TK1REN TK0REN Name Description TK7 Reference Enable TK7REN 0 = TK7 is not reference. 1 = TK7 is set as reference, and TKDAT7 is invalid. TK6 Reference Enable TK6REN 0 = TK6 is not reference.
  • Page 681 ML51/ML54/ML56 TKREN1 – Touch Key Reference Enable 1 Register Register Memory Address Reset Value TKREN1 8006H 0100_0000 b TK14REN TK13REN TK12REN TK11REN TK10REN TK9REN TK8REN Name Description Reserved. TK14 Reference Enable TK14REN 0 = TK14 is not reference. 1 = TK14 is set as reference, and TKDAT14 is invalid. TK13 Reference Enable TK13REN 0 = TK13 is not reference.
  • Page 682 ML51/ML54/ML56 TKINTEN – Touch Key Interrupt Enable Register Register Memory Address Reset Value TKINTEN 8007H 0000_0000 b TKSCIE TKSCTHIE Name Description [7:2] Reserved. Touch Key Scan Complete Interrupt Enable TKSCIE 0 = Key scan complete without threshold control interrupt is disable. 1 = Key scan complete without threshold control interrupt is enable.
  • Page 683 ML51/ML54/ML56 TKSTA0 – Touch Key Status 0 Register Register Memory Address Reset Value TKSTA0 8008H 0000_0000 b TKIF_ALL TKIF TKSCIF TKBUSY Name Description [7:4] Reserved. All Keys Scan Interrupt Flag 0 = No threshold control event with All Keys Scan. TKIF_ALL 1 = Threshold control event occurs with All Keys Scan.
  • Page 684 ML51/ML54/ML56 TKSTA1 – Touch Key Status 1 Register Register Memory Address Reset Value TKSTA1 8009H 0000_0000 b TKIF7 TKIF6 TKIF5 TKIF4 TKIF3 TKIF2 TKIF1 TKIF0 Name Description TK7 Interrupt Flag TKIF7 0 = No threshold control event with TK7. 1 = Threshold control event occurs with TK7. TK6 Interrupt Flag TKIF6 0 = No threshold control event with TK6.
  • Page 685 ML51/ML54/ML56 TKSTA2 – Touch Key Status 2 Register Register Memory Address Reset Value TKSTA2 800AH 0000_0000 b TKIF14 TKIF13 TKIF12 TKIF11 TKIF10 TKIF9 TKIF8 Name Description Reserved. TK14 Interrupt Flag TKIF14 0 = No threshold control event with TK14. 1 = Threshold control event occurs with TK14. TK13 Interrupt Flag TKIF13 0 = No threshold control event with TK13.
  • Page 686 ML51/ML54/ML56 TKCCBD0~14 – Touch Key Complement Capacitor Bank Data Register Register Memory Address Reset Value TKCCBD0 8010H 0000_0000 b TKCCBD1 8011H 0000_0000 b TKCCBD2 8012H 0000_0000 b TKCCBD3 8013H 0000_0000 b TKCCBD4 8014H 0000_0000 b TKCCBD5 8015H 0000_0000 b TKCCBD6 8016H 0000_0000 b TKCCBD7...
  • Page 687 ML51/ML54/ML56 TKCCBDALL – Touch Key Complement Capacitor Bank Data Register Register Memory Address Reset Value TKCCBDALL 801FH 0000_0000 b CCBDALL Name Description TK All Scans Complement CB Data [7:0] CCBDALL This is register is used for TK all scans sensitivity adjustment Sep.
  • Page 688 ML51/ML54/ML56 REFCBD0~14 – Reference Capacitor Bank Data Register Register Memory Address Reset Value REFCBD0 8020H 0000_0000 b REFCBD1 8021H 0000_0000 b REFCBD2 8022H 0000_0000 b REFCBD3 8023H 0000_0000 b REFCBD4 8024H 0000_0000 b REFCBD5 8025H 0000_0000 b REFCBD6 8026H 0000_0000 b REFCBD7 8027H 0000_0000 b...
  • Page 689 ML51/ML54/ML56 REFCBDALL – Reference Capacitor Bank Data Register Register Memory Address Reset Value REFCBDALL 802FH 0000_0000 b REFCBDALL Name Description Touch Key All Scans Reference CB Data [7:0] REFCBDALL This is register is used for Touch Key All Scans Reference sensitivity adjustment. Sep.
  • Page 690 ML51/ML54/ML56 TKIDLPOL0~14 – Touch Key Idle State / Polarity Select Register Register Memory Address Reset Value TKIDLPOL0 8030H 1100_0000 b TKIDLPOL1 8031H 1100_0000 b TKIDLPOL2 8032H 1100_0000 b TKIDLPOL3 8033H 1100_0000 b TKIDLPOL4 8034H 1100_0000 b TKIDLPOL5 8035H 1100_0000 b TKIDLPOL6 8036H 1100_0000 b...
  • Page 691 ML51/ML54/ML56 Name Description TKx Idle State Control This register is ignored if both TKxSEN and POLENx are “0” or TKxREN is “1”. 00 = TKx connected to Gnd. [1:0] IDLSx 01 = TKx connected to AV 10 = Reserved. 11 = TKx connected to V Where x = 0~14 Sep.
  • Page 692 ML51/ML54/ML56 TKDATx – Touch Key x Data Register Register Memory Address Reset Value TKDAT0 8040H 0000_0000 b TKDAT1 8041H 0000_0000 b TKDAT2 8042H 0000_0000 b TKDAT3 8043H 0000_0000 b TKDAT4 8044H 0000_0000 b TKDAT5 8045H 0000_0000 b TKDAT6 8046H 0000_0000 b TKDAT7 8047H 0000_0000 b...
  • Page 693 ML51/ML54/ML56 TKDATALL – Touch Key x Data Register Register Memory Address Reset Value TKDATALL 804FH 0000_0000 b TKDATALL Name Description All Keys Scan Sensing Result Data (Read Only) [7:0] TKDATALL This data is invalid if SCAN_ALL (TKCON0[3]) is “0”. Sep. 01, 2020 Page 693 of 719 Rev 2.00...
  • Page 694 ML51/ML54/ML56 TKHTHx – Touch Key x High Threshold Register Register Memory Address Reset Value TKHTH0 8050H 1111_1111 b 1111_1111 b TKHTH1 8051H 1111_1111 b TKHTH2 8052H 1111_1111 b TKHTH3 8053H 1111_1111 b TKHTH4 8054H 1111_1111 b TKHTH5 8055H 1111_1111 b TKHTH6 8056H 1111_1111 b...
  • Page 695 ML51/ML54/ML56 TKHTHALL – Touch Key x High Threshold Register Register Memory Address Reset Value 1111_1111 b TKHTHALL 805FH HTH_ALL Name Description High Threshold of All Keys Scan [7:0] HTH_ALL High level for All Keys Scan threshold control. Sep. 01, 2020 Page 695 of 719 Rev 2.00...

  • Page 696: Table 6.20-1 Instruction Set And Addressing Modes

    ML51/ML54/ML56 6.20 Instruction Set 6.20.1 Instruction Set And Addressing Modes The ML51/ML54/ML56 Series executes all the instructions of the standard 80C51 family fully compatible with MCS-51. However, the timing of each instruction is different for it uses high performance 1T 8051 core. The architecture eliminates redundant bus states and implements parallel execution of fetching, decode, and execution phases.

  • Page 697: Table 6.20-2 Instructions Affect Flag Settings

    ML51/ML54/ML56 Instruction Instruction X[1] CLR C ADDC CPL C SUBB ANL C, bit ANL C, /bit ORL C, bit DA A ORL C, /bit RRC A MOV C, bit RLC A CJNE SETB C Note: X indicates the modification depends on the result of the instruction. Table 6.20-2 Instructions Affect Flag Settings Sep.
  • Page 698 ML51/ML54/ML56 6.20.2 Read-Modify-Write Instructions Instructions that read a byte from SFR or internal RAM, modify it, and rewrite it back, are called “Read- Modify-Write” instructions. When the destination is an I/O port or a port bit, these instructions read the internal output latch rather than the external pin state.
  • Page 699 ML51/ML54/ML56 ML51/ML54/ML56 Series VS. Instruction OPCODE Bytes Clock Cycles Tradition 80C51 Speed Ratio INC A INC Rn 08~0F INC direct INC @Ri 06, 07 INC DPTR 18~1F direct 16, 17 DIV AB DA A A, Rn 58~5F A, direct A, @Ri 56, 57 A, #data direct, A...
  • Page 700 ML51/ML54/ML56 ML51/ML54/ML56 Series VS. Instruction OPCODE Bytes Clock Cycles Tradition 80C51 Speed Ratio Rn, A F8~FF Rn, direct A8~AF Rn, #data 78~7F direct, A direct, Rn 88~8F direct, direct direct, @Ri 86, 87 direct, #data @Ri, A F6, F7 @Ri, direct A6, A7 @Ri, #data 76, 77...

  • Page 701: Table 6.20-3 Instruction Set

    ML51/ML54/ML56 ML51/ML54/ML56 Series VS. Instruction OPCODE Bytes Clock Cycles Tradition 80C51 Speed Ratio AJMP addr11 01, 21, 41, 61, 81, A1, C1, E1[3] LJMP addr16 SJMP rel @A+DPTR JZ rel JC rel JB bit, rel bit, rel bit, rel CJNE A, direct, rel CJNE A, #data, rel CJNE Rn, #data, rel B8~BF...
  • Page 702 ML51/ML54/ML56 APPLICATION CIRCUIT 7.1 Power Supply Scheme EXT_PWR For external VREF source from VDD only L=30S VREF as close to VREF as possible 10uF+0.1uF ML51 Series as close to the EXT_PWR as possible EXT_VSS 0.1uF*N as close to VDD as possible ®...
  • Page 703 ML51/ML54/ML56 7.2 Peripheral Application Scheme DVCC DVCC SPI_SS ICE / ICP SPI_CLK Interface Device SPI_MISO MISO SPI_MOSI MOSI 100K 100K ICE_CLK DVCC DVCC 4.7K 4.7K XT1_IN 20pF Device I2C_SCL 4~24 MHz crystal I2C_SDA 20pF XT1_OUT ML51 Series Crystal X32_IN RS 232 Transceiver 20pF 32.768 kHz UART_RXD...
  • Page 704 ML51/ML54/ML56 ELECTRICAL CHARACTERISTICS Please refer to the relative Datasheet for detailed information about the ML51/ML54/ML56 Series electrical characteristics. Sep. 01, 2020 Page 704 of 719 Rev 2.00...

  • Page 705: Figure 9.1-1 Lqfp 64L Package Dimension

    ML51/ML54/ML56 PACKAGE DIMENSIONS 9.1 LQFP 64L-pin (7.0 x 7.0 x 1.4 mm) Figure 9.1-1 LQFP 64L Package Dimension Sep. 01, 2020 Page 705 of 719 Rev 2.00...

  • Page 706: Figure 9.2-1 Lqfp-48 Package Dimension

    ML51/ML54/ML56 9.2 LQFP 48-pin (7.0 x 7.0 x 1.4 mm)  C o n t r o l l i n g d i m e n s i o n : M i l l i m e t e r s Dimension in inch Dimension in mm Symbol...

  • Page 707: Figure 9.3-1 Lfp44 Package Dimension

    ML51/ML54/ML56 9.3 LQFP 44-pin (10 x 10 x 1.4mm Figure 9.3-1 LFP44 Package Dimension Sep. 01, 2020 Page 707 of 719 Rev 2.00...

  • Page 708: Figure 9.4-1 Qfn-33 Package Dimension

    ML51/ML54/ML56 9.4 QFN 33-pin (4.0 x 4.0 x 0.8 mm) Figure 9.4-1 QFN-33 Package Dimension Sep. 01, 2020 Page 708 of 719 Rev 2.00...

  • Page 709: Figure 9.5-1 Lqfp-32 Package Dimension

    ML51/ML54/ML56 9.5 LQFP 32-pin (7.0 x 7.0 x 1.4 mm) Figure 9.5-1 LQFP-32 Package Dimension Sep. 01, 2020 Page 709 of 719 Rev 2.00...

  • Page 710: Figure 9.6-1 Tssop-28 Package Dimension

    ML51/ML54/ML56 9.6 TSSOP 28-pin (4.4 x 9.7 x 1.0 mm) Figure 9.6-1 TSSOP-28 Package Dimension Sep. 01, 2020 Page 710 of 719 Rev 2.00...

  • Page 711: Figure 9.7-1 Sop-28 Package Dimension

    ML51/ML54/ML56 9.7 SOP 28-pin (300mil) Control demensions are in milmeters .  Figure 9.7-1 SOP-28 Package Dimension Sep. 01, 2020 Page 711 of 719 Rev 2.00...

  • Page 712: Figure 9.8-1 Tssop-20 Package Dimension

    ML51/ML54/ML56 9.8 TSSOP 20-pin (4.4 x 6.5 x 0.9 mm) Figure 9.8-1 TSSOP-20 Package Dimension Sep. 01, 2020 Page 712 of 719 Rev 2.00...

  • Page 713: Figure 9.9-1 Sop-20 Package Dimension

    ML51/ML54/ML56 9.9 SOP 20-pin (300 mil) Control demensions are in milmeters .  Figure 9.9-1 SOP-20 Package Dimension Sep. 01, 2020 Page 713 of 719 Rev 2.00...

  • Page 714: Figure 9.10-1 Qfn-20 Package Dimension

    ML51/ML54/ML56 9.10 QFN 20-pin ( 3.0 x 3.0 x 0.8 mm ) Figure 9.10-1 QFN-20 Package Dimension Sep. 01, 2020 Page 714 of 719 Rev 2.00...

  • Page 715: Figure 9.11-1 Tssop-14 Package Dimension

    ML51/ML54/ML56 9.11 TSSOP 14-pin (4.4 x 5.0 x 0.9 mm) Figure 9.11-1 TSSOP-14 Package Dimension Sep. 01, 2020 Page 715 of 719 Rev 2.00...

  • Page 716: Figure 9.12-1 Msop-10 Package Dimension

    ML51/ML54/ML56 9.12 MSOP 10-pin (3.0 x 3.0 x 0.85 mm) Figure 9.12-1 MSOP-10 Package Dimension Sep. 01, 2020 Page 716 of 719 Rev 2.00...

  • Page 717: Table 10.1-1 List Of Abbreviations

    ML51/ML54/ML56 10 ABBREVIATIONS 10.1 Abbreviations Acronym Description Analog-to-Digital Converter Brown-out Detection GPIO General-Purpose Input/Output Fsys Frequency of system clock HIRC 12 MHz Internal High Speed RC Oscillator In Application Programming In Circuit Programming In System Programming Low Dropout Regulator LIRC 10 kHz internal low speed RC oscillator (LIRC) Low Voltage $eset PDMA...
  • Page 718 ML51/ML54/ML56 11 REVISION HISTORY Date Revision Description 2018.12.05 1.00 Initial release. Section 3.1 Added package type table. Section 4.2.2 Added Multi-function summary table Section 7.2 Added description that all about PWM1 register is only for 64K 2019.3.18 1.01 flash body product. Section 24.3 Added PDMA support in different part number.
  • Page 719 ML51/ML54/ML56 Important Notice Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”.

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