Nuvoton NuMicro Family Technical Reference Manual

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Mini57

ARM Cortex

-M0

32-bit Microcontroller

NuMicro

Family

Mini57 Series

Technical Reference Manual

The information described in this document is the exclusive intellectual property of

Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.

Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based

system design. Nuvoton assumes no responsibility for errors or omissions.

All data and specifications are subject to change without notice.

For additional information or questions, please contact: Nuvoton Technology Corporation.

www.nuvoton.com

Apr. 06, 2017

Page 1 of 475

Rev.1.00

Table of Contents

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Summary of Contents for Nuvoton NuMicro Family

Page 1 The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions.
Page 2: Table Of Contents
Mini57 TABLE OF CONTENTS 1 GENERAL DESCRIPTION ................12 2 FEATURES ...................... 13 3 ABBREVIATIONS .................... 17 4 PARTS INFORMATION LIST AND PIN CONFIGURATION ......18 ® NuMicro Mini57 Naming Rule ................... 18 ® NuMicro Mini57 Series Selection Guide ..............19 Pin Configuration ......................
Page 3 Mini57 6.4.1 Overview ........................133 6.4.2 Features ........................133 6.4.3 Block Diagram ......................133 6.4.4 Functional Description ....................135 6.4.5 Register Map ........................ 150 6.4.6 Register Description ..................... 151 General Purpose I/O (GPIO) ..................162 6.5.1 Overview ........................162 6.5.2 Features ........................
Page 4 Mini57 6.9.6 Register Description ..................... 285 6.10 Watchdog Timer (WDT) ................... 295 6.10.1 Overview ........................295 6.10.2 Features ........................295 6.10.3 Block Diagram ......................295 6.10.4 Clock Control ........................ 296 6.10.5 Basic Configuration ...................... 296 6.10.6 Functional Description ....................296 6.10.7 Registers Map ......................
Page 5 Mini57 6.15.6 Register Description ..................... 425 6.16 Analog to Digital Converter (ADC) ................430 1.1.1 Overview ........................430 1.1.2 Features ........................430 1.1.3 Block Diagram ......................430 6.16.1 Basic Configuration ...................... 431 6.16.2 Functional Description ....................431 6.16.3 Register Map ........................ 435 6.16.4 Register Description .....................
Page 6 Mini57 List of Figures ® Figure 4.1-1 NuMicro Mini57 Series Selection Code ..............18 ® Figure 4.3-1 NuMicro Mini57 Series TSSOP 28-pin Diagram ............20 ® Figure 4.3-2 NuMicro Mini57 Series TSSOP 28-pin Multi-function Diagram ....... 20 ® Figure 4.3-3 NuMicro Mini57 Series TSSOP 20-pin Diagram ............
Page 7 Mini57 Figure 6.5-2 GPIO Controller Block Diagram ................163 Figure 6.5-3 Push-Pull Output ...................... 164 Figure 6.5-4 Open-Drain Output ....................165 Figure 6.5-5 Quasi-Bidirectional I/O Mode ................... 165 Figure 6.6-1 Timer Controller Block Diagram ................188 Figure 6.6-2 Clock Source of Timer Controller ................188 Figure 6.6-3 Continuous Counting Mode ..................
Page 8 Mini57 Figure 6.8-20 EPWM Initial State and Polarity Control with Rising Edge Dead-time Insertion ... 241 Figure 6.8-21 EPWM Interrupt Architecture ................. 242 Figure 6.8-22 EPWM Brake Architecture ..................243 Figure 6.8-23 EPWM 3-phase Motor Mask Diagram ..............244 Figure 6.8-24 EPWM 3-phase Motor Mask Example 1 ..............245 Figure 6.8-25 EPWM 3-phase Motor Mask Example 2 ..............
Page 9 Mini57 Figure 6.12-5 UART Auto Baud Rate Control ................320 Figure 6.12-6 Incoming Data Wake-Up ..................321 Figure 6.13-1 SPI Master Mode Application Block Diagram (x=0, 1) .......... 346 Figure 6.13-2 SPI Slave Mode Application Block Diagram (x=0, 1) ..........346 Figure 6.13-3 USCI - SPI Mode Block Diagram ................
Page 10 Mini57 Figure 6.14-18 Hold Time Wrong Adjustment ................400 Figure 6.14-19 I C Time-out Count Block Diagram ..............400 Figure 6.14-20 EEPROM Random Read ..................401 Figure 6.14-21 Protocol of EEPROM Random Read..............402 Figure 6.15-1 Hardware Divider Operation Flow ................. 423 Figure 6.16-1 ADC Control Block Diagram ..................
Page 11 Mini57 List of Tables Table 3-1 List of Abbreviations ....................... 17 ® Table 4.2-1 NuMicro Mini57 Series Selection Guide ..............19 Table 4.4-1 TSSOP28 Pin Description ..................27 Table 4.4-2 TSSOP20 Pin Description ..................31 Table 4.4-3 QFN33 Pin Description ....................35 Table 4.4-4 TSSOP20 Multi-function Pin Summary ...............
Page 12: General Description
Mini57 GENERAL DESCRIPTION ® ® ® The NuMicro Mini57 series 32-bit microcontrollers are embedded with ARM Cortex -M0 core for ® industrial applications which need high performance, high integration, and low cost. The Cortex ® M0 is the newest ARM embedded processor with 32-bit performance at a cost equivalent to the traditional 8-bit microcontroller.
Page 13: Features
Mini57 FEATURES  Core ARM® Cortex® -M0 core running up to 48 MHz One 24-bit system timer Supports low power Idle mode A single-cycle 32-bit hardware multiplier NVIC for the 32 interrupt inputs, each with 4-level of priority Supports Serial Wire Debug (SWD) interface and two watchpoints/four breakpoints ...
Page 14 Mini57 Supports software selectable slew rate control GPIO built-in Pull-up/Pull-low resistor for selection.  Timer Provides two channel 32-bit Timers; one 8-bit pre-scalar counter with 24-bit up- timer for each timer Independent clock source for each timer Provides One-shot, Periodic, Toggle and Continuous operation modes 24-bit up counter value is readable through CNT (Timer Data Register) Provides trigger counting/free counting/counter reset function triggered by external capture pin or internal comparator signal...
Page 15 Mini57 Hardware fault brake and software brake protections Supports rising, falling, central, period, and fault break interrupts Supports duty/period trigger A/D conversion Timer comparing matching event trigger PWM to do phase change Supports comparator event trigger PWM to force PWM output low for current period Provides interrupt accumulation function ...
Page 16 Mini57  BOD (Brown-out Detector) 8 programmable threshold levels: 4.3V/4.0V/3.7V/3.0V/2.7V/2.4V/2.2V/2.0V Supports Brown-out interrupt and reset option  96-bit unique ID  LVR (Low Voltage Reset)  Operating Temperature: -40℃~105℃  Reliability: EFT > ± 4KV, ESD HBM pass 4KV  Packages: Green package (RoHS) 20-pin TSSOP, 28-pin TSSOP, 33-pin QFN...
Page 17: Abbreviations
Mini57 ABBREVIATIONS Acronym Description ACMP Analog Comparator Controller Analog-to-Digital Converter Advanced High-Performance Bus Advanced Peripheral Bus Brown-out Detection BPWM Basic Pulse Width Modulation Debug Access Port EPWM Enhanced Pulse Width Modulation FIFO First In, First Out Flash Memory Controller GPIO General-Purpose Input/Output HCLK The Clock of Advanced High-Performance Bus...
Page 18: Parts Information List And Pin Configuration
Mini57 PARTS INFORMATION LIST AND PIN CONFIGURATION ® 4.1 NuMicro Mini57 Naming Rule ARM–Based Mini57-X X X 32-bit Microcontroller CPU Core Corte ® Temperature E: -40 C ~ +105 Flash ROM : 29.5 KB Flash ROM Reserved Package Type F: TSSOP 20 E: TSSOP 28 T: QFN 33 4x4mm ®...
Page 19: Numicro Mini57 Series Selection Guide
Mini57 ® 4.2 NuMicro Mini57 Series Selection Guide * USCI can be set to UART, SPI or I Connectivity Part APROM RAM Data Flash Loader Timer Comp. PWM 10 kHz Package Number USCI* 48 MHz Mini57TDE 29.5 KB 4 KB Configurable 2.5 KB up to 22 2x32-bit 8x12-bit QFN33(4x4) Mini57EDE 29.5 KB 4 KB Configurable 2.5 KB up to 22 2x32-bit...
Page 20: Pin Configuration
Mini57 4.3 Pin Configuration 4.3.1 TSSOP 28-Pin PD.6 LDO_CAP PB.0 PC.4 PB.1 PA.0 PB.2 PA.1 PB.4 PA.2 PC.1 PA.3 nRESET PA.4 PB.3 PA.5 PC.2 PD.5 PD.2 PC.3 PD.3 PD.1 PD.4 PC.0 ® Figure 4.3-1 NuMicro Mini57 Series TSSOP 28-pin Diagram PD.6/UART0_RXD LDO_CAP PB.0/ADC0_CH0/ACMP0_P0/ECAP_P0...
Page 21: Tssop 20-Pin
Mini57 4.3.2 TSSOP 20-Pin PB.0 PA.0 PB.1 PA.1 PB.2 PA.2 PB.4 PA.3 PC.1 PA.4 nRESET PA.5 PB.3 PC.3 PC.2 PD.1 PD.2 PC.0 ® Figure 4.3-3 NuMicro Mini57 Series TSSOP 20-pin Diagram PB.0/ADC0_CH0/ACMP0_P0/ECAP_P0 PA.0/CLKO/EPWM_CH0/I2C1_SCL/SPI0_SS/SPI1_CLK/UART1_TXD PB.1/ADC0_CH1/ACMP0_P1/ECAP_P1 PA.1/EPWM_CH1/I2C1_SDA/SPI0_MISO/SPI1_MOSI/UART1_RXD PB.2/ADC0_CH2/BPWM_CH1/ACMP0_P2/ECAP_P2 PA.2/EPWM_CH2/I2C0_SDA/SPI0_MOSI/SPI1_MISO/UART0_RXD PB.4/ADC1_CH0/ACMP0_N/TM1 PA.3/EPWM_CH3/I2C0_SCL/SPI0_CLK/SPI1_SS/UART0_TXD PC.1/ADC0_CH4/STADC/ACMP0_P3/ACMP1_P1/SPI0_MOSI/SPI1_MISO PA.4/XT_IN/EPWM_CH4 nRESET PA.5/XT_OUT/EPWM_CH5/ACMP0_O...
Page 22: Qfn 33-Pin
Mini57 4.3.3 QFN 33-Pin 31 30 29 28 27 26 25 LDO_CAP PA.2 PA.3 PD.6 Mini57 PA.4 QFN 33-pin PB.0 PA.5 PD.5 PB.1 PB.2 33 V PB.4 11 12 13 14 15 16 ® Figure 4.3-5 NuMicro Mini57 Series QFN 33-pin Diagram Apr.
Page 23: Figure 4.3-6 Numicro ® Mini57 Series Qfn 33-Pin Multi-Function Diagram
Mini57 31 30 29 28 27 26 25 LDO_CAP PA.2/EPWM_CH2/I2C0_SDA/SPI0_MOSI/SPI1_MISO/UART0_RXD PA.3/EPWM_CH3/I2C0_SCL/SPI0_CLK/SPI1_SS/UART0_TXD PD.6/UART0_RXD Mini57 PA.4/XT_IN/EPWM_CH4 QFN 33-pin PB.0/ADC0_CH0/ACMP0_P0/ECAP_P0 PA.5/XT_OUT/EPWM_CH5/ACMP0_O PB.1/ADC0_CH1/ACMP0_P1/ECAP_P1 PD.5/UART0_TXD PB.2/ADC0_CH2/BPWM_CH1/ACMP0_P2/ECAP_P2 33 VSS PB.4/ADC1_CH0/ACMP0_N/TM1 11 12 13 14 15 16 ® Figure 4.3-6 NuMicro Mini57 Series QFN 33-pin Multi-function Diagram Apr.
Page 24: Pin Description
Mini57 4.4 Pin Description 4.4.1 Mini57 Series Pin Description MFP* = Multi-function pin. (Refer to section SYS_GPx_MFP) PA.0 MFP0 means SYS_GPA_MFP[3:0]=0x0. PA.4 MFP5 means SYS_GPA_MFP[19:16]=0x5. MFP only configures the ouput data or input data of PAD; the direction of PAD is configured by PMD. The priority of MFP in the same multi-function was GPA >...
Page 25 Mini57 Pin No. Pin Name Type MFP* Description STADC MFP3 ADC external trigger input. ACMP0_P3 MFP4 Analog comparator0 positive input pin. ACMP1_P1 MFP5 Analog comparator1 positive input pin. SPI0_MOSI MFP9 SPI0 1st MOSI (Master Out, Slave In) pin. SPI1_MISO MFPA SPI1 MISO (Master In, Slave Out) pin.
Page 26 Mini57 Pin No. Pin Name Type MFP* Description BPWM_CH0 MFP3 PWM channel0 output/capture input. ACMP1_P0 MFP5 Analog comparator1 positive input pin. I2C1_SCL MFP8 C1 clock pin. SPI0_SS MFP9 SPI0 slave select pin. SPI1_CLK MFPA SPI1 serial clock pin UART1_TXD MFPB Data transmitter output pin for UART1.
Page 27: Table 4.4-1 Tssop28 Pin Description
Mini57 Pin No. Pin Name Type MFP* Description SPI0_CLK MFP9 SPI0 serial clock pin. SPI1_SS MFPA SPI1 slave select pin UART0_TXD MFPB Data transmitter output pin for UART0. PA.2 MFP0 General purpose digital I/O pin. EPWM_CH2 MFP3 PWM channel2 output/capture input. I2C0_SDA MFP8 C0 data input/output pin.
Page 28 Mini57 4.4.1.2 Mini57 Series TSSOP20 Pin Description Pin No. Pin Name Type MFP* Description MFP0 Power supply for I/O ports and LDO source for internal PLL and digital function. PB.0 MFP0 General purpose digital I/O pin. ADC0_CH0 MFP2 ADC0 channel0 analog input. ACMP0_P0 MFP4 Analog comparator0 positive input pin.
Page 29 Mini57 Pin No. Pin Name Type MFP* Description ADC1_CH2 MFP2 ADC1 channel2 analog input. BRAKE MFP3 Brake input pin of EPWM. CCAP_P1 MFP7 Timer Continuous Capture input pin I2C1_SDA MFP8 C1 data input/output pin. SPI0_MISO MFP9 SPI0 1st MISO (Master In, Slave Out) pin. SPI1_MOSI MFPA SPI1 MOSI (Master Out, Slave In) pin.
Page 30 Mini57 Pin No. Pin Name Type MFP* Description SPI0_CLK MFP9 SPI0 serial clock pin. SPI1_SS MFPA SPI1 slave select pin PA.5 MFP0 General purpose digital I/O pin. XT_OUT MFP1 External 4~24 MHz (high speed) crystal output pin. EPWM_CH5 MFP3 PWM channel5 output/capture input. ACMP0_O MFP4 Analog comparator0 output.
Page 31: Table 4.4-2 Tssop20 Pin Description
Mini57 Pin No. Pin Name Type MFP* Description UART1_TXD MFPB Data transmitter output pin for UART1. MFP0 Ground pin for digital circuit. Table 4.4-2 TSSOP20 Pin Description Apr. 06, 2017 Page 31 of 475 Rev.1.00...
Page 32 Mini57 4.4.1.3 Mini57 Series QFN33 Pin Description QFN33 Pin Pin Name Type MFP* Description LDO_CAP MFP0 LDO output pin. MFP0 Ground pin for digital circuit. Power supply for I/O ports and LDO source for internal PLL and digital MFP0 function. PD.6 MFP0 General purpose digital I/O pin.
Page 33 Mini57 PB.3 MFP0 General purpose digital I/O pin. ACMP1_N MFP5 Analog comparator1 negative input pin. PGA_I MFP6 PGA input pin MFP7 Timer0event counter input / toggle output PC.2 MFP0 General purpose digital I/O pin. ADC1_CH2 MFP2 ADC1 channel2 analog input. BRAKE MFP3 Brake input pin of EPWM.
Page 34 Mini57 XT_IN MFP1 External 4~24 MHz (high speed) crystal input pin. EPWM_CH4 MFP3 PWM channel4 output/capture input. No Connection PA.3 MFP0 General purpose digital I/O pin. EPWM_CH3 MFP3 PWM channel3 output/capture input. I2C0_SCL MFP8 C0 clock pin. SPI0_CLK MFP9 SPI0 serial clock pin. SPI1_SS MFPA SPI1 slave select pin...
Page 35: Table 4.4-3 Qfn33 Pin Description
Mini57 I2C1_SCL MFP8 C1 clock pin. SPI0_SS MFP9 SPI0 slave select pin. SPI1_CLK MFPA SPI1 serial clock pin UART1_TXD MFPB Data transmitter output pin for UART1. PD.4 MFP0 General purpose digital I/O pin. BPWM_CH0 MFP3 PWM channel0 output/capture input. UART1_RXD MFPB Data receiver input pin for UART1.
Page 36: Gpio Multi-Function Pin Summary
Mini57 4.4.2 GPIO Multi-function Pin Summary MFP* = Multi-function pin. (Refer to section SYS_GPx_MFP) PA.0 MFP0 means SYS_GPA_MFP[3:0]=0x0. PA.4 MFP5 means SYS_GPA_MFP[19:16]=0x5. Group Pin Name GPIO MFP* Type Description ACMP0_P0 PB.0 MFP4 Comparator0 positive input pin. ACMP0_P1 PB.1 MFP4 Comparator0 positive input pin. ACMP0_P2 PB.2 MFP4...
Page 37 Mini57 BRAKE PC.2 MFP3 EPWM brake pin. EPWM_CH5 PA.5 MFP3 Enhanced PWM output pin. EPWM_CH4 PA.4 MFP3 Enhanced PWM output pin. EPWM EPWM_CH3 PA.3 MFP3 Enhanced PWM output pin. EPWM_CH2 PA.2 MFP3 Enhanced PWM output pin. EPWM_CH1 PA.1 MFP3 Enhanced PWM output pin. EPWM_CH0 PA.0 MFP3...
Page 38: Table 4.4-4 Tssop20 Multi-Function Pin Summary
Mini57 SPI1_SS PD.1 MFPA SPI1 Slave Select SPI1_CLK PC.0 MFPA SPI1 clock pin. SPI1_SS PA.3 MFPA SPI1 slave selection pin. SPI1_MISO PA.2 MFPA SPI1 MISO (Master In, Slave Out) pin. SPI1_MOSI PA.1 MFPA SPI1 MOSI (Master Out, Slave In) pin. SPI1_CLK PA.0 MFPA...
Page 39: Block Diagram
Mini57 BLOCK DIAGRAM ® 5.1 NuMicro Mini57 Block Diagram ® Figure 5.1-1 NuMicro Mini57 Block Diagram Apr. 06, 2017 Page 39 of 475 Rev.1.00...
Page 40: Functional Description
Mini57 FUNCTIONAL DESCRIPTION ® ® 6.1 ARM Cortex -M0 Core 6.1.1 Overview ® The Cortex -M0 processor is a configurable, multistage, 32-bit RISC processor, which has an AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug ®...
Page 41 Mini57 C Application Binary Interface compliant exception model. This is the ARMv6-M, C Application Binary Interface (C-ABI) compliant exception model that enables the use of pure C functions as interrupt handlers Low Power Sleep mode entry using the Wait For Interrupt (WFI), Wait For Event (WFE) instructions, or return from interrupt sleep-on-exit feature ...
Page 42: System Manager
Mini57 6.2 System Manager 6.2.1 Overview System management includes the following sections:  System Reset  System Power Architecture  System Memory Map  System management registers for Part Number ID, chip reset and on-chip controllers reset, and multi-functional pin control ...
Page 43: Figure 6.2-1 System Reset Resources
Mini57 Glitch Filter nRESET 16.8 us ~50k ohm Power-on Reset Reset Pulse Width Low Voltage 3.2ms Reset BODRSTEN(SYS_BODCTL[3]) Brown-out Reset System Reset Reset Pulse Width Reset 64 WDT clocks CHIP Reset CHIPRST(SYS_IPRST0[0]) MCU Reset Reset Pulse Width Software Reset SYSRSTREQ(SCS_AIRCR[2]) 2 system clocks CPU Reset CPURST(SYS_IPRST0[1])
Page 44: Table 6.2-1 Reset Value Of Registers
Mini57 HCLKSEL (CLK_CLKSEL0[1:0]) WDTSEL (CLK_CLKSEL1[1:0]) XLTSTB (CLK_STATUS[0]) LIRCSTB (CLK_STATUS[3]) HIRCSTB (CLK_STATUS[4]) CLKSFAIL (CLK_STATUS[7]) WDT_CTL 0x0700 0x0700 0x0700 0x0700 0x0700 0x0700 WDT_ALTCTL 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 WWDT_RLDCNT 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 WWDT_CTL 0x3F0800 0x3F0800 0x3F0800 0x3F0800 0x3F0800 0x3F0800 WWDT_STATUS 0x0000...
Page 45: Figure 6.2-2 Nreset Reset Waveform
Mini57 0.7 V and the state keeps longer than 36 us (glitch filter). The PINRF (SYS_RSTSTS[1]) will be set to 1 if the previous reset source is nRESET reset. Figure 6.2-2 shows the nRESET reset waveform. nRESET 0.7 V 16.8 us 0.2 V 16.8 us nRESET Reset...
Page 46: Figure 6.2-4 Low Voltage Reset (Lvr) Waveform
Mini57 keeps longer than De-glitch time. The PINRF (SYS_RSTSTS[1]) will be set to 1 if the previous reset source is nRESET reset. Figure 6.2-4 shows the Low Voltage Reset waveform. ( < de-glitch time) ( = de-glitch time) Low Voltage Reset ( = de-glitch time) Figure 6.2-4 Low Voltage Reset (LVR) Waveform 6.2.2.4...
Page 47: Figure 6.2-5 Brown-Out Detector (Bod) Waveform
Mini57 BODH Hysteresis BODL (< de-glitch time) (= de-glitch time) BODOUT (= de-glitch time) BODRSTEN Brown-out Reset Figure 6.2-5 Brown-out Detector (BOD) Waveform 6.2.2.5 Watchdog Timer Reset In most industrial applications, system reliability is very important. To automatically recover the MCU from failure status is one way to improve system reliability.
Page 48: Power Modes And Wake-Up Sources
Mini57 6.2.3 Power Modes and Wake-up Sources There are several wake-up sources in Idle mode and Power-down mode. Table 6.2-2 lists the available clocks for each power mode. Power Mode Normal Mode Idle Mode Power-Down Mode Definition CPU is in active state CPU is in sleep state CPU is in sleep state and all clocks stop except LXT and...
Page 49: Table 6.2-3 Clocks In Power Modes
Mini57 LXT (32768 Hz XTL) ON/OFF LIRC (10 kHz OSC) ON/OFF Halt Halt HCLK/PCLK Halt SRAM retention FLASH Halt GPIO Halt TIMER ON/OFF BPWM Halt EPWM Halt ON/OFF USCI Halt Halt ACMP Halt ECAP Halt HDIV Halt Halt Table 6.2-3 Clocks in Power Modes Wake-up sources in Power-down mode: WDT, I²C, Timer, UART, SPI, BOD, ACMP and GPIO After chip enters power down, the following wake-up sources can wake chip up to normal mode.
Page 50: Table 6.2-4 Condition Of Entering Power-Down Mode Again
Mini57 USCI SPI SS transaction wake-up After software writes 1 to clear WKF (USPI_WKSTS[0]). USCI I Data toggle After software writes 1 to clear WKF (UI2C_WKSTS[0]). After software writes 1 to clear WKAKDONE (UI2C_PROTSTS[16], then writes 1 Address match to clear WKF (UI2C_WKSTS[0]). Comparator Power-down After software writes 1 to clear ACMPF0 (ACMP_STATUS[0]) and ACMPF1 ACMP...
Page 51: System Power Architecture
Mini57 6.2.4 System Power Architecture In this chip, the power distribution is divided into three segments.  Analog power from AV and AV provides the power for analog components operation. AV must be equal to V to avoid leakage current. ...
Page 52: System Memory Mapping
Mini57 6.2.5 System Memory Mapping Mini57 System Control 4 GB 0xFFFF_FFFF System C ontrol 0xE000_ED00 SC S_BA Reserved External Interrupt C ontrol 0xE000_E100 SC S_BA 0xE000_F000 System Timer C ontrol 0xE000_E010 SC S_BA 0xE000_EFFF System C ontrol 0xE000_E000 0xE000_E00F Reserved 0x6002_0000 0x6001_FFFF Reserved...
Page 53: Register Protection
Mini57 6.2.6 Register Protection Some of the system control registers need to be protected to avoid inadvertent write and disturb the chip operation. These system control registers are protected after the power on reset till user to disable register protection. For user to program these protected registers, a register protection disable sequence needs to be followed by a special programming.
Page 54: Table 6.2-6 Protected Registers
Mini57 [3] APUEN APROM Update Enable Control (Write Protect) [2] SPUEN SPROM Update Enable Control (Write Protect) [1] BS Boot Select (Write Protect) [0] ISPEN ISP Enable Control (Write Protect) FMC_ISPTRG [0] ISPGO ISP Start Trigger (Write Protect) FMC_ISPSTS [6] ISPFF ISP Fail Flag (Write Protect) TIMER0_CTL [31] ICEDEBUG...
Page 55: Memory Organization
Mini57 6.2.7 Memory Organization 6.2.7.1 Overview ® The NuMicro Mini57 series provides 4G-byte addressing space. The addressing space assigned to each on-chip controllers is shown in Figure 6.2-8. The detailed register definition, addressing space, and programming details will be described in the following sections for each on-chip peripheral.
Page 56: Table 6.2-7 Address Space Assignments For On-Chip Modules
Mini57 Address Space Token Controllers Flash and SRAM Memory Space 0x0000_0000 – 0x0000_75FF FLASH_BA FLASH Memory Space (29.5KB) 0x0010_0000 – 0x0010_07FF LD_BA Loader Memory Space (2 KB) 0x0020_0000 – 0x0020_01FF SP0_BA Security Program Memory 0 Space (0.5 KB) 0x0024_0000 – 0x0024_01FF SP1_BA Security Program Memory 1 Space (0.5 KB) 0x0028_0000 –...
Page 57: Figure 6.2-9 Sram Block Diagram
Mini57 6.2.7.3 SRAM Memory Organization The Mini57 supports embedded SRAM with total 4 Kbytes size.  Supports total 4 Kbytes SRAM  Supports byte / half word / word write  Supports oversize response error AHB interface SRAM decoder SRAM 4KB controller Figure 6.2-9 SRAM Block Diagram Apr.
Page 58: Register Map
Mini57 6.2.8 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value SYS Base Address: SYS_BA = 0x5000_0000 0xXXXX_XXXX SYS_PDID SYS_BA+0x00 Part Device Identification Number Register SYS_RSTSTS SYS_BA+0x04 R/W System Reset Status Register 0x0000_00XX SYS_IPRST0 SYS_BA+0x08...
Page 59: Register Description
Mini57 6.2.9 Register Description Part Device Identification Number Register (SYS_PDID) Register Offset Description Reset Value 0xXXXX_XXXX SYS_PDID SYS_BA+0x00 Part Device Identification Number Register [1] Every part number has a unique default reset value. PDID PDID PDID PDID Bits Description Part Device Identification Number (Read Only) [31:0] PDID This register reflects device part number code.
Page 60 Mini57 System Reset Status Register (SYS_RSTSTS) This register provides specific information for software to identify this chip’s reset source from last operation. Register Offset Description Reset Value SYS_RSTSTS SYS_BA+0x04 System Reset Status Register 0x0000_00XX Reserved Reserved Reserved CPURF Reserved SYSRF BODRF LVRF WDTRF...
Page 61 Mini57 Bits Description LVR Reset Flag The LVR reset flag is set by the “Reset Signal” from the Low Voltage Reset Controller to indicate the previous reset source. LVRF 0 = No reset from LVR. 1 = LVR controller had issued the reset signal to reset the system. Note: Write 1 to clear this bit to 0.
Page 62 Mini57 Peripheral Reset Control Register 0 (SYS_IPRST0) Register Offset Description Reset Value Peripheral Reset Control Register 0 SYS_IPRST0 SYS_BA+0x08 0x0000_0000 Reserved Reserved Reserved Reserved CPURST CHIPRST Bits Description [31:2] Reserved Reserved. Processor Core One-shot Reset (Write Protect) Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles.
Page 63 Mini57 Peripheral Reset Control Register 1 (SYS_IPRST1) Setting these bits 1 will generate asynchronous reset signals to the corresponding module controller. Users need to set these bits to 0 to release corresponding module controller from reset state. Register Offset Description Reset Value SYS_IPRST1 SYS_BA+0x0C...
Page 64 Mini57 Basic PWM Controller Reset [16] BPWMRST 0 = BPWM controller normal operation. 1 = BPWM controller reset. Reserved [15:13] Reserved. PGA Controller Reset [12] PGARST 0 = PGA controller normal operation. 1 = PGA controller reset. [11:9] Reserved Reserved. ECAP Controller Reset CAPRST 0 = ECAP controller normal operation.
Page 65 Mini57 HCLK Wait State Cycle Control Register (SYS_WAIT) Register Offset Description Reset Value SYS_WAIT SYS_BA+0x10 HCLK Wait State Cycle Control Register 0x0000_0001 Reserved Reserved Reserved Reserved HCLKWS Bits Description [31:1] Reserved Reserved. HCLK Wait State Cycle Control Bit This bit is used to enable/disable HCLK wait state when access Flash. HCLKWS 0 = No wait state.
Page 66 Mini57 Brown-out Detector Control Register (SYS_BODCTL) Partial of the SYS_BODCTL control registers values are initiated by the Flash configuration and partial bits are write-protected bit. Register Offset Description Reset Value SYS_BODCTL SYS_BA+0x18 Brown-Out Detector Control Register 0x0000_80XX Reserved Reserved LVREN Reserved BODOUT BODLPM...
Page 67 Mini57 Bits Description Brown-out Detector Interrupt Flag 0 = Brown-out Detector does not detect any voltage draft at V down through or up through the voltage of BODVL setting. BODIF 1 = When Brown-out Detector detects the V is dropped down through the voltage of BODVL setting or the V is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled.
Page 68 Mini57 Internal Voltage Source Control Register (SYS_IVSCTL) Register Offset Description Reset Value SYS_IVSCTL SYS_BA+0x1C Internal Voltage Source Control Register 0x0000_0000 Reserved Reserved Reserved Reserved VTEMPEN Bits Description [31:1] Reserved Reserved. Temperature Sensor Enable Bit This bit is used to enable/disable temperature sensor function. 0 = Temperature sensor function Disabled (default).
Page 69 Mini57 Power-on Reset Controller Register (SYS_PORCTL) Register Offset Description Reset Value SYS_PORCTL SYS_BA+0x24 Power-On-Reset Controller Register 0x0000_00XX Reserved Reserved POROFF POROFF Bits Description [31:16] Reserved Reserved. Power-on Reset Enable Bit (Write Protect) When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again.
Page 70 Mini57 GPIOA Multiple Function Control Register (SYS_GPA_MFP) Please refer to GPIO Multi-function Pin Summary Register Offset R/W Description Reset Value SYS_GPA_MFP SYS_BA+0x30 R/W GPIOA Multiple Function Control Register 0x0000_0000 Reserved PA5MFP PA4MFP PA3MFP PA2MFP PA1MFP PA0MFP Bits Description [31:24] Reserved Reserved.
Page 71 Mini57 GPIOB Multiple Function Control Register (SYS_GPB_MFP) Please refer to GPIO Multi-function Pin Summary Register Offset Description Reset Value SYS_GPB_MFP SYS_BA+0x34 R/W GPIOB Multiple Function Control Register 0x0000_0000 Reserved Reserved PB4MFP PB3MFP PB2MFP PB1MFP PB0MFP Bits Description [31:20] Reserved Reserved. [19:16] PB4MFP PB.4 Multi-function Pin Selection...
Page 72 Mini57 GPIOC Multiple Function Control Register (SYS_GPC_MFP) Please refer to GPIO Multi-function Pin Summary Register Offset R/W Description Reset Value SYS_GPC_MFP SYS_BA+0x38 R/W GPIOC Multiple Function Control Register 0x0000_0000 Reserved Reserved PC4MFP PC3MFP PC2MFP PC1MFP PC0MFP Bits Description [31:20] Reserved Reserved.
Page 73 Mini57 GPIOD Multiple Function Control Register (SYS_GPD_MFP) Please refer to GPIO Multi-function Pin Summary Register Offset Description Reset Value SYS_GPD_MFP SYS_BA+0x3C R/W GPIOD Multiple Function Control Register 0x0000_0111 Reserved PD6MFP PD5MFP PD4MFP PD3MFP PD2MFP PD1MFP Reserved Bits Description [31:28] Reserved Reserved.
Page 74 Mini57 HIRC Trim Control Register (SYS_IRCTCTL) Register Offset Description Reset Value SYS_IRCTCTL SYS_BA+0x80 HIRC Trim Control Register 0x0000_0030 Reserved Reserved Reserved RETRYCNT LOOPSEL Reserved FREQSEL Bits Description [31:8] Reserved Reserved. Trim Value Update Limitation Count This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.
Page 75 Mini57 HIRC Trim Interrupt Enable Register (SYS_IRCTIEN) Register Offset Description Reset Value SYS_IRCTIEN SYS_BA+0x84 HIRC Trim Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved CLKEIEN TFAILIEN Reserved Bits Description [31:3] Reserved Reserved. Clock Error Interrupt Enable Bit This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.
Page 76 Mini57 HIRC Trim Interrupt Status Register (SYS_IRCTISTS) Register Offset Description Reset Value SYS_IRCTISTS SYS_BA+0x88 HIRC Trim Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved Reserved CLKERRIF TFAILIF FREQLOCK Bits Description [31:3] Reserved Reserved. Clock Error Interrupt Status When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy CLKERRIF...
Page 77 Mini57 Register Lock Control Register (SYS_REGLCTL) Some of the system control registers need to be protected to avoid inadvertent write and disturb the chip operation. These system control registers are protected after the power-on reset till user to disable register protection. For user to program these protected registers, a register protection disable sequence needs to be followed by a special programming.
Page 78 Mini57 Temperature Sensor Offset Register (SYS_TSOFFSET) Register Offset Description Reset Value SYS_TSOFFSE SYS_BA+0x114 Temperature sensor offset Register 0x0XXX_0XXX Reserved VTEMP1 VTEMP1 Reserved VTEMP0 VTEMP0 Bits Description [31:28] Reserved Reserved. Temperature Sensor Offset Value VTEMP1 [27:16] This field reflects temperature sensor output voltage offset at 125 [15:12] Reserved Reserved.
Page 79: System Timer (Systick)
Mini57 6.2.10 System Timer (SysTick) ® The Cortex -M0 includes an integrated system timer, SysTick, which provides a simple, 24-bit cleared-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example: An RTOS tick timer fires at a programmable rate (for example 100Hz) and invokes a SysTick routine.
Page 80 Mini57 6.2.10.1 System Timer Control Register Map R: read only, W: write only, R/W: both read and write, W&C: write 1 to clear Register Offset Description Reset Value SCS Base Address: SCS_BA = 0xE000_E000 SYST_CTL SCS_BA+0x10 SysTick Control and Status 0x0000_0004 SYST_RVR SCS_BA+0x14...
Page 81 Mini57 6.2.10.2 System Timer Control Register Description SysTick Control and Status （SYST_CTL） Register Offset Description Reset Value SYST_CTL SCS_BA+0x10 SysTick Control and Status 0x0000_0004 Reserved Reserved COUNTFLAG Reserved Reserved CLKSRC TICKINT ENABLE Bits Description [31:17] Reserved Reserved. System Tick Counter Flag Return 1 If Timer Counted to 0 Since Last Time this Register Was Read [16] COUNTFLAG...
Page 82 Mini57 SysTick Reload Value Register (SYST_RVR） Register Offset Description Reset Value SYST_RVR SCS_BA+0x14 SysTick Reload Value Register 0xXXXX_XXXX Reserved RELOAD RELOAD RELOAD Bits Description [31:24] Reserved Reserved. System Tick Reload Value [23:0] RELOAD Value to load into the Current Value register when the counter reaches 0. Apr.
Page 83 Mini57 SysTick Current Value Register （SYST_CVR） Register Offset Description Reset Value SYST_CVR SCS_BA+0x18 SysTick Current Value Register 0xXXXX_XXXX Reserved CURRENT CURRENT CURRENT Bits Description [31:24] Reserved Reserved. System Tick Current Value Current counter value. This is the value of the counter at the time it is sampled. The [23:0] CURRENT counter does not provide read-modify-write protection.
Page 84: Nested Vectored Interrupt Control (Nvic)
Mini57 6.2.11 Nested Vectored Interrupt Control (NVIC) 6.2.11.1 Overview ® The Cortex -M0 CPU provides an interrupt controller as an integral part of the exception mode, named as “Nested Vectored Interrupt Controller (NVIC)”, which is closely coupled to the processor core and provides following features. 6.2.11.2 Features ...
Page 85: Table 6.2-8 Exception Model
Mini57 Exception Name Vector Number Priority Reset Hard Fault Reserved 4 ~ 10 Reserved SVCall Configurable Reserved 12 ~ 13 Reserved PendSV Configurable SysTick Configurable Interrupt (IRQ0 ~ IRQ31) 16 ~ 47 Configurable Table 6.2-8 Exception Model Interrupt Number Vector Interrupt Name Interrupt Description (Bit...
Page 86: Table 6.2-9 System Interrupt Map Vector Table
Mini57 Reserved Reserved Reserved Reserved Reserved Reserved HIRCTRIM_INT HIRC TRIM interrupt TMR0_INT Timer 0 interrupt TMR1_INT Timer 1 interrupt Reserved Reserved Reserved Reserved Analog Comparator 0 or Comparator 1 interrupt ACMP_INT Reserved Reserved Chip wake-up from Power-down state interrupt PWRWU_INT ADC0 interrupt ADC0_INT ADC1 interrupt...
Page 87 Mini57 to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers reading back the current pended state of the corresponding interrupts. The Clear-Pending Register has no effect on the execution status of an Active interrupt. NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register supporting four interrupts).
Page 88 Mini57 6.2.11.6 NVIC Control Registers Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value SCS Base Address: SCS_BA = 0xE000_E000 NVIC_ISER SCS_BA+0x100 IRQ0 ~ IRQ31 Set-Enable Control Register 0x0000_0000 NVIC_ICER SCS_BA+0x180 IRQ0 ~ IRQ31 Clear-Enable Control Register 0x0000_0000 NVIC_ISPR SCS_BA+0x200...
Page 89 Mini57 IRQ0 ~ IRQ31 Set-enable Control Register (NVIC_ISER) Register Offset Description Reset Value NVIC_ISER SCS_BA+0x100 IRQ0 ~ IRQ31 Set-Enable Control Register 0x0000_0000 SETENA SETENA SETENA SETENA Bits Description Interrupt Enable Register Enable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).
Page 90 Mini57 IRQ0 ~ IRQ31 Clear-enable Control Register (NVIC_ICER) Register Offset Description Reset Value NVIC_ICER SCS_BA+0x180 IRQ0 ~ IRQ31 Clear-Enable Control Register 0x0000_0000 CLRENA CLRENA CLRENA CLRENA Bits Description Interrupt Disable Register Disable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).
Page 91 Mini57 IRQ0 ~ IRQ31 Set-pending Control Register (NVIC_ISPR) Register Offset Description Reset Value NVIC_ISPR SCS_BA+0x200 IRQ0 ~ IRQ31 Set-Pending Control Register 0x0000_0000 SETPEND SETPEND SETPEND SETPEND Bits Description Set Interrupt Pending Register Write operation: 0 = No effect. 1 = Write 1 to set pending state. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).
Page 92 Mini57 IRQ0 ~ IRQ31 Clear-pending Control Register (NVIC_ICPR) Register Offset Description Reset Value NVIC_ICPR SCS_BA+0x280 IRQ0 ~ IRQ31 Clear-Pending Control Register 0x0000_0000 CLRPEND CLRPEND CLRPEND CLRPEND Bits Description Clear Interrupt Pending Register Write operation: 0 = No effect. 1 = Write 1 to clear pending state. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).
Page 93 Mini57 IRQ0 ~ IRQ3 Interrupt Priority Register (NVIC_IPR0) Register Offset Description Reset Value NVIC_IPR0 SCS_BA+0x400 IRQ0 ~ IRQ3 Interrupt Priority Control Register 0x0000_0000 PRI_3 Reserved PRI_2 Reserved PRI_1 Reserved PRI_0 Reserved Bits Description Priority of IRQ3 [31:30] PRI_3 0 denotes the highest priority and 3 denotes the lowest priority. [29:24] Reserved Reserved.
Page 94 Mini57 IRQ4 ~ IRQ7 Interrupt Priority Register (NVIC_IPR1) Register Offset Description Reset Value NVIC_IPR1 SCS_BA+0x404 IRQ4 ~ IRQ7 Interrupt Priority Control Register 0x0000_0000 PRI_7 Reserved PRI_6 Reserved PRI_5 Reserved PRI_4 Reserved Bits Description Priority of IRQ7 [31:30] PRI_7 0 denotes the highest priority and 3 denotes the lowest priority. [29:24] Reserved Reserved.
Page 95 Mini57 IRQ8 ~ IRQ11 Interrupt Priority Register (NVIC_IPR2) Register Offset Description Reset Value NVIC_IPR2 SCS_BA+0x408 IRQ8 ~ IRQ11 Interrupt Priority Control Register 0x0000_0000 PRI_11 Reserved PRI_10 Reserved PRI_9 Reserved PRI_8 Reserved Bits Description Priority of IRQ11 [31:30] PRI_11 0 denotes the highest priority and 3 denotes the lowest priority. [29:24] Reserved Reserved.
Page 96 Mini57 IRQ12 ~ IRQ15 Interrupt Priority Register (NVIC_IPR3) Register Offset Description Reset Value NVIC_IPR3 SCS_BA+0x40C IRQ12 ~ IRQ15 Interrupt Priority Control Register 0x0000_0000 PRI_15 Reserved PRI_14 Reserved PRI_13 Reserved PRI_12 Reserved Bits Description Priority of IRQ15 [31:30] PRI_15 0 denotes the highest priority and 3 denotes the lowest priority. [29:24] Reserved Reserved.
Page 97 Mini57 IRQ16 ~ IRQ19 Interrupt Priority Register (NVIC_IPR4) Register Offset Description Reset Value NVIC_IPR4 SCS_BA+0x410 IRQ16 ~ IRQ19 Interrupt Priority Control Register 0x0000_0000 PRI_19 Reserved PRI_18 Reserved PRI_17 Reserved PRI_16 Reserved Bits Description Priority of IRQ19 [31:30] PRI_19 0 denotes the highest priority and 3 denotes the lowest priority. [29:24] Reserved Reserved.
Page 98 Mini57 IRQ20 ~ IRQ23 Interrupt Priority Register (NVIC_IPR5) Register Offset Description Reset Value NVIC_IPR5 SCS_BA+0x414 IRQ20 ~ IRQ23 Interrupt Priority Control Register 0x0000_0000 PRI_23 Reserved PRI_22 Reserved PRI_21 Reserved PRI_20 Reserved Bits Description Priority of IRQ23 [31:30] PRI_23 0 denotes the highest priority and 3 denotes the lowest priority. [29:24] Reserved Reserved.
Page 99 Mini57 IRQ24 ~ IRQ27 Interrupt Priority Register (NVIC_IPR6) Register Offset Description Reset Value NVIC_IPR6 SCS_BA+0x418 IRQ24 ~ IRQ27 Interrupt Priority Control Register 0x0000_0000 PRI_27 Reserved PRI_26 Reserved PRI_25 Reserved PRI_24 Reserved Bits Description Priority of IRQ27 [31:30] PRI_27 0 denotes the highest priority and 3 denotes the lowest priority. [29:24] Reserved Reserved.
Page 100 Mini57 IRQ28 ~ IRQ31 Interrupt Priority Register (NVIC_IPR7) Register Offset Description Reset Value NVIC_IPR7 SCS_BA+0x41C IRQ28 ~ IRQ31 Interrupt Priority Control Register 0x0000_0000 PRI_31 Reserved PRI_30 Reserved PRI_29 Reserved PRI_28 Reserved Bits Description Priority of IRQ31 [31:30] PRI_31 0 denotes the highest priority and 3 denotes the lowest priority. [29:24] Reserved Reserved.
Page 101 Mini57 6.2.11.7 Interrupt Source Control Registers Besides the interrupt control registers associated with the NVIC, the Mini57 series also implements some specific control registers to facilitate the interrupt functions, including ”NMI source selection” and “IRQ number identity”, which are described below. R: read only, W: write only, R/W: both read and write Register Offset...
Page 102 Mini57 NMI Interrupt Source Select Control Register (INT_NMICTL) Register Offset Description Reset Value INT_NMICTL INT_BA+0x80 NMI Source Interrupt Select Control Register 0x0000_0000 Reserved Reserved Reserved NMISELEN Reserved NMISEL Bits Description [31:9] Reserved Reserved. NMI Interrupt Enable Bit (Write Protected) 0 = NMI interrupt Disabled. 1 = NMI interrupt Enabled.
Page 103 Mini57 MCU Interrupt Request Source Register (INT_IRQSTS) Register Offset Description Reset Value INT_IRQSTS INT_BA+0x84 MCU IRQ Number Identity Register 0x0000_0000 Bits Description MCU IRQ Source Register The IRQ collects all the interrupts from the peripherals and generates the synchronous ® ®...
Page 104: System Control Registers
Mini57 6.2.12 System Control Registers ® Key control and status features of Cortex -M0 are managed centrally in a System Control Block within the System Control Registers. ® ® For more detailed information, please refer to the “ARM Cortex -M0 Technical Reference ®...
Page 105 Mini57 6.2.12.1 System Control Register Memory Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value SCS Base Address: SCS_BA = 0xE000_E000 SCS_CPUID SCS_BA+0xD00 CPUID Base Register 0x410C_C200 SCS_ICSR SCS_BA+0xD04 Interrupt Control State Register 0x0000_0000 Application Interrupt...
Page 106 Mini57 6.2.12.2 System Control Register Description CPUID Base Register (CPUID) Register Offset Description Reset Value SCS_CPUID SCS_BA+0xD00 CPUID Base Register 0x410C_C200 IMPLEMENTER Reserved PART PARTNO PARTNO REVISION Bits Description Implementer Code [31:24] IMPLEMENTER Implementer code assigned by ARM ( ARM = 0x41). [23:20] Reserved Reserved.
Page 107 Mini57 Interrupt Control State Register (ICSR) Register Offset Description Reset Value SCS_ICSR SCS_BA+0xD04 Interrupt Control State Register 0x0000_0000 NMIPENDSET Reserved PENDSVSET PENDSVCLR PENDSTSET PENDSTCLR Reserved ISRPREEMPT ISRPENDING Reserved VECTPENDING VECTPENDING Reserved VECTACTIVE VECTACTIVE Bits Description NMI Set-pending Bit Write Operation: 0 = No effect.
Page 108 Mini57 Write Operation: 0 = No effect. 1 = Changes SysTick exception state to pending. Read Operation: 0 = SysTick exception is not pending. 1 = SysTick exception is pending. SysTick Exception Clear-pending Bit Write Operation: 0 = No effect. [25] PENDSTCLR 1 = Removes the pending state from the SysTick exception.
Page 109 Mini57 Application Interrupt and Reset Control Register (AIRCR) Register Offset Description Reset Value SCS_AIRCR SCS_BA+0xD0C Application Interrupt and Reset Control Register 0xFA05_0000 VECTORKEY VECTORKEY Reserved Reserved SYSRESETRE VECTCLRAC Reserved TIVE Bits Description Register Access Key Write Operation: When writing to this register, the VECTORKEY field need to be set to 0x05FA, otherwise VECTORKEY the write operation would be ignored.
Page 110 Mini57 System Control Register (SCR) Register Offset Description Reset Value SCS_SCR SCS_BA+0xD10 System Control Register 0x0000_0000 Reserved Reserved Reserved Reserved SEVONPEND Reserved SLEEPDEEP SLEEPONEXI Reserved Bits Description [31:5] Reserved Reserved. Send Event on Pending Bit 0 = Only enabled interrupts or events can wake-up the processor, disabled interrupts areexcluded.
Page 111 Mini57 System Handler Priority Register 2 (SHPR2) Register Offset Description Reset Value SCS_SHPR2 SCS_BA+0xD1C System Handler Priority Register 2 0x0000_0000 PRI_11 Reserved Reserved Reserved Reserved Bits Description Priority of System Handler 11 – SVCall [31:30] PRI_11 “0” denotes the highest priority and “3” denotes the lowest priority. [29:0] Reserved Reserved.
Page 112 Mini57 System Handler Priority Register 3 (SHPR3) Register Offset Description Reset Value SCS_SHPR3 SCS_BA+0xD20 System Handler Priority Register 3 0x0000_0000 PRI_15 Reserved PRI_14 Reserved Reserved Reserved Bits Description Priority of System Handler 15 – SysTick [31:30] PRI_15 “0” denotes the highest priority and “3” denotes the lowest priority. [29:24] Reserved Reserved.
Page 113: Clock Controller
Mini57 6.3 Clock Controller 6.3.1 Overview The clock controller generates clocks for the whole chip, including system clocks and all peripheral clocks. The clock controller also implements the power control function with the individually clock ON/OFF control, clock source selection and clock divider. The chip enters ®...
Page 114: Figure 6.3-2 Clock Generator Global View Diagram
Mini57 HIRC CPUCLK 48 MHz 1/(HCLKDIV+1) HCLK 10 kHz 4~24 MHz/32.768kHz PCLK LIRC CLK_CLKSEL0[1:0] 48 MHz TMR 0 10 kHz T0~T1 TMR 1 HCLK 48 MHz 10 kHz HCLK HDIV 4~24 MHz/32.768kHz HCLK ECAP CLK_CLKSEL1 [10:8] HCLK CLK_CLKSEL1[14:12] ACMP HCLK 1/(PGADIV+1) 48 MHz HCLK...
Page 115: Auto Trim
Mini57 6.3.2 Auto Trim This chip supports auto-trim function: the HIRC trim (48 MHz RC oscillator), according to the accurate LXT (32.768 kHz crystal oscillator), automatically gets accurate HIRC output frequency, 0.25 % deviation within all temperature ranges. For instance, the system needs an accurate 48MHz clock. In such case, if users do not want to use PLL as the system clock source, they need to solder 32.768 kHz crystal in system, and set FREQSEL (SYS_IRCTCTL[0] trim frequency selection) to “1”, and the auto-trim function will be enabled.
Page 116: Peripherals Clock Source Selection
Mini57 48 MHz HIRC HCLK CPUCLK 4~24 MHz HXT or SysTick 32.768 kHz LXT 4~24 MHz HXT or 32.768 kHz LXT SYST_CTL[2] CLK_CLKSEL0[4:3] Legend: HXT = 4~24 MHz external high speed crystal oscillator HIRC = 48 MHz internal high speed RC oscillator LIRC = 10 kHz internal low speed RC oscillator Figure 6.3-4 SysTick Clock Control Block Diagram 6.3.4...
Page 117: Figure 6.3-5 Peripherals Bus Clock Source Selection For Pclk
Mini57 PCLK Watch Dog Timer WDTCKEN (CLK_APBCLK[0]) Timer0 TMR0CKEN (CLK_APBCLK[2]) Timer1 TMR1CKEN (CLK_APBCLK[3]) Frequency Divider CLKOCKEN (CLK_APBCLK[6]) ECAP ECAPCKEN (CLK_APBCLK[8]) PGACKEN (CLK_APBCLK[12]) EPWM EPWMCKEN (CLK_APBCLK[20]) BPWM BPWMCKEN (CLK_APBCLK[16]) UART1 UART1CKEN (CLK_APBCLK[17]) USCI0 USCI0CKEN (CLK_APBCLK[24]) USCI1 USCI1CKEN (CLK_APBCLK[25]) ADCCKEN (CLK_APBCLK[28]) ACMP ACMPCKEN (CLK_APBCLK[30]) Figure 6.3-5 Peripherals Bus Clock Source Selection for PCLK Apr.
Page 118: Power-Down Mode Clock
Mini57 Ext. CLK Peripheral Clock Selectable HIRC LIRC HCLK (HXT Or LXT) WWDT Timer0 Timer1 USCI0 USCI1 ACMP ECAP EBWM BPWM HDIV Table 6.3-1 Peripheral Clock Source Selection Table Note: For the peripherals those peripheral clock are not selectable, its clock source is fixed to PCLK.
Page 119: Figure 6.3-6 Clock Source Of Frequency Divider
Mini57 multiplexer is reflected to the CKO pin. Therefore there are 16 options of power-of-2 divided clocks with the frequency from F to F where F is input clock frequency to the clock divider. (N+1) The output formula is F , where F is the input clock frequency, F is the clock...
Page 120: Register Map
Mini57 6.3.7 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value CLK Base Address: CLK_BA = 0x5000_0200 CLK_PWRCTL CLK_BA+0x00 System Power-down Control Register 0x0000_001C CLK_AHBCLK CLK_BA+0x04 AHB Devices Clock Enable Control Register 0x0000_0014 CLK_APBCLK CLK_BA+0x08 APB Devices Clock Enable Control Register...
Page 121: Register Description
Mini57 6.3.8 Register Description Power-down Control Register (CLK_PWRCTL) Except the BIT[6], all the other bits are protected, and programming these bits need to write 0x59, 0x16, 0x88 to address 0x5000_0100 to disable register protection. Refer to the SYS_REGLCTL register at address SYS_BA + 0x100. Register Offset Description...
Page 122 Mini57 peripheral clock source is from LXT or LIRC. 0 = Chip operating normally or chip in idle mode because of WFI/WFE command. 1 = Chip enters Power-down mode when CPU sleep command WFI/WFE. Note: This bit is write protected. Refer to the SYS_REGLCTL register. Power-down Mode Wake-up Interrupt Status Set by “Power-down wake-up event”, it indicates that resume from Power-down mode”...
Page 123: Table 6.3-2 Power-Down Mode Control Table
Mini57 Register/Instruction SLEEPDEEP PDEN Clock Disable Instruction Mode (SCS_SCR[2]) (CLK_PWRCTL [7]) Normal operation All clocks are controlled by control register. Idle mode Only CPU clock is disabled. (CPU enters Sleep mode) Power-down mode Most clocks are disabled except LIRC/LXT, only (CPU enters Deep Sleep RTC/WDT/Timer peripheral...
Page 124 Mini57 AHB Devices Clock Enable Control Register (CLK_AHBCLK) The bits in this register are used to enable/disable clock for system clock, AHB bus devices clock. Register Offset Description Reset Value CLK_AHBCLK CLK_BA+0x04 AHB Devices Clock Enable Control Register 0x0000_0014 Reserved Reserved Reserved Reserved...
Page 125 Mini57 APB Devices Clock Enable Control Register (CLK_APBCLK) The bits in this register are used to enable/disable clock for peripheral controller clocks. Register Offset Description Reset Value CLK_APBCLK CLK_BA+0x08 APB Devices Clock Enable Control Register 0x0000_0001 Reserved ACMPCKEN Reserved ADCCKEN Reserved USCI1CKEN USCI0CKEN...
Page 126 Mini57 [19:13] Reserved Reserved. PGA Clock Enable Bit [12] PGACKEN 0 = PGA clock Disabled. 1 = PGA clock Enabled. [11:9] Reserved Reserved. Input Capture Clock Enable Bit ECAPCKEN 0 = ECAP clock Disabled. 1 = ECAP clock Enabled. Reserved Reserved.
Page 127 Mini57 Clock Source Select Control Register 0 (CLK_CLKSEL0) Register Offset Description Reset Value CLK_CLKSEL0 CLK_BA+0x10 Clock Source Select Control Register 0 0x0000_001B Reserved Reserved Reserved Reserved STCLKSEL Reserved HCLKSEL Bits Description [31:5] Reserved Reserved. ® Cortex -M0 SysTick Clock Source Selection (Write Protect) If SYST_CTL[2]=0, SysTick uses the clock source listed below.
Page 128 Mini57 Clock Source Select Control Register 1 (CLK_CLKSEL1) Before clock switching, the related clock sources (pre-selected and newly-selected) must be turned Register Offset Description Reset Value CLK_CLKSEL CLK_BA+0x14 Clock Source Select Control Register 1 0xC307_7733 CLKOSEL Reserved Reserved Reserved TMR1SEL Reserved TMR0SEL Reserved...
Page 129 Mini57 ADC Peripheral Clock Source Selection 00 = Clock source from external crystal oscillator (HXT or LXT). [5:4] ADCSEL 01 = Reserved. 10 = Clock source is from HCLK. 11 = Clock source from 48 MHz internal high speed RC oscillator (HIRC). Reserved [3:2] Reserved.
Page 130 Mini57 Clock Divider Number Register (CLK_CLKDIV) Register Offset Description Reset Value CLK_CLKDIV CLK_BA+0x20 Clock Divider Number Register 0x0000_0000 Reserved ADCDIV Reserved Reserved HCLKDIV Bits Description [31:24] Reserved Reserved. ADC Clock Divide Number From ADC Clock Source ADCDIV [23:16] ADC clock frequency = (ADC clock source frequency) / (ADCDIV + 1). [15:4] Reserved Reserved.
Page 131 Mini57 Clock Status Monitor Register (CLK_STATUS) The bits in this register are used to monitor if the chip clock source is stable or not, and whether the clock switch is failed. Register Offset Description Reset Value CLK_STATUS CLK_BA+0x50 R Clock Status Monitor Register 0x0000_00XX Reserved Reserved...
Page 132 Mini57 Clock Output Control Register (CLK_CLKOCTL) Register Offset Description Reset Value CLK_CLKOCTL CLK_BA+0x60 Clock Output Control Register 0x0000_0000 Reserved Reserved Reserved Reserved DIV1EN CLKOEN FREQSEL Bits Description [31:6] Reserved Reserved. Clock Output Divide One Enable Bit DIV1EN 0 = Clock Output will output clock with source frequency divided by FREQSEL. 1 = Clock Output will output clock with source frequency.
Page 133: Flash Memory Controller (Fmc)
Mini57 6.4 Flash Memory Controller (FMC) 6.4.1 Overview The Mini57 series is equipped with 29.5 Kbytes on chip embedded Flash for application program memory (APROM) that can be updated through ISP procedure. In System Programming (ISP) function enables user to update program memory when chip is soldered on PCB. After chip ®...
Page 134: Figure 6.4-1 Flash Memory Control Block Diagram
Mini57 Cortex-M0 Debug Access Port AHB Lite interface AHB Bus DFBADR AHB Slave Interface ISP Controller Flash Operation Power On Control Initialization Data Out Config & Map Control Figure 6.4-1 Flash Memory Control Block Diagram Apr. 06, 2017 Page 134 of 475 Rev.1.00...
Page 135: Functional Description
Mini57 6.4.4 Functional Description 6.4.4.1 Flash Memory Organization The Mini57 Flash memory consists of program memory (APROM), Data Flash, ISP loader program memory (LDROM), and user configuration. Program memory is main memory for user applications and called APROM. User can write their application to APROM and set system to boot from APROM.
Page 136: Figure 6.4-2 Flash Memory Organization
Mini57 The Flash memory organization is shown in Figure 6.4-2: 0x0030_03FF User Configuration 0x0030_0000 Reserved 0x0028_01FF SPROM2 0x0028_0000 Reserved 0x0024_01FF SPROM1 0x0024_0000 Reserved 0x0020_01FF SPROM0 0x0020_0000 Reserved 0x0010_07FF LDROM 0x0010_0000 Reserved (29.5KB) 0x0000_75FF Data Flash DFBA APROM CONFIG1 0x0030_0004 CONFIG0 0x0030_0000 0x0000_0000 Figure 6.4-2 Flash Memory Organization...
Page 137: Figure 6.4-3 Data Flash Shared With Aprom
Mini57 0x0000_75FF DataFlash 0.5*N k bytes Programmable start DFBA[31:0] address Application Program (29.5-0.5*N)K bytes 29.5K Flash Memory Device Figure 6.4-3 Data Flash Shared with APROM 6.4.4.3 Security Program Memory (SPROM) The Mini57 series provides security program memory for user to store instruction of security. It is read/write through ISP procedure and ICE, and this memory cannot be erased by “whole chip erase command”...
Page 138 Mini57  (The last byte=Others): Secured code ICE Debug ISP/IAP CPU Data CPU Instruction Whole chip erase √ Page-erase Program Read CPU Instruction SPROM0/1/2 0x200000 ~ 0x2001FF/0x240000 ~ 0x2401FF/0x280000 ~ 0x2801FF ISP/IAP/ICP/Writer Lock unLock Lock unLock whole chip erase √ √...
Page 139: Figure 6.4-4 Sprom Security Mode
Mini57 Reserved 0x0030_0004 User Configuration 0x0030_0000 (8B) Reserved 0x0028_01FF Security Protection ROM 2 0x0028_0000 (SPROM1 0.5KB) SPROM Non-security Mode SPROM Debug Mode SPROM Security Mode Reserved 0x002x_01FF 0xFF 0xAA others 0x0024_01FF Security Protection 0x002x_01FE ROM 1 (SPROM1 0.5KB) 0x0024_0000 Reserved 0x0020_01FF Security Protection ROM 0...
Page 140 Mini57 Config0 (Address = 0x0030_0000) Reserved GPA5RINI GPA4RINI GPA3RINI GPA2RINI GPA1RINI GPA0RINI CBOV CBORST CBODEN CIOINI Reserved Reserved LOCK DFEN Config0 Address = 0x0030_0000 Bits Description [31:28] Reserved Reserved. POWER-oN Pull Resistor Initial State Selection 00 = Pull-low Resistor enabled. [27:26] GPA5RINI 01 = Pull-high Resistor enabled.
Page 141 Mini57 Config0 Address = 0x0030_0000 Bits Description 01 = Pull-high Resistor Enabled. 1x = Pull-high/low Resistor Disabled. GPA0 is set as this state mode after power-on. Brown-out Voltage Selection Brown-out voltages are as follows: 000 = 2.0V. 001 = 2.2V. 010 = 2.4V.
Page 142 Mini57 Config0 Address = 0x0030_0000 Bits Description Data Flash Enabled DFEN 0 = Data Flash Enabled. 1 = Data Flash Disabled. Note: The reserved bits of user configuration should be kept as ‘1’. Apr. 06, 2017 Page 142 of 475 Rev.1.00...
Page 143 Mini57 Config1 (Address = 0x0030_0004) Reserved Reserved Reserved DFBA DFBA Config1 Address = 0x0030_0004 Bits Description [31:14] Reserved Reserved Data Flash Base Address [13:0] DFBA The Data Flash base address is defined by user. Since on chip Flash erase unit is 512 bytes, it is mandatory to keep bit 8-0 as 0.
Page 144: Figure 6.4-5 Boot Select (Bs) For Power-On Action
Mini57 6.4.4.5 Brown-out Detection The Mini57 series includes the brown-out detection function for monitoring the voltage on V pin. If V voltage falls below level setting CBOV, the BOD event will be triggered when BOD enabled. User can decide to use BOD reset by enable CBORST or just enable BOD interrupt by NVIC when BOD detected.
Page 145: Figure 6.4-6 Flash Memory Mapping Of Cbs In Config0
Mini57 be access by ISP commands. APROM is write-protected in this mode. Table 6.4-3 Boot Selection Run In LDROM Run In APROM Boot Vector Run In APROM Run In LDROM CBS[1:0] Write To Write To Write To LDROM Write To LDROM From Re-Map APROM...
Page 146: Figure 6.4-7 Executable Range Of Code With Iap Function Enabled
Mini57 6.4.4.7 In Application Programming The Mini57 series provides In-application-programming (IAP) function for user to switch the code executing between APROM and LDROM without reset. User can enable the IAP function by re- booting chip and setting the chip boot selection bits in Config0 (CBS[1:0]) as 10’b or 00’b. In the case that the chip boots from APROM with the IAP function enabled (CBS[1:0] = 10’b), the executable range of code includes all of APROM and LDROM.
Page 147: Figure 6.4-8 Example Flow Of Boot Selection By Bs Bit When Cbs[0] = 1
Mini57 6.4.4.8 In System Programming (ISP) The Mini57 series supports In-System-Programming which allows a device to be reprogrammed under software control and avoids system fail risk when download or programming fail. Furthermore, the capability to update the application firmware makes a wide range of applications possible.
Page 148 Mini57 Updating APROM by software in LDROM or updating LDROM by software in APROM can avoid a system failure when update fails. The ISP controller supports to read, erase and program embedded Flash memory. Several control bits of ISP controller are write-protected, thus it is necessary to unlock before we can set them.
Page 149: Figure 6.4-9 Isp Flow Example
Mini57 Start Enable ISPEN Write End of Flash ISPADDR/ ISPCMD/ Operation ISPDAT ? (Read ISPDAT) Set ISPGO = 1 & Check ISPFF = 1? Add ISP instruction End of ISP Operation Check ISPGO = 0 Stop Figure 6.4-9 ISP Flow Example Table 6.4-5 lists ISP commands supported by the Mini57 series.
Page 150: Register Map
Mini57 6.4.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value FMC Base Address: FMC_BA = 0x5000_C000 FMC_ISPCTL FMC_BA+0x00 ISP Control Register 0x0000_0000 FMC_ISPADDR FMC_BA+0x04 ISP Address Register 0x0000_0000 FMC_ISPDAT FMC_BA+0x08 ISP Data Register 0x0000_0000 FMC_ISPCMD...
Page 151: Register Description
Mini57 6.4.6 Register Description ISP Control Register (FMC_ISPCTL) Register Offset Description Reset Value FMC_ISPCTL FMC_BA+0x00 ISP Control Register 0x0000_0000 Reserved Reserved Reserved Reserved ISPFF LDUEN CFGUEN APUEN SPUEN ISPEN Bits Description [31:7] Reserved Reserved. ISP Fail Flag (Write Protect) This bit is set by hardware when a triggered ISP meets any of the following conditions: (1) APROM writes to itself if APUEN is set to 0.
Page 152 Mini57 Bits Description Boot Select (Write Protect) Set/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in CONFIG0 after any reset is happened except CPU reset (CPURF is 1) or system reset (SYSRF) is happened.
Page 153 Mini57 ISP Address (FMC_ISPADDR) Register Offset Description Reset Value FMC_ISPADD FMC_BA+0x04 ISP Address Register 0x0000_0000 ISPADR ISPADR ISPADR ISPADR Bits Description ISP Address ISPADR [31:0] The Mini57 series supports word program only. ISPADR[1:0] must be kept 00 for ISP operation. Apr.
Page 154 Mini57 FMC_ISPDAT (ISP Data Register) Register Offset Description Reset Value FMC_ISPDAT FMC_BA+0x08 ISP Data Register 0x0000_0000 ISPDAT ISPDAT ISPDAT ISPDAT Bits Description ISP Data [31:0] ISPDAT Write data to this register before ISP program operation. Read data from this register after ISP read operation. Apr.
Page 155 Mini57 ISP Command (FMC_ISPCMD) Register Offset Description Reset Value FMC_ISPCMD FMC_BA+0x0C ISP Command Register 0x0000_0000 Reserved Reserved Reserved Reserved Bits Description [31:6] Reserved Reserved. ISP Command ISP commands are shown below: 0x00 = Read. 0x04 = Read Unique ID. 0x0B = Read Company ID (0xDA). [5:0] 0x0D = Read CRC32 Checksum Result After Calculating.
Page 156 Mini57 ISP Trigger Control Register (FMC_ISPTRG) Register Offset Description Reset Value FMC_ISPTRG FMC_BA+0x10 ISP Trigger Register 0x0000_0000 Reserved Reserved Reserved Reserved ISPGO Bits Description [31:1] Reserved Reserved. ISP Start Trigger (Write Protect) Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
Page 157 Mini57 Data Flash Base Address Register (FMC_DFBA) Register Offset Description Reset Value FMC_DFBA FMC_BA+0x14 Data Flash Start Address 0x0000_3800 DFBA DFBA DFBA DFBA Bits Description Data Flash Base Address This register indicates Data Flash start address. It is a read only register. DFBA [31:0] The Data Flash start address is defined by user.
Page 158 Mini57 ISP Status Register (FMC_ISPSTS) Register Offset Description Reset Value FMC_ISPSTS FMC_BA+0x40 ISP Status Register 0xXXXX_XXXX SCODE Reserved Reserved VECMAP VECMAP Reserved Reserved ISPFF Reserved ISPBUSY Bits Description Security Code Active Flag This bit field set by hardware when detecting SPROM secured code is active at Flash initiation, or software writes 1 to this bit to make secured code active;...
Page 159 Mini57 ISP Start Trigger (Read Only) Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. ISPBUSY 0 = ISP operation is finished. 1 = ISP operation is progressed. Note: This bit is the same with FMC_ISPTRG bit 0.
Page 160 Mini57 ISP CRC Seed Register (FMC_CRCSEED) Register Offset Description Reset Value FMC_CRCSE FMC_BA+0x50 ISP CRC Seed Register 0xFFFF_FFFF CRCSEED CRCSEED CRCSEED CRCSEED Bits Description CRC Seed Data This register was provided to be the initial value for CRC operation. [31:0] CRCSEED Write data to this register before ISP CRC operation.
Page 161 Mini57 ISP CRC Current Value Register (FMC_CRCCV) Register Offset Description Reset Value FMC_CRCCV FMC_BA+0x54 ISP CRC Current Value Register 0xXXXX_XXXX CRCCV CRCCV CRCCV CRCCV Bits Description CRC Current Value [31:0] CRCCV This register provided current value of CRC durning calculation. Apr.
Page 162: General Purpose I/O (Gpio)
Mini57 6.5 General Purpose I/O (GPIO) 6.5.1 Overview The Mini57 series has up to 22 General Purpose I/O pins. These pins could be shared with other functions depending on the chip configuration. 22 pins are arranged in 4 ports named as PA, PB, PC, and PD.
Page 163: Block Diagram
Mini57  I/O pin can be configured as interrupt source with edge/level setting  Supports High Drive and High Sink I/O mode  Supports software selectable slew rate control  Configurable default I/O mode of all pins after reset by CIOINI (CONFIG0[10]) setting ...
Page 164: Figure 6.5-3 Push-Pull Output
Mini57 6.5.5.1 Input Mode Set MODEn (Px_MODE[2n+1:2n]) to 00 as the Px.n pin is in Input mode and the I/O pin is in tri- state (high impedance) without output drive capability. The PIN (Px_PIN[n]) value reflects the status of the corresponding port pins. 6.5.5.2 Push-pull Output Mode Set MODEn (Px_MODE[2n+1:2n]) to 01 as the Px.n pin is in Push-pull Output mode and the I/O...
Page 165: Figure 6.5-4 Open-Drain Output
Mini57 Port Pin Port Pin Port Latch Data Port Latch Data Input Data Input Data Figure 6.5-4 Open-Drain Output 6.5.5.4 Quasi-bidirectional Mode Set MODEn (Px_MODE[2n+1:2n]) to 11 as the Px.n pin is in Quasi-bidirectional mode and the I/O pin supports digital output and input function at the same time but the source current is only up to hundreds uA.
Page 166: Gpio Interrupt And Wake-Up Function
Mini57 6.5.6 GPIO Interrupt and Wake-up Function Each GPIO pin can be set as chip interrupt source by setting correlative RHIEN (Px_INTEN[n+16])/ FLIEN (Px_INTEN[n]) bit and TYPE (Px_INTTYPE[n]). There are five types of interrupt conditions to be selected: low level trigger, high level trigger, falling edge trigger, rising edge trigger and both rising and falling edge trigger.
Page 167: Register Map
Mini57 6.5.7 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value GPIO Base Address: GPIO_BA = 0x5000_4000 PA_MODE GPIO_BA+0x000 PA I/O Mode Control 0x0000_0XXX PA_DINOFF GPIO_BA+0x004 PA Digital Input Path Disable Control 0x0000_0000 PA_DOUT GPIO_BA+0x008...
Page 168 Mini57 PB_PHEN GPIO_BA+0x070 PB Pull-High Control Register 0x0000_001F PC_MODE GPIO_BA+0x080 PC I/O Mode Control 0x0000_0XXX PC_DINOFF GPIO_BA+0x084 PC Digital Input Path Disable Control 0x0000_0000 PC_DOUT GPIO_BA+0x088 PC Data Output Value 0x0000_001F PC_DATMSK GPIO_BA+0x08C PC Data Output Write Mask 0x0000_0000 PC_PIN GPIO_BA+0x090 PC Pin Value 0x0000_00XX...
Page 169 Mini57 PBn_PDIO GPIO_BA+0x840+(0x04 * n) GPIO PB.n Pin Data Input/Output Register 0x0000_000X n=0,1..4 PCn_PDIO GPIO_BA+0x880+(0x04 * n) GPIO PC.n Pin Data Input/Output Register 0x0000_000X n=0,1..4 PDn_PDIO GPIO_BA+0x8C0+(0x04 * n) GPIO PD.n Pin Data Input/Output Register 0x0000_000X n=0,1..6 Apr. 06, 2017 Page 169 of 475 Rev.1.00...
Page 170: Register Description
Mini57 6.5.8 Register Description Port A-D I/O Mode Control (Px_MODE) Register Offset Description Reset Value PA_MODE GPIO_BA+0x000 PA I/O Mode Control 0x0000_0XXX PB_MODE GPIO_BA+0x040 PB I/O Mode Control 0x0000_0XXX PC_MODE GPIO_BA+0x080 PC I/O Mode Control 0x0000_0XXX PD_MODE GPIO_BA+0x0C0 PD I/O Mode Control 0x0000_00XX Reserved Reserved...
Page 171 Mini57 Port A-D Digital Input Path Disable Control (Px_DINOFF) Register Offset Description Reset Value PA_DINOFF GPIO_BA+0x004 PA Digital Input Path Disable Control 0x0000_0000 PB_DINOFF GPIO_BA+0x044 PB Digital Input Path Disable Control 0x0000_0000 PC_DINOFF GPIO_BA+0x084 PC Digital Input Path Disable Control 0x0000_0000 PD_DINOFF GPIO_BA+0x0C4...
Page 172 Mini57 Port A-D Data Output Value (Px_DOUT) Register Offset Description Reset Value PA_DOUT GPIO_BA+0x008 PA Data Output Value 0x0000_003F PB_DOUT GPIO_BA+0x048 PB Data Output Value 0x0000_001F PC_DOUT GPIO_BA+0x088 PC Data Output Value 0x0000_001F PD_DOUT GPIO_BA+0x0C8 PD Data Output Value 0x0000_007F Reserved Reserved Reserved...
Page 173 Mini57 Port A-D Data Output Write Mask (Px_DATMSK) Register Offset Description Reset Value PA_DATMSK GPIO_BA+0x00C PA Data Output Write Mask 0x0000_0000 PB_DATMSK GPIO_BA+0x04C PB Data Output Write Mask 0x0000_0000 PC_DATMSK GPIO_BA+0x08C PC Data Output Write Mask 0x0000_0000 PD_DATMSK GPIO_BA+0x0CC PD Data Output Write Mask 0x0000_0000 Reserved Reserved...
Page 174 Mini57 Port A-D Pin Value (Px_PIN) Register Offset Description Reset Value PA_PIN GPIO_BA+0x010 PA Pin Value 0x0000_00XX PB_PIN GPIO_BA+0x050 PB Pin Value 0x0000_00XX PC_PIN GPIO_BA+0x090 PC Pin Value 0x0000_00XX PD_PIN GPIO_BA+0x0D0 PD Pin Value 0x0000_00XX Reserved Reserved Reserved PINn Bits Description Reserved [31:8]...
Page 175 Mini57 Port A-D De-bounce Enable Control Register (Px_DBEN) Register Offset Description Reset Value PA_DBEN GPIO_BA+0x014 PA De-Bounce Enable Control Register 0x0000_0000 PB_DBEN GPIO_BA+0x054 PB De-Bounce Enable Control Register 0x0000_0000 PC_DBEN GPIO_BA+0x094 PC De-Bounce Enable Control Register 0x0000_0000 PD_DBEN GPIO_BA+0x0D4 PD De-Bounce Enable Control Register 0x0000_0000 Reserved Reserved...
Page 176 Mini57 Port A-D Interrupt Type Control (Px_INTTYPE) Register Offset Description Reset Value PA_INTTYPE GPIO_BA+0x018 PA Interrupt Trigger Type Control 0x0000_0000 PB_INTTYPE GPIO_BA+0x058 PB Interrupt Trigger Type Control 0x0000_0000 PC_INTTYPE GPIO_BA+0x098 PC Interrupt Trigger Type Control 0x0000_0000 PD_INTTYPE GPIO_BA+0x0D8 PD Interrupt Trigger Type Control 0x0000_0000 Reserved Reserved...
Page 177 Mini57 Port A-D Interrupt Enable Control Register (Px_INTEN) Register Offset Description Reset Value PA_INTEN GPIO_BA+0x01C PA Interrupt Enable Control Register 0x0000_0000 PB_INTEN GPIO_BA+0x05C PB Interrupt Enable Control Register 0x0000_0000 PC_INTEN GPIO_BA+0x09C PC Interrupt Enable Control Register 0x0000_0000 PD_INTEN GPIO_BA+0x0DC PD Interrupt Enable Control Register 0x0000_0000 Reserved RHIENn...
Page 178 Mini57 If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 0 = Px.n level low or high to low interrupt Disabled. 1 = Px.n level low or high to low interrupt Enabled.
Page 179 Mini57 Port A-D Interrupt Source Flag (Px_INTSRC) Register Offset Description Reset Value PA_INTSRC GPIO_BA+0x020 PA Interrupt Source Flag 0x0000_00XX PB_INTSRC GPIO_BA+0x060 PB Interrupt Source Flag 0x0000_00XX PC_INTSRC GPIO_BA+0x0A0 PC Interrupt Source Flag 0x0000_00XX PD_INTSRC GPIO_BA+0x0E0 PD Interrupt Source Flag 0x0000_00XX Reserved Reserved Reserved...
Page 180 Mini57 Port A-D Input Schmitt Trigger Enable Register (Px_SMTEN) Register Offset Description Reset Value PA_SMTEN GPIO_BA+0x024 PA Input Schmitt Trigger Enable Register 0x0000_0000 PB_SMTEN GPIO_BA+0x064 PB Input Schmitt Trigger Enable Register 0x0000_0000 PC_SMTEN GPIO_BA+0x0A4 PC Input Schmitt Trigger Enable Register 0x0000_0000 PD_SMTEN GPIO_BA+0x0E4...
Page 181 Mini57 Port A-D High Slew Rate Control Register (Px_SLEWCTL) Register Offset Description Reset Value PA_SLEWCTL GPIO_BA+0x028 PA High Slew Rate Control Register 0x0000_0000 PB_SLEWCTL GPIO_BA+0x068 PB High Slew Rate Control Register 0x0000_0000 PC_SLEWCTL GPIO_BA+0x0A8 PC High Slew Rate Control Register 0x0000_0000 PD_SLEWCTL GPIO_BA+0x0E8 PD High Slew Rate Control Register...
Page 182 Mini57 Port Pull-low Resistor Control Register (Px_PLEN) Register Offset Description Reset Value PA_PLEN GPIO_BA+0x02C PA Pull-Low Control Register 0x0000_0000 PB_PLEN GPIO_BA+0x06C PB Pull-Low Control Register 0x0000_0000 PC_PLEN GPIO_BA+0x0AC PC Pull-Low Control Register 0x0000_0000 PD_PLEN GPIO_BA+0x0EC PD Pull-Low Control Register 0x0000_0000 Reserved Reserved Reserved...
Page 183 Mini57 Port Pull High Resistor Control Register (Px_PHEN) Register Offset Description Reset Value PA_PHEN GPIO_BA+0x030 PA Pull-High Control Register 0x0000_003F PB_PHEN GPIO_BA+0x070 PB Pull-High Control Register 0x0000_001F PC_PHEN GPIO_BA+0x0B0 PC Pull-High Control Register 0x0000_001F PD_PHEN GPIO_BA+0x0F0 PD Pull-High Control Register 0x0000_007F Reserved Reserved...
Page 184 Mini57 Interrupt De-bounce Control Register (GPIO_DBCTL) Register Offset Description Reset Value GPIO_DBCTL GPIO_BA+0x440 Interrupt De-bounce Control Register 0x0000_0020 Reserved Reserved Reserved Reserved ICLKON DBCLKSRC DBCLKSEL Bits Description [31:6] Reserved Reserved. Interrupt Clock on Mode 0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1.
Page 185 Mini57 Bits Description De-bounce Sampling Cycle Selection 0000 = Sample interrupt input once per 1 clocks. 0001 = Sample interrupt input once per 2 clocks. 0010 = Sample interrupt input once per 4 clocks. 0011 = Sample interrupt input once per 8 clocks. 0100 = Sample interrupt input once per 16 clocks.
Page 186 Mini57 GPIO Px.n Pin Data Input/Outut Register (Pxn_PDIO) Register Offset Description Reset Value PAn_PDIO GPIO_BA+0x800+(0x04 * n) GPIO PA.n Pin Data Input/Output Register 0x0000_000X n=0,1..5 PBn_PDIO GPIO_BA+0x840+(0x04 * n) GPIO PB.n Pin Data Input/Output Register 0x0000_000X n=0,1..4 PCn_PDIO GPIO_BA+0x880+(0x04 * n) GPIO PC.n Pin Data Input/Output Register 0x0000_000X n=0,1..4...
Page 187: Timer Controller (Timer)
Mini57 6.6 Timer Controller (TIMER) 6.6.1 Overview The Timer Controller includes two 32-bit timers, TIMER0 ~ TIMER1, allowing user to easily implement a timer control for applications. The timer can perform functions, such as frequency measurement, delay timing, clock generation, and event counting by external input pins, and interval measurement by external capture pins.
Page 188: Block Diagram
Mini57 6.6.3 Block Diagram Each channel is equipped with an 8-bit pre-scale counter, a 24-bit up-timer, a 24-bit compare register and an interrupt request signal. Refer to Figure 6.6-1. There are five options of clock sources for each channel. Figure 6.6-2 illustrates the clock source control function. WKEN (TIMERx_CTL[23]) CMPDAT...
Page 189: Basic Configuration
Mini57 6.6.4 Basic Configuration The peripheral clock source of Tiimer0 ~ Timer1 can be enabled in TMRxCKEN (CLK_APBCLK[3:2]) and selected as different frequency in TMR0SEL (CLK_CLKSEL1[10:8]) for Timer0, TMR1SEL (CLK_CLKSEL1[14:12]) for Timer1. 6.6.5 Functional Description The timer controller provides One-shot, Period, Toggle and Continuous Counting operation modes.
Page 190: Figure 6.6-3 Continuous Counting Mode
Mini57 (TIMERX_CTL[30]) bit is set, the timer counter starts up counting. The counting operation of toggle-out mode is almost the same as periodic mode, except toggle-out mode has associated output pin to output signal while specify TIF bit is set. Thus, the toggle-output signal on output pin is changing back and forth with 50% duty cycle.
Page 191: Figure 6.6-4 Free-Counting Capture Mode
Mini57 less than 1/8 HCLK if TMx pin de-bounce enabled to assure the returned CNT value is incorrect, and software can also select edge detection phase of TMx pin by CNTPHASE (TIMERx_EXTCTL[0]) bit. In event counting mode, the timer counting operation mode can be selected as one-shot, periodic and continuous counting mode to counts the CNT value by input event from TMx pin.
Page 192: Figure 6.6-5 External Reset Counter Mode
Mini57 select ACMPOx (x= 0~1) transition is using to trigger reset counter value. The operation method is also described in Table 6.6-1. TIMERx_CNT ACMPOx (CAPEDGE=0x02) Clear by software CAPIF Figure 6.6-5 External Reset Counter Mode 6.6.5.11 Trigger-Counting Capture Mode If CAPMODE (TIMERx_EXTCTL[8]) is set to 1, CAPEN (TIMERx_EXTCTL[3]) is set to 1 and CAPFUNCS (TIMERx_EXTCTL[4]) is set to 0, the CNT will be reset to 0 then captured into CAPDAT register when ACMPOx (x= 0~1) trigger condition occurred.
Page 193: Table 6.6-1 Input Capture Mode Operation
Mini57 pin is detected to reset CNT as 0 and then starts counting, while the 2nd 1 to 0 transition stops counting. Rising Edge Trigger: The 1st 0 to 1 transition to on ACMPOx (x= 0~1) pin is detected to reset CNT as 0 and then starts counting, while the 2nd 0 to 1 transition stops counting.
Page 194: Figure 6.6-6 Continuous Capture Mode Block
Mini57 24-bit TM0/TM1 CNTSEL Counter Latch timer CCAPEN counter TIMER_CCAP0 CAPR1F Input Capture TIMER_CCAP1 CAPF1F PD.2 Signal 2-to-1 PC.2 Mux. TIMER_CCAP2 CAPR2F CAPF2F TIMER_CCAP3 CAPCHSEL Figure 6.6-6 Continuous Capture Mode Block Apr. 06, 2017 Page 194 of 475 Rev.1.00...
Page 195: Figure 6.6-7 Continuous Capture Mode Behavior
Mini57 CCAPEN Input Signal H/W clears 'CCAPEN' bit S/W sets 'CCAPEN' bit H/W loads Timer0/1's counter value into 'TIMER_CCAP3' register at the 2nd falling edge and set CAPF2F to 1. H/W loads Timer0/1's counter value into 'TIMER_CCAP2' register at the 2nd rising-edge and set CAPR2F to 1. H/W loads Timer0/1's counter value into 'TIMER_CCAP1' register at the 1st falling edge and set CAPF1F to 1.
Page 196: Register Map
Mini57 6.6.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value TMR Base Address TMR_BA = 0x4001_0000 TIMER0_CTL TMR_BA+0x00 Timer0 Control and Status Register 0x0000_0005 TIMER0_CMP TMR_BA+0x04 Timer0 Compare Register 0x0000_0000 TIMER0_INTSTS TMR_BA+0x08 Timer0 Interrupt Status Register...
Page 197: Register Description
Mini57 6.6.7 Register Description Timer Control Register (TIMERx_CTL) Register Offset Description Reset Value TIMER0_CTL TMR_BA+0x00 Timer0 Control and Status Register 0x0000_0005 TIMER1_CTL TMR_BA+0x20 Timer1 Control and Status Register 0x0000_0005 ICEDEBUG CNTEN INTEN OPMODE RSTCNT ACTSTS EXTCNTEN WKEN Reserved CMPCTL CNTDATEN Reserved Bits Description...
Page 198 Mini57 Bits Description 11 = The timer is operating in Continuous Counting mode. The associated interrupt signal is generated when TIMERx_CNT = TIMERx_CMP (if INTEN is enabled). However, the 24-bit up-timer counts continuously. Please refer to 6.12.5.2 for detailed description about Continuous Counting mode operation.
Page 199 Mini57 Timer Compare Register (TIMERx_CMP) Register Offset Description Reset Value TIMER0_CMP TMR_BA+0x04 Timer0 Compare Register 0x0000_0000 TIMER1_CMP TMR_BA+0x24 Timer1 Compare Register 0x0000_0000 Reserved CMPDAT CMPDAT CMPDAT Bits Description [31:24] Reserved Reserved. Timer Compared Value CMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF flag will set to 1.
Page 200 Mini57 Timer Interrupt Status Register (TIMERx_INTSTS) Register Offset Description Reset Value TIMER0_INTST TMR_BA+0x08 Timer0 Interrupt Status Register 0x0000_0000 TIMER1_INTST TMR_BA+0x28 Timer1 Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved Reserved TWKF Bits Description [31:2] Reserved Reserved. Timer Wake-up Flag This bit indicates the interrupt wake-up flag status of Timer. 0 = Timer does not cause chip wake-up.
Page 201 Mini57 Timer Data Register (TIMERx_CNT) Register Offset Description Reset Value TIMER0_CNT TMR_BA+0x0C Timer0 Data Register 0x0000_0000 TIMER1_CNT TMR_BA+0x2C Timer1 Data Register 0x0000_0000 Reserved Bits Description [31:24] Reserved Reserved. Timer Data Register [23:0] If CNTDATEN is set to 1, CNT register value will be updated continuously to monitor 24- bit up counter value.
Page 202 Mini57 Timer Capture Data Register (TIMERx_CAP) Register Offset Description Reset Value TIMER0_CAP TMR_BA+0x10 Timer0 Capture Data Register 0x0000_0000 TIMER1_CAP TMR_BA+0x30 Timer1 Capture Data Register 0x0000_0000 Reserved CAPDAT CAPDAT CAPDAT Bits Description [31:24] Reserved Reserved. Timer Capture Data Register When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is [23:0] CAPDAT 0, and a transition on ACMPOx matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting,...
Page 203 Mini57 Timer Extended Event Control Register (TIMERx_EXTCTL) Register Offset Description Reset Value TIMER0_EXTCTL TMR_BA+0x14 Timer0 Extended Event Control Register 0x0000_0000 TIMER1_EXTCTL TMR_BA+0x34 Timer1 Extended Event Control Register 0x0000_0000 Reserved Reserved Reserved CAPMODE ECNTDBEN Reserved CAPIEN CAPFUNCS CAPEN CAPEDGE CNTPHASE Bits Description [31:9] Reserved...
Page 204 Mini57 Bits Description Timer Capture Function Enable Bit This bit enables the Timer Capture Function CAPEN 0 = Timer Capture Function Disabled. 1 = Timer Capture Function Enabled. Timer Capture Pin Edge Detection 00 = A falling edge on ACMPOx will be detected. [2:1] CAPEDGE 01 = A rising edge on ACMPOx will be detected.
Page 205 Mini57 Timer Extended Event Interrupt Status Register (TIMERx_EINTSTS) Register Offset Description Reset Value TIMER0_EINT Timer0 Extended Event Interrupt Status TMR_BA+0x18 0x0000_0000 Register TIMER1_EINT Timer1 Extended Event Interrupt Status TMR_BA+0x38 0x0000_0000 Register Reserved Reserved Reserved Reserved CAPIF Bits Description [31:1] Reserved Reserved.
Page 206 Mini57 Timer Continuous Capture Control Register (TIMER_CCAPCTL) Register Offset Description Reset Value TIMER_CCAPCTL TMR_BA+0x40 Timer Continuous Capture Control Register 0x0000_0000 Reserved Reserved CCAPIEN Reserved CAPF2F CAPR2F CAPF1F CAPR1F Reserved CAPCHSEL CNTSEL CCAPEN Bits Description [31:18] Reserved Reserved. Capture Interrupt Enable Bit 00 = Interrupt Disabled.
Page 207 Mini57 Bits Description Capture Rising Edge 1 Flag First rising edge already captured, this bit will be set to 1. CAPR1F 0 = None. 1 = CAPDAT(TIMER_CCAP0[23:0]) data is ready for read. Note: This bit is cleared by hardware automatically when writing 1 to this bit. [7:5] Reserved Reserved.
Page 208 Mini57 Timer Continuous Capture Register 0-3 (TIMER_CCAP0-3) Register Offset Description Reset Value TIMER_CCAP0 TMR_BA+0x44 Timer Continuous Capture Data Register 0 0x0000_0000 TIMER_CCAP1 TMR_BA+0x48 Timer Continuous Capture Data Register 1 0x0000_0000 TIMER_CCAP2 TMR_BA+0x4C Timer Continuous Capture Data Register 2 0x0000_0000 TIMER_CCAP3 TMR_BA+0x50 Timer Continuous Capture Data Register 3 0x0000_0000 Reserved...
Page 209: Enhanced Input Capture Timer (Ecap)
Mini57 6.7 Enhanced Input Capture Timer (ECAP) 6.7.1 Overview This device provides an Input Capture Timer/Counter whose capture function can detect the digital edge-changed signal at channel inputs. This unit has three input capture channels. The timer/counter is equipped with up counting, reload and compare-match capabilities. 6.7.2 Features ...
Page 210: Input Noise Filter
Mini57 ECAPCKEN (CLK_APBCLK[8]) ECAP_CLK HCLK Figure 6.7-2 Enhanced Input Capture Timer/Counter Clock Source Control Figure 6.7-1 illustrates the architecture of the Input Capture. This input capture timer/counter unit supports 3 input channels with programmable input signal sources. The port pins ECAP_P0 to ECAP_P2 can be fed to the inputs of capture unit through noise filter or bypass it (CAPNFDIS = 1).
Page 211: Operation Of Input Capture Timer/Counter
Mini57 6.7.5 Operation of Input Capture Timer/Counter The Input Capture Timer/Counter unit consists of 2 main functional blocks, Capture block and Operation block. There are 3 Input Capture units in Capture block for 3 input channel. The capture units function as detecting and measuring the pulse width and the period of a square wave.
Page 212: Figure 6.7-5 Enhanced Input Capture Timer/Counter Functions Block
Mini57 ECAP_HLD0 ECAP_HLD1 ECAP_HLD2 CAPEDG0 CAPEDG1 CAPEDG2 Capture Unit 0 Block [00] Capture Capture CAPTF0 Unit 1 Block Unit 2 Block CAP0 [01] [1x] CAP1 CAP2 CAPTF0 CAPTF1 CAPTF2 CPTCLR CMPCLR Clear CAPTF0 ECAP_CNT CAPTF1 CNTSRC CAPTF2 CAP2 DIV by 24-bit up counter CAP1 1, 4, 16, 32,...
Page 213: Input Capture Timer/Counter Interrupt Architecture
Mini57 6.7.5.3 Reload Mode The Input Capture Timer/Counter can also be configured for reload mode. The reload function is enabled by setting RLDEN (ECAP_CTL0[27]) to 1. In this mode, ECAP_CNTCMP serves as a reload register. A reload event is generated and causes the content of the ECAP_CNTCMP register to be loaded into the ECAP_CNT register when ECAP_CNT overflows, CAPTF2, CAPTF1 or CAPTF0 setting by configuring the CPRLDS (ECAP_CTL1[10:8]).
Page 214: Register Map
Mini57 6.7.7 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value ECAP Base Address: ECAP_BA = 0x401B_0000 ECAP_CNT ECAP_BA+0x00 Input Capture Counter 0x0000_0000 ECAP_HLD0 ECAP_BA+0x04 Input Capture Counter Hold Register 0 0x0000_0000 ECAP_HLD1 ECAP_BA+0x08...
Page 215: Register Description
Mini57 6.7.8 Register Description Input Capture Counter (ECAP_CNT) Register Offset Description Reset Value ECAP_CNT ECAP_BA+0x00 Input Capture Counter 0x0000_0000 Reserved Bits Description [31:24] Reserved Reserved. Input Capture Timer/Counter [23:0] The input Capture Timer/Counter is a 24-bit up-counting counter. The clock source for the counter is from thme clock divider.
Page 216 Mini57 Input Capture Counter Hold Register 0-2 (ECAP_HLD0-2) Register Offset Description Reset Value ECAP_HLD0 ECAP_BA+0x04 Input Capture Counter Hold Register 0 0x0000_0000 ECAP_HLD1 ECAP_BA+0x08 Input Capture Counter Hold Register 1 0x0000_0000 ECAP_HLD2 ECAP_BA+0x0C Input Capture Counter Hold Register 2 0x0000_0000 Reserved HOLD HOLD...
Page 217 Mini57 Input Capture Counter Compare Register (ECAP_CNTCMP) Register Offset Description Reset Value ECAP_CNTCMP ECAP_BA+0x10 Input Capture Counter Compare Register 0x0000_0000 Reserved CNTCMP CNTCMP CNTCMP Bits Description [31:24] Reserved Reserved. Input Capture Counter Compare Register If the compare function is enabled (CMPEN = 1), t this register (ECAP_CNTCMP) is used to [23:0] CNTCMP compare with the capture counter (ECAP_CNT).
Page 218 Mini57 Input Capture Timer/Counter Control Register (ECAP_CTL0) Register Offset Description Reset Value ECAP_CTL0 ECAP_BA+0x14 Input Capture Control Register 0 0x0000_0000 Reserved CAPPHGEN CAPEN CMPEN RLDEN CPTCLR CMPCLR CPTST Reserved CAPCMPIEN CAPOVIEN Reserved CAPTF2IEN CAPTF1IEN CAPTF0IEN Reserved CAPSEL2 CAPSEL1 CAPSEL0 Reserved IC2EN IC1EN IC0EN...
Page 219 Mini57 Bits Description Input Capture Counter Clear by Compare-match Control If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to 0 when the compare-match event (CAPCMPF = 1) occurs. [25] CMPCLR 0 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Disabled. 1 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Enabled.
Page 220 Mini57 Bits Description CAP0 Input Source Selection 00 = CAP0 input is from port pin ECAP_P0. CAPSEL0 01 = CAP0 input is from signal ACMP0_O (Analog comparator 0 output). [9:8] 10 = CAP0 input is from signal ACMP1_O (Analog comparator 1 output). 11 = CAP0 input is from signal ADC_CPR (ADC compare output).
Page 221 Mini57 Input Capture Timer/Counter Control Register (ECAP_CTL1) Register Offset Description Reset Value ECAP_CTL1 ECAP_BA+0x18 Input Capture Control Register 1 0x0000_0000 Reserved Reserved CNTSRC Reserved CAPDIV Reserved CPRLDS Reserved CAPEDG2 CAPEDG1 CAPEDG0 Bits Description [31:18] Reserved Reserved. Capture Timer/Counter Clock Source Selection Select the capture timer/counter clock source 00 = ECAP_CLK (Default).
Page 222 Mini57 Bits Description ECAP_CNT Reload Trigger Source Selection If the reload function is enabled (RLDEN = 1), when a reload trigger event comes, the ECAP_CNT is reloaded with ECAP_CNTCMP. CPRLDS[2:0] determines the ECAP_CNT reload trigger source 000 = CAPTF0. [10:8] CPRLDS 001 = CAPTF1.
Page 223 Mini57 Input Capture Timer/Counter Status Register (ECAP_STS) Register Offset Description Reset Value ECAP_STS ECAP_BA+0x1C Input Capture Status Register 0x0000_0000 Reserved Reserved Reserved CAP2 CAP1 CAP0 Reserved CAPOVF CAPCMPF Reserved CAPTF2 CAPTF1 CAPTF0 Bits Description [31:11] Reserved Reserved. Input Capture Pin 2 Status (Read Only) CAP2 [10] Input capture pin 2 (ECAP_P2) status.
Page 224 Mini57 Bits Description Input Capture Channel 2 Captured Flag When the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high. CAPTF2 0 = No valid edge change has been detected at CAP2 input since last clear. 1 = At least a valid edge change has been detected at CAP2 input since last clear.
Page 225: Enhanced Pwm Generator (Epwm)
Mini57 6.8 Enhanced PWM Generator (EPWM) 6.8.1 Overview The Mini57 series has built in one PWM unit which is specially designed for motor driving control applications. The PWM unit supports six PWM generators which can be configured as six independent PWM outputs, PWM0~PWM5, or as three complementary PWM pairs, (PWM0, PWM1), (PWM2, PWM3) and (PWM4, PWM5) with three programmable dead-zone generators.
Page 226: Block Diagram
Mini57  fault brake source:  BRK0: ACMP0, ACMP1, EADC and External pin (BRAKE).  BRK1: ACMP0, ACMP1, EADC and External pin (BRAKE).  The PWM signals before polarity control stage are defined in the view of positive logic. The PWM ports is active high or active low are controlled by polarity control register.
Page 227: Figure 6.8-2 Epwm Block Diagram
Mini57 Figure 6.8-2 EPWM Block Diagram Figure 6.8-3 illustrates the architecture of PWM in pair (e.g. PWM-Timer 0/1 are in one pair and PWM- Timer 2/3 are in another one, and PWM-Timer 4/5 are in one pair.). DTCNT01 (EPWM_DTCTL[7:0]) 0000 EPWM_CH0 signal 0001 (from ECAP)
Page 228: Basic Configuration
Mini57 DTCNT45 (EPWM_DTCTL[23:16]) 0000 0001 (from ECAP) EPWM_CH4 signal Dead-Zone 0010 CAP2_PCHG Generator 45 EPWM_CH5 signal to ADC 0011 CAP1_PCHG HCLK PWM_CLK 1/16 PWM clock 0100 CAP0_PCHG Generator 1/32 0101 1/64 DTCNT45 0110 EPWM_INTSTS (EPWM_CTL[26]) PA4MFP 1/128 0111 EPWM_INTEN (SYS_GPA_MFP[19:16]) 1/256 1000 GPIO Output...
Page 229: Figure 6.8-6 Epwm Edge-Aligned Waveform Output
Mini57 at this moment, it toggles the EPWM_CHn generator output to low and CMPDATn (new) and PERIOD (new) are updated with CNTMODE=1 and requests the PWM interrupt if PWM interrupt is enabled (EPWM_INTEN). Figure 6.8-6 shows the Edge-aligned PWM timing and operation flow. If 16-bit down counter underflow 1.
Page 230: Figure 6.8-7 Epwm Edge-Aligned Mode Operation Timing
Mini57 Edge Aligned mode : Period = (PERIOD + 1) * clock cycle Duty ratio = CMPDAT / (PERIOD + 1) CMRDAT > PERIOD --> always High CMRDAT = 0 --> always Low Edge Aligned mode PERIOD = 99 Period = PERIOD + 1 = 99 + 1 = 100 period CMRDAT=0 CMRDAT=1...
Page 231: Figure 6.8-8 Epwm Edge-Aligned Interrupt Diagram
Mini57 PWM_PERIOD 16-bit PWM counter PWM_CMPDATn PWM period generator ouput CMPDIENn/ PIEN/ (n:0~5) CMPDIFn Figure 6.8-8 EPWM Edge-aligned Interrupt Diagram Apr. 06, 2017 Page 231 of 475 Rev.1.00...
Page 232: Figure 6.8-9 Epwm Edge-Aligned Flow Diagram
Mini57 Set GPA_MFP, PA_MODE, APBCLK[20] = 1 Set EPWM_CTL[31] = 0 (Edge-Aligned type) Set CLKDIV, CTL, PERIOD,CMPDATn Set INTEN Start: Set CNTENn = 1 Set CNTCLR = 1 H/w will load CMPDATn and PERIOD to working registers. Down-counting start from PERIOD. PWMn output: 0 if counter >...
Page 233: Figure 6.8-10 Epwm Legend Of Internal Comparator Output Of Pwm-Timer
Mini57 The EPWM period and duty control are decided by PWM down-counter register (PERIOD) and PWM comparator register (CMPDATn). The PWM-Timer timing operation is shown in Figure 6.8-11 EPWM-Timer Operation Timing. The pulse width modulation follows the formula below and the legend of PWM-Timer Comparator is shown in Figure 6.8-10 EPWM Legend of Internal Comparator Output of PWM-Timer.
Page 234: Figure 6.8-12 Epwm Center-Aligned Type
Mini57 The center-aligned PWM signals are produced by the module when the PWM time base is configured in an Down/Up Counting mode. The PWM counter first state is Down-counter mode which it will start from PERIOD plus one value and decrase to match the value of CMPDATn (old); this will cause the toggling of the EPWM_CHn generator output to high.
Page 235: Figure 6.8-13 Epwm Center-Aligned Mode Operation Timing
Mini57 Central Aligned mode : Period = 2* (PERIOD + 1) * clock cycle Duty ratio = 2* (CMRDAT / (PERIOD + 1)) CMRDAT > PERIOD --> always High CMRDAT = 0 --> always Low Central Aligned mode PERIOD = 99 Period = 2 * (PERIOD + 1) = 2* (99 + 1) = 200 central period...
Page 236: Figure 6.8-14 Epwm Center-Aligned Waveform Output
Mini57 PERIOD (7FF) CMPDATn(3FF) s/w clear s/w clear s/w clear s/w clear s/w clear PWMn generator ouput PWM Period PWM Period Figure 6.8-14 EPWM Center-aligned Waveform Output PWM_PERIODn 16-bit PWM counter PWM_CMPDATn PWM period generator ouput CIEN/ CMPUIENn/ CMPDIENn/ PIEN/ (n:0~5) CMPDIFn CMPUIFn...
Page 237: Figure 6.8-16 Epwm Center-Aligned Flow Diagram
Mini57 Set GPA_MFP, PA_MODE, APBCLK[20] = 1 Set EPWM_CTL[31] = 1 (Central-Aligned type) Set CLKDIV, CTL, PERIOD, CMPDATn Set INTEN Start: Set CNTENn= 1 Set CNTCLR= 1 H/W will load CMPDATn and PERIOD to working registers. Down-counting start from (PERIOD + 1) value. PWMn output: 0 if counter >...
Page 238 Mini57 6.8.5.2 EPWM Port Output Control EPWM unit has six output pins in this device. The PWM port outputs are PA.0~PA.5. The driving type of PWM output ports can be initialized as Tri-state type or other types depending on the PA_MODE register setting after any reset, as shown in Figure 6.8-10. 6.8.5.3 Independent Mode The EPWM is set as independent mode when MODE (EPWM_CTL[29:28]) = 00, there are six...
Page 239: Figure 6.8-17 Epwm Dead-Time Insertion
Mini57 EPWM0_CH0 without dead-time EPWM0_CH1 without dead-time EPWM0_CH0 with dead-time EPWM0_CH1 with dead-time Dead-time Interval Effect of dead-time for complementary pairs Figure 6.8-17 EPWM Dead-time Insertion 6.8.5.7 Group Mode Group mode is enabled when GROUPEN (EPWM_CTL[30]) = 1. This device supports Group mode control which allows all even PWM channels output to be duty controllable by EPWM_CH0 duty register.
Page 240: Figure 6.8-18 Epwm Asymmetric Mode Timing Diagram
Mini57 Figure 6.8-18 EPWM Asymmetric Mode Timing Diagram 6.8.5.9 One-Shot Mode The EPWM set as one-shot mode when CNTMODE (EPWM_CTL[8]) = 0. The EPWM output one pulse in one period when EPWM start run is set. Figure 6.8-19 shows one-shot mode status. period period CMRDAT = 0...
Page 241: Figure 6.8-20 Epwm Initial State And Polarity Control With Rising Edge Dead-Time Insertion
Mini57 Original waveform without Dead-time Initial State PWM Starts and ploarity control PWM_CH0 PWM_CH1 (NEGPOLAR0=0) PWM_CH0 (NEGPOLAR1=0) PWM_CH1 PWM_CH0 (NEGPOLAR0=0) PWM_CH1 (NEGPOLAR1=1) NEGPOLARn: Negative Polarity control bits; It controls the PWM output initial state and polarity Dead-time insertion; It is only effective in complementary mode Figure 6.8-20 EPWM Initial State and Polarity Control with Rising Edge Dead-time Insertion 6.8.5.11 Interrupt Architecture There are sixteen interrupt sources for EPWM unit, which are PIF (EPWM_INTSTS[0]) PWM...
Page 242: Figure 6.8-21 Epwm Interrupt Architecture
Mini57 CMPUIF0 (EPWM_INTSTS[8]) CMPUIEN0 (EPWM_INTEN[8]) CMPDIF0 (EPWM_INTSTS[24]) CMPDIEN0 (EPWM_INTEN[24]) CMPUIF1 (EPWM_INTSTS[9]) CMPUIEN1 (EPWM_INTEN[9]) CMPDIF1 (EPWM_INTSTS[25]) CMPDIEN1 (EPWM_INTEN[25]) CMPUIF2 (EPWM_INTSTS[10]) CMPUIEN2 (EPWM_INTEN[10]) CMPDIF2 (EPWM_INTSTS[26]) CMPDIEN2 (EPWM_INTEN[26]) IFAEN EPWM_IFA[0] CMPUIF3 (EPWM_INTSTS[11]) CMPUIEN3 (EPWM_INTEN[11]) CMPDIF3 IFCNT (EPWM_INTSTS[27]) CMPDIEN3 EPWM_INT (EPWM_INTEN[27]) CMPUIF4 (EPWM_INTSTS[12]) CMPUIEN4 (EPWM_INTEN[12]) CMPDIF4 (EPWM_INTSTS[28])
Page 243: Figure 6.8-22 Epwm Brake Architecture
Mini57 ACMP0_PBRK BK0A0EN BKODn (n:0~5) (EPWM_BRKCTL[2]) (EPWM_BRKCTL[29:24]) EPWM Output 0~5 ACMP1_PBRK EPWM_CHn Output BK0A1EN (EPWM_BRKCTL[3]) BRK0IF *NED BRAKE0_INT ADC_PBRK EPWM_INTSTS[16] BRK0IEN BK0ADCEN *NED : Negative Edge Detection (EPWM_INTEN[16]) (EWPM_BRKCTL[4]) BRAKE Noise Filter /PC.2 BRK0EN BK0PEN (EPWM_BRKCTL[0]) (EPWM_BRLCTL[5]) SWBRK NFPEN (EPWM_BRKCTL[9]) (EPWM_BRKCTL[31]) BRK1IF *NED...
Page 244: Figure 6.8-23 Epwm 3-Phase Motor Mask Diagram
Mini57 cycle comparison units. MSKENn register contains bits, MSKEN[5:0] (EPWM_PHCHG[13:8] / EPWM_PHCHGNXT[13:8]) determine which PWM I/O pins will be overridden. On reset MSKENn is 00H. The MSKDATn register contains six bits, MSKDAT[5:0] (EPWM_PHCHG[5:0] / EPWM_PHCHGNXT[5:0]) determine the state of the PWM I/O pins when a particular output is masked via the MSKDATn bits.
Page 245: Figure 6.8-24 Epwm 3-Phase Motor Mask Example 1
Mini57 MSKENn MSKDATn PWM0 PWM2MD PWM4MD PWM1MD PWM3MD PWM5MD Current path = (0,3) Figure 6.8-24 EPWM 3-phase Motor Mask Example 1 For example 2, Motor activating path is path 2 connects path 5, and path 2 is used as EPWM2 and path 5 is ON (short).
Page 246 Mini57 1.1.1.1.2 EPWM Phase Change Hall_State Sensor Mode The EPWM can also direct check Hall sensor state to change motor phase. When TRGSEL = 011b (EPWM_PHCHGNXT[22:20]) trigger by next Hall state, the Phase-Change controller will check CAPn_PCHG (n:0,2) status. If matched HALLSTS (EPWM_PHCHGNXT[18:16]) setting value then EPWM output data can be copied to EPWM_PHCHG from EPWM_PHCHGNEXT and change status of MOTOR simultaneously.
Page 247: Register Map
Mini57 6.8.6 Register Map R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written Register Offset Description Reset Value EPWM Base Address: EPWM_BA = 0x4004_0000 EPWM_NPCTL EPWM_BA+0x00 EPWM Negative Polarity Control Register 0x0000_0000 EPWM_CLKDIV EPWM_BA+0x04...
Page 248: Register Description
Mini57 6.8.7 Register Description EPWM Negative Polarity Control Register (EPWM_NPCTL) Register Offset R/W Description Reset Value EPWM_NPCTL EPWM_BA+0x00 R/W EPWM Negative Polarity Control Register 0x0000_0000 Reserved Reserved Reserved Reserved NEGPOLAR5 NEGPOLAR4 NEGPOLAR3 NEGPOLAR2 NEGPOLAR1 NEGPOLAR0 Bits Description [31:6] Reserved Reserved. PWM5 Negative Polarity Control The register bit controls polarity/active state of real PWM output.
Page 249 Mini57 Bits Description PWM0 Negative Polarity Control The register bit controls polarity/active state of real PWM output. NEGPOLAR0 0 = PWM output is active high. 1 = PWM output is active low. Apr. 06, 2017 Page 249 of 475 Rev.1.00...
Page 250 Mini57 EPWM Clock Selector Register (EPWM_CLKDIV) Register Offset Description Reset Value EPWM_CLKDI EPWM_BA+0x04 EPWM Clock Select Register 0x0000_0000 Reserved Reserved Reserved Reserved CLKDIV Bits Description [31:4] Reserved Reserved. EPWM Clock Divider (9 Step Divider) Select clock input for PWM timer 0000 = 1 (HCLK / 2^0).
Page 251 Mini57 EPWM Control Register (EPWM_CTL) Register Offset Description Reset Value EPWM_CTL EPWM_BA+0x08 EPWM Control Register 0x0000_0000 CNTTYPE GROUPEN MODE CNTCLR DTCNT45 DTCNT23 DTCNT01 DBGTRIOFF Reserved ASYMEN Reserved HCUPDT Reserved CNTMODE Reserved CNTEN5 CNTEN4 CNTEN3 CNTEN2 CNTEN1 CNTEN0 Bits Description PWM Aligned Type Selection [31] CNTTYPE 0 = Edge-aligned type.
Page 252 Mini57 Bits Description Dead-zone 0 Generator Enable/Disable (PWM0 and PWM1 Pair for PWM Group) 0 = Dead-zone 0 Generator Disabled. [24] DTCNT01 1 = Dead-zone 0 Generator Enabled. Note: When the dead-zone generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group.
Page 253 Mini57 Bits Description PWM-timer 0 Enable/Disable Start Run CNTEN0 0 = Corresponding PWM-timer running Stopped. 1 = Corresponding PWM-timer start run Enabled. Apr. 06, 2017 Page 253 of 475 Rev.1.00...
Page 254 Mini57 EPWM Period Counter Register (EPWM_PERIOD) Register Offset Description Reset Value EPWM_PERIOD EPWM_BA+0x0C EPWM Period Counter Register 0x0000_0000 Reserved Reserved PERIOD PERIOD Bits Description [31:16] Reserved Reserved. PWM Counter/Timer Loaded Value PERIODn determines the PWM Period. Edge-aligned mode: where xy, could be 01, 23, 45 depending on the selected PWM channel.
Page 255 Mini57 EPWM Comparator Register 0-5 (EPWM_CMPDAT0-5) Register Offset Description Reset Value EPWM_CMPDAT0 EPWM_BA+0x24 EPWM Comparator Register 0 0x0000_0000 EPWM_CMPDAT1 EPWM_BA+0x28 EPWM Comparator Register 1 0x0000_0000 EPWM_CMPDAT2 EPWM_BA+0x2C R/W EPWM Comparator Register 2 0x0000_0000 EPWM_CMPDAT3 EPWM_BA+0x30 EPWM Comparator Register 3 0x0000_0000 EPWM_CMPDAT4 EPWM_BA+0x34 EPWM Comparator Register 4 0x0000_0000...
Page 256 Mini57 Bits Description PWM Comparator Register CMP determines the PWM Duty. Edge-aligned mode: where xy, could be 01, 23, 45 depending on the selected PWM channel. Period = (PERIOD + 1) unit. Duty ratio = CMP / (PERIOD+1). CMP > PERIOD: PWM output is always high CMP <= PERIOD: PWM output high duty = (CMP) unit.
Page 257 Mini57 EPWM Data Register (EPWM_CNT) Register Offset Description Reset Value EPWM_CNT EPWM_BA+0x3C EPWM Data Register 0x0000_0000 CNTDIR Reserved Reserved Bits Description PWM Counter (Up/Down) Direction [31] CNTDIR 0 = PWM counter is down counting. 1 = PWM counter is up counting. Reserved [30:16] Reserved.
Page 258 Mini57 EPWM Interrupt Enable Register (EPWM_INTEN) Register Offset Description Reset Value EPWM_INTEN EPWM_BA+0x54 EPWM Interrupt Enable Register 0x0000_0000 Reserved CMPDIEN5 CMPDIEN4 CMPDIEN3 CMPDIEN2 CMPDIEN1 CMPDIEN0 Reserved CIEN BRK1IEN BRK0IEN Reserved CMPUIEN5 CMPUIEN4 CMPUIEN3 CMPUIEN2 CMPUIEN1 CMPUIEN0 Reserved PIEN Bits Description [31:30] Reserved Reserved.
Page 259 Mini57 Bits Description PWM Channel 0 DOWN Interrupt Enable Bit DOWN for Edge-aligned and Center-aligned [24] CMPDIEN0 0 = Interrupt compare Disabled. 1 = interrupt when EPWM_CH0 PWM DOWN counter reaches EPWM_CMPDAT0 Enabled. Reserved [23:19] Reserved. PWM Central Interrupt Enable Bit for Center-aligned only CIEN [18]...
Page 260 Mini57 Bits Description Reserved [7:1] Reserved. PWM Channel 0 Period Interrupt Enable Bit for Edge-aligned and Center-aligned PIEN 0 = EPWM Period interrupt Disabled . 1 = EPWM Period interrupt Enabled . Apr. 06, 2017 Page 260 of 475 Rev.1.00...
Page 261 Mini57 EPWM Interrupt Status Register (EPWM_INTSTS) Register Offset R/W Description Reset Value EPWM_INTSTS EPWM_BA+0x58 R/W EPWM Interrupt Status Register 0x0000_0000 Reserved CMPDIF5 CMPDIF4 CMPDIF3 CMPDIF2 CMPDIF1 CMPDIF0 Reserved BRK1IF BRK0IF Reserved CMPUIF5 CMPUIF4 CMPUIF3 CMPUIF2 CMPUIF1 CMPUIF0 Reserved Bits Description [31:30] Reserved Reserved.
Page 262 Mini57 Bits Description PWM Brake1 Flag 0 = PWM Brake does not recognize a falling signal at BKP1. [17] BRK1IF 1 = When PWM Brake detects a falling signal at pin BKP1, this flag will be set to high. Note: Software can write 1 to clear this bit. PWM Brake0 Flag 0 = PWM Brake does not recognize a falling signal at BKP0.
Page 263 Mini57 EPWM BRK Low Voltage Detect Resume Delay (EPWM_RESDLY) Register Offset Description Reset Value EPWM_RESD EPWM_BA+0x5C EPWM BRK Low Voltage Detect Resume Delay 0x0000_0000 Reserved Reserved Reserved DELAY DELAY Bits Description [31:12] Reserved Reserved. PWM BRK Low Voltage Detect Resume Delay [11:0] DELAY 12 bits Down-Counter...
Page 264 Mini57 EPWM Fault Brake Control Register (EPWM_BRKCTL) Register Offset Description Reset Value EPWM_BRKC EPWM_BA+0x60 EPWM Fault Brake Control Register 0x0000_0000 NFPEN Reserved BKOD5 BKOD4 BKOD3 BKOD2 BKOD1 BKOD0 Reserved LVDTYPE LVDBKEN BRK1PEN BK1ADCEN BRK1A1EN BRK1A0EN SWBRK Reserved Reserved BRK0PEN BK0ADCEN BRK0A1EN BRK0A0EN BRK1EN...
Page 265 Mini57 Bits Description Low-level Detection Resume Type [15] LVDTYPE 0 = Brake resume at BRK resume delay counter counting to 0. 1 = Brake resume at period edge. Low-level Detection Trigger PWM Brake Function 1 Enable Bit [14] LVDBKEN 0 = Brake Function 1 triggered by Low-level detection Disabled. 1 = Brake Function 1 triggered by Low-level detection Enabled.
Page 266 Mini57 EPWM Dead-zone Interval Register (EPWM_DTCTL) Register Offset Description Reset Value EPWM_DTCT EPWM_BA+0x64 EPWM Dead-zone Interval Register 0x0000_0000 Reserved DTCNT45 DTCNT23 DTCNT01 Bits Description [31:24] Reserved Reserved. Dead-zone Interval Register for Pair of Channel4 and Channel5 (PWM4 and PWM5 Pair) [23:16] DTCNT45 These 8 bits determine dead-zone length.
Page 267 Mini57 EPWM Phase Change Register (EPWM_PHCHG) Register Offset Description Reset Value EPWM_PHCH EPWM_BA+0x78 EPWM Phase Changed Register 0x0000_0000 Reserved ACMP1TEN ACMP0TEN A1POSSEL A0POSSEL Reserved TRGSEL Reserved Reserved MSKEN5 MSKEN4 MSKEN3 MSKEN2 MSKEN1 MSKEN0 Reserved MSKDAT5 MSKDAT4 MSKDAT3 MSKDAT2 MSKDAT1 MSKDAT0 Bits Description [31:30]...
Page 268 Mini57 Bits Description Phase Change Trigger Selection Select the trigger condition to load PHCHG from PHCHG_NXT. When the trigger condition occurs it will load PHCHG_NOW with PHCHG_NXT. Phase Change: PWM outputs are masked according with the definition of MSKENn and MSKDATn in PHCHG_NOW.
Page 269 Mini57 Bits Description Enable PWM2 Mask Data MSKDAT2 0 = PWM2 state is masked with zero. 1 = PWM2 state is masked with one. Enable PWM1 Mask Data MSKDAT1 0 = PWM1 state is masked with zero. 1 = PWM1 state is masked with one. Enable PWM0 Mask Data MSKDAT0 0 = PWM0 state is masked with zero.
Page 270 Mini57 EPWM Next Phase Change Register (EPWM_PHCHGNXT) Register Offset Description Reset Value EPWM_PHCH EPWM_BA+0x7C EPWM Next Phase Change Register 0x0000_0000 GNXT Reserved ACMP1TEN ACMP0TEN A1POSSEL A0POSSEL Reserved TRGSEL Reserved HALLSTS Reserved MSKEN5 MSKEN4 MSKEN3 MSKEN2 MSKEN1 MSKEN0 Reserved MSKDAT5 MSKDAT4 MSKDAT3 MSKDAT2 MSKDAT1...
Page 271 Mini57 Bits Description Phase Change Trigger Selection Preset Bits This bit field will be load to bit field TRGSEL in PHCHG_NOW when load trigger condition occurs. 000 = Triggered by Timer0 event. 001 = Triggered by Timer1 event. 010 = Triggered by Timer2 event. [22:20] TRGSEL 011 = Triggered by HALLSTS (EPWM_PHCHGNXT[18:16]) matched hall sensor state.
Page 272 Mini57 Bits Description Enable PWM4 Mask Data Preset Bit MSKDAT4 This bit will be load to bit MSKDAT4 in PHCHG_NOW when load trigger condition occurs. Refer to register PHCHG_NOW for detailed definition. Enable PWM3 Mask Data Preset Bit MSKDAT3 This bit will be load to bit MSKDAT3 in PHCHG_NOW when load trigger condition occurs. Refer to register PHCHG_NOW for detailed definition.
Page 273 Mini57 EPWM Phase Change Alternative Control Register (EPWM_PHCHGALT) Register Offset Description Reset Value EPWM_PHCHGA EPWM_BA+0x80 R/W EPWM Phase Change Alternative Control Register 0x0000_0000 Reserved Reserved Reserved Reserved POSCTL1 POSCTL0 Bits Description [31:2] Reserved Reserved. Positive Input Control for ACMP1 0 = The input of ACMP1 is controlled by ACMP_CTL1. POSCTL1 1 = The input of ACMP1 is controlled by A1POSSEL in PHCHG_NOW register.
Page 274 Mini57 EPWM Period Interrupt Accumulation Control Register (EPWM_IFA) Register Offset Description Reset Value EPWM_IFA EPWM_BA+0x84 R/W EPWM Period Interrupt Accumulation Control Register 0x0000_00F0 Reserved Reserved IFDAT Reserved IFCNT Reserved IFAEN Bits Description [31:16] Reserved Reserved. Period Interrupt Down-counter Data Register (Read Only) When IFAEN is set, IFDAT will decrease when every PWM Interrupt flag is set, [15:12] IFDAT...
Page 275: Basic Pwm Generator (Bpwm)
Mini57 6.9 Basic PWM Generator (BPWM) 6.9.1 Overview The Mini57 series has one set of BPWM group supporting one set of PWM generator that can be configured as 2 independent PWM outputs, BPWM CH0~BPWM CH1, or as 1 complementary PWM pairs, (BPWM CH0, BPWM CH1) with programmable Dead-zone generators. The PWM generator has one 8-bit pre-scalar, one clock divider with 5 divided frequencies (1, 1/2, 1/4, 1/8, 1/16), two PWM Timers including two clock selectors, two 16-bit PWM down-counters for PWM period control, two 16-bit comparators for PWM duty control and one dead-zone generator.
Page 276: Pwm-Timer Operation
Mini57 BPWM_EN(APBCLK[23]) BPWM_CLK HCLK Figure 6.9-1 PWM Clock Source Control DTI01(BPWM_CLKPSC[23:16]) Dead Zone Generator 0 (BPWM_PERIOD0) (BPWM_CMPDAT0) CLKDIV0 (BPWM_CTL) (BPWM_CLKDIV[2:0]) POEN0(BPWM_POEN[0]) (BPWM_CNT0) PWM20 PWM- Timer0 Logic Clock Divider 1/16 (from clock PINV0 controller) CMPINV0 (BPWM_CTL[1]) (BPWM_CTL[2]) PIEN0 PIF0 (BPWM_INTEN[0]) (BPWM_INTSTS[0]) DIEN0 DIF0 (BPWM_INTEN[8])
Page 277: Figure 6.9-3 Legend Of Internal Comparator Output Of Pwm-Timer
Mini57 output to high and CMP and PERIOD are updated with CNTMODEn=1 and request the BPWM interrupt if BPWM interrupt is enabled BPWM_INTEN(PWM_INTEN.n=1). The PWM period and duty control are configured by BPWM counter register (BPWM_PERIOD0- 1) and BPWM comparator register (BPWM_CMPDAT0-1). The PWM-timer timing operation is shown in Figure 6.9-4.
Page 278: Figure 6.9-4 Pwm-Timer Operation Timing
Mini57 down- counter PWM- Timer output CMP = 1 PERIOD = 3 CMP = 0 Auto reload = 1 PERIOD = 4 (S/W write new value) (CNTMODEx=1) (Write initial setting) Auto-load Auto-load Set CNTENx=1 (H/W update value) (PIFx is set by H/W) (PWM-Timer starts running) (PIFx is set by H/W) Note: x = 0,1...
Page 279: Figure 6.9-6 Center-Aligned Type Output Waveform
Mini57 configured in an Up/Down Counting mode. The PWM counter will start counting-up from 0 to match the value of CMP (BPWM_CMPDAT0-1[15:0]); this will cause the toggling of the PWMn generator output to low. The counter will continue counting to match with the PERIOD (BPWM_PERIOD0-1[15:0]) .
Page 280: Figure 6.9-7 Pwm Center-Aligned Interrupt Generate Timing Waveform
Mini57 PERIOD (7FF) (BPWM_PERIODn[15:0]) CMP (3FF) (BPWM_CMPDATn[15:0) PIF(PINTTYPE=0) (BPWM_INTSTS[0],[1]) clear clear clear PIF(PINTTYPE=1) clear (BPWM_INTSTS[0], [1]) clear DIF(BPWM_INTSTS[0], [1]) clear clear PWMn generator ouput PWM period PWM period Note: n = 0,1 denote BPWM0/1 Figure 6.9-7 PWM Center-aligned Interrupt Generate Timing Waveform 6.9.4.3 PWM Double Buffering, Auto-reload and One-shot Operation PWM Timers have double buffering function the reload value is updated at the start of next period...
Page 281: Figure 6.9-8 Pwm Double Buffering Illustration
Mini57 Write Write Write Write PERIOD=150 PERIOD=199 PERIOD=99 PERIOD=0 CMP=50 CMP=49 CMP=0 CMP=XX Start Stop Waveform write a nonzero number to prescaler & setup clock dividor Figure 6.9-8 PWM Double Buffering Illustration 6.9.4.4 Modulate Duty Ratio The double buffering function allows CMP written at any point in current cycle. The loaded value will take effect from next cycle.
Page 282: Figure 6.9-10 Paired-Pwm Output With Dead-Zone Generation Operation
Mini57 PWM-Timer Output 0 PWM-Timer Inversed output Dead-Zone Generator output 0 Dead-Zone Generator output 1 Dead zone interval Figure 6.9-10 Paired-PWM Output with Dead-zone Generation Operation 6.9.4.6 PWM-Timer Interrupt Architecture There are two PWM interrupts, BPWM0_INT and BPWM1_INT. Figure 6.9-11 demonstrates the architecture of PWM Timer interrupts.
Page 283 Mini57 6.9.4.8 PWM-Timer Re-Start Procedure in Single-shot mode After PWM waveform is generated once in PWM One-shot mode, PWM-Timer will be stopped automatically. The following procedure is recommended for re-starting PWM single-shot waveform.  Set comparator register (BPWM_CMPDAT) for setting PWM duty. ...
Page 284: Register Map
Mini57 6.9.5 Register Map R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written Register Offset R/W Description Reset Value BPWM Base Address: BPWM_BA = 0x4014_0000 BPWM_CLKPSC BPWM_BA+0x00 R/W Basic PWM Pre-scalar Register 0x0000_0000 BPWM_CLKDIV BPWM_BA+0x04...
Page 285: Register Description
Mini57 6.9.6 Register Description BPWM Pre-scale Register (BPWM_CLKPSC) Register Offset Description Reset Value BPWM_CLKP BPWM_BA+0x00 Basic PWM Pre-scalar Register 0x0000_0000 Reserved DTI01 Reserved CLKPSC01 Bits Description [31:24] Reserved Reserved. Dead-zone Interval for Pair of Channel 0 and Channel 1 [23:16] DTI01 These 8-bit determine the Dead-zone length.
Page 286 Mini57 BPWM Clock Source Divider Select Register (BPWM_CLKDIV) Register Offset Description Reset Value BPWM_CLKD BPWM_BA+0x04 Basic PWM Clock Source Divider Select Register 0x0000_0000 Reserved Reserved Reserved Reserved CLKDIV1 Reserved CLKDIV0 Bits Description [31:7] Reserved Reserved. PWM Timer 1 Clock Source Divider Selection Select clock source divider for PWM timer 1.
Page 287 Mini57 BPWM Control Register (BPWM_CTL) Register Offset Description Reset Value BPWM_CTL BPWM_BA+0x08 Basic PWM Control Register 0x0000_0000 Reserved CNTTYPE01 Reserved Reserved Reserved CNTMODE1 CMPINV1 PINV1 CNTEN1 Reserved DTCNT01 CNTMODE0 CMPINV0 PINV0 CNTEN0 Bits Description [31] Reserved Reserved. PWM01 Aligned Type Selection [30] CNTTYPE01 0 = Edge-aligned type.
Page 288 Mini57 PWM-timer 0 Auto-reload/One-shot Mode 0 = One-shot mode. CNTMODE0 1 = Auto-reload mode. Note: If there is a transition at this bit, it will cause BPWM_PERIOD0 and BPWM_CMPDAT0 be cleared. PWM-timer 0 Output Inverter Enable Bit CMPINV0 0 = Inverter Disabled. 1 = Inverter Enabled.
Page 289 Mini57 BPWM Counter Register 0-1 (BPWM_PERIOD0-1) Register Offset Description Reset Value BPWM_PERI BPWM_BA+0x0C Basic PWM Period Counter Register 0 0x0000_0000 BPWM_PERI BPWM_BA+0x18 Basic PWM Period Counter Register 1 0x0000_0000 Reserved Reserved PERIOD PERIOD Bits Description [31:16] Reserved Reserved. Basic PWM Period Counter Register PERIOD data determines the PWM period.
Page 290 Mini57 BPWM Comparator Register0-1 (BPWM_CMPDAT0-1) Register Offset Description Reset Value BPWM_CMPD BPWM_BA+0x10 Basic PWM Comparator Register 0 0x0000_0000 BPWM_CMPD BPWM_BA+0x1C Basic PWM Comparator Register 1 0x0000_0000 Reserved Reserved Bits Description [31:16] Reserved Reserved. PWM Comparator Register CMP determines the PWM duty. PWM frequency = BPWM_CLK/[(prescale+1)*(clock divider)*(PERIOD+1)].
Page 291 Mini57 BPWM Data Register 0-1 (BPWM_CNT0-1) Register Offset Description Reset Value BPWM_CNT0 BPWM_BA+0x14 Basic PWM Data Register 0 0x0000_0000 BPWM_CNT1 BPWM_BA+0x20 Basic PWM Data Register 1 0x0000_0000 Reserved Reserved Bits Description [31:16] Reserved Reserved. PWM Data Register [15:0] User can monitor CNT to know the current value in 16-bit counter. Apr.
Page 292 Mini57 BPWM Interrupt Enable Register (BPWM_INTEN) Register Offset Description Reset Value BPWM_INTEN BPWM_BA+0x40 Basic PWM Interrupt Enable Register 0x0000_0000 Reserved Reserved PINTTYPE Reserved DIEN1 DIEN0 Reserved PIEN1 PIEN0 Bits Description [31:17] Reserved Reserved. BPWM Interrupt Period Type Selection 0 = PIFn will be set if BPWM counter underflow. [16] PINTTYPE 1 = PIFn will be set if BPWM counter matches PERIODn register.
Page 293 Mini57 BPWM Interrupt Indication Register (BPWM_INTSTS) Register Offset R/W Description Reset Value BPWM_INTSTS BPWM_BA+0x44 R/W Basic PWM Interrupt Indication Register 0x0000_0000 Reserved Reserved Reserved DIF1 DIF0 Reserved PIF1 PIF0 Bits Description [31:10] Reserved Reserved. BPWM Channel 1 Duty Interrupt Flag Flag is set by hardware when channel 1 BPWM counter down count and reaches DIF1 BPWM_CMPDAT 1, software can clear this bit by writing a one to it.
Page 294 Mini57 BPWM Output Enable Register (BPWM_POEN) Register Offset Description Reset Value BPWM_POEN BPWM_BA+0x7C Basic PWM Output Enable 0x0000_0000 Reserved Reserved Reserved Reserved POEN1 POEN0 Bits Description [31:2] Reserved Reserved. Channel 1 Output Enable Register 0 = BPWM channel 1 output to pin Disabled. POEN1 1 = BPWM channel 1 output to pin Enabled.
Page 295: Watchdog Timer (Wdt)
Mini57 6.10 Watchdog Timer (WDT) 6.10.1 Overview The Watchdog Timer is used to perform a system reset when system runs into an unknown state. This prevents system from hanging for an infinite period of time. Besides, the Watchdog Timer supports the function to wake-up system from Idle/Power-down mode. 6.10.2 Features ...
Page 296: Clock Control
Mini57 6.10.4 Clock Control The Watchdog Timer clock control and block diagram are shown as follows. WDTSEL (CLK_CLKSEL1[1:0]) WDTCEN (CLK_APBCLK[0]) 10 kHz LIRC WDT_CLK HCLK/2048 HXT or LXT Legend: LIRC = Low-Speed Internal clock signal Figure 6.10-2 Watchdog Timer Clock Control Diagram 6.10.5 Basic Configuration The WDT peripheral clock is enabled in WDTKEN (CLK_APBCLK[0]) and clock source can be selected in WDTSEL (CLK_CLKSEL1[1:0]).
Page 297: Figure 6.10-3 Watchdog Timer Time-Out Interval And Reset Period Timing
Mini57 6.10.6.3 WDT Wake-up If WDT clock source is selected to 10 kHz, system can be woken-up from Power-down mode while WDT time-out interrupt signal is generated and WKEN (WDT_CTL[4]) bit enabled. In the meanwhile, the WKF (WDT_CTL[5]) flag will set to 1 automatically, and user can check WKF (WDT_CTL[5]) flag by software to recognize if the system has been woken-up by WDT time-out interrupt or not.
Page 298: Registers Map
Mini57 6.10.7 Registers Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value WDT Base Address: WDT_BA = 0x4000_4000 WDT_CTL WDT_BA+0x00 Watchdog Timer Control Register 0x0000_0700 Apr. 06, 2017 Page 298 of 475 Rev.1.00...
Page 299: Register Description
Mini57 6.10.8 Register Description Watchdog Timer Control Register (WDT_CTL) Register Offset Description Reset Value WDT_CTL WDT_BA+0x00 Watchdog Timer Control Register 0x0000_0700 Note: All bits in this register are write-protected. To program it, an open lock sequence is needed, by sequentially writing 0x59, 0x16, and 0x88 to register REGWRPROT at address SYS_BA + 0x100. ICEDEBUG Reserved Reserved...
Page 300 Mini57 Bits Description Watchdog Timer Time-out Wake-up Flag This bit indicates the interrupt wake-up flag status of WDT. 0 = WDT does not cause chip wake-up. 1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated.
Page 301: Usci - Universal Serial Control Interface Controller
Mini57 6.11 USCI – Universal Serial Control Interface Controller 6.11.1 Overview The Universal Serial Control Interface (USCI) is a flexible interface module covering several serial communication protocols. The user can configure this controller as UART, SPI, or I C functional protocol.
Page 302: Functional Description
Mini57 6.11.4 Functional Description The structure of the Universal Serial Control Interface (USCI) controller is shown in Figure 6.11-1. The input signal is implemented in an input processor. The data buffers and the data shift unit support the data transfers. Each protocol-specific function is handled by the protocol processor unit.
Page 303: Figure 6.11-2 Input Conditioning For Uscix_Dat[1:0] And Uscix_Ctl[1:0]
Mini57 ININV SYNCSEL (USCI_DATIN0[2] / ( USCI_DATIN0[0] / USCI_CTLIN0[2]) USCI_CTLIN0[0]) USCIx_DAT[1:0] Data Shift Unit IN_SYNC Digital USCIx_CTL[1:0] Filter Protocol Processor Unit Edge Detection (data signal only) Note: x = 0, 1 Figure 6.11-2 Input Conditioning for USCIx_DAT[1:0] and USCIx_CTL[1:0] The input structure of USCIx_CLK is similar to USCIx_CTL[1:0] input structure, except it does not support inverse function.
Page 304: Table 6.11-2 Output Signals For Different Protocols
Mini57 synchronized to f ). The synchronized input signal is taken into account by SYNCSEL = 1. The PCLK synchronization leads to a delay in the signal path of 2-3 times the period of f PCLK Output Signals Table 6.11-2 shows the relative output signals for each protocol. The number of actually used outputs depends on the selected protocol and they can be classified according to their meaning for the protocols.
Page 305: Figure 6.11-4 Block Diagram Of Data Buffering
Mini57 Figure 6.11-4 Block Diagram of Data Buffering The operation of data handling includes:  The peripheral device user interface (APB) is used to handle data, interrupts, status and control information.  A transmitter includes transmit shift register (TX_SFTR) and a transmit data buffer (TX_BUF).
Page 306: Figure 6.11-6 Transmit Data Path
Mini57 data is valid for transmission. Serial Bus Shift Data Control Input Clock Input Output USCI_LINECTL Control Shift Control USCI_BUFSTS Status & Status Data USCI_TXDAT TX_SFTR TX_BUF Transmit Buffer Figure 6.11-6 Transmit Data Path Transmit Data Validation The status of TXEMPTY (USCI_BUFSTS[8]) indicates the transmission data is valid or not in the transmit buffer (TX_BUF) and the TXSTIF (USCI_PROTSTS[1]) labels the start conditions for each data.
Page 307: Figure 6.11-7 Receive Data Path
Mini57 Receive Data Path The receive data path is based on 16-bit wide receive shift register RX_SFTR and receive buffers RX_BUF0 and RX_BUF1. The data transfer parameters like data word length, or the shift direction are controlled commonly for transmission and reception by the line control register USCI_LINECTL.
Page 308: Figure 6.11-8 Protocol-Relative Clock Generator
Mini57 SAMP_CLK RCLKSEL Protocol (USCI_BRGEN[0] Processor Unit DS_CNT Enable Protocol PCLK Protocol REF_CLK Related Clock Output Related Configration Counter HXT/LXT Note: Refer the Basic Clock Divider Counter section to get the SAMP_CLK Figure 6.11-8 Protocol-Relative Clock Generator The protocol related counter contains basic clock divider counter and timing measurement counter.
Page 309: Figure 6.11-9 Basic Clock Divider Counter
Mini57 SAMP_CLK Divide by Divider CLKDIV +1 by 2 Divider REF_CLK PROT_CLK DIV_CLK SCLK by 2 REF_CLK2 SPCLKSEL PTCLKSEL (USCI_BRGEN[3:2]) (USCI_BRGEN[1]) Figure 6.11-9 Basic Clock Divider Counter Timing Measurement Counter The timing measurement counter is used for time interval measurement and is enabled by TMCNTEN (USCI_BRGEN [4]) = 1.
Page 310: Figure 6.11-11 Sample Time Counter
Mini57  C: The timing measurement counter indicates time-out clock cycle. Sample Time Counter A sample time counter associated to the protocol related counter defining protocol specific timings, such shift control signals or bit timings, based on the input frequency f .
Page 311: Figure 6.11-12 Event And Interrupt Structure
Mini57  Receive event to indicate that a data word has been received: If a new received word becomes available in the receive buffer, a receive event occurs. It is indicated by flag RXENDIF (USCI_PROTSTS [4]) and, if enabled, leads to receive interrupt. ...
Page 312: Table 6.11-4 Protocol-Specific Events And Interrupt Handling
Mini57 6.11.4.6 Protocol-specific Events and Interrupts These events are related to protocol-specific actions that are described in the corresponding protocol chapters. The related indication flags are located in register USCI_PROTSTS. All events can be individually enabled for the generation of the common protocol interrupt. Interrupt Enabled Event Indication Flag...
Page 313: Usci - Uart Mode
Mini57 6.12 USCI – UART Mode 6.12.1 Overview The asynchronous serial channel UART covers the reception and the transmission of asynchronous data frames. It performs a serial-to-parallel conversion on data received from the peripheral, and a parallel-to-serial conversion on data transmitted from the controller. The receiver and transmitter are independent, frames can start at different points in time for transmission and reception.
Page 314: Basic Configuration
Mini57 6.12.4 Basic Configuration The basic configurations of USCI0 for UART mode are as follows.  USCI0 pins are configured in SYS_GPA_MFP, SYS_GPC_MFP, SYS_GPD_MFP registers.  Enable USCI0 peripheral clock in USCI0CKEN (CLK_APBCLK[24]).  Reset USCI0 controller in USCI0RST (SYS_IPRST1[24]). The basic configurations of USCI1 for UART mode are as follows.
Page 315: Table 6.12-1 Input Signals For Uart Protocols
Mini57 Input Signals For UART protocol, the number of input signals is demonstratedTable 6.12-1 Each input signal is handled by an input processor for signal conditioning, such as signal inverse selection control, or a digital input filter. The input signals can be classified according to their meaning for the protocols, as shown in Table 6.12-1.
Page 316: Figure 6.12-3 Uart Standard Frame Format
Mini57 IDLE DATA STOP IDLE 1 Bit 6~13 Bit 0~1 Bit 1~2 Bit Figure 6.12-3 UART Standard Frame Format The protocol specific bits (SOF, P, STOP) are automatically handled by the UART protocol state machine and do not appear in the data flow via the receive and transmit buffers. Start Bit The receiver input signal USCIx_DAT0 is checked for a falling edge.
Page 317 Mini57 6.12.5.4 Operating Mode In order to operate the UART protocol, the following issues have to be considered: Select UART Mode The UART protocol can be selected by setting FUNMODOE (UUART_CTL[2:0]) to 0x2 and the UART protocol can be enabled by setting PROTEN (UUART_PROTCTL [31]) to 1. Note that the FUNMODE must be set 0 before protocol changing and it is recommended to configure all parameters of the UART before UART protocol is enabled.
Page 318: Figure 6.12-4 Uart Bit Timing (Data Sample Time)
Mini57 Sample Time sample taken Figure 6.12-4 UART Bit Timing (Data Sample Time) 6.12.5.6 Baud Rate Generation The baud rate f in UART mode depends on the number of data sample time per bit time and UART their timing. The baud rate setting should only be changed while the transmitter and the receiver are idle.
Page 319: Table 6.12-3 Baud Rate Relationship
Mini57 HCLK PCLK Expect CLKDIV DSCNT PDSCNT Active Error Source Source Baud Rate (UUART_BRGEN[25:16]) (UUART_BRGEN[14:10]) Baud Percentage Rate HXT12M 115200 115384 1.6% (HCLK) HIRC/2, 9600 0xF9 9600 (HCLK) HIRC48M 48M 115200 115384 1.6% (HCLK) Table 6.12-3 Baud rate Relationship Note: SPCLKSEL = 0x0, PTCLKSEL = 0, RCLKSEL = 0 6.12.5.7 Auto Baud Rate Detection The UART controller supports auto baud rate detection function.
Page 320: Figure 6.12-5 Uart Auto Baud Rate Control
Mini57 is 0x1FE for BRDETITV. Clear this bit by H/W at the 4th falling edge Enable this bit by User ABREN falling edge falling edge 3th falling edge 4th falling edge USCI_DATAIN0 CLKDIV DSCNT BRDETITV ABRDETIF Can be cleared by write 1 Falling edge clear the TMCNT Timing measurement...
Page 321: Figure 6.12-6 Incoming Data Wake-Up
Mini57 device can either receive this symbol without any further action (and can discard it) or use the falling edges for baud rate measurement. ABREN is used to capture a timer counter value for the receiver synchronization byte. The valid captured values can be read out after the frame is transmitted done.
Page 322 Mini57 6.12.5.10 Interrupt Events Protocol Interrupt Events The following protocol-related events are generated in UART mode and can lead to a protocol interrupt. Please note that the bits in register UUART_PROTSTS are not automatically cleared by hardware and have to be cleared by software in order to monitor new incoming events. Receiver line status protocol-related error...
Page 323 Mini57 TXENDIF (UUART_PROTSTS [2]) becomes set at the end of the last stop bit. The controller wil issue an interrupt if TXENDIEN (UUART_INTEN[2]) is also set to 1. Receiver starts interrupt Bit RXSTIF (UUART_PROTSTS [3]) is set after the sample point of the start bit. The controller wil issue an interrupt if RXSTIEN (UUART_INTEN[3]) is also set to 1.
Page 324: Register Map
Mini57 6.12.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value UUART_CTL UUARTx_BA+0x00 R/W USCI Control Register 0x0000_0000 x = 0, 1 UUART_INTEN UUARTx_BA+0x04 R/W USCI Interrupt Enable Register 0x0000_0000 x = 0, 1 UUART_BRGEN UUARTx_BA+0x08...
Page 325: Register Description
Mini57 6.12.7 Register Description USCI Control Register (UUART_CTL) Register Offset Description Reset Value UUART_CTL UUARTx_BA+0x00 R/W USCI Control Register 0x0000_0000 x = 0, 1 Reserved Reserved Reserved Reserved FUNMODE Bits Description [31:3] Reserved Reserved. Function Mode This bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI.
Page 326 Mini57 USCI Interrupt Enable Register (UUART_INTEN) Register Offset Description Reset Value UUART_INTEN UUARTx_BA+0x04 R/W USCI Interrupt Enable Register 0x0000_0000 x = 0, 1 Reserved Reserved Reserved Reserved RXENDIEN RXSTIEN TXENDIEN TXSTIEN Reserved Bits Description [31:5] Reserved Reserved. Receive End Interrupt Enable Bit This bit enables the interrupt generation in case of a receive finish event.
Page 327 Mini57 USCI Baud Rate Generator Register (UUART_BRGEN) Register Offset R/W Description Reset Value UUART_BRGEN UUARTx_BA+0x08 R/W USCI Baud Rate Generator Register 0x0000_3C00 x = 0, 1 Reserved CLKDIV CLKDIV Reserved DSCNT PDSCNT Reserved TMCNTSRC TMCNTEN SPCLKSEL PTCLKSEL RCLKSEL Bits Description [31:26] Reserved Reserved.
Page 328 Mini57 Sample Clock Source Selection This bit field used for the clock source selection of a sample clock (f ) for the SAMP_CLK protocol processor. 00 = f [3:2] SPCLKSEL SAMP_CLK DIV_CLK. 01 = f SAMP_CLK PROT_CLK. 10 = f SAMP_CLK SCLK.
Page 329 Mini57 USCI Input Data Signal Configuration (UUART_DATIN0) Register Offset R/W Description Reset Value UUART_DATIN0 UUARTx_BA+0x10 R/W USCI Input Data Signal Configuration Register 0 0x0000_0000 x = 0, 1 Reserved Reserved Reserved Reserved EDGEDET ININV Reserved SYNCSEL Bits Description [31:5] Reserved Reserved.
Page 330 Mini57 USCI Input Control Signal Configuration (UUART_CTLIN0) Register Offset R/W Description Reset Value UUART_CTLIN0 UUARTx_BA+0x20 R/W USCI Input Control Signal Configuration Register 0 0x0000_0000 x = 0, 1 Reserved Reserved Reserved Reserved ININV Reserved SYNCSEL Bits Description [31:3] Reserved Reserved. Input Signal Inverse Selection This bit defines the inverter enable of the input asynchronous signal.
Page 331 Mini57 USCI Input Clock Signal Configuration (UUART_CLKIN) Register Offset Description Reset Value UUART_CLKIN UUARTx_BA+0x28 R/W USCI Input Clock Signal Configuration Register 0x0000_0000 x = 0, 1 Reserved Reserved Reserved Reserved SYNCSEL Bits Description [31:1] Reserved Reserved. Input Synchronization Signal Selection This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
Page 332 Mini57 USCI Line Control Register (UUART_LINECTL) Register Offset R/W Description Reset Value UUART_LINECTL UUARTx_BA+0x2C R/W USCI Line Control Register 0x0000_0000 x = 0, 1 Reserved Reserved Reserved DWIDTH CTLOINV Reserved DATOINV Reserved Bits Description [31:12] Reserved Reserved. Word Length of Transmission This bit field defines the data word length (amount of bits) for reception and transmission.
Page 333 Mini57 Reserved [4:1] Reserved. LSB First Transmission Selection 0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first. 1 = The LSB, the bit 0 of data buffer, will be transmitted/received first. Apr.
Page 334 Mini57 USCI Transmit Data Register (UUART_TXDAT) Register Offset Description Reset Value UUART_TXDAT UUARTx_BA+0x30 W USCI Transmit Data Register 0x0000_0000 x = 0, 1 Reserved Reserved TXDAT TXDAT Bits Description [31:16] Reserved Reserved. Transmit Data [15:0] TXDAT Software can use this bit field to write 16-bit transmit data for transmission. Apr.
Page 335 Mini57 USCI Receive Data Register (UUART_RXDAT) Register Offset R/W Description Reset Value UUART_RXDAT UUARTx_BA+0x34 R USCI Receive Data Register 0x0000_0000 x = 0, 1 Reserved Reserved RXDAT RXDAT Bits Description [31:16] Reserved Reserved. Received Data This bit field monitors the received data which stored in receive data buffer. [15:0] RXDAT Note: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and...
Page 336 Mini57 USCI Transmitter/Receive Buffer Control Register (UUART_BUFCTL) Register Offset R/W Description Reset Value UUART_BUFCTL UUARTx_BA+0x38 R/W USCI Transmit/Receive Buffer Control Register 0x0000_0000 x = 0, 1 Reserved Reserved RXRST TXRST RXCLR RXOVIEN Reserved TXCLR Reserved Bits Description [31:18] Reserved Reserved. Receive Reset 0 = No effect.
Page 337 Mini57 pointer value). Should only be used while the buffer is not taking part in data traffic. Note: It is cleared automatically after one PCLK cycle. [6:0] Reserved Reserved. Apr. 06, 2017 Page 337 of 475 Rev.1.00...
Page 338 Mini57 USCI Transmit/Receive Buffer Status Register (UUART_BUFSTS) Register Offset R/W Description Reset Value UUART_BUFSTS UUARTx_BA+0x3C R USCI Transmit/Receive Buffer Status Register 0x0000_0101 x = 0, 1 Reserved Reserved Reserved TXFULL TXEMPTY Reserved RXOVIF Reserved RXFULL RXEMPTY Bits Description [31:10] Reserved Reserved.
Page 339 Mini57 USCI Wake-up Control Register (UUART_WKCTL) Register Offset R/W Description Reset Value UUART_WKCTL UUARTx_BA+0x54 R/W USCI Wake-up Control Register 0x0000_0000 x = 0, 1 Reserved Reserved Reserved Reserved PDBOPT Reserved WKEN Bits Description [31:3] Reserved Reserved. Power Down Blocking Option 0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately.
Page 340 Mini57 USCI Wake-up Status Register (UUART_WKSTS) Register Offset R/W Description Reset Value UUART_WKSTS UUARTx_BA+0x58 R/W USCI Wake-up Status Register 0x0000_0000 x = 0, 1 Reserved Reserved Reserved Reserved Bits Description [31:1] Reserved Reserved. Wake-up Flag When chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
Page 341 Mini57 USCI Protocol Control Register – UART (UUART_PROTCTL) Register Offset R/W Description Reset Value UUART_PROTCTL UUARTx_BA+0x5C R/W USCI Protocol Control Register 0x0000_0000 x = 0, 1 PROTEN Reserved BCEN Reserved Reserved STICKEN Reserved BRDETITV BRDETITV Reserved WAKECNT Reserved DATWKEN LINRXEN LINBRKEN ABREN Reserved...
Page 342 Mini57 [10] Reserved Reserved. Data Wake-up Mode Enable Bit DATWKEN 0 = Data wake-up mode Disabled. 1 = Data wake-up mode Enabled. LIN RX Duplex Mode Enable Bit 0 = LIN RX Duplex mode Disabled. LINRXEN 1 = LIN RX Duplex mode Enabled. The LIN can be play as Slave to receive the LIN frame. Note: This bit is used to check the break duration for incoming data when the LIN operation is active.
Page 343 Mini57 USCI Protocol Interrupt Enable Register – UART (UUART_PROTIEN) Register Offset R/W Description Reset Value UUART_PROTIEN UUARTx_BA+0x60 R/W USCI Protocol Interrupt Enable Register 0x0000_0000 x = 0, 1 Reserved Reserved Reserved Reserved RLSIEN ABRIEN BRKIEN Bits Description [31:3] Reserved Reserved. Receive Line Status Interrupt Enable Bit 0 = Receive line status interrupt Disabled.
Page 344 Mini57 USCI Protocol Status Register – UART (UUART_PROTSTS) Register Offset R/W Description Reset Value UUART_PROTSTS UUARTx_BA+0x64 R/W USCI Protocol Status Register 0x0000_0000 x = 0, 1 Reserved Reserved Reserved ABERRSTS RXBUSY ABRDETIF BRKDETIF BREAK FRMERR PARITYERR RXENDIF RXSTIF TXENDIF TXSTIF Reserved Bits Description...
Page 345 Mini57 1 = LIN Break is detected. Note: This bit is read only, but can be cleared by writing ‘1’ to it. Break Flag This bit is set to logic 1 whenever the received data input (RX) is held in the “spacing state” (logic 0) for longer than a full word transmission time (that is, the total time of “start bit”...
Page 346: Usci - Spi Mode
Mini57 6.13 USCI – SPI Mode 6.13.1 Overview The SPI protocol of USCI controller applies to synchronous serial data communication and allows full duplex transfer. It supports both master and Slave operation mode with the 4-wire bi-direction interface. SPI mode of USCI controller performs a serial-to-parallel conversion on data received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device.
Page 347: Block Diagram
Mini57  Supports master or slave mode operation (the maximum frequency for Master = f PCLK 2, for Slave < f / 5) PCLK  Configurable bit length of a transfer word from 4 to 16-bit  Supports one transmit buffer and two receive buffers for data payload ...
Page 348: Functional Description
Mini57  USCI1 pins are configured in SYS_GPA_MFP, SYS_GPC_MFP, and SYS_GPD_MFP registers.  Enable USCI1 peripheral clock in USCI1CKEN (CLK_APBCLK[25]).  Reset USCI1 controller in USCI1RST (SYS_IPRST1[25]).  6.13.5 Functional Description 6.13.5.1 USCI Common Function Description Please refer to section 6.11.4 for detailed information. 6.13.5.2 Signal Description A device operating in master mode controls the start and end of a data transfer, as well as the generation of the SPI bus clock and slave select signal.
Page 349: Figure 6.13-5 4-Wire Full-Duplex Spi Communication Signals (Slave Mode)
Mini57 SPI_SS Data Frame (USCIx_CTL0) SPI_CLK (USCIx_CLK) SPI_MOSI RX Data Word 0 RX Data Word N (USCIx_DAT0) SPI_MISO TX Data Word 0 TX Data Word N (USCIx_DAT1) Note: x = 0, 1 Figure 6.13-5 4-Wire Full-Duplex SPI Communication Signals (Slave Mode) 6.13.5.3 Serial Bus Clock Configuration The USCI controller needs the peripheral clock to drive the USCI logic unit to perform the data transfer.
Page 350: Figure 6.13-6 Spi Communication With Different Spi Clock Configuration (Sclkmode=0X0)
Mini57 SPI_SS Data Frame (USCIx_CTL0) SPI_CLK (USCIx_CLK) SPI_MOSI TX[n] [n-1] TX[0] TX[n] [n-1] TX[0] (USCIx_DAT0) SPI_MISO RX[n] [n-1] RX[0] RX[n] [n-1] RX[0] (USCIx_DAT1) Data N Data (N+1) SLAVE (USPI_PROTCTL[0]) = 0; SCLKMODE (USPI_PROTCTL[7:6]) = 0x0; ININV (USPI_CTLIN0[2]) = 1; LSB (USPI_LINECTL[0]) = 0; CTLOINV (USPI_LINECTL[7]) = 1;...
Page 351: Figure 6.13-8 Spi Communication With Different Spi Clock Configuration (Sclkmode=0X2)
Mini57 SPI_SS Data Frame (USCIx_CTL0) SPI_CLK (USCIx_CLK) SPI_MOSI TX[n] [n-1] TX[0] TX[n] [n-1] TX[0] (USCIx_DAT0) SPI_MISO RX[n] [n-1] RX[0] RX[n] [n-1] RX[0] (USCIx_DAT1) Data N Data (N+1) SLAVE (USPI_PROTCTL[0]) = 0; SCLKMODE (USPI_PROTCTL[7:6]) = 0x2; ININV (USPI_CTLIN0[2]) = 1; LSB (USPI_LINECTL[0]) = 0; CTLOINV (USPI_LINECTL[7]) = 1;...
Page 352: Figure 6.13-10 16-Bit Data Length In One Word Transaction With Msb First Format
Mini57 needed to set as 1 for the external SPI Slave device whose slave select signal is active low. The duration between the slave select active edge and the first SPI clock input edge shall over 2 USCI peripheral clock cycles. The input slave select signal of SPI Slave has to be keep inactive for at least 2 USCI peripheral clock cycles between two consecutive frames in order to correctly detect the end of a frame.
Page 353: Figure 6.13-11 Word Suspend Interval Between Two Transaction Words
Mini57 Suspend Suspend Interval Interval SPI_CLK (USCIx_CLK) SPI_MOSI TX[14] TX[14] TX[15] TX[0] TX[15] TX[0] (USCIx_DAT0) SPI_MISO RX[14] RX[14] RX[15] RX[0] RX[15] RX[0] (USCIx_DAT1) 1st Transaction Word 2nd Transaction Word Transfer Frame Note 1: x = 0, 1 Note 2: Timing Condition is SCLKMODE[1:0] = 0x0; LSB = 0; DWIDTH[3:0] = 0x0; Figure 6.13-11 Word Suspend Interval between Two Transaction Words 6.13.5.7 Automatic Slave Select Function AUTOSS (USPI_PROTCTL[3]) is used for SPI Master mode to enable the automatic slave select...
Page 354: Figure 6.13-12 Auto Slave Select (Suspitv ≧ 0X3)
Mini57 (USPI_PROTCTL[2]) CTLOINV (USPI_LINECTL[7]) TXEMPTY (USPI_BUFSTS[8]) SPI_SS (USCIx_CTL0) 1 SPI clock 1.5 SPI clock SPI_CLK (USCIx_CLK) Note: Automatic slave select is enabled Figure 6.13-12 Auto Slave Select (SUSPITV ≧ 0x3) (USPI_PROTCTL[2]) CTLOINV (USPI_LINECTL[7]) TXEMPTY (USPI_BUFSTS[8]) SPI_SS (USCIx_CTL0) One word One word transaction transaction SPI_CLK...
Page 355 Mini57 is set to 1, the SPI Slave will be ready to transmit/receive data after the SPI protocol is enabled by setting FUNMODE(USPI_CTL [2:0]) to 0x1. 6.13.5.9 Data Transfer Mode The USCI controller supports full-duplex SPI transfer. In full-duplex SPI transfer, there are two data pins. One is used for transmitting data and the other is used for receiving data.
Page 356 Mini57 Slave time-out interrupt In SPI slave mode, there is Slave time-out function for user to know that there is no serial clock input during the period of one word transaction. The Slave time-out function uses the timing measurement counter for the calculation of Slave time-out period which is defined by SLVTOCNT (USPI_PROTCTL[25:16]).
Page 357: Figure 6.13-14 Spi Timing In Master Mode
Mini57 CTLOINV=0 SPI_SS (USCIx_CTL0) CTLOINV=1 SCLKMODE=0x0 SPI_CLK (USCIx_CLK) SCLKMODE=0x2 SPI_MOSI TX[6] TX[5] TX[4] TX[3] TX[2] TX[1] TX[7] TX[0] (USCIx_DAT0) SPI_MISO RX[6] RX[5] RX[4] RX[3] RX[2] RX[1] RX[7] RX[0] (USCIx_DAT1) Master Mode: FUNMODE=0x1, SLAVE=0, LSB=0, DWIDTH=0x8 Note: x = 0, 1 Figure 6.13-14 SPI Timing in Master Mode CTLOINV=0 SPI_SS...
Page 358: Figure 6.13-16 Spi Timing In Slave Mode
Mini57 CTLOINV=0 SPI_SS (USCIx_CTL0) CTLOINV=1 SCLKMODE=0x0 SPI_CLK (USCIx_CLK) SCLKMODE=0x2 SPI_MOSI TX0[6] TX0[0] TX1[7] TX1[6] TX0[7] TX1[0] (USCIx_DAT0) SPI_MISO RX0[6] RX0[0] RX1[7] RX1[6] RX0[7] RX1[0] (USCIx_DAT1) Slave Mode: FUNMODE=0x1, SLAVE=1, SLV3WIRE=0, LSB=0, DWIDTH=0x8 Note: x = 0, 1 Figure 6.13-16 SPI Timing in Slave Mode CTLOINV=0 SPI_SS (USCIx_CTL0)
Page 359 Mini57 3. Set FUNMODE (USPI_CTL[2:0]) to 0x1 to select SPI mode. 4. Set USPI_BRGEN register to determine the SPI bus clock frequency. 5. According to the requirements of user’s application, configured the settings as follows.  CTLOINV (USPI_LINECTL[7]): If the slave selection signal is active low, set this bit to 1; otherwise, set it to 0.
Page 360 Mini57 6.13.5.13 Wake-up Function The USCI Controller in SPI mode supports wake-up system function. The wake-up source in SPI protocol is the transition of input slave select signal. Apr. 06, 2017 Page 360 of 475 Rev.1.00...
Page 361: Register Map
Mini57 6.13.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value USPI Base Address: USPIx_BA = 0x4007_0000 + (0x10_0000 * x) x = 0, 1 USPI_CTL USPIx_BA+0x00 R/W USCI Control Register 0x0000_0000 x = 0, 1 USPI_INTEN...
Page 362: Register Description
Mini57 6.13.7 Register Description USCI Control Register (USPI_CTL) Register Offset Description Reset Value USPI_CTL USPIx_BA+0x00 USCI Control Register 0x0000_0000 x = 0, 1 Reserved Reserved Reserved Reserved FUNMODE Bits Description [31:3] Reserved Reserved. Function Mode This bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI.
Page 363 Mini57 USCI Interrupt Enable Register (USPI_INTEN) Register Offset Description Reset Value USPI_INTEN USPIx_BA+0x04 USCI Interrupt Enable Register 0x0000_0000 x = 0, 1 Reserved Reserved Reserved Reserved RXENDIEN RXSTIEN TXENDIEN TXSTIEN Reserved Bits Description [31:5] Reserved Reserved. Receive End Interrupt Enable Bit This bit enables the interrupt generation in case of a receive finish event.
Page 364 Mini57 USCI Baud Rate Generator Register (USPI_BRGEN) Register Offset Description Reset Value USPI_BRGEN USPIx_BA+0x08 USCI Baud Rate Generator Register 0x0000_3C00 x = 0, 1 Reserved CLKDIV CLKDIV Reserved Reserved TMCNTSRC TMCNTEN SPCLKSEL PTCLKSEL RCLKSEL Bits Description [31:26] Reserved Reserved. Clock Divider [25:16] CLKDIV This bit field defines the ratio between the protocol clock frequency f...
Page 365 Mini57 Reference Clock Source Selection This bit selects the source of reference clock (f REF_CLK RCLKSEL 0 = Peripheral device clock f PCLK. 1 = HXT/LXT. Apr. 06, 2017 Page 365 of 475 Rev.1.00...
Page 366 Mini57 USCI Input Data Signal Configuration (USPI_DATIN0) Register Offset Description Reset Value USPI_DATIN0 USCI Input Data Signal Configuration Register 0 0x0000_0000 x = 0, 1 USPIx_BA+0x10 Reserved Reserved Reserved Reserved ININV Reserved SYNCSEL Bits Description [31:0] Reserved Reserved. Input Signal Inverse Selection This bit defines the inverter enable of the input asynchronous signal.
Page 367 Mini57 USCI Input Control Signal Configuration (USPI_CTLIN0) Register Offset Description Reset Value USPI_CTLIN0 USPIx_BA+0x20 USCI Input Control Signal Configuration Register 0 0x0000_0000 x = 0, 1 Reserved Reserved Reserved Reserved ININV Reserved SYNCSEL Bits Description [31:3] Reserved Reserved. Input Signal Inverse Selection This bit defines the inverter enable of the input asynchronous signal.
Page 368 Mini57 USCI Input Clock Signal Configuration (USPI_CLKIN) Register Offset Description Reset Value USPI_CLKIN USPIx_BA+0x28 USCI Input Clock Signal Configuration Register 0x0000_0000 x = 0, 1 Reserved Reserved Reserved Reserved SYNCSEL Bits Description [31:1] Reserved Reserved. Input Synchronization Signal Selection This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
Page 369 Mini57 USCI Line Control Register (USPI_LINECTL) Register Offset Description Reset Value USPI_LINECTL USPIx_BA+0x2C USCI Line Control Register 0x0000_0000 x = 0, 1 Reserved Reserved Reserved DWIDTH CTLOINV Reserved DATOINV Reserved Bits Description [31:12] Reserved Reserved. Word Length of Transmission This bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer.
Page 370 Mini57 Reserved [4:1] Reserved. LSB First Transmission Selection 0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first. 1 = The LSB, the bit 0 of data buffer, will be transmitted/received first. Apr.
Page 371 Mini57 USCI Transmit Data Register (USPI_TXDAT) Register Offset Description Reset Value USPI_TXDAT USPIx_BA+0x30 USCI Transmit Data Register 0x0000_0000 x = 0, 1 Reserved Reserved TXDAT TXDAT Bits Description [31:16] Reserved Reserved. Transmit Data Software can use this bit field to write 16-bit transmit data for transmission. In order to [15:0] TXDAT avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8])
Page 372 Mini57 USCI Receive Data Register (USPI_RXDAT) Register Offset Description Reset Value USPI_RXDAT USPIx_BA+0x34 USCI Receive Data Register 0x0000_0000 x = 0, 1 Reserved Reserved RXDAT RXDAT Bits Description [31:16] Reserved Reserved. Received Data [15:0] RXDAT This bit field monitors the received data which stored in receive data buffer. Apr.
Page 373 Mini57 USCI Transmit/Receive Buffer Control Register (USPI_BUFCTL) Register Offset Description Reset Value USPI_BUFCTL USPIx_BA+0x38 USCI Transmit/Receive Buffer Control Register 0x0000_0000 x = 0, 1 Reserved Reserved RXRST TXRST RXCLR RXOVIEN Reserved TXCLR TXUDRIEN Reserved Bits Description [31:18] Reserved Reserved. Receive Reset 0 = No effect.
Page 374 Mini57 Slave Transmit Under-run Interrupt Enable Bit TXUDRIEN 0 = Transmit under-run interrupt Disabled. 1 = Transmit under-run interrupt Enabled. Reserved [5:0] Reserved. Apr. 06, 2017 Page 374 of 475 Rev.1.00...
Page 375 Mini57 USCI Transmit/Receive Buffer Status Register (USPI_BUFSTS) Register Offset Description Reset Value USPI_BUFSTS USPIx_BA+0x3C USCI Transmit/Receive Buffer Status Register 0x0000_0101 x = 0, 1 Reserved Reserved Reserved TXUDRIF Reserved TXFULL TXEMPTY Reserved RXOVIF Reserved RXFULL RXEMPTY Bits Description [31:12] Reserved Reserved.
Page 376 Mini57 1 = Receive buffer is full. Apr. 06, 2017 Page 376 of 475 Rev.1.00...
Page 377 Mini57 USCI Wake-up Control Register (USPI_WKCTL) Register Offset Description Reset Value USPI_WKCTL USPIx_BA+0x54 USCI Wake-up Control Register 0x0000_0000 x = 0, 1 Reserved Reserved Reserved Reserved PDBOPT Reserved WKEN Bits Description [31:3] Reserved Reserved. Power Down Blocking Option 0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately.
Page 378 Mini57 USCI Wake-up Status Register (USPI_WKSTS) Register Offset Description Reset Value USPI_WKSTS USPIx_BA+0x58 USCI Wake-up Status Register 0x0000_0000 x = 0, 1 Reserved Reserved Reserved Reserved Bits Description [31:1] Reserved Reserved. Wake-up Flag When chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
Page 379 Mini57 USCI Protocol Control Register – SPI (USPI_PROTCTL) Register Offset Description Reset Value USPI_PROTCTL USPIx_BA+0x5C R/W USCI Protocol Control Register 0x0000_0300 x = 0, 1 PROTEN Reserved TXUDRPOL Reserved SLVTOCNT SLVTOCNT Reserved TSMSEL SUSPITV SCLKMODE Reserved AUTOSS SLV3WIRE SLAVE Bits Description SPI Protocol Enable Bit PROTEN...
Page 380 Mini57 transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.
Page 381 Mini57 USCI Protocol Interrupt Enable Register – SPI (USPI_PROTIEN) Register Offset Description Reset Value USPI_PROTIEN USPIx_BA+0x60 USCI Protocol Interrupt Enable Register 0x0000_0000 x = 0, 1 Reserved Reserved Reserved Reserved SLVBEIEN SLVTOIEN SSACTIEN SSINAIEN Bits Description [31:4] Reserved Reserved. Slave Mode Bit Count Error Interrupt Enable Bit If data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH SLVBEIEN...
Page 382 Mini57 USCI Protocol Status Register – SPI (USPI_PROTSTS) Register Offset Description Reset Value USPI_PROTSTS USPIx_BA+0x64 USCI Protocol Status Register 0x0000_0000 x = 0, 1 Reserved Reserved SLVUDR BUSY SSLINE Reserved SSACTIF SSINAIF Reserved SLVBEIF SLVTOIF RXENDIF RXSTIF TXENDIF TXSTIF Reserved Bits Description [31:19]...
Page 383 Mini57 software writes one to this bit 0 = The slave select signal has not changed to active. 1 = The slave select signal has changed to active. Note: The internal slave select signal is active high. Slave Select Inactive Interrupt Flag (for Slave Only) This bit indicates that the internal slave select signal has changed to inactive.
Page 384: Usci - I C Mode
Mini57 6.14 USCI – I C Mode 6.14.1 Overview On I C bus, data is transferred between a Master and a Slave. Data bits transfer on the SCL and SDA lines are synchronously on a byte-by-byte basis. Each data byte is 8-bit. There is one SCL clock pulse for each data bit with the MSB being transmitted first, and an acknowledge bit follows each transferred byte.
Page 385: Block Diagram
Mini57 6.14.3 Block Diagram PCLK Baud Rate USCI_CLK Generation Peripheral Input Protocol USCI_DATx Device Data Processor Processor Buffer Data User Shift Control Buffer Unit Interface Unit Output Configuration Wake-up Control Control Register To Interrupt Interrupt Signal Generation Figure 6.14-2 USCI - I²C Mode Block Diagram 6.14.4 Basic Configuration The basic configurations of USCI0 for I2C are as follows: ...
Page 386: Figure 6.14-3 I 2 C Protocol
Mini57 6.14.5.2 START or Repeated START Signal Figure 6.14-3 shows the typical I C protocol. Normally, a standard communication consists of four parts:  START or Repeated START signal generation  Slave address and R/W bit transfer  Data transfer ...
Page 387 Mini57 6.14.5.4 Slave Address Transfer After a (repeated) start condition, the master sends a slave address to identify the target device of the communication. The start address can comprise one or two address bytes (for 7-bit or for 10- bit addressing schemes). After an address byte, a slave sensitive to the transmitted address has to acknowledge the reception.
Page 388: Figure 6.14-5 Bit Transfer On I C Bus
Mini57 Data line stable; Change of data data valid allowed Figure 6.14-5 Bit Transfer on I C Bus If the master received data, does Not Acknowledge (NACK) the slave, the slave releases the SDA line for the master to generate a STOP or Repeated START signal. Clock pulse for acknowledgement from Master...
Page 389 Mini57 to define the number of data sample time per bit time The standard setting is given by RCLKSEL = 0 (f ), PTCLKSEL = 0 (f REF_CLK PCLK PROT_CLK ) and SPCLKSEL = 2’b00 (f ). Under these conditions, the baud rate is REF_CLK SAMP_CLK DIV_CLK...
Page 390: Figure 6.14-7 Arbitration Lost
Mini57 Master 1 loses arbitration DATA 1 ≠ SDA DATA1 DATA2 Figure 6.14-7 Arbitration Lost In this case, during the address and data transmission, the master transmitter checks at the rising edge of SCL for each data bit if the value it is sending is equal to the value read on the SDA line. If yes, the next data bit values can be 0.
Page 391 Mini57 C Protocol Interrupt Events The following protocol-related events are generated in I C mode and can lead to a protocol interrupt. Please note that the bits in register UI2C_PROTSTS are not all automatically cleared by hardware and have to be cleared by software to monitor new incoming events. ...
Page 392: Figure 6.14-8 Control I
Mini57 Control flow The on-chip I C ports support three operation modes, Master, Slave, and General Call Mode. In a given application, I C port may operate as a master or as a slave. In Slave mode, the I C port hardware looks for its own slave address and the general call address.
Page 393: Figure 6.14-9 Master Transmits Data To Slave With A 7-Bit Address
Mini57 Data Transfer on the I C Bus Figure 6.14-9 shows a master transmits data to slave. A master addresses a slave with a 7-bit address and 1-bit write index to denote that the master wants to transmit data to the slave. The master keeps transmitting data after the slave returns acknowledge to the master.
Page 394: Figure 6.14-12 Master Reads Data From Slave By 10-Bit Address
Mini57 ADDRESS 1st byte ADDRESS 2nd byte ‘0’ : write 11110XX ADDRESS 1st byte DATA DATA data transfer ‘1’ : read (n bytes + acknowlegde) 11110XX Figure 6.14-12 Master Reads Data from Slave by 10-bit Address Master Mode In Figure 6.14-13, all possible protocols for I C master are shown.
Page 395: Figure 6.14-14 Master Receiver Mode Control Flow With 7-Bit Address
Mini57 ACKIF = 1 STARIF = 1 ACKIF = 1 TXDAT RXDAT (SLA+R) (Data) (RTRG, STA, STO, AA)=(0, 1, 0, x) (PTRG, STA, STO, AA)=(1, 0, 0, 1) Clear protocol status register Writing 1 to ACKIF ARBLOIF = 1 TXDAT = SLA+R RXDAT (PTRG, STA, STO, AA)=(1, 0, 0, x) Write 1 to STARIF...
Page 396: Figure 6.14-15 Save Mode Control Flow With 7-Bit Address
Mini57 arbitration lost, the ARBLOIF will be set to 1. C communication, the SCL clock will be released when writing ‘1’ to PTRG Note: During I (UI2C_PROTCTL [5]) in Slave mode. ACKIF = 1 ACKIF = 1 Switch to not addressed mode Own SLA will be recognized RXDAT RXDAT...
Page 397 Mini57 START, the register STORIF (UI2C_PROTSTS [9]) or STARIF (UI2C_PROTSTS [8]) will be set. User could follow the action for NACKIF (UI2C_PROTSTS [10]) as shown in Figure 6.14-15 when got STARIF (UI2C_PROTSTS [8]) is set. Note: After slave gets interrupt flag of NACKIF (UI2C_PROTSTS [10]) and start/stop symbol including STARIF (UI2C_PROTSTS [8]) and STORIF (UI2C_PROTSTS [9]), slave can switch to not address mode and own SLA will not be recognized.
Page 398: Figure 6.14-16 Gc Mode With 7-Bit Address
Mini57 ACKIF = 1 ACKIF = 1 Switch to not addressed mode Address 0x0 will be recognized RXDAT RXDAT (SLA+W=0x00) (Data) (PTRG, STA, STO, AA)=(0, 0, 0, 1) (PTRG, STA, STO, AA)=(1, 0, 0, 1) GCFUNC = 1 Writing 1 to ACKIF Clear protocol status register ACKIF = 1 RXDAT...
Page 399: Figure 6.14-17 Setup Time Wrong Adjustment
Mini57 Protocol Functional Description Programmable Setup and Hold Time To guarantee a correct data setup and hold time, the timing must be configured. By programming HTCTL [5:0] (UI2C_TMCTL[11:6]) to configure hold time and STCTL [5:0] (UI2C_TMCTL[5:0]) to configure setup time. The delay timing refer peripheral clock (PCLK).
Page 400: Figure 6.14-18 Hold Time Wrong Adjustment
Mini57 decides PCLK = 12MHz and baud rate =100k, the UI2C_BRGEN[25:16] must set 59, and the HTCTL [5:0] maximum value is 51. Bus error SDA delay over SCL low duty Figure 6.14-18 Hold Time Wrong Adjustment C Time-out Function There is a time-out counter TOCNT (UI2C_PROTCTL [25:16]) which can be used to deal with the C bus hang-up.
Page 401: Figure 6.14-20 Eeprom Random Read
Mini57 confirm this frame has transaction done and then to do the wake-up procedure. Therefore, when the chip is woken-up by address match with one of the device address register (UI2C_DEVADDR0), the user shall check the WKAKDONE (UI2C_PROTSTS [16]) bit is set to 1 to confirm the address wake-up frame has done.
Page 402: Figure 6.14-21 Protocol Of Eeprom Random Read
Mini57 Figure 6.14-21 shows how to use the I C controller to implement the protocol of EEPROM random read. STARIF = 1 ACKIF = 1 TXDAT TXDAT (SLA+W) ROM Address High Byte TXDAT = SLA+W TXDAT = Data (PTRG, STA, STO, AA)=(1, 0, 0, x) STORIF = 1 NACKIF = 1 ((PTRG, STA, STO, AA)=(1, 0, 0, x)
Page 403: Register Map
Mini57 6.14.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value UI2C Base Address: UI2Cx_BA = 0x4007_0000 + (0x10_0000 * x) x = 0, 1 UI2C_CTL R/W USCI Control Register 0x0000_0000 UI2Cx_BA+0x00 UI2C_BRGEN...
Page 404: Register Description
Mini57 6.14.7 Register Description USCI Control Register (UI2C_CTL) Register Offset Description Reset Value UI2C_CTL UI2Cx_BA+0x00 USCI Control Register 0x0000_0000 Reserved Reserved Reserved Reserved FUNMODE Bits Description [31:3] Reserved Reserved. Function Mode This bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI.
Page 405 Mini57 USCI Baud Rate Generator Register (UI2C_BRGEN) Register Offset Description Reset Value UI2C_BRGEN UI2Cx_BA+0x08 USCI Baud Rate Generator Register 0x0000_3C00 Reserved CLKDIV CLKDIV Reserved DSCNT PDSCNT Reserved TMCNTSRC TMCNTEN SPCLKSEL PTCLKSEL RCLKSEL Bits Description [31:26] Reserved Reserved. Clock Divider This bit field defines the ratio between the protocol clock frequency f and the clock PROT_CLK divider frequency f...
Page 406 Mini57 This bit field used for the clock source selection of a sample clock (f ) for the SAMP_CLK protocol processor. 00 = f SAMP_CLK DIV_CLK. 01 = f SAMP_CLK PROT_CLK. 10 = f SAMP_CLK SCLK. 11 = f SAMP_CLK REF_CLK.
Page 407 Mini57 USCI Line Control Register (UI2C_LINECTL) Register Offset Description Reset Value UI2C_LINECTL UI2Cx_BA+0x2C USCI Line Control Register 0x0000_0000 Reserved Reserved Reserved DWIDTH Reserved Bits Description [31:12] Reserved Reserved. Word Length of Transmission This bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer.
Page 408 Mini57 USCI Transmit Data Register (UI2C_TXDAT) Register Offset Description Reset Value UI2C_TXDAT UI2Cx_BA+0x30 USCI Transmit Data Register 0x0000_0000 Reserved Reserved TXDAT TXDAT Bits Description [31:16] Reserved Reserved. Transmit Data [15:0] TXDAT Software can use this bit field to write 16-bit transmit data for transmission. Apr.
Page 409 Mini57 USCI Receive Data Register (UI2C_RXDAT) Register Offset Description Reset Value UI2C_RXDAT UI2Cx_BA+0x34 USCI Receive Data Register 0x0000_0000 Reserved Reserved RXDAT RXDAT Bits Description [31:16] Reserved Reserved. Received Data [15:0] RXDAT This bit field monitors the received data which stored in receive data buffer. Note 1: In I C protocol, only use RXDAT[7:0].
Page 410 Mini57 USCI Device Address Register (UI2C_DEVADDR) Register Offset R/W Description Reset Value UI2C_DEVADDR0 UI2Cx_BA+0x44 R/W USCI Device Address Register 0 0x0000_0000 Reserved Reserved Reserved DEVADDR DEVADDR Bits Description [31:10] Reserved Reserved. Device Address In I C protocol, this bit field contains the programmed slave address. If the first received address byte is b1111 0AAX, the AA bits are compared to the bits DEVADDR[9:8] to [9:0] DEVADDR...
Page 411 Mini57 USCI Device Address Mask Register (UI2C_ADDRMSK) – for I C Only Register Offset R/W Description Reset Value UI2C_ADDRMSK0 UI2Cx_BA+0x4C R/W USCI Device Address Mask Register 0 0x0000_0000 Reserved Reserved Reserved ADDRMSK ADDRMSK Bits Description [31:10] Reserved Reserved. USCI Device Address Mask 0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
Page 412 Mini57 USCI Wake-up Control Register (UI2C_WKCTL) Register Offset Description Reset Value UI2C_WKCTL UI2Cx_BA+0x54 USCI Wake-up Control Register 0x0000_0000 Reserved Reserved Reserved Reserved WKADDREN WKEN Bits Description [31:2] Reserved Reserved. Wake-up Address Match Enable Bit WKADDREN 0 = The chip is woken up according to data toggle. 1 = The chip is woken up according to address match.
Page 413 Mini57 USCI Wake-up Status Register (UI2C_WKSTS) Register Offset Description Reset Value UI2C_WKSTS UI2Cx_BA+0x58 USCI Wake-up Status Register 0x0000_0000 Reserved Reserved Reserved Reserved Bits Description [31:1] Reserved Reserved. Wake-up Flag When chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
Page 414 Mini57 USCI Protocol Control Register – I C (UI2C_PROTCTL) Register Offset Description Reset Value UI2C_PROTCTL UI2Cx_BA+0x5C USCI Protocol Control Register 0x0000_0000 PROTEN Reserved TOCNT TOCNT Reserved Reserved PTRG ADDR10EN GCFUNC Bits Description C Protocol Enable Bit [31] PROTEN 0 = I C Protocol disable.
Page 415 Mini57 Assert Acknowledge Control When AA =1 prior to address or data received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter.
Page 416 Mini57 USCI Protocol Interrupt Enable Register – I C (UI2C_PROTIEN) Register Offset Description Reset Value UI2C_PROTIEN UI2Cx_BA+0x60 USCI Protocol Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved ACKIEN ERRIEN ARBLOIEN NACKIEN STORIEN STARIEN TOIEN Bits Description [31:7] Reserved Reserved. Acknowledge Interrupt Enable Bit This bit enables the generation of a protocol interrupt if an acknowledge is detected by a master.
Page 417 Mini57 Start Condition Received Interrupt Enable Bit This bit enables the generation of a protocol interrupt if a start condition is detected. STARIEN 0 = The start condition interrupt Disabled. 1 = The start condition interrupt Enabled. Time-out Interrupt Enable Bit In I C protocol, this bit enables the interrupt generation in case of a time-out event.
Page 418 Mini57 USCI Protocol Status Register – I C (UI2C_PROTSTS) Register Offset Description Reset Value UI2C_PROTSTS UI2Cx_BA+0x64 USCI Protocol Status Register 0x0000_0000 Reserved Reserved BUSHANG WRSTSWK WKAKDONE SLAREAD SLASEL ACKIF ERRIF ARBLOIF NACKIF STORIF STARIF Reserved ONBUSY TOIF Reserved Bits Description [31:19] Reserved Reserved.
Page 419 Mini57 Acknowledge Received Interrupt Flag This bit indicates that an acknowledge has been received in master mode. This bit is not set in slave mode. A protocol interrupt can be generated if UI2C_PROTCTL.ACKIEN = 1. ACKIF [13] 0 = An acknowledge has not been received. 1 = An acknowledge has been received.
Page 420 Mini57 1 = The bus is busy. Time-out Interrupt Flag 0 = A time-out interrupt status has not occurred. TOIF 1 = A time-out interrupt status has occurred. Note: It is cleared by software writing one into this bit [4:3] Reserved Reserved.
Page 421 Mini57 USCI Timing Configure Control Register (UI2C_TMCTL) Register Offset Description Reset Value UI2C_TMCTL UI2Cx_BA+0x8C C Timing Configure Control Register 0x0000_0000 Reserved Reserved Reserved HTCTL HTCTL STCTL Bits Description [31:8] Reserved Reserved. Hold Time Configure Control Register This field is used to generate the delay timing between SCL falling edge SDA edge in [11:6] HTCTL transmission mode.
Page 422: Hardware Divider (Hdiv)
Mini57 6.15 Hardware Divider (HDIV) 6.15.1 Overview The hardware divider (HDIV) is useful to the high performance application. The hardware divider is a signed, integer divider with both quotient and remainder outputs. 6.15.2 Features  Signed (two’s complement) integer calculation ...
Page 423: Functional Description
Mini57 6.15.4 Functional Description To use hardware divider, it needs to set dividend first. Then set divisor and the hardware divider will trigger calculation automatically after divisor written. The calculation results including the quotient and remainder could be got by reading QUOTIENT (HDIV_QUOTIENT[31:0]) and REM (HDIV_REM[31:0]) register.
Page 424: Register Map
Mini57 6.15.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value HDIV Base Address: HDIV_BA = 0x5001_4000 HDIV_DIVIDEND HDIV_BA+0x00 R/W Dividend Source Register 0x0000_0000 HDIV_DIVISOR HDIV_BA+0x04 R/W Divisor Source Resister 0x0000_FFFF HDIV_QUOTIENT HDIV_BA+0x08 R/W Quotient Result Resister...
Page 425: Register Description
Mini57 6.15.6 Register Description Dividend Source Register (HDIV_DIVIDEND) Register Offset Description Reset Value HDIV_DIVIDEND HDIV_BA+0x00 Dividend Source Register 0x0000_0000 DIVIDEND DIVIDEND DIVIDEND DIVIDEND Bits Description Dividend Source [31:0] DIVIDEND This register is given the dividend of divider before calculation is started. Apr.
Page 426 Mini57 Divisor Source Register (HDIV_DIVISOR) Register Offset Description Reset Value HDIV_DIVISOR HDIV_BA+0x04 Divisor Source Resister 0x0000_FFFF Reserved Reserved DIVISOR DIVISOR Bits Description [31:16] Reserved Reserved. Divisor Source [15:0] DIVISOR This register is given the divisor of divider before calculation starts. Note: When this register is written, hardware divider will start calculation.
Page 427 Mini57 Quotient Result Register (HDIV_QUOTIENT) Register Offset Description Reset Value HDIV_QUOTIENT HDIV_BA+0x08 Quotient Result Resister 0x0000_0000 QUOTIENT QUOTIENT QUOTIENT QUOTIENT Bits Description Quotient Result [31:0] QUOTIENT This register holds the quotient result of divider after calculation is completed. Apr. 06, 2017 Page 427 of 475 Rev.1.00...
Page 428 Mini57 Remainder Result Register (HDIV_REM) Register Offset Description Reset Value HDIV_REM HDIV_BA+0x0C Remainder Result Register 0x0000_0000 Bits Description Remainder Result [31:0] The remainder of hardware divider is 16-bit sign integer (REM[15:0]) with sign extension (REM[31:16]) to 32-bit integer. Apr. 06, 2017 Page 428 of 475 Rev.1.00...
Page 429 Mini57 Divider Status Register (HDIV_STATUS) Register Offset Description Reset Value HDIV_STATUS HDIV_BA+0x10 Divider Status Register 0x0000_0001 Reserved Reserved Reserved Reserved DIVBYZERO Reserved Bits Description [31:2] Reserved Reserved. Divisor Zero Warning (Read Only) 0 = The divisor is not 0. DIVBYZERO 1 = The divisor is 0.
Page 430: Analog To Digital Converter (Adc)
Mini57 6.16 Analog to Digital Converter (ADC) 1.1.1 Overview The Mini57 series contains one 12-bit successive approximation analog-to-digital converter (SAR A/D converter) with 8 single-end external input channels. The A/D converters can be started by software, external pin (STADC/PC.1) or PWM trigger. 1.1.2 Features ...
Page 431: Basic Configuration
Mini57 6.16.1 Basic Configuration The Mini57 series has two sample and hold (S/H) to sampling two input ADC channel simultaneously. And support four type operating mode for BLDC motor used. The ADC pin functions are configured in SYS_PB_MFP, SYS_PC_MFP and SYS_PD_MFP register.
Page 432: Figure 6.16-3 Single Mode Conversion Timing Diagram
Mini57 6.16.2.2 ADC Operation A/D conversion is performed only once on the specified single channel. The operation is as follows: A/D conversion will be started when the ADCnSWTRG bit of ADC_CTL is set to 1 by software or hardware trigger input. When A/D conversion is finished, the result is stored in the A/D data register.
Page 433: Figure 6.16-4 Adc Hardware Trigger Source
Mini57 ADCnSTADCSEL (ADC_TRGSOR[23:22]/[7:6]) Trigger level select STADC Rising/Falling/ (external pin) Rising-Falling EPWM0 EPWM1 Trigger level select EPWM2 Falling/Center/ EPWM3 Rising/Period TM0_ADC EPWM4 TM1_ADC trigger EPWM5 TM2_ADC source ADC0F ADC1F ADCnPWMTRGSEL (ADC_TRGSOR[21:20]/[5:4]) ADCnTRGSOR Note: n = 0,1 (ADC_TRGSOR[3:0]) Figure 6.16-4 ADC Hardware Trigger Source 6.16.2.5 Conversion Result Monitor by Window Compare Mode Function The ADC controller in the Mini57 series provides a window comparator function, Software can write ADC_WCMPDAT register to set low and high bound range and to monitor three step ADC...
Page 434: Figure 6.16-6 Simultaneous Simple Mode Conversion Timing Diagram
Mini57 6.16.2.8 Independent 2SH Mode The Mini57 can also be set to independent, but it needs to convert S/H twice continuously (S/H0 and S/H1) and only generates ADC0IF interrupt when ADCMODE is set as 01b (ADC_CTL[7:6]). For example, ADC0 trigger source is set as PWM0 and ADC1 trigger source is set as PWM2. If PWM0 triggers ADC0 first, when ADC0 conversion is finished, it does not generate interrupts, and needs to wait for ADC1 conversion.
Page 435: Register Map
Mini57 6.16.3 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value ADC Base Address: ADC_BA = 0x400E_0000 ADC_DAT0 ADC_BA+0x00 ADC data register 0 0x0000_0000 ADC_DAT1 ADC_BA+0x04 ADC Data Register 1 0x0000_0000 ADC_CTL ADC_BA+0x20 ADC Control Register...
Page 436: Register Description
Mini57 6.16.4 Register Description ADC Data Register 0 (ADC_DAT0) Register Offset R/W Description Reset Value ADC_DAT0 ADC_BA+0x00 ADC data register 0 0x0000_0000 ADC1VALID ADC1OV Reserved ADC1DAT0 ADC1DAT0 ADC0VALID ADC0OV Reserved ADC0DAT0 ADC0DAT0 Bits Description ADC1 Valid Flag 0 = Data in ADC1DAT0[27:16] bits not valid. [31] ADC1VALID 1 = Data in ADC1DAT0[27:16] bits valid.
Page 437 Mini57 Bits Description ADC0 over Run Flag 0 = Data in ADC0DAT0[11:0] is recent conversion result. 1 = Data in ADC0DAT0[11:0] overwritten. [14] ADC0OV Note1: If converted data in ADC0DAT0[11:0] has not been read before the new conversion result is loaded to this register, OV is set to “1”. Note2: It is cleared by hardware after the ADC_DAT0 register is read.
Page 438 Mini57 ADC Data Register 1 (ADC_DAT1) Register Offset Description Reset Value ADC_DAT1 ADC_BA+0x04 ADC Data Register 1 0x0000_0000 ADC1VALID ADC1OV Reserved ADC1DAT1 ADC1DAT1 ADC0VALID ADC0OV Reserved ADC0DAT1 ADC0DAT1 Bits Description ADC1 Valid Flag 0 = Data in ADC1DAT1[27:16] bits not valid. ADC1VALID [31] 1 = Data in ADC1DAT1[27:16] bits valid.
Page 439 Mini57 Bits Description ADC0 Conversion Result for FIFO1 [11:0] ADC0DAT1 This field contains conversion result of ADC. Apr. 06, 2017 Page 439 of 475 Rev.1.00...
Page 440 Mini57 ADC Control Register (ADC_CTL) Register Offset Description Reset Value ADC_CTL ADC_BA+0x20 ADC Control Register 0x0000_0000 Reserved ADC1SEQSEL Reserved ADC1CHSEL Reserved ADC0SEQSEL Reserved ADC0CHSEL Reserved ADC1SWTRG ADC1HWTRG ADC1IEN Reserved ADCMODE ADCSS3R Reserved ADC0SWTRG ADC0HWTRG ADC0IEN ADCEN Bits Description [31] Reserved Reserved.
Page 441 Mini57 Bits Description ADC0 Sequential Input Pin Selection 000 = ADC0_CH0. 001 = ADC0_CH1. 010 = ADC0_CH2. ADC0SEQSEL 011 = ADC0_CH3. [22:20] 100 = ADC0_CH4. 101 = PGA_ADC. 110 = BAND_GAP. 111 = VSS. [19] Reserved Reserved. ADC1 Channel Select 000 = ADC0_CH0.
Page 442 Mini57 Bits Description Reserved Reserved. ADC0 Conversion Start 0 = Conversion stopped and A/D converter entered idle state. ADC0SWTRG 1 = Conversion start. Note: ADC0SWTRG can be set to “1” from two sources: software and external pin STADC. This bit will be cleared to “0” by hardware automatically. Hardware Trigger ADC Convertion Enable Enable or disable triggering of A/D conversion by Hardware (PWM, Timer, ADC self) ADC0HWTRGEN...
Page 443 Mini57 ADC Hardware Trigger Source Control Register (ADC_TRGSOR) Register Offset Description Reset Value ADC_TRGSOR ADC_BA+0x24 ADC Hardware Trigger Source Control Register 0x0000_0000 Reserved ADC1STADCSEL ADC1PWMTRGSEL ADC1TRGSOR Reserved ADC0STADCSEL ADC0PWMTRGSEL ADC0TRGSOR Bits Description [31:24] Reserved Reserved. ADC1 External Trigger Pin (STADC) Trigger Selection 00 = Rising.
Page 444 Mini57 Bits Description ADC0 External Trigger Pin (STADC) Trigger Selection 00 = Rising. ADC0STADCSEL 01 = Falling. [7:6] 10 = Rising or Falling. 11 = Reserved. PWM Trigger Selection for ADC0 00 = EPWM Signal Falling. ADC0PWMTRGSE [5:4] 01 = EPWM Counter Central. 10 = EPWM signal Rising.
Page 445 Mini57 ADC Trigger Delay Control Register (ADC_TRGDLY) Register Offset Description Reset Value ADC_TRGDLY ADC_BA+0x28 ADC Trigger Delay Control Register 0x0000_0000 Reserved ADC1DELAY Reserved ADC0DELAY Bits Description [31:24] Reserved Reserved. ADC1 Trigger Delay Timer Setting this field will delay ADC start conversion time after ADCxTRGCTL trigger is [23:16] ADC1DELAY coming.
Page 446 Mini57 ADC Sampling Time Counter Register (ADC_SMPCNT) Register Offset Description Reset Value ADC_SMPCNT ADC_BA+0x2C ADC Sampling Time Counter Register 0x0000_0005 Reserved Reserved Reserved Reserved ADCSMPCNT Bits Description [31:4] Reserved Reserved. ADC Sampling Counter ADC sampling counters are 6 ADC clock is suggestion 0 = 1 * ADC Clock.
Page 447 Mini57 ADC Status Register (ADC_STATUS) Register Offset Description Reset Value ADC_STATUS ADC_BA+0x30 ADC Status Register 0x0000_0000 Reserved Reserved HIGHFG MIDFG LOWFG WCMPIF ADC1CH ADC1BUSY Reserved ADC1OV ADC1IF ADC0CH ADC0BUSY Reserved ADC0OV ADC0IF Bits Description [31:20] Reserved Reserved. Window Comparator High Bound Flag When A/D conversion result higher than the setting condition in High Bound (WCMPHIGHDAT), this bit is set to “1”.
Page 448 Mini57 Bits Description Current Conversion Channel This filed reflects the current conversion channel when ADC1BUSY =1. [15:12] ADC1CH When ADC1BUSY =0, it shows the number of the next converted channel. It is read only. BUSY/IDLE 0 = A/D converter is in idle state. [11] ADC1BUSY 1 = A/D converter is busy at conversion.
Page 449 Mini57 ADC Window Comparator Control Register (ADC_WCMPCTL) Register Offset Description Reset Value ADC_WCMPC ADC_BA+0x34 ADC Window Comparator Control Register 0x0000_0000 Reserved Reserved Reserved WCMPMCNT WFLAGCTL WCMPHIGHE WCMPMIDEN WCMPLOWE Reserved WCMPIEN WCMPEN Bits Description [31:12] Reserved Reserved. Window Compare Match Count When the A/D conversion result matches the compare condition defined Flag...
Page 450 Mini57 Bits Description Window Comparator Interrupt Enable Bit WCMPIEN 0 = Window Comparator Interrupt Disabled. 1 = Window Comparator Interrupt Enabled. Window Comparator Enable Bit WCMPEN 0 = Window Comparator Disabled. 1 = Window Comparator Enabled. Apr. 06, 2017 Page 450 of 475 Rev.1.00...
Page 451 Mini57 ADC Window Comparator Data Register (ADC_WCMPDAT) Register Offset Description Reset Value ADC_WCMPD ADC_BA+0x38 ADC Window Comparator Data Register 0x0000_0000 Reserved WCMPHIGHDAT WCMPHIGHDAT Reserved WCMPLOWDAT WCMPLOWDAT Bits Description [31:28] Reserved Reserved. [27:16] WCMPHIGHDAT Window Comparator High Bound Data [15:12] Reserved Reserved.
Page 452: Analog Comparator (Acmp)
Mini57 6.17 Analog Comparator (ACMP) 6.17.1 Overview The Mini57 series contains two comparators which can be used in a number of different configurations. The comparator output is logic 1 when positive input greater than negative input, otherwise the output is 0. Each comparator can be configured to generate interrupt when the comparator output value changes.
Page 453: Block Diagram
Mini57 6.17.3 Block Diagram (risingm falling, rising/falling) ACMPEN (ACMP_STATUS[1]/[0]) (ACMPn_CTL[0]) Edge ACMP_INT ACMPFx Detection PRESET CPPSEL (ACMPn_CTL[31]) ACMPIE (ACMPn_CTL[30:28]) (ACMP_STATUS[5]/[4]) EDGESEL ACMPHYSEN (ACMPn_CTL[5:4]) ACMP_PHASE (ACMPn_CTL[3:2]) ACMPn_P0 (to PWM Phase Change) NFDIS ACMPn_P1 (ACMPn_CTL[23]) ACMPn_P2 ACMPn_P3 ACMPn_O (pin) PGA_CMP ACMP Noise (ACMP_STATUS[3]/[2]) Result Filter...
Page 454: Functional Description
Mini57 6.17.5 Functional Description 6.17.5.1 Interrupt Sources The output of comparators are sampled by PCLK and reflected at ACMPOx(ACMP_STATUS[3] and ACMP_STATUS[2]). If ACMPIE(ACMP_CTLx[1]) is set to 1, the comparator interrupt will be enabled. As the output state of comparator is changed, the comparator interrupt will be asserted and the corresponding flag, ACMPFx(ACMP_STATUS[1] and ACMP_STATUS[0]), will be set.
Page 455: Comparator Reference Voltage (Crv)
Mini57 6.17.6 Comparator Reference Voltage (CRV) 6.17.6.1 Introduction The comparator reference voltage (CRV) module is responsible for generating reference voltage for comparators. The CRV module consists of resisters ladder and analog switch, and user can set the CRV output voltage using CRVCTL(ACMP_VREF[3:0]) and select the reference voltage to ACMP by setting CPNSEL ( ACMP_CTL[25:24]).
Page 456: Register Map
Mini57 6.17.7 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value ACMP Base Address: ACMP_BA = 0x400D_0000 ACMP_CTL0 ACMP_BA+0x00 R/W Analog Comparator0 Control Register 0x0000_0000 ACMP_CTL1 ACMP_BA+0x04 R/W Analog Comparator1 Control Register 0x0000_0000 ACMP_STATUS ACMP_BA+0x08...
Page 457: Register Description
Mini57 6.17.8 Register Description Analog Comparator0 Control Register (ACMP_CTL0) Register Offset Description Reset Value ACMP_CTL0 ACMP_BA+0x00 Analog Comparator0 Control Register 0x0000_0000 PRESET CPPSEL Reserved CPNSEL NFDIS Reserved NFCLKS POLARITY Reserved Reserved DLYTRGIE DLYTRGEN DLYTRGSOR DLYTRGSEL Reserved PBRKSEL EDGESEL ACMPHYSEN ACMPIE ACMPEN Bits Description...
Page 458 Mini57 Bits Description Noise Filter Clock Pre-divided Selection To determine the sampling frequency of the Noise Filter clock 00 = PCLK. [21:20] NFCLKS 01 = PCLK / 2. 10 = PCLK / 4. 11 = PCLK / 16. Analog Comparator Polarity Control [19] POLARITY 0 = Analog Comparator normal output.
Page 459 Mini57 Bits Description Comparator Interrupt Enable Bit 0 = ACMP interrupt function Disabled. ACMPIE 1 = ACMP interrupt function Enabled. Note1: Interrupt is generated if ACMPIE bit is set to “1” after ACMP conversion is finished. Note2: ACMP interrupt will wake CPU up in Power-down mode. Comparator Enable Bit 0 = Comparator Disabled.
Page 460 Mini57 Analog Comparator1 Control Register (ACMP_CTL1) Register Offset Description Reset Value ACMP_CTL1 ACMP_BA+0x04 Analog Comparator1 Control Register 0x0000_0000 PRESET CPPSEL Reserved CPNSEL NFDIS Reserved NFCLKS POLARITY Reserved Reserved DLYTRGIE DLYTRGEN DLYTRGSOR DLYTRGSEL Reserved PBRKSEL EDGESEL ACMPHYSEN ACMPIE ACMPEN Bits Description Comparator Result Preset Value [31] PRESET...
Page 461 Mini57 Bits Description Analog Comparator Polarity Control [19] POLARITY 0 = Analog Comparator normal output. 1 = Analog Comparator invert output. [18:14] Reserved Reserved. Analog Comparator Delay Trigger Mode Interrupt Enable DLYTRGIE [13] 0 = Analog Comparator Delay Trigger Mode Interrupt Disabled. 1 = Analog Comparator Delay Trigger Mode Interrupt Enabled.
Page 462 Mini57 Bits Description Comparator Enable Bit 0 = Comparator Disabled. ACMPEN 1 = Comparator Enabled. Note: Comparator output needs to wait 2 us stable time after ACMPEN is set. Apr. 06, 2017 Page 462 of 475 Rev.1.00...
Page 463 Mini57 Analog Comparator Status Register (ACMP_STATUS) Register Offset Description Reset Value ACMP_STATUS ACMP_BA+0x08 R/W Analog Comparator Status Register 0x0000_0000 Reserved Reserved Reserved DLYTRGO1 DLYTRGO0 DLYTRGF1 DLYTRGF0 ACMPO1 ACMPO0 ACMPF1 ACMPF0 Bits Description [31:8] Reserved Reserved. Analog Comparator1 Delay Trigger Mode Comparator Output DLYTRGO1 Synchronized to the APB clock to allow reading by software.
Page 464 Mini57 Bits Description Comparator0 Flag This bit is set by hardware whenever the comparator0 output changes state. This will ACMPF0 cause an interrupt if ACMPIE set. Note: Write “1” to clear this bit to 0. Apr. 06, 2017 Page 464 of 475 Rev.1.00...
Page 465 Mini57 Analog Comparator Reference Voltage Control Register (ACMP_VREF) Register Offset Description Reset Value ACMP_VREF ACMP_BA+0x0C Analog Comparator Reference Voltage Control Register 0x0000_0000 Reserved Reserved Reserved Reserved CRVCTL Bits Description [31:4] Reserved Reserved. Comparator Reference Voltage Setting [3:0] CRVCTL CRVS = AV x (1/6+CRV[3:0]/24).
Page 466 Mini57 Analog Comparator Delay Trigger Mode Dleay Register (ACMP_TRGDLY) Register Offset Description Reset Value ACMP_TRGDLY ACMP_BA+0x10 Analog Comparator Delay Trigger Mode Dleay Register 0x0000_0000 Reserved Reserved Reserved DELAY DELAY Bits Description [31:9] Reserved Reserved. DELAY Analog Comparator Delay Trigger Mode Dleay cycle [8:0] Apr.
Page 467: Programmable Gain Amplifier
Mini57 6.18 Programmable Gain Amplifier (PGA) 6.18.1 Overview The Mini57 series contains a programmable gain amplifier (PGA) which can be enabled through the PGAEN bit. User can measure the outputs of the programmable gain amplifier as the programmable gain amplifier output to the integrated A/D converter channel, where digital results can be taken.
Page 468: Register Description
Mini57 6.18.2 Register Description PGA Control Register (PGA_CTL) Register Offset Description Reset Value PGA_CTL PGA_BA+0x00 Programmable Gain Amplifier Control Register 0x0000_0000 Reserved Reserved Reserved Reserved GAIN Reserved PGAEN Bits Description [31:7] Reserved Reserved. PGA Gain Selection 000 = 2. 001 = 3. 010 = 5.
Page 469: Application Circuit
Mini57 APPLICATION CIRCUIT DVCC AVCC SPI_SS SPI Device SPI_CLK DVCC MISO SPI_MISO Power SPI_MOSI MOSI 0.1uF 0.1uF DVCC DVCC ICE_DAT ICE_CLK Interface nRESET 4.7K 4.7K XT_IN Mini57EDE I2Cx_SCL C Device TSSOP28 4~24 MHz I2Cx_SDA 32.768 kHz Crystal crystal XT_OUT DVCC Reset RS232 Transceiver PC COM Port...
Page 470: Electrical Characteristics
Mini57 ELECTRICAL CHARACTERISTICS ® For information on the Mini57 series electrical characteristics, please refer to NuMicro Mini57 Series Datasheet. Apr. 06, 2017 Page 470 of 475 Rev.1.00...
Page 471: Package Dimensions
Mini57 PACKAGE DIMENSIONS 1.2 28-Pin TSSOP (4.4x9.7x1.0 mm) Apr. 06, 2017 Page 471 of 475 Rev.1.00...
Page 472: 20-Pin Tssop (4.4X6.5X0.9 Mm)
Mini57 1.3 20-Pin TSSOP (4.4x6.5x0.9 mm) Apr. 06, 2017 Page 472 of 475 Rev.1.00...
Page 473: 33-Pin Qfn33 (4X4X0.8 Mm)
Mini57 9.1 33-pin QFN33 (4x4x0.8 mm) Apr. 06, 2017 Page 473 of 475 Rev.1.00...
Page 474: Revision History
Mini57 10 REVISION HISTORY Date Revision Description 2017.04.06 1.00 Preliminary version. Apr. 06, 2017 Page 474 of 475 Rev.1.00...
Page 475 Mini57 Important Notice Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”.

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