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Nuvoton Mini51 Series Technical Reference Manual

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NuMicro™ Mini51 Technical Reference Manual
ARM Cortex™-M0
32-BIT MICROCONTROLLER
NuMicro™ Family
Mini51 Series
Technical Reference Manual
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system
design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com

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Summary of Contents for Nuvoton Mini51 Series

  • Page 1 The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions.

  • Page 2: Table Of Contents

    NuMicro™ Mini51 Technical Reference Manual CONTENTS GENERAL DESCRIPTION ....................10 FEATURES ........................... 11 PARTS INFORMATION LIST AND PIN CONFIGURATION ..........14 NuMicro Mini51 Series Product Selection Guide ............ 14 PIN CONFIGURATION ....................15 3.2.1 LQFP 48-pin ........................15 3.2.2 QFN 33-pin ........................16 Pin Description ......................
  • Page 3 NuMicro™ Mini51 Technical Reference Manual 5.5.5 Comparator Reference Voltage (CRV) ................ 101 5.5.6 Register Map ....................... 102 5.5.7 Register Description ....................103 Analog-to-Digital Converter (ADC) Controller ............107 5.6.1 Overview ........................107 5.6.2 Features ........................107 5.6.3 Block Diagram ......................108 5.6.4 ADC Operation Procedure ...................
  • Page 4 NuMicro™ Mini51 Technical Reference Manual 5.10.10 PWM Controller Register ..................208 5.11 Serial Peripheral Interface (SPI) Controller .............. 228 5.11.1 Overview ........................228 5.11.2 Features ........................228 5.11.3 SPI Block Diagram ..................... 228 5.11.4 Functional Description ....................229 5.11.5 SPI Serial Interface Control Register Map ..............239 5.11.6 Register Description ....................
  • Page 5 NuMicro™ Mini51 Technical Reference Manual 8.3.3 Typical Crystal Application Circuit................331 8.3.4 External 32.768 KHz XTAL Oscillator ................332 8.3.5 Internal 22.1184 MHz RC Oscillator ................332 8.3.6 Internal 10 KHz RC Oscillator ..................333 Analog Characteristics ..................... 334 8.4.1 Brown-Out Reset (BOD) ....................
  • Page 6 NuMicro™ Mini51 Technical Reference Manual List of Figures Figure 3.1-1 NuMicro Mini51 Series Product Selection Guide ............ 14 Figure 3.2-1 NuMicro Mini51 Series LQFP 48-pin Assignment ..........15 Figure 3.2-2 NuMicro Mini51 Series QFN 33-pin Assignment ............ 16 Figure 4.1-1 NuMicro Mini51 Series Block Diagram ..............21 Figure 5.3-1 NuMicro Mini51...
  • Page 7 NuMicro™ Mini51 Technical Reference Manual Figure 5.9-9 I C Time-out Count Block Diagram ................173 Figure 5.9-10 Legend for the Following Five Figures ..............185 Figure 5.9-11 Master Transmitter Mode ..................186 Figure 5.9-12 Master Receiver Mode ................... 187 Figure 5.9-13 Slave Transmitter Mode ..................188 Figure 5.9-14 Slave Receiver Mode .....................
  • Page 8 NuMicro™ Mini51 Technical Reference Manual Figure 5.12-1 Timer Controller Block Diagram................252 Figure 5.12-2 Clock Source of Timer Controller................252 Figure 5.12-3 Continuous Counting Mode ................... 254 Figure 5.13-1 UART Clock Control Diagram ................270 Figure 5.13-2 UART Block Diagram ..................... 271 Figure 5.13-3 Auto Flow Control Block Diagram ................
  • Page 9 NuMicro™ Mini51 Technical Reference Manual List of Tables Table 3.3-1 NuMicro Mini51 Series Pin Description ..............20 Table 5.1-1 Address Space Assignments for On-Chip Modules............ 23 Table 5.2-1 Exception Model ......................25 Table 5.2-2 System Interrupt Map ....................26 Table 5.2-3 Vector Table Format ....................26 Table 5.3-1 Memory Mapping Table ....................

  • Page 10: General Description

    NuMicro™ Mini51 Technical Reference Manual GENERAL DESCRIPTION ® Cortex™-M0 core The NuMicro Mini51™ series 32-bit microcontroller is embedded with an ARM for industrial controls and applications which require high performance, high integration, and low cost. The Cortex™-M0 is the newest ARM embedded processor with 32-bit performance at a cost equivalent to the traditional 8-bit microcontroller.

  • Page 11: Features

    NuMicro™ Mini51 Technical Reference Manual FEATURES  Core ®  Cortex™-M0 core running up to 24 MHz  One 24-bit system timer  Supports low power Idle mode  A single-cycle 32-bit hardware multiplier  NVIC for 32 interrupt inputs, each with 4-level priority ...
  • Page 12 NuMicro™ Mini51 Technical Reference Manual  Supports external trigger in Pulse Width Measurement mode  Supports external trigger in Pulse Width Capture mode  Watchdog Timer  Programmable clock source and time-out period  Supports wake-up function in Power-down mode and Idle mode ...
  • Page 13 NuMicro™ Mini51 Technical Reference Manual communicate via one serial bus  Serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer  Programmable clocks allowing for versatile rate control  Supports multiple address recognition (4 slave addresses with mask option) ...

  • Page 14: Parts Information List And Pin Configuration

    NuMicro™ Mini51 Technical Reference Manual PARTS INFORMATION LIST AND PIN CONFIGURATION NuMicro Mini51 Series Product Selection Guide Connectivity Part Number APROM RAM Data Flash Loader Timer Comp. PWM 22.1184 Package UART SPI MINI51LAN 4 KB 2 KB Configurable 2 KB up to 30 2x32-bit 8x10-bit LQFP48...

  • Page 15: Pin Configuration

    NuMicro™ Mini51 Technical Reference Manual PIN CONFIGURATION 3.2.1 LQFP 48-pin CPP0, AIN5, P1.5 P0.4, SPISS,PWM5 P0.5, MOSI /RESET P0.6, MISO CPN1, AIN6, P3.0 AVSS P0.7, SPICLK Mini51 P5.4 LQFP 48-pin CPP1, AIN7, P3.1 P4.7, ICE_DAT T0EX, STADC, INT0, P3.2 P4.6, ICE_CLK SDA, T0, P3.4 SCL, T1, P3.5 P2.6, PWM4, CPO1...

  • Page 16: Qfn 33-Pin

    NuMicro™ Mini51 Technical Reference Manual 3.2.2 QFN 33-pin 31 30 29 28 27 26 25 CPP0,AIN5, P1.5 P0.4, SPISS,PWM5 /RESET P0.5, MOSI CPN1,AIN6, P3.0 P0.6, MISO Mini51 P5.4 P0.7, SPICLK QFN 33-pin CPP1,AIN7, P3.1 P4.7, ICE_DAT T0EX,STADC,INT0, P3.2 P4.6, ICE_CLK SDA, T0, P3.4 P2.6, PWM4,CPO1 33 VSS...

  • Page 17: Pin Description

    NuMicro™ Mini51 Technical Reference Manual Pin Description Pin Number Pin Name Pin Type Description LQFP 48-pin 33-pin Not connected P1.5 Digital GPIO pin AIN5 ADC analog input pin CPP0 Analog comparator Positive input pin The Schmitt trigger input pin for hardware device reset. A “Low”...
  • Page 18 NuMicro™ Mini51 Technical Reference Manual Pin Number Pin Name Pin Type Description LQFP 48-pin 33-pin P3.6 Digital GPIO pin CPO0 Analog comparator output pin Frequency divider output pin T1EX Timer 1 external capture/reset trigger input pin P5.1 Digital GPIO pin The output pin from the internal inverting amplifier.
  • Page 19 NuMicro™ Mini51 Technical Reference Manual Pin Number Pin Name Pin Type Description LQFP 48-pin 33-pin Not connected P4.6 Digital GPIO pin ICE_CLK Serial wired debugger clock pin P4.7 Digital GPIO pin ICE_DAT Serial wired debugger data pin Not connected P0.7 Digital GPIO pin SPICLK SPI serial clock pin...

  • Page 20: Table 3.3-1 Numicro Mini51 Series Pin Description

    NuMicro™ Mini51 Technical Reference Manual Pin Number Pin Name Pin Type Description LQFP 48-pin 33-pin AIN1 ADC analog input pin P1.2 Digital GPIO pin AIN2 ADC analog input pin UART data receiver input pin P1.3 Digital GPIO pin AIN3 ADC analog input pin UART transmitter output pin P1.4 Digital GPIO pin...

  • Page 21: Block Diagram

    NuMicro™ Mini51 Technical Reference Manual BLOCK DIAGRAM NuMicro Mini51™ Block Diagram 10K RC OSC CONFIG Info 22.1184M RC OSC Cortex-M0 CLK_CTL 32.768K XTAL 24 MHz Option ROMMAP ISP 4KB ISP 2KB 4~24M XTAL 2.5 ~ 5.5V Flash Control SRAM APB- GPIO Bridge P0~P5...

  • Page 22: Functional Description

    NuMicro™ Mini51 Technical Reference Manual FUNCTIONAL DESCRIPTION Memory Organization 5.1.1 Overview The NuMicro Mini51 series provides a 4G-byte address space for programmers. The memory locations assigned to each on-chip modules are shown in Table 5.1-1. The detailed register and memory addressing and programming will be described in the following sections for individual on- chip modules.

  • Page 23: System Memory Map

    NuMicro™ Mini51 Technical Reference Manual 5.1.2 System Memory Map The memory locations assigned to each on-chip controllers are shown in the following table. Address Space Token Controllers Flash and SRAM Memory Space 0x0000_0000 – 0x0000_3FFF FLASH_BA Flash Memory Space (16 KB) 0x2000_0000 –...

  • Page 24: Nested Vectored Interrupt Controller (Nvic)

    NuMicro™ Mini51 Technical Reference Manual Nested Vectored Interrupt Controller (NVIC) 5.2.1 Overview The Cortex™-M0 CPU provides an interrupt controller as an integral part of the exception mode, named “Nested Vectored Interrupt Controller (NVIC)”. It is closely coupled to the processor kernel and provides the following features.

  • Page 25: Table 5.2-1 Exception Model

    NuMicro™ Mini51 Technical Reference Manual Fault”. Exception Name Exception Number Priority Reset Hard Fault Reserved 4 ~ 10 Reserved SVCall Configurable Reserved 12 ~ 13 Reserved PendSV Configurable SysTick Configurable Interrupt (IRQ0 ~ IRQ31) 16 ~ 47 Configurable Table 5.2-1 Exception Model IRQ Number Exception Exception...

  • Page 26: Vector Table

    NuMicro™ Mini51 Technical Reference Manual IRQ Number Exception Exception Power-down (Bit in Interrupt Source IP Exception Description Number Name Wake-up Registers) SPI_INT SPI interrupt External signal interrupt from GP5_INT GPIO GPIO group P5 except P5.2 HFIRC_TRIM HFIRC HFIRC trim interrupt _INT I2C_INT C interrupt...

  • Page 27: Nvic Operation

    NuMicro™ Mini51 Technical Reference Manual 5.2.5 NVIC Operation NVIC interrupts can be enabled or disabled by writing to their corresponding Interrupt Set-Enable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-1-to- clear policy, and both registers reading back the current enabled state of the corresponding interrupts.

  • Page 28: Nvic Control Registers

    NuMicro™ Mini51 Technical Reference Manual 5.2.6 NVIC Control Registers R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value SCS_BA = 0xE000_E000 NVIC_ISER SCS_BA+0x100 IRQ0 ~ IRQ31 Set-Enable Control Register 0x0000_0000 NVIC_ICER SCS_BA+0x180 IRQ0 ~ IRQ31 Clear-Enable Control Register 0x0000_0000 NVIC_ISPR SCS_BA+0x200...
  • Page 29 NuMicro™ Mini51 Technical Reference Manual IRQ0 ~ IRQ31 Set-Enable Control Register (NVIC_ISER) Register Offset Description Reset Value NVIC_ISER SCS _BA+0x100 IRQ0 ~ IRQ31 Set-Enable Control Register 0x0000_0000 SETENA SETENA SETENA SETENA Bits Description Enable one or more interrupts within a group of 32 bits. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).
  • Page 30 NuMicro™ Mini51 Technical Reference Manual IRQ0 ~ IRQ31 Clear-Enable Control Register (NVIC_ICER) Register Offset Description Reset Value NVIC_ICER SCS _BA+0x180 IRQ0 ~ IRQ31 Clear-Enable Control Register 0x0000_0000 CLRENA CLRENA CLRENA CLRENA Bits Description Disable one or more interrupts within a group of 32 bits. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).
  • Page 31 NuMicro™ Mini51 Technical Reference Manual IRQ0 ~ IRQ31 Set-Pending Control Register (NVIC_ISPR) Register Offset Description Reset Value NVIC_ISPR SCS _BA+0x200 IRQ0 ~ IRQ31 Set-Pending Control Register 0x0000_0000 SETPEND SETPEND SETPEND SETPEND Bits Description 1 = The associated interrupt under software control pended. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).
  • Page 32 NuMicro™ Mini51 Technical Reference Manual IRQ0 ~ IRQ31 Clear-Pending Control Register (NVIC_ICPR) Register Offset Description Reset Value NVIC_ICPR SCS _BA+0x280 IRQ0 ~ IRQ31 Clear-Pending Control Register 0x0000_0000 CLRPEND CLRPEND CLRPEND CLRPEND Bits Description 1 = The associated interrupt under software control un-pended. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).
  • Page 33 NuMicro™ Mini51 Technical Reference Manual IRQ0 ~ IRQ3 Interrupt Priority Register (NVIC_IPR0) Register Offset Description Reset Value NVIC_IPR0 SCS _BA+0x400 IRQ0 ~ IRQ3 Interrupt Priority Control Register 0x0000_0000 PRI_3 PRI_2 PRI_1 PRI_0 Bits Description Priority of IRQ3 [31:30] PRI_3[1:0] “0” denotes the highest priority and “3” denotes the lowest priority. [29:24] Reserved Priority of IRQ2...
  • Page 34 NuMicro™ Mini51 Technical Reference Manual IRQ4 ~ IRQ7 Interrupt Priority Register (NVIC_IPR1) Register Offset Description Reset Value NVIC_IPR1 SCS _BA+0x404 IRQ4 ~ IRQ7 Interrupt Priority Control Register 0x0000_0000 PRI_7 PRI_6 PRI_5 PRI_4 Bits Description Priority of IRQ7 [31:30] PRI_7[1:0] “0” denotes the highest priority and “3” denotes the lowest priority. [29:24] Reserved Priority of IRQ6...
  • Page 35 NuMicro™ Mini51 Technical Reference Manual IRQ8 ~ IRQ11 Interrupt Priority Register (NVIC_IPR2) Register Offset Description Reset Value NVIC_IPR2 SCS _BA+0x408 IRQ8 ~ IRQ11 Interrupt Priority Control Register 0x0000_0000 PRI_11 PRI_10 PRI_9 PRI_8 Bits Description Priority of IRQ11 [31:30] PRI_11[1:0] “0” denotes the highest priority and “3” denotes the lowest priority. [29:24] Reserved Priority of IRQ10...
  • Page 36 NuMicro™ Mini51 Technical Reference Manual IRQ12 ~ IRQ15 Interrupt Priority Register (NVIC_IPR3) Register Offset Description Reset Value NVIC_IPR3 SCS _BA+0x40C R/W IRQ12 ~ IRQ15 Interrupt Priority Control Register 0x0000_0000 PRI_15 PRI_14 PRI_13 PRI_12 Bits Description Priority of IRQ15 [31:30] PRI_15[1:0] “0”...
  • Page 37 NuMicro™ Mini51 Technical Reference Manual IRQ16 ~ IRQ19 Interrupt Priority Register (NVIC_IPR4) Register Offset Description Reset Value NVIC_IPR4 SCS _BA+0x410 IRQ16 ~ IRQ19 Interrupt Priority Control Register 0x0000_0000 PRI_19 PRI_18 PRI_17 PRI_16 Bits Description Priority of IRQ19 [31:30] PRI_19[1:0] “0” denotes the highest priority and “3” denotes the lowest priority. [29:24] Reserved Priority of IRQ18...
  • Page 38 NuMicro™ Mini51 Technical Reference Manual IRQ20 ~ IRQ23 Interrupt Priority Register (NVIC_IPR5) Register Offset Description Reset Value NVIC_IPR5 SCS _BA+0x414 IRQ20 ~ IRQ23 Interrupt Priority Control Register 0x0000_0000 PRI_23 PRI_22 PRI_21 PRI_20 Bits Description Priority of IRQ23 [31:30] PRI_23[1:0] “0” denotes the highest priority and “3” denotes the lowest priority. [29:24] Reserved Priority of IRQ22...
  • Page 39 NuMicro™ Mini51 Technical Reference Manual IRQ24 ~ IRQ27 Interrupt Priority Register (NVIC_IPR6) Register Offset Description Reset Value NVIC_IPR6 SCS _BA+0x418 IRQ24 ~ IRQ27 Interrupt Priority Control Register 0x0000_0000 PRI_27 PRI_26 PRI_25 PRI_24 Bits Description Priority of IRQ27 [31:30] PRI_27[1:0] “0” denotes the highest priority and “3” denotes the lowest priority. [29:24] Reserved Priority of IRQ26...
  • Page 40 NuMicro™ Mini51 Technical Reference Manual IRQ28 ~ IRQ31 Interrupt Priority Register (NVIC_IPR7) Register Offset Description Reset Value NVIC_IPR7 SCS _BA+0x41C R/W IRQ28 ~ IRQ31 Interrupt Priority Control Register 0x0000_0000 PRI_31 PRI_30 PRI_29 PRI_28 Bits Description Priority of IRQ31 [31:30] PRI_31[1:0] “0”...

  • Page 41: Interrupt Source Control Registers

    NuMicro™ Mini51 Technical Reference Manual 5.2.7 Interrupt Source Control Registers Besides the interrupt control registers associated with the NVIC, the NuMicro Mini51 series also implements some specific control registers to facilitate the interrupt functions, including “interrupt source identify”, ”NMI source selection” and “interrupt test mode”, which are described below. R: read only, W: write only, R/W: both read and write Register Offset...
  • Page 42 NuMicro™ Mini51 Technical Reference Manual Register Offset Description Reset Value INT_BA = 0x5000_0300 Reserved IRQ24_SRC INT_BA+0x60 0xXXXX_XXXX IRQ25_SRC INT_BA+0x64 IRQ25 (ACMP) Interrupt Source Identity 0xXXXX_XXXX IRQ26_SRC INT_BA+0x68 Reserved 0xXXXX_XXXX IRQ27_SRC INT_BA+0x6C Reserved 0xXXXX_XXXX IRQ28_SRC INT_BA+0x70 IRQ28 (PWRWU) Interrupt Source Identity 0xXXXX_XXXX IRQ29_SRC INT_BA+0x74...
  • Page 43 NuMicro™ Mini51 Technical Reference Manual Interrupt Source Identify Register (IRQn_SRC) Register Offset Description Reset Value MCU IRQ0 (BOD) Interrupt Source Identity INT_BA+0x00 …….. ： IRQn_SRC 0xXXXX_XXXX INT_BA+0x7C MCU IRQ31 (Reserved) Interrupt Source Identity INT_SRC Bits Address IRQ No. Description [31:3] Reserved.
  • Page 44 NuMicro™ Mini51 Technical Reference Manual Bits Address IRQ No. Description Bit1~2: Reserved [2:0] INT_BA+0x20 Bit0: TMR0_INT Bit1~2: Reserved [2:0] INT_BA+0x24 Bit0: TMR1_INT [2:0] INT_BA+0x28 Reserved [2:0] INT_BA+0x2C Reserved Bit1~2: Reserved [2:0] INT_BA+0x30 Bit0: UART_INT [2:0] INT_BA+0x34 Reserved Bit1~2: Reserved [2:0] INT_BA+0x38 Bit0: SPI_INT [2:0]...
  • Page 45 NuMicro™ Mini51 Technical Reference Manual NMI Interrupt Source Select Control Register (NMI_SEL) Register Offset Description Reset Value NMI_SEL INT_BA+0x80 NMI Source Interrupt Select Control Register 0x0000_0000 NMI_SEL_EN NMI_SEL Bits Description [31:9] Reserved NMI Interrupt Source Enable (Write-protected) NMI_SEL_EN Setting this bit will enable NMI_SEL to generate NMI interrupt source of Cortex-M0. Reserved [7:5] NMI Interrupt Source Selection...
  • Page 46 NuMicro™ Mini51 Technical Reference Manual MCU Interrupt Request Source Register (MCU_IRQ) Register Offset Description Reset Value MCU_IRQ INT_BA+0x84 MCU Interrupt Request Source Register 0x0000_0000 MCU_IRQ MCU_IRQ MCU_IRQ MCU_IRQ Bits Description MCU IRQ Source Register The MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0 core.

  • Page 47: System Manager

    NuMicro™ Mini51 Technical Reference Manual System Manager 5.3.1 Overview The following functions are included in the system manager section:  System Memory Map  System Timer (SysTick)  Nested Vectored Interrupt Controller (NVIC)  System management registers for product ID ...

  • Page 48: Figure 5.3-1 Numicro Mini51 Series Power Distribution Diagram

    NuMicro™ Mini51 Technical Reference Manual ™ Mini51 Power Distribution AVDD AVSS Comparator 10-bit Brown Out Detector SAR-ADC Digital Logic FLASH 22.1184MHz Timer/UART/I2C/SPI… & 10KHz Osc. 1.8V POR18 P0~P5 5V to 1.8V IO cell POR50 Figure 5.3-1 NuMicro Mini51 Series Power Distribution Diagram Feb 9, 2012 Page 48 of 342 Revision V1.03...

  • Page 49: Memory Mapping Table

    NuMicro™ Mini51 Technical Reference Manual 5.3.4 Memory Mapping Table Mini51/52/54 System Control 4 GB 0xFFFF_FFFF System Control 0xE000_ED00 SCS_BA Reserved External Interrupt Control 0xE000_E100 SCS_BA 0xE000_F000 System Timer Control 0xE000_E010 SCS_BA 0xE000_EFFF System Control 0xE000_E000 0xE000_E00F Reserved 0x6002_0000 0x6001_FFFF Reserved 0x6000_0000 0x5FFF_FFFF Reserved...

  • Page 50: System Manager Control Registers

    NuMicro™ Mini51 Technical Reference Manual 5.3.5 System Manager Control Registers R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value GCR_BA = 0x5000_0000 PDID GCR_BA+0x00 Part Device Identification Number Register 0xXXXX_XXXX RSTSRC GCR_BA+0x04 System Reset Source Register 0x0000_00XX IPRSTC1 GCR_BA+0x08...
  • Page 51 NuMicro™ Mini51 Technical Reference Manual Part Device Identification Number Register (PDID) Register Offset Description Reset Value PDID GCR_BA+0x00 Part Device Identification number Register 0xXXXX_XXXX [1] Every part number has a unique default reset value. PDID PDID PDID PDID Bits Description Product Device Identification Number This register reflects the device part number code.
  • Page 52 NuMicro™ Mini51 Technical Reference Manual System Reset Source Register (RSTSRC) This register provides specific information for software to identify the chip‟s reset source from the last operation. Register Offset Description Reset Value RSTSRC GCR_BA+0x04 System Reset Source Register 0x0000_00XX RSTS_CPU RSTS_MCU RSTS_BOD RSTS_WDT RSTS_RESET RSTS_POR...
  • Page 53 NuMicro™ Mini51 Technical Reference Manual Bits Description The RSTS_WDT flag is set by the “reset signal” from the Watchdog module to indicate the previous reset source. 1 = The Watchdog module had issued the reset signal to reset the system. RSTS_WDT 0 = No reset from Watchdog.
  • Page 54 NuMicro™ Mini51 Technical Reference Manual IP Reset Control Register 1 (IPRSTC1) Register Offset Description Reset Value IPRSTC1 GCR_BA+0x08 IP Reset Control Resister 1 0x0000_0000 CPU_RST CHIP_RST Bits Description [31:2] Reserved CPU Kernel One Shot Reset Setting this bit will reset the CPU kernel, and this bit will automatically return to “0” after the 2 clock cycles.
  • Page 55 NuMicro™ Mini51 Technical Reference Manual IP Reset Control Register 2 (IPRSTC2) Setting the bit “1” will generate the asynchronous reset signal to the corresponding IP. User needs to set the bit to “0” to release IP from the reset state. Register Offset Description...
  • Page 56 NuMicro™ Mini51 Technical Reference Manual Bits Description [11:9] Reserved C Controller Reset I2C _RST 1 = I C block reset. 0 = I C normal operation. [7:4] Reserved Timer1 Controller Reset TMR1_RST 1 = Timer1 block reset. 0 = Timer1 normal operation. Timer0 Controller Reset TMR0_RST 1 = Timer0 block reset.
  • Page 57 NuMicro™ Mini51 Technical Reference Manual Brown-out Detector Control Register (BODCR) Partial of the BODCR control register values are initiated by the flash configuration and writeprotected by the lock function. If user needs to program the write-protected content, an unlocked sequence is needed. The unlocked sequence is to continuously write the data 0x59, 0x16, 0x88 to the key controller address 0x5000_0100.
  • Page 58 NuMicro™ Mini51 Technical Reference Manual Bits Description Brown-out Reset Enable (Initiated and Write-protected bit) 1 = Brown-out “RESET” function Enabled; when the Brown-out Detector function is enable and the detected voltage is lower than the threshold then assert a signal to reset the chip.
  • Page 59 NuMicro™ Mini51 Technical Reference Manual Multiple Function Port0 Control Register (P0_MFP) Register Offset Description Reset Value P0_MFP GCR_BA+0x30 P0 Multiple Function and Input Type Control Register 0x0000_0000 P0_TYPE P0_ALT P0_MFP Bits Description [31:24] Reserved P0[7:0] input Schmitt Trigger function Enable [23:16] P0_TYPE[n] 1 = P0[7:0] I/O input Schmitt Trigger function Enabled.
  • Page 60 NuMicro™ Mini51 Technical Reference Manual Bits Description P0.5 Alternate Function Selection The pin function of P0.5 depends on P0_MFP[5] and P0_ALT[5]. P0_ALT[5] P0_MFP[5] P0.5 function P0.5 [13] P0_ ALT[5] Reserved MOSI (SPI) Reserved P0.4 Alternate Function Selection The pin function of P0.4 depends on P0_MFP[4] and P0_ALT[4]. P0_ALT[4] P0_MFP[4] P0.4 function...
  • Page 61 NuMicro™ Mini51 Technical Reference Manual Multiple Function Port1 Control Register (P1_MFP) Register Offset Description Reset Value P1_MFP GCR_BA+0x34 P1 Multiple Function and Input Type Control Register 0x0000_0000 P1_TYPE P1_ALT P1_MFP Bits Description [31:24] Reserved P1[7:0] input Schmitt Trigger function Enable [23:16] P1_TYPE[n] 1 = P1[7:0] I/O input Schmitt Trigger function enable.
  • Page 62 NuMicro™ Mini51 Technical Reference Manual Bits Description P1.3 Alternate Function Selection The pin function of P1.3 depends on P1_MFP[3] and P1_ALT[3]. P1_ALT[3] P1_MFP[3] P1.3 function P1.3 [11] P1_ ALT[3] AIN3 (ADC) TX (UART) Reserved P1.2 Alternate Function Selection The pin function of P1.2 depends on P1_MFP[2] and P1_ALT[2]. P1_ALT[2] P1_MFP[2] P1.2 function...
  • Page 63 NuMicro™ Mini51 Technical Reference Manual Multiple Function Port2 Control Register (P2_MFP) Register Offset Description Reset Value P2_MFP GCR_BA+0x38 P2 Multiple Function and Input Type Control Register 0x0000_0000 P2_TYPE P2_ALT P2_MFP Bits Description [31:24] Reserved P2[7:0] input Schmitt Trigger function Enable [23:16] P2_TYPE[n] 1 = P2[7:0] I/O input Schmitt Trigger function Enabled.
  • Page 64 NuMicro™ Mini51 Technical Reference Manual Bits Description P2.4 Alternate Function Selection The pin function of P2.4 depends on P2_MFP[4] and P2_ALT[4]. P2_ALT[4] P2_MFP[4] P2.4 function P2.4 [12] P2_ ALT[4] Reserved PWM2 (PWM) Reserved P2.3 Alternate Function Selection The pin function of P2.3 depends on P2_MFP[3] and P2_ALT[3]. P2_ALT[3] P2_MFP[3] P2.3 function...
  • Page 65 NuMicro™ Mini51 Technical Reference Manual Multiple Function Port3 Control Register (P3_MFP) Register Offset Description Reset Value P3_MFP GCR_BA+0x3C P3 Multiple Function and Input Type Control Register 0x0000_0000 P3_TYPE P3_ALT P3_MFP Bits Description [31:24] Reserved P3[7:0] input Schmitt Trigger function Enable [23:16] P3_TYPE[n] 1 = P3[7:0] I/O input Schmitt Trigger function Enabled.
  • Page 66 NuMicro™ Mini51 Technical Reference Manual Bits Description P3.4 Alternate Function Selection The pin function of P3.4 depends on P3_MFP[4] and P3_ALT[4]. P3_ALT[4] P3_MFP[4] P3.4 function P3.4 [12] P3_ ALT[4] T0 (Timer0) SDA (I Reserved [11] Reserved P3.2 Alternate Function Selection The pin function of P3.2 depends on P3_MFP[2] and P3_ALT[2].
  • Page 67 NuMicro™ Mini51 Technical Reference Manual Multiple Function Port4 Control Register (P4_MFP) Register Offset Description Reset Value P4_MFP GCR_BA+0x40 P4 Multiple Function and Input Type Control Register 0x0000_00C0 P4_TYPE P4_ALT P4_MFP Bits Description [31:24] Reserved P4[7:0] input Schmitt Trigger function Enable [23:16] P4_TYPE[n] 1 = P4[7:0] I/O input Schmitt Trigger function Enabled.
  • Page 68 NuMicro™ Mini51 Technical Reference Manual Multiple Function Port5 Control Register (P5_MFP) Register Offset Description Reset Value P5_MFP GCR_BA+0x44 P5 Multiple Function and Input Type Control Register 0x0000_0000 P5_TYPE P5_ALT P5_MFP Bits Description [31:24] Reserved P5[7:0] input Schmitt Trigger function Enable [23:16] P5_TYPE[n] 1 = P5[7:0] I/O input Schmitt Trigger function Enabled.
  • Page 69 NuMicro™ Mini51 Technical Reference Manual Bits Description P5.3 Alternate Function Selection The pin function of P5.3 depends on P5_MFP[3] and P5_ALT[3]. P5_ALT[3] P5_MFP[3] P5.3 function [11] P5_ ALT[3] P5.3 AIN0 (ADC) Reserved P5.2 Alternate Function Selection The pin function of P5.2 depends on P5_MFP[2] and P5_ALT[2]. P5_ALT[2] P5_MFP[2] P5.2 function...
  • Page 70 NuMicro™ Mini51 Technical Reference Manual HFIRC Trim Control Register (IRCTRIMCTL) Register Offset Description Reset Value IRCTRIMCTL GCR_BA+0x80 HIRC Trim Control Register 0x0000_0000 Reserved TRIM_LOOP TRIM_SEL Bits Description [31:8] Reserved Reserved. Keep the default value “00”. [7:6] Trim Calculation Loop This field defines trim value calculation based on the number of 32.768 KHz clock. For example, if TRIM_LOOP is set as “00”, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 KHz clock.
  • Page 71 NuMicro™ Mini51 Technical Reference Manual Bits Description Trim Frequency Selection This bit is to enable the HFIRC auto trim. When setting this bit to “1”, the HFIRC auto trim function will trim HFIRC to 22 MHz automatically based on the 32.768 KHz reference clock. TRIM_SEL During auto trim operation, if 32.768 KHz clock error is detected or trim retry limitation count reached, this field will be cleared to “0”...
  • Page 72 NuMicro™ Mini51 Technical Reference Manual HFIRC Trim Interrupt Enable Register (IRCTRIMIEN) Register Offset Description Reset Value IRCTRIMIEN GCR_BA+0x84 HIRC Trim Interrupt Enable Register 0x0000_0000 32K_ERR_IE TRIM_FAIL_I Bits Description [31:3] Reserved 32.768 KHz Clock Error Interrupt Enable This bit controls if CPU could get an interrupt while 32.768 KHz clock is inaccurate during auto trim operation.
  • Page 73 NuMicro™ Mini51 Technical Reference Manual HFIRC Trim Interrupt Status Register (IRCTRIMINT) Register Offset Description Reset Value IRCTRIMINT GCR_BA+0x88 HIRC Trim Interrupt Status Register 0x0000_0000 32K_ERR_IN TRIM_FAIL_I FREQ_LOCK Bits Description [31:3] Reserved 32.768 KHz Clock Error Interrupt Status This bit indicates that 32.768 KHz clock frequency is inaccuracy. Once this bit is set, the auto trim operation stopped and TRIM_SEL will be cleared to “0”...
  • Page 74 NuMicro™ Mini51 Technical Reference Manual Register Lock Key Address Register (RegLockAddr) Some of the system control registers need to be protected to avoid inadvertent write and disturb the chip operation. These system control registers are locked after the power on reset until user opens the lock.

  • Page 75: Clock Controller

    NuMicro™ Mini51 Technical Reference Manual Clock Controller 5.4.1 Overview The clock controller generates the clocks for the whole chip, including system clocks and all peripheral clocks. The clock controller also implements the power control function with the individually clock ON/OFF control, clock source selection and a 4-bit clock divider. The chip will not enter Power-down mode until CPU sets the power-down enable bit (PWR_DOWN_EN) and Cortex-M0 core executes the WFI instruction.

  • Page 76: System Clock And Systick Clock

    NuMicro™ Mini51 Technical Reference Manual 5.4.3 System Clock and SysTick Clock The system clock has 3 clock sources which were generated from clock generator block. The clock source switch depends on the register HCLK_S (CLKSEL0[2:0]). The block diagram is shown below. HCLK_S (CLKSEL0[2:0]) 22.1184M CPUCLK...

  • Page 77: Ahb Clock Source Selection

    NuMicro™ Mini51 Technical Reference Manual 5.4.4 AHB Clock Source Selection HCLK ISP (In System Programmer) ISP_EN (AHBCLK[2]) Figure 5.4-4 AHB Clock Source for HCLK Feb 9, 2012 Page 77 of 342 Revision V1.03...

  • Page 78: Peripheral Clock Source Selection

    NuMicro™ Mini51 Technical Reference Manual 5.4.5 Peripheral Clock Source Selection The peripheral clock has different clock source switch settings depending on different peripherals. Please refer to the CLKSEL1 and APBCLK register description in section 5.4.9. PCLK Watch Dog Timer WDT_EN (APBCLK[0]) Timer0 TMR0_EN (APBCLK[2]) Timer1...

  • Page 79: Table 5.4-1 Peripherals Engine Clock Source Selection Table

    NuMicro™ Mini51 Technical Reference Manual Ext. CLK (12M or 32K) IRC22.1184M IRC10K PCLK Timer0 Timer1 UART ACMP Table 5.4-1 Peripherals Engine Clock Source Selection Table Feb 9, 2012 Page 79 of 342 Revision V1.03...

  • Page 80: Power-Down Mode Clock

    NuMicro™ Mini51 Technical Reference Manual 5.4.6 Power-down Mode Clock When entering Power-down mode, some clock sources and peripheral clocks and system clocks will be disabled. Some clock sources and peripheral clocks are still active in Power-down mode. Clocks that still be kept active are listed below. ...

  • Page 81: Frequency Divider Output

    NuMicro™ Mini51 Technical Reference Manual 5.4.7 Frequency Divider Output This device is equipped with a power-of-2 frequency divider which is composed of 16 chained divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one multiplexer is reflected to P3.6.

  • Page 82: Clock Control Register Map

    NuMicro™ Mini51 Technical Reference Manual 5.4.8 Clock Control Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value CLK_BA = 0x5000_0200 PWRCON CLK_BA+0x00 System Power-down Control Register 0x0000_001C AHBCLK CLK_BA+0x04 AHB Device Clock Enable Control Register 0x0000_0005 APBCLK CLK_BA+0x08...

  • Page 83: Clock Control Register

    NuMicro™ Mini51 Technical Reference Manual 5.4.9 Clock Control Register Power-down Control Register (PWRCON) Except the BIT[6], all the other bits are protected, programming these bits needs an open lock sequence, write 0x59, 0x16, 0x88 to address 0x5000_0100 to un-lock these bits. Refer to the register RegLockAddr at address GCR_BA + 0x100.
  • Page 84 NuMicro™ Mini51 Technical Reference Manual Bits Description Power-down Mode Wake-up Interrupt Status When set by “power-down wake-up event”, it indicates that resume from Power-down mode. PD_WU_STS The flag is set if the GPIO, UART, WDT, ACMP, Timer or BOD wake-up occurred. Write “1”...

  • Page 85: Table 5.4-2 Power-Down Mode Control Table

    NuMicro™ Mini51 Technical Reference Manual Register CPU run WFI PWR_DOWN_EN Clock Disabled instruction Instruction Mode Normal Running Mode All clocks are disabled by control register IDLE Mode Only CPU clock is disabled Most clocks are disabled except 10K and some Power-down Mode WDT/Timer/PWM/ADC peripheral clock are still active.
  • Page 86 NuMicro™ Mini51 Technical Reference Manual AHB Devices Clock Enable Control Register （AHBCLK） These register bits are used to enable/disable clock for AMBA clock, AHB engine and peripheral. Register Offset Description Reset Value AHBCLK CLK_BA+0x04 AHB Devices Clock Enable Control Register 0x0000_0005 ISP_EN Bits...
  • Page 87 NuMicro™ Mini51 Technical Reference Manual APB Devices Clock Enable Control Register (APBCLK) These register bits are used to enable/disable clock for APB engine and peripheral. Register Offset Description Reset Value APBCLK CLK_BA+0x08 APB Devices Clock Enable Control Register 0x0000_0001 CMP_EN ADC_EN PWM45_EN PWM23_EN...
  • Page 88 NuMicro™ Mini51 Technical Reference Manual Bits Description UART Clock Enable Control [16] UART_EN 1 = Both the UART APB and the engine clock Enabled. 0 = Both the UART APB and the engine clock Disabled. [15:13] Reserved SPI Clock Enable Control SPI_EN [12] 0 = Disabled.
  • Page 89 NuMicro™ Mini51 Technical Reference Manual Clock status Register (CLKSTATUS) These register bits are used to monitor if the chip clock source is stable or not, and if the clock switch is failed. Register Offset Description Reset Value CLKSTATUS CLK_BA+0x0C Clock Status Monitor Register 0x0000_0018 CLK_SW_FAIL OSC22M_STB OSC10K_STB...
  • Page 90 NuMicro™ Mini51 Technical Reference Manual Clock Source Select Control Register 0 (CLKSEL0) Register Offset Description Reset Value CLKSEL0 CLK_BA+0x10 Clock Source Select Control Register 0 0x0000_003F STCLK_S HCLK_S Bits Description [31:6] Reserved Cortex™-M0 CPU SysTick Clock Source Selection If SYST_CSR[2]=0, SysTick uses clock source listed below. These bits are protected bit;...
  • Page 91 NuMicro™ Mini51 Technical Reference Manual Bits Description HCLK Clock Source Selection Note: Before clock switch the related clock sources (pre-select and new-select) must be turned on. These bits are protected bit; programming this needs an open lock sequence, write 0x59, 0x16, 0x88 to address 0x5000_0100 to un-lock this bit. Refer to the register RegLockAddr at address GCR_BA + 0x100.
  • Page 92 NuMicro™ Mini51 Technical Reference Manual Clock Source Select Control Register 1（CLKSEL1） Before clock switch the related clock sources (pre-select and new-select) must be turned on. Register Offset Description Reset Value CLKSEL1 CLK_BA+0x14 Clock Source Select Control Register 1 0xAFFF_FFFF PWM23_S PWM01_S UART_S TMR1_S...
  • Page 93 NuMicro™ Mini51 Technical Reference Manual Bits Description UART Clock Source Selection 00 = Clock source from external 12 MHz or 32 KHz crystal clock. 01 = Reserved. [25:24] UART_S[1:0] 10 = Clock source from internal 22.1184 MHz oscillator clock. 11 = Reserved. Note: To set PWRCON[1:0], select 12 MHz or 32 KHz crystal clock.
  • Page 94 NuMicro™ Mini51 Technical Reference Manual Bits Description WDT CLK Clock Source Selection These bits are protected bit, programming this needs an open lock sequence, write 0x59, 0x16, 0x88 to address 0x5000_0100 to un-lock this bit. Refer to the register RegLockAddr at address GCR_BA + 0x100. 00 = Clock source from external 12 MHz or 32 KHz crystal clock.
  • Page 95 NuMicro™ Mini51 Technical Reference Manual Clock Source Select Control Register (CLKSEL2) Before clock switch the related clock sources (pre-select and new-select) must be turned on. Register Offset Description Reset Value CLKSEL2 CLK_BA+0x1C Clock Source Select Control Register 2 0x0000_00EF PWM45_S FRQDIV_S Bits Description...
  • Page 96 NuMicro™ Mini51 Technical Reference Manual Clock Divider Register (CLKDIV) Register Offset Description Reset Value CLKDIV CLK_BA+0x18 Clock Divider Number Register 0x0000_0000 ADC_N UART_N HCLK_N Bits Description [31:24] Reserved ADC Clock Divide Number from ADC Clock Source [23:16] ADC_N[7:0] The ADC clock frequency = (ADC clock source frequency) / (ADC_N + 1). Reserved [15:12] UART Clock Divide Number from UART Clock Source...
  • Page 97 NuMicro™ Mini51 Technical Reference Manual Frequency Divider Control Register (FRQDIV) Register Offset Description Reset Value FRQDIV CLK_BA+0x24 Frequency Divider Control Register 0x0000_0000 DIVIDER_EN FSEL Bits Description [31:5] Reserved Frequency Divider Enable Bit DIVIDER_EN 0 = Frequency Divider Disabled. 1 = Frequency Divider Enabled. Divider Output Frequency Selection Bits The formula of output frequency is: (N+1)

  • Page 98: Comparator Controller (Cmpc)

    NuMicro™ Mini51 Technical Reference Manual Comparator Controller (CMPC) 5.5.1 Overview The NuMicro Mini51 Series contains two comparators which can be used in a number of different configurations. The comparator output is a logical one when positive input is greater than negative input;...

  • Page 99: Block Diagram

    NuMicro™ Mini51 Technical Reference Manual 5.5.3 Block Diagram APB Bus COMP control registers COMP Status Register (CMP0CR, CMP1CR) (CMPSR) COMPF0, CMPF1 Comparator Interrupt Digital Control Logics CO0, CO1 CMP0_HYSEN,CMP0EN CMP1_HYSEN,CMP1EN CN0,CN1 CPP0 CMPSR[CO0] CPO0 CMP0CR[CN0] CPN0 Comparator 0 CPP1 CMP1CR[CN1] CMPSR[CO1] CPO1 CPN1...

  • Page 100: Functional Description

    NuMicro™ Mini51 Technical Reference Manual 5.5.4 Functional Description 5.5.4.1 Interrupt Sources The comparator generates an output CO1 (CO2) in CMPSR register which is sampled by PCLK. If CMP0IE (CMP1IE) bit in CMP0CR (CMP1CR) is set then a state change on the comparator output CO0 (CO1) will cause comparator flag CMPF0 (CMPF1) set and the comparator interrupt requested.

  • Page 101: Comparator Reference Voltage (Crv)

    NuMicro™ Mini51 Technical Reference Manual 5.5.5 Comparator Reference Voltage (CRV) 5.5.5.1 Introduction The comparator reference voltage (CRV) module is responsible for generating reference voltage for comparators. The CRV module consists of resisters ladder and analog switch, and user can set the CRV output voltage using CRVS[3:0] registers and select the reference voltage to CMP by setting OUL_SEL register.

  • Page 102: Register Map

    NuMicro™ Mini51 Technical Reference Manual 5.5.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value CMP_BA = 0x400D_0000 CMP0CR CMP_BA+0x00 Comparator0 Control Register 0x0000_0000 CMP1CR CMP_BA+0x04 Comparator1 Control Register 0x0000_0000 CMPSR CMP_BA+0x08 Comparator Status Register 0x0000_0000...

  • Page 103: Register Description

    NuMicro™ Mini51 Technical Reference Manual 5.5.7 Register Description Comparator0 Control Register (CMP0CR) Register Offset Description Reset Value CMP0CR CMP_BA+0x00 Comparator0 Control Register 0x0000_0000 CMP0_HYSEN CMP0IE CMP0EN Bits Description Reserved [31:5] Comparator0 Negative Input Selection 1 = The internal comparator reference voltage (Vref = 1.35V or from CRV setting value) is selected as the negative comparator input.
  • Page 104 NuMicro™ Mini51 Technical Reference Manual Comparator1 Control Register (CMP1CR) Register Offset Description Reset Value CMP1CR CMP_BA+0x04 Comparator1 Control Register 0x0000_0000 CMP1_HYSEN CMP1IE CMP1EN Bits Description [31:5] Reserved Comparator1 Negative Input Selection 1 = The internal comparator reference voltage (Vref=1.35V or from CRV setting value) is selected as the negative comparator input.
  • Page 105 NuMicro™ Mini51 Technical Reference Manual Comparator Status Register (CMPSR) Register Offset Description Reset Value CMPSR CMP_BA+0x08 Comparator Status Register 0x0000_0000 CMPF1 CMPF0 Bits Description [31:4] Reserved Comparator1 Output Synchronized to the APB clock to allow reading by software. Cleared when the comparator is disabled (CMP1EN = 0).
  • Page 106 NuMicro™ Mini51 Technical Reference Manual CMPRV Control Register (CMPRVCR) Register Offset Description Reset Value CMPRVCR CMP_BA+0x0C Comparator Reference Voltage Control Register 0x0000_0000 OUT_SEL CRVS Bits Description [31:8] Reserved CRV Module Output Selection OUT_SEL 1= CRVS setting voltage Selected. 0= Band-gap 1.35 V voltage Selected. Reserved [6:4] Comparator Reference Voltage Setting...

  • Page 107: Analog-To-Digital Converter (Adc) Controller

    NuMicro™ Mini51 Technical Reference Manual Analog-to-Digital Converter (ADC) Controller 5.6.1 Overview The NuMicro Mini51 series contains one 10-bit successive approximation analog-to-digital converters (SAR A/D converter) with 8 input channels. The A/D converters can be started by software and external STADC/P3.2 pin. Note that the analog input pins must be configured as input type before ADC function is enabled.

  • Page 108: Block Diagram

    NuMicro™ Mini51 Technical Reference Manual 5.6.3 Block Diagram VALID & OVERRUN Digatal Control Logics STADC & ADC_INT ADC Clock Generator RSLT[9:0] Successive Approximations VREF Register 10-bit DAC AIN0 AIN1 Analog Control Logics AIN7 Comparator Sample and Hold PRESEL Analog Macro * The source of channel 7 is selected by PRESEL Figure 5.6-1 ADC Controller Block Diagram 5.6.4...

  • Page 109: Figure 5.6-2 Adc Clock Control

    NuMicro™ Mini51 Technical Reference Manual 5.6.4.1 ADC Clock Generator The maximum sampling rate is up to 150 K. The ADC engine has clock source selected by 2-bit ADC_S (CLKSEL1[3:2]), the ADC clock frequency is divided by an 8-bit prescaler with the formula: The ADC clock frequency = (ADC clock source frequency) / (ADC_N+1);...

  • Page 110: Figure 5.6-3 A/D Conversion Result Monitor Logics Diagram

    NuMicro™ Mini51 Technical Reference Manual ADCMPR1 to monitor the maximum two specified channel conversion results from A/D conversion module (refer to Figure 5.6-3). Software can select which channel to be monitored by setting CMPCH (ADCMPRx[5:0]) and CMPCOND bit is used to check if conversion results are less than the specified value or greater than (or equal to) the value specified in CMPD[9:0].

  • Page 111: Adc Register Map

    NuMicro™ Mini51 Technical Reference Manual 5.6.5 ADC Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value ADC_BA = 0x400E_0000 ADDR ADC_BA+0x00 A/D Data Register 0x0000_0000 ADCR ADC_BA+0x20 A/D Control Register 0x0000_0000 ADCHER ADC_BA+0x24 A/D Channel Enable Register...

  • Page 112: Adc Register

    NuMicro™ Mini51 Technical Reference Manual 5.6.6 ADC Register A/D Data Registers (ADDR) Register Offset Description Reset Value ADDR ADC_BA+0x00 A/D Data Register 0x0000_0000 VALID OVERRUN RSTL RSTL Bits Description [31:18] Reserved Valid Flag 1 = Data in RSLT[9:0] bits valid. [17] VALID 0 = Data in RSLT[9:0] bits not valid.
  • Page 113 NuMicro™ Mini51 Technical Reference Manual A/D Control Register (ADCR) Register Offset Description Reset Value ADCR ADC_BA+0x20 ADC Control Register 0x0000_0000 ADST TRGEN TRGCOND ADIE ADEN Bits Description [31:12] Reserved A/D Conversion Start 1 = Conversion started. [11] ADST 0 = Conversion stopped and A/D converter entered idle state. ADST bit can be set to “1”...
  • Page 114 NuMicro™ Mini51 Technical Reference Manual Bits Description A/D Converter Enable 1 = Enabled. ADEN 0 = Disabled. Before starting the A/D conversion function, this bit should be set to “1”. Clear it to “0” to disable A/D converter analog circuit power consumption. Feb 9, 2012 Page 114 of 342 Revision V1.03...
  • Page 115 NuMicro™ Mini51 Technical Reference Manual A/D Channel Enable Register (ADCHER) Register Offset Description Reset Value ADCHER ADC_BA+0x24 A/D Channel Enable 0x0000_0000 PRESEL CHEN7 CHEN6 CHEN5 CHEN4 CHEN3 CHEN2 CHEN1 CHEN0 Bits Description [31:9] Reserved Analog Input Channel 7 Selection 0 = Analog Input Channel 7. PRESEL 1 = Band-gap (VBG) Analog Input.
  • Page 116 NuMicro™ Mini51 Technical Reference Manual Bits Description 1 = Enabled. 0 = Disabled. Analog Input Channel 1 Enable CHEN1 1 = Enabled. 0 = Disabled. Analog Input Channel 0 Enable 1 = Enabled. 0 = Disabled. CHEN0 Note: If software enables more than one channel, the channel with the lowest number will be selected and the other enabled channels will be ignored.
  • Page 117 NuMicro™ Mini51 Technical Reference Manual A/D Compare Register 0/1 (ADCMPR0/1) Register Offset Description Reset Value ADCMPR0 ADC_BA+0x28 A/D Compare Register 0 0x0000_0000 ADCMPR1 ADC_BA+0x2C A/D Compare Register 1 0x0000_0000 CMPD CMPD CMPMATCNT CMPCH CMPCOND CMPIE CPMEN Bits Description [31:26] Reserved Comparison Data [25:16] CMPD[9:0]...
  • Page 118 NuMicro™ Mini51 Technical Reference Manual Bits Description Compare Condition 1 = Set the compare condition as that when a 10-bit A/D conversion result is greater or equal to the 10-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one. CMPCOND 0 = Set the compare condition as that when a 10-bit A/D conversion result is less than the 10-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one.
  • Page 119 NuMicro™ Mini51 Technical Reference Manual A/D Status Register (ADSR) Register Offset Description Reset Value ADSR ADC_BA+0x30 ADC Status Register 0x0000_0000 OVERRUN VALID CHANNEL BUSY CMPF1 CMPF0 Bits Description [31:17] Reserved Over Run Flag OVERRUN [16] It is a mirror to OVERRUN bit in ADDR. [15:9] Reserved Data Valid Flag...
  • Page 120 NuMicro™ Mini51 Technical Reference Manual Bits Description When the selected channel A/D conversion result meets the setting condition in ADCMPR0, this bit is set to “1”. Then it is cleared by writing “1” to itself. 1 = Conversion result in ADDR meets the ADCMPR0 setting. 0 = Conversion result in ADDR does not meet the ADCMPR0 setting.

  • Page 121: Flash Memory Controller (Fmc)

    NuMicro™ Mini51 Technical Reference Manual Flash Memory Controller (FMC) 5.7.1 Overview The NuMicro Mini51 series is equipped with 4K/8K/16K bytes on chip embedded Flash EPROM for application program memory (APROM) that can be updated through ISP procedure. In System Programming (ISP) function enables user to update program memory when chip is soldered on PCB.

  • Page 122: Figure 5.7-1 Flash Memory Control Block Diagram

    NuMicro™ Mini51 Technical Reference Manual Cortex-M0 Debug Access AHB Lite Port interface Data Flash AHB Bus DFBA AHB Slave Interface Parallel Writer Controller APROM Flash Power On Operation Initialization Control 0x0000_07FF LDROM Data Out Config & (2KB) Control 0x0000_0000 0x0000_0000 CBS=1 CBS=0 Figure 5.7-1 Flash Memory Control Block Diagram...

  • Page 123: Functional Description

    NuMicro™ Mini51 Technical Reference Manual 5.7.4 Functional Description 5.7.4.1 Flash Memory Organization The NuMicro Mini51 flash memory consists of program memory (4K/8K/16KB), data flash, ISP loader program memory, and user configuration. User configuration block provides several bytes to control system logic, such as flash security lock, boot selection, Brown-out voltage level, data flash base address, and so on.

  • Page 124: Figure 5.7-2 Flash Memory Organization

    NuMicro™ Mini51 Technical Reference Manual The Flash memory organization is shown below: 0x 0030_01FF User Configuration 0x 0030_ 0000 0x 0010_0 7FF ISP Loader Program Memory 0x 0010_ 0000 Reserved for Future Used (16KB) 0x0000_3FFF ( 8KB) 0x0000_1FFF ( 4KB) 0x0000_0FFF Data Flash DFBA Application Program Memory...

  • Page 125: Table 5.7-2 Boot Selection Table

    NuMicro™ Mini51 Technical Reference Manual 5.7.4.2 Boot Selection The NuMicro Mini51 provides in system programming (ISP) feature for user to update program memory when chip is mounted on PCB. A dedicated 2KB program memory is used to store ISP firmware. User can select to start program fetch from APROM or LDROM by (CBS) in Config0. There are two kinds of mapping for booting selection.

  • Page 126: Figure 5.7-3 Flash Memory Structure

    NuMicro™ Mini51 Technical Reference Manual 0x0000_3FFF 0x0000_3FFF 0x0000_3FFF DataFlash 0.5*N k bytes Programmable start DFBA[31:0] address Reserved Reserved 0x0000_1FFF DataFlash Application Program 0.5*N K bytes (16-0.5*N)K bytes Programmable start 0x0000_0FFF DFBA[31:0] address DataFlash 0.5*N K bytes Programmable start Application Program DFBA[31:0] address (8-0.5*N)K bytes...
  • Page 127 NuMicro™ Mini51 Technical Reference Manual 5.7.4.4 User Configuration Config0 (Address = 0x0030_0000) CBOV CBORST LOCK DFEN Bits Description [31:29] Reserved HXT/LXT Clock Filter Enable [28] 0 = HXT/LXT clock filter Disabled. 1 = HXT/LXT clock filter Enabled. [27:23] Reserved Brown-out Voltage Selection CBOV[1] CBOV[0] Brown-out voltage...
  • Page 128 NuMicro™ Mini51 Technical Reference Manual Bits Description [6:2] Reserved Security Lock 0 = Flash data locked. 1 = Flash data unlocked. LOCK When flash data is locked, only device ID, unique ID, Config0 and Config1 can be read by writer and ICP through serial debug interface. Other data is locked as 0xFFFFFFFF.

  • Page 129: Table 5.7-4 Data Flash Configuration Example

    NuMicro™ Mini51 Technical Reference Manual Config1 (Address = 0x0030_0004) DFBA DFBA DFBA Bits Description [31:18] Reserved Data Flash Base Address [17:0] DFBA[17:0] The data flash base address is defined by user. Since on chip flash erase unit is 512 bytes, it is mandatory to keep bit 8-0 as “0”. Example: Table 5.7-4 Data Flash Configuration Example Data Flash...

  • Page 130: Figure 5.7-4 Isp Procedure

    UART along with the firmware in LDROM. General speaking, PC transfers the new APROM code through serial port. Then LDROM firmware receives it and re-programs into APROM through ISP commands. Nuvoton provides ISP firmware and PC application program for NuMicro Mini51 . It is quite easy to perform ISP through Nuvoton ISP tool.

  • Page 131: Figure 5.7-5 Isp Operation Flow

    NuMicro™ Mini51 Technical Reference Manual Power CBS = 1 ? Enable ISPEN Write ISPADR/ ISPCMD/ Fetch code from LD- Fetch code from AP- ISPDAT ? Set ISPGO = 1 Update LD-ROM or Execute ISP? write DataFlash End of Flash Operation (Read ISPDAT) &...

  • Page 132: Table 5.7-5 Isp Command Table

    NuMicro™ Mini51 Technical Reference Manual Table 5.7-5 ISP Command Table ISPCMD ISPADR ISPDAT ISP Mode FOEN FCEN FCTRL[3:0] A[19:0] D[31:0] Standby Data out Read Company ID 1011 D[31:0] = 0x0000_00DA Address Data out Read Device ID 1100 D[31:0] = A[19:0] = Device ID 0x00000 Address...

  • Page 133: Flash Control Register Map

    NuMicro™ Mini51 Technical Reference Manual 5.7.5 Flash Control Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value FMC_BA = 0x5000_C000 ISPCON FMC_BA+0x00 ISP Control Register 0x0000_0000 ISPADR FMC_BA+0x04 ISP Address Register 0x0000_0000 ISPDAT FMC_BA+0x08...

  • Page 134: Flash Control Register

    NuMicro™ Mini51 Technical Reference Manual 5.7.6 Flash Control Register ISP Control Register (ISPCON) Register Offset Description Reset Value ISPCON FMC_BA+0x00 ISP Control Register 0x0000_0000 SWRST ISPFF LDUEN CFGUEN ISPEN Bits Description [31:15] Reserved Flash Erase Time ET[2] ET[1] ET[0] Erase Time (ms) 20 (default) ET[2:0] [14:12]...
  • Page 135 NuMicro™ Mini51 Technical Reference Manual Bits Description Flash Program Time PT[2] PT[1] PT[0] Program Time (us) [10:8] PT[2:0] Software Reset Writing “1” to this bit to start software reset. SWRST It is cleared by hardware after reset is finished. ISP Fail Flag This bit is set by hardware when a triggered ISP meets any of the following conditions: (1) APROM writes to itself.
  • Page 136 NuMicro™ Mini51 Technical Reference Manual Bits Description ISP Enable ISP function enable bit. Set this bit to enable ISP function. ISPEN 1 = ISP function Enabled. 0 = ISP function Disabled. Feb 9, 2012 Page 136 of 342 Revision V1.03...
  • Page 137 NuMicro™ Mini51 Technical Reference Manual ISP Address (ISPADR) Register Offset Description Reset Value ISPADR FMC_BA+0x04 ISP Address Register 0x0000_0000 ISPADR ISPADR ISPADR ISPADR Bits Description ISP Address [31:0] ISPADR[31:0] The NuMicro Mini51 series supports word program only. ISPADR[1:0] must be kept 00 for ISP operation.
  • Page 138 NuMicro™ Mini51 Technical Reference Manual ISPDAT (ISP Data Register) Register Offset Description Reset Value ISPDAT FMC_BA+0x08 ISP Data Register 0x0000_0000 ISPDAT ISPDAT ISPDAT ISPDAT Bits Description ISP Data ISPDAT[31:0] [31:0] Write data to this register before ISP program operation. Read data from this register after ISP read operation. Feb 9, 2012 Page 138 of 342 Revision V1.03...
  • Page 139 NuMicro™ Mini51 Technical Reference Manual ISP Command (ISPCMD) Register Offset Description Reset Value ISPCMD FMC_BA+0x0C ISP Command Register 0x0000_0000 FOEN FCEN FCTRL Bits Description Reserved [31:6] ISP Command ISP command is the same as writer mode except whole chip erase is not supported. Operation Mode FOEN FCEN...
  • Page 140 NuMicro™ Mini51 Technical Reference Manual ISP Trigger Control Register (ISPTRG) Register Offset Description Reset Value ISPTRG FMC_BA+0x10 ISP Trigger Control Register 0x0000_0000 ISPGO Bits Description [31:1] Reserved ISP Start Trigger Write “1” to start ISP operation; this bit will be cleared to “0” by hardware automatically when ISP operation is finished.
  • Page 141 NuMicro™ Mini51 Technical Reference Manual Data Flash Base Address Register (DFBA) Register Offset Description Reset Value DFBA FMC_BA+0x14 Data flash Base Address 0x0000_3800 DFBA DFBA DFBA DFBA Bits Description Data Flash Base Address This register indicates data flash start address. It is a read only register. [31:0] DFBA[31:0] The data flash start address is defined by user.

  • Page 142: General Purpose I/O

    NuMicro™ Mini51 Technical Reference Manual General Purpose I/O 5.8.1 Overview There are 30 General Purpose I/O pins shared with special feature functions in this MCU. The 30 pins are arranged in 6 ports named P0, P1, P2, P3, P4 and P5. Each of the 30 pins is independent and has the corresponding register bits to control the pin mode function and data.

  • Page 143: Figure 5.8-1 Push-Pull Output

    NuMicro™ Mini51 Technical Reference Manual Port Pin Port Latch Data Input Data Figure 5.8-1 Push-Pull Output 5.8.3.3 Open-drain Mode When Px_PMD (PMDn[1:0]) is set to 10, the Px[n] pin is in Open-Drain mode and the digital output function of I/O pin supports only sink current capability, and an additional pull-up register is needed for driving high state.

  • Page 144: Figure 5.8-3 Quasi-Bidirectional I/O Mode

    NuMicro™ Mini51 Technical Reference Manual 2 CPU Very Clock Delay Strong Weak Weak Port Pin Port Latch Data Input Data Figure 5.8-3 Quasi-bidirectional I/O Mode Feb 9, 2012 Page 144 of 342 Revision V1.03...

  • Page 145: Port 0-5 Control Register Map

    NuMicro™ Mini51 Technical Reference Manual 5.8.4 Port 0-5 Control Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value GP_BA = 0x5000_4000 P0_PMD GP_BA+0x000 P0 Pin I/O Mode Control 0x0000_0000 P0_OFFD GP_BA+0x004 P0 Pin OFF Digital Enable 0x0000_0000 P0_DOUT...
  • Page 146 NuMicro™ Mini51 Technical Reference Manual Register Offset Description Reset Value GP_BA = 0x5000_4000 P2_ISRC GP_BA+0x0A0 P2 Interrupt Trigger Source Indicator 0x0000_0000 P3_PMD GP_BA+0x0C0 P3 Pin Mode Enable 0x0000_0000 P3_OFFD GP_BA+0x0C4 P3 Pin OFF Digital Enable 0x0000_0000 P3_DOUT GP_BA+0x0C8 P3 Data Output Value 0x0000_0077 P3_DMASK GP_BA+0x0CC...
  • Page 147 NuMicro™ Mini51 Technical Reference Manual Register Offset Description Reset Value GP_BA = 0x5000_4000 P00_DOUT GP_BA+0x200 P0.0 Data Output Value 0x0000_0001 P01_DOUT GP_BA+0x204 P0.1 Data Output Value 0x0000_0001 P04_DOUT GP_BA+0x210 P0.4 Data Output Value 0x0000_0001 P05_DOUT GP_BA+0x214 P0.5 Data Output Value 0x0000_0001 P06_DOUT GP_BA+0x218...
  • Page 148 NuMicro™ Mini51 Technical Reference Manual Register Offset Description Reset Value GP_BA = 0x5000_4000 P54_DOUT GP_BA+0x2B0 P5.4 Data Output Value 0x0000_0001 P55_DOUT GP_BA+0x2B4 P5.5 Data Output Value 0x0000_0001 Note: Software must set the un-bonding out pin P5.5 to output mode when using QFN-33 package IC to minimize the power-down consumption.

  • Page 149: Port 0-5 Control Register

    NuMicro™ Mini51 Technical Reference Manual 5.8.5 Port 0-5 Control Register Port 0-5 Pin I/O Mode Control (Px_PMD) Register Offset Description Reset Value P0_PMD GP_BA+0x000 P0 Pin I/O Mode Control 0x0000_0000 P1_PMD GP_BA+0x040 P1 Pin I/O Mode Control 0x0000_0000 P2_PMD GP_BA+0x080 P2 Pin I/O Mode Control 0x0000_0000 P3_PMD...
  • Page 150 NuMicro™ Mini51 Technical Reference Manual Bits Description P4_PMD[11:0] are reserved. P5_PMD[15:12] are reserved. Feb 9, 2012 Page 150 of 342 Revision V1.03...
  • Page 151 NuMicro™ Mini51 Technical Reference Manual Port 0-5 Pin OFF Digital Enable (Px_OFFD) Register Offset Description Reset Value P0_OFFD GP_BA+0x004 P0 Pin OFF Digital Enable 0x0000_0000 P1_OFFD GP_BA+0x044 P1 Pin OFF Digital Enable 0x0000_0000 P2_OFFD GP_BA+0x084 P2 Pin OFF Digital Enable 0x0000_0000 P3_OFFD GP_BA+0x0C4...
  • Page 152 NuMicro™ Mini51 Technical Reference Manual Port 0-5 Data Output Value (Px_DOUT) Register Offset Description Reset Value P0_DOUT GP_BA+0x008 P0 Data Output Value 0x0000_00F3 P1_DOUT GP_BA+0x048 P1 Data Output Value 0x0000_003D P2_DOUT GP_BA+0x088 P2 Data Output Value 0x0000_007C P3_DOUT GP_BA+0x0C8 P3 Data Output Value 0x0000_0077 P4_DOUT GP_BA+0x108...
  • Page 153 NuMicro™ Mini51 Technical Reference Manual Port 0-5 Data Output Write Mask (Px_DMASK) Register Offset Description Reset Value P0_DMASK GP_BA+0x00C P0 Data Output Write Mask 0x0000_0000 P1_DMASK GP_BA+0x04C P1 Data Output Write Mask 0x0000_0000 P2_DMASK GP_BA+0x08C P2 Data Output Write Mask 0x0000_0000 P3_DMASK GP_BA+0x0CC...
  • Page 154 NuMicro™ Mini51 Technical Reference Manual Port 0-5 Pin Value (Px_PIN) Register Offset Description Reset Value P0_PIN GP_BA+0x010 P0 Pin Value 0x0000_00XX P1_PIN GP_BA+0x050 P1 Pin Value 0x0000_00XX P2_PIN GP_BA+0x090 P2 Pin Value 0x0000_00XX P3_PIN GP_BA+0x0D0 P3 Pin Value 0x0000_00XX P4_PIN GP_BA+0x110 P4 Pin Value 0x0000_00XX...
  • Page 155 NuMicro™ Mini51 Technical Reference Manual Port 0-5 De-bounce Enable (Px_DBEN) Register Offset Description Reset Value P0_DBEN GP_BA+0x014 P0 De-bounce Enable 0x0000_0000 P1_DBEN GP_BA+0x054 P1 De-bounce Enable 0x0000_0000 P2_DBEN GP_BA+0x094 P2 De-bounce Enable 0x0000_0000 P3_DBEN GP_BA+0x0D4 P3 De-bounce Enable 0x0000_0000 P4_DBEN GP_BA+0x114 P4 De-bounce Enable 0x0000_0000...
  • Page 156 NuMicro™ Mini51 Technical Reference Manual Bits Description Note: P0_DBEN[3:2] are reserved. P1_DBEN [7:6], [1] are reserved. P2_DBEN [7], [1:0] are reserved. P3_DBEN [7], [3] are reserved. P4_DBEN [5:0] are reserved. P5_DBEN [7:6] are reserved. Feb 9, 2012 Page 156 of 342 Revision V1.03...
  • Page 157 NuMicro™ Mini51 Technical Reference Manual Port 0-5 Interrupt Mode Control (Px_IMD) Register Offset Description Reset Value P0_IMD GP_BA+0x018 P0 Interrupt Mode Control 0x0000_0000 P1_IMD GP_BA+0x058 P1 Interrupt Mode Control 0x0000_0000 P2_IMD GP_BA+0x098 P2 Interrupt Mode Control 0x0000_0000 P3_IMD GP_BA+0x0D8 P3 Interrupt Mode Control 0x0000_0000 P4_IMD GP_BA+0x118...
  • Page 158 NuMicro™ Mini51 Technical Reference Manual Bits Description Note: P0_IMD[3:2] are reserved. P1_IMD [7:6], [1] are reserved. P2_IMD [7], [1:0] are reserved. P3_IMD [7], [3] are reserved. P4_IMD [5:0] are reserved. P5_IMD [7:6] are reserved. Feb 9, 2012 Page 158 of 342 Revision V1.03...
  • Page 159 NuMicro™ Mini51 Technical Reference Manual Port 0-5 Interrupt Enable (Px_IEN) Register Offset Description Reset Value P0_IEN GP_BA+0x01C P0 Interrupt Enable 0x0000_0000 P1_IEN GP_BA+0x05C P1 Interrupt Enable 0x0000_0000 P2_IEN GP_BA+0x09C P2 Interrupt Enable 0x0000_0000 P3_IEN GP_BA+0x0DC P3 Interrupt Enable 0x0000_0000 P4_IEN GP_BA+0x11C P4 Interrupt Enable 0x0000_0000...
  • Page 160 NuMicro™ Mini51 Technical Reference Manual Bits Description Port 0-5 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Setting bit “1” also enables the pin wake-up function. When the IF_EB[n] bit is set to “1”: If the interrupt is level mode trigger, the input Px[n] state at level “low”...
  • Page 161 NuMicro™ Mini51 Technical Reference Manual Port 0-5 Interrupt Trigger Source Indicator (Px_ISRC) Register Offset Description Reset Value P0_ISRC GP_BA+0x020 P0 Interrupt Trigger Source Indicator 0x0000_0000 P1_ISRC GP_BA+0x060 P1 Interrupt Trigger Source Indicator 0x0000_0000 P2_ISRC GP_BA+0x0A0 P2 Interrupt Trigger Source Indicator 0x0000_0000 P3_ISRC GP_BA+0x0E0...
  • Page 162 NuMicro™ Mini51 Technical Reference Manual Bits Description Note: P0_ISRC [3:2] are reserved. P1_ISRC [7:6], [1] are reserved. P2_ISRC [7], [1:0] are reserved. P3_ISRC [7], [3] are reserved. P4_ISRC [5:0] are reserved. P5_ISRC [7:6] are reserved. Feb 9, 2012 Page 162 of 342 Revision V1.03...
  • Page 163 NuMicro™ Mini51 Technical Reference Manual Interrupt De-bounce Cycle Control (DBNCECON) Register Offset Description Reset Value DBNCECON GP_BA+0x180 External Interrupt De-bounce Control 0x0000_0020 ICLK_ON DBCLKSRC DBCLKSEL Bits Description [31:6] Reserved Interrupt Clock On Mode Setting this bit to “0” will disable the interrupt generate circuit clock if the pin[n] interrupt is disabled.
  • Page 164 NuMicro™ Mini51 Technical Reference Manual Bits Description De-bounce Sampling Cycle Selection DBCLKSEL Description Sample interrupt input once per 1 clock Sample interrupt input once per 2 clocks Sample interrupt input once per 4 clocks Sample interrupt input once per 8 clocks Sample interrupt input once per 16 clocks Sample interrupt input once per 32 clocks Sample interrupt input once per 64 clocks...
  • Page 165 NuMicro™ Mini51 Technical Reference Manual GPIO Port [P0/P1/P2/P3/P4/P5] I/O Bit Output Control (P[x][n]_DOUT) P[x][n]_DOUT: x = 0~5, n = 0~7 Register Offset Description Reset Value GP_BA+0x200 P0 Pin I/O Bit Output/Input Control. P0[n]_DOUT 0x0000_0001 For P0, n = 0, 1, 4, 5, 6, 7 GP_BA+0x21C GP_BA+0x220 P1 Pin I/O Bit Output/Input Control.
  • Page 166 NuMicro™ Mini51 Technical Reference Manual Bits Description [31:1] Reserved P[x][n] I/O Pin Bit Output/Input Control Writing this bit can control one GPIO pin output value. 1 = The corresponding GPIO pin set to high. 0 = The corresponding GPIO pin set to low. Read this register to get IO pin status.

  • Page 167: I 2 C Serial Interface Controller (Master/Slave)

    NuMicro™ Mini51 Technical Reference Manual C Serial Interface Controller (Master/Slave) 5.9.1 Overview C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. The I C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously.

  • Page 168: C Protocol

    NuMicro™ Mini51 Technical Reference Manual and timer-out counter overflows  External pull-up needed for higher output pull-up speed  Programmable clocks allowing for versatile rate control  Supports 7-bit addressing mode  Supports multiple address recognition (four slave address registers with mask option) 5.9.3 C Protocol Normally, a standard communication consists of four parts:...

  • Page 169: Figure 5.9-4 Master Reads Data From Slave

    NuMicro™ Mini51 Technical Reference Manual SLAVE ADDRESS DATA DATA data transfer (n bytes + acknowledge) '1'(read) Figure 5.9-4 Master Reads Data from Slave 5.9.3.2 START or Repeated START signal When the bus is free/idle, meaning no master device is engaging the bus (both SCL and SDA lines are high), a master can initiate a transfer by sending a START signal.

  • Page 170: Figure 5.9-6 Bit Transfer On The I C Bus

    NuMicro™ Mini51 Technical Reference Manual If the master, as the receiving device, does Not Acknowledge (NACK) the slave, the slave releases the SDA line for the master to generate a STOP or Repeated START signal. data line change stable; of data data valid allowed Figure 5.9-6 Bit Transfer on the I...

  • Page 171: I 2 C Protocol Registers

    NuMicro™ Mini51 Technical Reference Manual clock pulse for acknowledgement SCL FROM MASTER DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge START condition Figure 5.9-7 Acknowledge on the I C Bus 5.9.4 C Protocol Registers The CPU interfaces to the I C port through the following thirteen special function registers: I2CON (control register), I2CSTATUS (status register), I2CDAT (data register), I2CADDRn (address registers, n=0~3), I2CADMn (address mask registers, n=0~3), I2CLK (clock rate register) and...

  • Page 172: Figure 5.9-8 I 2 C Data Shifting Direction

    NuMicro™ Mini51 Technical Reference Manual 5.9.4.2 Data Register (I2CDAT) This register contains a byte of serial data to be transmitted or a byte which just has been received. The CPU can read from or write to this 8-bit (I2CDAT[7:0]) directly while it is not in the process of shifting a byte.

  • Page 173: Figure 5.9-9 I 2 C Time-Out Count Block Diagram

    NuMicro™ Mini51 Technical Reference Manual 5.9.4.4 Status Register (I2CSTATUS) I2CSTATUS[7:0] is an 8-bit read-only register. The three least significant bits are always “0”. The bit field I2CSTATUS[7:3] contain the status code. There are 27 possible status code. All states are listed in section 5.9.12.

  • Page 174: Register Mapping

    NuMicro™ Mini51 Technical Reference Manual 5.9.5 Register Mapping R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value I2C_BA = 0x4002_0000 I2CON I2C_BA+0x00 C Control Register 0x0000_0000 I2CADRR0 I2C_BA+0x04 C Slave Address Register 0 0x0000_0000 I2CDAT I2C_BA+0x08...

  • Page 175: Register Description

    NuMicro™ Mini51 Technical Reference Manual 5.9.6 Register Description C CONTROL REGISTER (I2CON) Register Offset Description Reset Value I2CON I2C_BA+0x00 C Control Register 0x0000_0000 ENSI Bits Description Reserved [31:8] Enable Interrupt 1 = I C interrupt Enabled. 0 = I C interrupt Disabled. C Controller Enable Bit 1 = Enabled.
  • Page 176 NuMicro™ Mini51 Technical Reference Manual Bits Description Assert Acknowledge Control Bit When AA=1 is prior to address or data received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter.
  • Page 177 NuMicro™ Mini51 Technical Reference Manual C DATA REGISTER (I2CDAT) Register Offset Description Reset Value I2CDAT I2C_BA+0x08 C DATA Register 0x0000_0000 I2CDAT Bits Description [31:8] Reserved C Data Register [7:0] I2CDAT[7:0] Bit [7:0] is located with the 8-bit transferred data of the I C serial port.
  • Page 178 NuMicro™ Mini51 Technical Reference Manual C STATUS REGISTER ( I2CSTATUS ) Register Offset Description Reset Value I2CSTATUS I2C_BA+0x0C C STATUS Register 0x0000_00F8 I2CSTATUS Bits Description [31:8] Reserved C Status Register The status register of I C controller: The three least significant bits are always “0”. The five most significant bits contain the status code.
  • Page 179 NuMicro™ Mini51 Technical Reference Manual STATUS Description STATUS Description 0x08 Start 0xA0 Slave Transmit Repeat Start or Stop 0x10 Master Repeat Start 0xA8 Slave Transmit Address ACK 0x18 Master Transmit Address ACK 0xB0 Slave Transmit Arbitration Lost 0x20 Master Transmit Address NACK 0xB8 Slave Transmit Data ACK 0x28...
  • Page 180 NuMicro™ Mini51 Technical Reference Manual C BAUD RATE CONTROL REGISTER (I2CLK) Register Offset Description Reset Value I2CLK I2C_BA+0x10 C Clock Divided Register 0x0000_0000 I2CLK Bits Description [31:8] Reserved C clock divided Register [7:0] I2CLK[7:0] The I C clock rate bits: Data Baud Rate of I2C = PCLK / (4x (I2CLK+1)). Feb 9, 2012 Page 180 of 342 Revision V1.03...
  • Page 181 NuMicro™ Mini51 Technical Reference Manual C TIME-OUT COUNTER REGISTER (I2CTOC) Register Offset Description Reset Value I2CTOC I2C_BA+0x14 C Time-out Counter Register 0x0000_0000 ENTI DIV4 Bits Description [31:3] Reserved Time-out CounterEenable 1 = Enabled. ENTI 0 = Disabled. When enabled, the 14-bit time-out counter will start counting when SI is clear. Setting flag SI to high will reset counter and re-start up counting after SI is cleared.
  • Page 182 NuMicro™ Mini51 Technical Reference Manual C SLAVE ADDRESS REGISTER (I2CADDRx) Register Offset Description Reset Value I2CADDR0 I2C_BA+0x04 C Slave Address Register 0 0x0000_0000 I2CADDR1 I2C_BA+0x18 C Slave Address Register 1 0x0000_0000 I2CADDR2 I2C_BA+0x1C C Slave Address Register 2 0x0000_0000 I2CADDR3 I2C_BA+0x20 C Slave Address Register 3 0x0000_0000...
  • Page 183 NuMicro™ Mini51 Technical Reference Manual C SLAVE ADDRESS REGISTER (I2CADDRx) Register Offset Description Reset Value I2CADM0 I2C_BA+0x24 C Slave Address Mask Register 0 0x0000_0000 I2CADM1 I2C_BA+0x28 C Slave Address Mask Register 1 0x0000_0000 I2CADM2 I2C_BA+0x2C C Slave Address Mask Register 2 0x0000_0000 I2CADM3 I2C_BA+0x30...

  • Page 184: Operation Modes

    NuMicro™ Mini51 Technical Reference Manual 5.9.7 Operation Modes The on-chip I C port supports five operation modes: Master transmitter, Master receiver, Slave transmitter, Slave receiver, and GC call. In a given application, I C port may operate as a master or as a slave. In Slave mode, the I C port hardware looks for its own slave address and the general call address.

  • Page 185: Figure 5.9-10 Legend For The Following Five Figures

    NuMicro™ Mini51 Technical Reference Manual Software's access to I2DAT with respect to "Expected next action": Last state (1) Data byte will be transmitted: A START has been Last action is done Software should load the data byte (to be transmitted) transmitted.

  • Page 186: Figure 5.9-11 Master Transmitter Mode

    NuMicro™ Mini51 Technical Reference Manual Set STA to generate a START. From Slave Mode (C) A START has been transmitted. (STA,STO,SI,AA)=(0,0,1,X) SLA+W will be transmitted; ACK bit will be received. From Master/Receiver (B) SLA+W will be transmitted; ACK bit will be received. SLA+W will be transmitted;...

  • Page 187: Figure 5.9-12 Master Receiver Mode

    NuMicro™ Mini51 Technical Reference Manual Set STA to generate a START. From Slave Mode (C) A START has been transmitted. (STA,STO,SI,AA)=(0,0,1,X) SLA+R will be transmitted; ACK bit will be received. From Master/Transmitter (A) SLA+R has been transmitted; SLA+R has been transmitted; NOT ACK has been received.

  • Page 188: Figure 5.9-13 Slave Transmitter Mode

    NuMicro™ Mini51 Technical Reference Manual Set AA Own SLA+R has been received; ACK has been return. Arbitration lost SLA+R/W as master; Own SLA+R has been received; ACK has been return. (STA,STO,SI,AA)=(0,0,1,0) (STA,STO,SI,AA)=(0,0,1,1) Last data byte will be transmitted; Data byte will be transmitted; ACK will be received.

  • Page 189: Figure 5.9-14 Slave Receiver Mode

    NuMicro™ Mini51 Technical Reference Manual Set AA Own SLA+W has been received; ACK has been return. Arbitration lost SLA+R/W as master; Own SLA+W has been received; ACK has been return. (STA,STO,SI,AA)=(0,0,1,0) (STA,STO,SI,AA)=(0,0,1,1) Data byte will be received; Data byte will be received; NOT ACK will be returned.

  • Page 190: Figure 5.9-15 Gc Mode

    NuMicro™ Mini51 Technical Reference Manual Set AA Reception of the general call address and one or more data bytes; ACK has been return. Arbitration lost SLA+R/W as master; and address as SLA by general call; ACK has been return. (STA,STO,SI,AA)=(X,0,1,0) (STA,STO,SI,AA)=(X,0,1,1) Data byte will be received;...

  • Page 191: Enhanced Pwm Generator

    NuMicro™ Mini51 Technical Reference Manual 5.10 Enhanced PWM Generator 5.10.1 Overview The NuMicro Mini51 series has built one PWM unit which is specially designed for motor driving control applications. The PWM unit supports 6 PWM generators which can be configured as 6 independent PWM outputs, PWM0~PWM5, or as 3 complementary PWM pairs, (PWM0, PWM1), (PWM2, PWM3) and (PWM4, PWM5) with 3 programmable dead-zone generators.

  • Page 192: Figure 5.10-1 Application Circuit Diagram

    NuMicro™ Mini51 Technical Reference Manual HyperTerminal Trapezoidal Commutation System Architecture DC Bus DC Bus + BLDC Isolation UART circuit UART Interface MINI51 UART Timer DC Bus - nINT0 CPO0 3-Phase Inverter Push PWM0 Button (IPM, MOSFET, IGBT) Enhanced PWM PWM1 PWM2 PWM3 PWM4...

  • Page 193: Pwm Block Diagram

    NuMicro™ Mini51 Technical Reference Manual 5.10.3 PWM Block Diagram PWM10 PCLK Register PRESETn ECK[0] PWM32 ECK[2:0] DFT_Test_Mode Register PRDATA[31:0] PWM10 Output Data Mux PWM54 Function Register Register RegAddr PWM10 RegAddrEn PCLK output ECK[1] PRESETn RegWrCLK p_out1~0 PADDR PWM32 PWM32 RegWrData p_out3~2 output PWDATA...

  • Page 194: Figure 5.10-4 Pwm Generator 2 Architecture Diagram

    NuMicro™ Mini51 Technical Reference Manual DZI23 Dead Zone Generator 1 CNR2 PWM Generator CMR2 CSR2(CSR[2:0]) in PWMB group PDR2 POE.PWM2 PWM2 PWM- Timer2 Logic Clock Divider 1/16 CH2INV PWMIE2 PWMIF2 8-bit PWM23_CLK Prescaler DZEN23 CNR1 (from clock PPR.CP23 CMR1 controller) PDR3 1/16 POE.PWM3...

  • Page 195: Pwm Function

    NuMicro™ Mini51 Technical Reference Manual 5.10.4 PWM Function 5.10.4.1 PWM-Timer Operation This device supports two operation modes: Edge-aligned and Center-aligned mode. Following equations show the formula for period and duty for each PWM operation mode: Edge aligned (Down counter) Duty ratio = (CMR+1) / (CNR+1) Duty = (CMR+1) x (clock period) Period...

  • Page 196: Figure 5.10-6 Edge-Aligned Pwm

    NuMicro™ Mini51 Technical Reference Manual Figure 5.10-6 Edge-aligned PWM CNRn (7FF) CMRn (3FF) s/w clear s/w clear PWMF (INT_TYPE=X) s/w clear s/w clear PWMn generator ouput PWM Period Figure 5.10-7 PWM Edge-aligned Waveform Output Feb 9, 2012 Page 196 of 342 Revision V1.03...

  • Page 197: Figure 5.10-8 Edge-Aligned Flow Diagram

    NuMicro™ Mini51 Technical Reference Manual Set PCR[31] = 0 Set CNRn,CMRn, CSR, PPR Set PWM_OE, CHnMODE Set PWMMODE=2'b00 Start: Set CHnEN = 1 Set CLRPWM = 1 H/w will load CMRn and CNRn to working registers. Down-counting start from CNRn. PWMn output: 0 if counter >...

  • Page 198: Figure 5.10-9 Legend Of Internal Comparator Output Of Pwm-Timer

    NuMicro™ Mini51 Technical Reference Manual The PWM period and duty control are decided by PWM down-counter register (CNRn) and PWM comparator register (CMRn). The PWM-Timer timing operation is shown in Figure 5.10-10. The pulse width modulation follows the formula below and the legend of PWM-Timer Comparator is shown in Figure 5.10-9.

  • Page 199: Figure 5.10-11 Center-Aligned Mode

    NuMicro™ Mini51 Technical Reference Manual Center-Aligned PWM (up/down counter) The center-aligned PWM signals are produced by the module when the PWM time base is configured in an Up/Down Counting mode. The PWM counter will start counting-up from 0 to match the value of CMRn (old); this will cause the toggling of the PWMn generator output to high. The counter will continue counting to match with the CNRn (old).

  • Page 200: Figure 5.10-12 Pwm Center-Aligned Waveform Output

    NuMicro™ Mini51 Technical Reference Manual CNRn (7FF) CMRn (3FF) PWMFn (INT_TYPE=0) s/w clear s/w clear s/w clear PWMFn (INT_TYPE=1) s/w clear s/w clear PWMn generator ouput PWM Period PWM Period Figure 5.10-12 PWM Center-aligned Waveform Output Feb 9, 2012 Page 200 of 342 Revision V1.03...

  • Page 201: Figure 5.10-13 Center-Aligned Flow Diagram (Int_Type = 0)

    NuMicro™ Mini51 Technical Reference Manual Set PCR[31] = 1 Set CNRn,CMRn, CSR, PPR Set PWM_OE, CHnMODE Set PWMMODE=2'b00 Start: Set CHnEN = 1 Set CLRPWM = 1 H/w will load CMRn and CNRn to working registers. up-counting start from zero. PWMn output: 1 if counter >...

  • Page 202: Figure 5.10-14 Pwm Double Buffering Illustration

    NuMicro™ Mini51 Technical Reference Manual 5.10.4.2 PWM Double Buffering, Auto-reload and One-shot Operation The NuMicro Mini51 series PWM Timers have double buffering function the reload value is updated at the start of next period without affecting current timer operation. The PWM counter value can be written into CNRn.

  • Page 203: Pwm Operation Modes

    NuMicro™ Mini51 Technical Reference Manual 5.10.5 PWM Operation Modes This powerful PWM unit supports independent mode which may be applied to DC or BLDC motor system, Complementary mode with dead-zone insertion which may be used in the application of AC induction motor and synchronous motor, and Synchronous mode that makes both pins of each pair are in phase.

  • Page 204: Polarity Control

    NuMicro™ Mini51 Technical Reference Manual In Power inverter applications, a dead-zone insertion avoids the upper and lower switches of the half bridge from being active at the same time. Hence the dead-zone control is crucial to proper operation of a system. Some amount of time must be provided between turning off of one PWM output in a complementary pair and turning on the other transistor as the power output devices cannot switch instantaneously.

  • Page 205: Figure 5.10-17 Initial State And Polarity Control With Rising Edge Dead-Zone Insertion

    NuMicro™ Mini51 Technical Reference Manual Initial State PWM Starts PWM0 (PNP.0=0) PWM1 (PNP.1=0) PWM0 (PNP.0=0) (PNP.1=1) PWM1 NPx: Negative Polarity control bits; It controls the PWM output initial state and polarity Dead-zone insertion; It is only effective in complementary mode Note: Only Odd channels can be set inverter bit when dead-zone insertion and polarity control.

  • Page 206: Pwm For Motor Control Interrupt Architecture

    NuMicro™ Mini51 Technical Reference Manual 5.10.7 PWM for Motor Control Interrupt Architecture There are 4 interrupt sources for a PWM unit, which are PWM period flag (PWMPIF), PWM duty interrupt(PWMDIF), Brake0 flag (BKF0) and Brake1 flag (BKF1). The bit BRKIE (PIER[16]) controls the brake interrupt enable;...

  • Page 207: Pwm Controller Register Map

    NuMicro™ Mini51 Technical Reference Manual 5.10.9 PWM Controller Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value PWM_BA = 0x4004_0000 PWM_BA+0x00 PWM Pre-scale Register 0x0000_0000 PWM_BA+0x04 PWM Clock Select Register 0x0000_0000 PWM_BA+0x08 PWM Control Register 0x0000_0000...

  • Page 208: Pwm Controller Register

    NuMicro™ Mini51 Technical Reference Manual 5.10.10 PWM Controller Register PWM Pre-Scale Register (PPR) Register Offset Description Reset Value PWM_BA+0x00 PWM Pre-scale Register 0x0000_0000 CP45 CP23 CP01 Bits Description Reserved [31:24] Clock Prescaler 4 (PWM Counter 4 and 5 for group) Clock input is divided by (CP45 + 1) before it is fed to the corresponding PWM [23:16] CP45[7:0]...
  • Page 209 NuMicro™ Mini51 Technical Reference Manual PWM Clock Selector Register (CSR) Register Offset Description Reset Value PWM_BA+0x04 PWM Clock Select Register 0x0000_0000 CSR5 CSR4 CSR3 CSR2 CSR1 CSR0 Bits Description [31:23] Reserved Timer 5 Clock Source Selection Select clock input for PWM timer. CSR5 [2:0] Input clock divided by [22:20]...
  • Page 210 NuMicro™ Mini51 Technical Reference Manual Bits Description Timer 2 Clock Source Selection [10:8] CSR2[2:0] Select clock input for PWM timer. (Table is the same as CSR5.) Reserved Timer 1 Clock Source Selection CSR1[2:0] [6:4] Select clock input for PWM timer. (Table is the same as CSR5.) Reserved Timer 0 Clock Source Selection...
  • Page 211 NuMicro™ Mini51 Technical Reference Manual PWM Control Register (PCR) Register Offset Description Reset Value PWM_BA+0x08 PWM Control Register 0x0000_0000 PWMTYPE PWMMOD CLRPWM DZEN45 DZEN23 DZEN01 CH5MOD CH5INV CH5EN CH4MOD CH4INV CH4EN CH3MOD CH3INV CH3EN CH2MOD CH2INV CH2EN CH1MOD CH1INV CH1EN CH0MOD CH0INV DB_MODE...
  • Page 212 NuMicro™ Mini51 Technical Reference Manual Bits Description Dead-zone 2 Generator Enable/Disable (PWM2 and PWM3 pair for PWM group) 1 = Enabled. [25] DZEN23 0 = Disabled. Note: When the dead-zone generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group. Dead-zone 0 Generator Enable/Disable (PWM0 and PWM1 pair for PWM group) 1 = Enabled.
  • Page 213 NuMicro™ Mini51 Technical Reference Manual Bits Description PWM-Timer 3 Output Inverter ON/OFF 1 = Inverter ON. [14] CH3INV 0 = Inverter OFF. Note: Only even channels (PWM0, PWM2 and PWM4) can be set as inverter bit in independent mode. [13] Reserved PWM-Timer 3 Enable/Disable Start Run [12]...
  • Page 214 NuMicro™ Mini51 Technical Reference Manual Bits Description PWM-Timer 0 Output Inverter ON/OFF CH0INV 1 = Inverter ON. 0 = Inverter OFF. PWM Debug Mode Configuration Bit (Available in DEBUG mode only) 1 = Normal mode: The timer continues to operate normally May be dangerous in some cases since a constant duty cycle is applied to the inverter (no more interrupts DB_MODE serviced).
  • Page 215 NuMicro™ Mini51 Technical Reference Manual PWM Counter Register 0-5 (CNR0-5) Register Offset Description Reset Value CNR0 PWM_BA+0x0C PWM Counter Register 0 0x0000_0000 CNR1 PWM_BA+0x10 PWM Counter Register 1 0x0000_0000 CNR2 PWM_BA+0x14 PWM Counter Register 2 0x0000_0000 CNR3 PWM_BA+0x18 PWM Counter Register 3 0x0000_0000 CNR4 PWM_BA+0x1C...
  • Page 216 NuMicro™ Mini51 Technical Reference Manual Bits Description CMRn = 0: PWM low width = 2 unit; PWM high width = (CNRn) x 2 unit. (Unit = one PWM clock cycle) Note: Any write to CNRn will take effect in next PWM cycle. Feb 9, 2012 Page 216 of 342 Revision V1.03...
  • Page 217 NuMicro™ Mini51 Technical Reference Manual PWM Comparator Register 0-5 (CMR0-5) Register Offset Description Reset Value CMR0 PWM_BA+0x24 PWM Comparator Register 0 0x0000_0000 CMR1 PWM_BA+0x28 PWM Comparator Register 1 0x0000_0000 CMR2 PWM_BA+0x2C PWM Comparator Register 2 0x0000_0000 CMR3 PWM_BA+0x30 PWM Comparator Register 3 0x0000_0000 CMR4 PWM_BA+0x34...
  • Page 218 NuMicro™ Mini51 Technical Reference Manual Bits Description CMRn = 0: PWM low width = 2 unit; PWM high width = (CNRn) x 2 unit (Unit = One PWM clock cycle) Note: Any write to CNRn will take effect in the next PWM cycle. Feb 9, 2012 Page 218 of 342 Revision V1.03...
  • Page 219 NuMicro™ Mini51 Technical Reference Manual PWM Interrupt Enable Register (PIER) Register Offset Description Reset Value PIER PWM_BA+0x54 PWM Interrupt Enable Register 0x0000_0000 INT_TYPE BRKIE PWMDIE5 PWMDIE4 PWMDIE3 PWMDIE2 PWMDIE1 PWMDIE0 PWMPIE5 PWMPIE4 PWMPIE3 PWMPIE2 PWMPIE1 PWMPIE0 Bits Description [31:18] Reserved PWM Interrupt Type Selection Bit 1 = PWMPIFn will be set if PWM counter matches CNRn register.
  • Page 220 NuMicro™ Mini51 Technical Reference Manual Bits Description PWM Channel 1 Duty Interrupt Enable PWMDIE1 1 = Enabled. 0 = Disabled. PWM Channel 0 Duty Interrupt Enable PWMDIE0 1 = Enabled. 0 = Disabled. [7:6] Reserved PWM Channel 5 Period Interrupt Enable PWMPIE5 1 = Enabled.
  • Page 221 NuMicro™ Mini51 Technical Reference Manual PWM Interrupt Indication Register (PIIR) Register Offset Description Reset Value PIIR PWM_BA+0x58 PWM Interrupt Indication Register 0x0000_0000 BKF1 BKF0 PWMDIF5 PWMDIF4 PWMDIF3 PWMDIF2 PWMDIF1 PWMDIF0 PWMPIF5 PWMPIF4 PWMPIF3 PWMPIF2 PWMPIF1 PWMPIF0 Bits Description [31:18] Reserved PWM Brake1 Flag 1 = When PWM Brake detects a falling signal at pin BKP1, this flag will be set to high.
  • Page 222 NuMicro™ Mini51 Technical Reference Manual Bits Description PWM Channel 1 Duty Interrupt Flag PWMDIF1 Flag is set by hardware when a channel 1 PWM counter reaches CMR1. Software can clear this bit by writing “1” to it. PWM Channel 0 Duty Interrupt Flag PWMDIF0 Flag is set by hardware when a channel 0 PWM counter reaches CMR0.
  • Page 223 NuMicro™ Mini51 Technical Reference Manual PWM Output Control Register (PWMPOE) Register Offset Description Reset Value PWMPOE PWM_BA+0x5C PWM Output Control Register for Channel 0~5 0x0000_0000 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 Bits Description [31:6] Reserved PWM Channel 5 Output Enable Register 1 = PWM channel 5 output to pin Enabled.
  • Page 224 NuMicro™ Mini51 Technical Reference Manual Bits Description PWM Channel 0 Output Enable Register 1 = PWM channel 0 output to pin Enabled. PWM0 0 = PWM channel 0 output to pin Disabled. Note: The corresponding GPIO pin must also be switched to PWM function. Feb 9, 2012 Page 224 of 342 Revision V1.03...
  • Page 225 NuMicro™ Mini51 Technical Reference Manual PWM Fault Brake Control Register (PFBCON) Register Offset Description Reset Value PFBCON PWM_BA+0x60 PWM Fault Brake Control Register 0x0000_0000 PWMBKO5 PWMBKO4 PWMBKO3 PWMBKO2 PWMBKO1 PWMBKO0 CPO0BKEN BKEN1 BKEN0 Bits Description [31:30] Reserved PWM Channel 5 Brake Output Select Register [29] PWMBKO5 1 = PWM output high when fault brake conditions asserted.
  • Page 226 NuMicro™ Mini51 Technical Reference Manual Bits Description PWM Fault Brake Event Flag (write “1” clear) 1 = PWM output fault brake state when fault brake conditions asserted. 0 = PWM output initial state when fault brake conditions asserted. [6:3] Reserved BKP1 Fault Brake Function Source Selection CPO0BKEN 1 = CPO0 as one brake source in BKP1.
  • Page 227 NuMicro™ Mini51 Technical Reference Manual PWM Dead-Zone Interval Register (PDZIR) Register Offset Description Reset Value PDZIR PWM_BA+0x64 PWM Dead-zone Interval Register 0x0000_0000 DZI45 DZI23 DZI01 Bits Description [31:24] Reserved Dead-zone Interval Register for Pair of channel4 and channel5 (PWM4 and PWM5 pair).

  • Page 228: Serial Peripheral Interface (Spi) Controller

    NuMicro™ Mini51 Technical Reference Manual 5.11 Serial Peripheral Interface (SPI) Controller 5.11.1 Overview The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol which operates in full duplex mode. Devices communicate in Master/Slave mode with 4-wire bi-direction interface. NuMicro Mini51 series contain one set of SPI controller performing a serial-to-parallel conversion on data received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device.

  • Page 229: Functional Description

    NuMicro™ Mini51 Technical Reference Manual 5.11.4 Functional Description 5.11.4.1 Master/Slave Mode This SPI controller can be set as Master or Slave mode by setting the SLAVE bit (SPI_CNTRL[18]) to communicate with the off-chip SPI slave or master device. The application block diagrams in Master and Slave mode are shown in the following figures.
  • Page 230 NuMicro™ Mini51 Technical Reference Manual 5.11.4.3 Automatic Slave Selection In Master mode, if the bit ASS (SPI_SSR[3]) is set, the slave select signal will be generated automatically and output to SPISS pin according to SSR (SPI_SSR[0]) whether enabled or not. It means that the slave select signal, which is enabled in SSR register is asserted by the SPI controller when transmit/receive is started by setting the GO_BUSY bit (SPI_CNTRL[0]) and is de- asserted after the data transfer is finished.

  • Page 231: Figure 5.11-4 Two Transfer (Burst Mode) In One Transaction

    NuMicro™ Mini51 Technical Reference Manual Figure 5.11-4 Two Transfer (Burst Mode) in One Transaction 5.11.4.8 LSB First The LSB bit (SPI_CNTRL[10]) defines the data transmission either from LSB or from MSB to start to transmit/receive data. 5.11.4.9 Transmit Edge The TX_NEG bit (SPI_CNTRL[2]) defines the data transmitted out either at negative edge or at positive edge of serial clock SPICLK.

  • Page 232: Figure 5.11-6 Byte Reorder

    NuMicro™ Mini51 Technical Reference Manual BYTE1, and BYTE2 will be transmitted/received data step by step in MSB first. The rule of 16-bit mode is the same as above. SPI_Tx0/SPI_Rx0 TX/RX Buffer MSB first LSB = 0 (MSB first) MSB first &...

  • Page 233: Figure 5.11-8 Variable Serial Clock Frequency

    NuMicro™ Mini51 Technical Reference Manual Byte reorder function active. Insert a clock idle interval among each byte. The setting of TX_BIT_LEN must be configured as 0x00 (32 bits/ word). Bytes reorder function active but no clock idle interval among each byte.

  • Page 234: Figure 5.11-9 Spi Timing In Master Mode

    NuMicro™ Mini51 Technical Reference Manual 5.11.4.16 SPI Timing Diagram In Master/Slave mode, the active level of device/slave select (SPISS) signal can be programmed to low active or high active in SS_LVL bit (SPI_SSR[2]), but the SPISS is level trigger or edge trigger which is defined in SS_LTRIG bit (SPI_SSR[4]).

  • Page 235: Figure 5.11-10 Spi Timing In Master Mode (Alternate Phase Of Spiclk)

    NuMicro™ Mini51 Technical Reference Manual SS_LVL=1 SPISS SS_LVL=0 CLKP=0 SPICLK CLKP=1 Tx0[1] Tx0[2] Tx0[3] Tx0[4] Tx0[5] Tx0[6] MOSI Tx0[0] Tx0[7] MISO Rx0[1] Rx0[2] Rx0[3] Rx0[4] Rx0[5] Rx0[6] Rx0[0] Rx0[7] Master Mode: CNTRL[SLAVE]=0, CNTRL[LSB]=1, CNTRL[Tx_NUM]=0x0, CNTRL[Tx_BIT_LEN]=0x08 1. CNTRL[CLKP]=0, CNTRL[Tx_NEG]=0, CNTRL[Rx_NEG]=1 or 2.

  • Page 236: Figure 5.11-12 Spi Timing In Slave Mode (Alternate Phase Of Spiclk)

    NuMicro™ Mini51 Technical Reference Manual SS_LVL=1 SPISS SS_LVL=0 CLKP=0 SPICLK CLKP=1 MISO Tx0[1] Tx0[7] Tx1[0] Tx1[6] Tx0[0] Tx1[7] MOSI Rx0[1] Rx0[7] Rx1[0] Rx1[6] Rx0[0] Rx1[7] Slave Mode: CNTRL[SLAVE]=1, CNTRL[LSB]=1, CNTRL[Tx_NUM]=0x01, CNTRL[Tx_BIT_LEN]=0x08 1. CNTRL[CLKP]=0, CNTRL[Tx_NEG]=0, CNTRL[Rx_NEG]=1 or 2. CNTRL[CLKP]=1, CNTRL[Tx_NEG]=1, CNTRL[Rx_NEG]=0 Figure 5.11-12 SPI Timing in Slave Mode (Alternate Phase of SPICLK) 5.11.4.17 SPI Programming Examples Example 1: The SPI controller is set as a master to access an off-chip slave device with following...
  • Page 237 NuMicro™ Mini51 Technical Reference Manual actions. Set this SPI controller as the master device in SLAVE bit (SPI_CNTRL[18] = 0). Force the serial clock idle state at low in CLKP bit (SPI_CNTRL[11] = 0). Select data transmitted at negative edge of serial clock in TX_NEG bit (SPI_CNTRL[2] = 1).
  • Page 238 NuMicro™ Mini51 Technical Reference Manual Write the related settings into the SPI_CNTRL register to control this SPI slave actions. Set this SPI controller as slave device in SLAVE bit (SPI_CNTRL[18] = 1). Select the serial clock idle state at high in CLKP bit (SPI_CNTRL[11] = 1). Select data transmitted at negative edge of serial clock in TX_NEG bit (SPI_CNTRL[2] = 1).

  • Page 239: Spi Serial Interface Control Register Map

    NuMicro™ Mini51 Technical Reference Manual 5.11.5 SPI Serial Interface Control Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value SPI_BA = 0x4003_4000 SPI_CNTRL SPI_BA+0x00 Control and Status Register 0x0000_0004 SPI_DIVIDER SPI_BA+0x04 Clock Divider Register 0x0000_0000 SPI_SSR...

  • Page 240: Register Description

    NuMicro™ Mini51 Technical Reference Manual 5.11.6 Register Description SPI Control and Status Register (SPI_CNTRL) Register Offset Description Reset Value SPI_CNTRL SPI_BA+0x00 Control and Status Register 0x0000_0004 VARCLK_EN REORDER SLAVE SP_CYCLE CLKP TX_NUM TX_BIT_LEN TX_NEG RX_NEG GO_BUSY Bits Description [31:24] Reserved Variable Clock Enable (Master Only) 1 = The serial clock output frequency is variable.
  • Page 241 NuMicro™ Mini51 Technical Reference Manual Bits Description 1 = Slave mode. 0 = Master mode. Interrupt Enable [17] 1 = SPI Interrupt Enabled. 0 = SPI Interrupt Disabled. Interrupt Flag 1 = The transfer done. The interrupt flag is set if it was enabled. [16] 0 =The transfer does not finish yet.
  • Page 242 NuMicro™ Mini51 Technical Reference Manual Bits Description Reserved Note: In Slave mode with level-trigger configuration, the slave select pin must be kept at active state during the successive data transfer. Transmit Bit Length This field specifies how many bits are transmitted in one transmit/receive. Up to 32 bits can be transmitted.
  • Page 243 NuMicro™ Mini51 Technical Reference Manual SPI Divider Register (SPI_DIVIDER) Register Offset Description Reset Value SPI_DIVIDER SPI_BA+0x04 Clock Divider Register (Master Only) 0x0000_0000 DIVIDER2 DIVIDER2 DIVIDER DIVIDER Bits Description Clock Divider 2 Register (Master Only) The value in this field is the 2nd frequency divider of the system clock, PCLK, to generate the serial clock on the output SPICLK.
  • Page 244 NuMicro™ Mini51 Technical Reference Manual SPI Slave Select Register (SPI_SSR) Register Offset Description Reset Value SPI_SSR SPI_BA+0x08 Slave Select Register 0x0000_0000 LTRIG_FLAG SS_LTRIG SS_LVL Bits Description Reserved [31:6] Level Trigger Flag When the SS_LTRIG bit is set in Slave mode, this bit can be read to indicate whether the received bit number meets the requirement or not.
  • Page 245 NuMicro™ Mini51 Technical Reference Manual Bits Description Slave Select Register (Master Only) If ASS bit is cleared, writing “1” to any bit location of this field will set the proper SPISS line to an active state and writing “0” will set the line back to inactive state. If ASS bit is set, writing “1”...
  • Page 246 NuMicro™ Mini51 Technical Reference Manual SPI Data Receive Register (SPI_RX) Register Offset Description Reset Value SPI_RX0 SPI_BA+0x10 Data Receive Register 0 0x0000_0000 SPI_RX1 SPI_BA+0x14 Data Receive Register 1 0x0000_0000 Bits Description Data Receive Register The Data Receive Registers hold the value of received data of the last executed transfer.
  • Page 247 NuMicro™ Mini51 Technical Reference Manual SPI Data Transmit Register (SPI_TX) Register Offset Description Reset Value SPI_TX0 SPI_BA+0x20 Data Transmit Register 0 0x0000_0000 SPI_TX1 SPI_BA+0x24 Data Transmit Register 1 0x0000_0000 Bits Description Data Transmit Register The Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the CNTRL register.
  • Page 248 NuMicro™ Mini51 Technical Reference Manual SPI Variable Clock Register (SPI_VARCLK) Register Offset Description Reset Value SPI_VARCLK SPI_BA+0x34 Variable Clock Pattern Register 0x007F_FF87 VARCLK VARCLK VARCLK VARCLK Bits Description Variable clock Pattern The value in this field is the frequency pattern of the SPI clock. If the bit pattern of VARCLK is “0”, the output frequency of SPICLK is in accordance with the value of DIVIDER.
  • Page 249 NuMicro™ Mini51 Technical Reference Manual SPI Control and Status Register 2 (SPI_CNTRL2) Register Offset Description Reset Value SPI_CNTRL SPI_BA+0x3C Control and Status Register 2 0x0000_0000 SLV_START_I SSTA_INTEN SLV_ABORT NOSLVSEL NTSTS DIV_ONE Bits Description [31:12] Reserved Slave Start Interrupt Status It is used to indicate that the transfer has started in Slave mode with no slave selected.
  • Page 250 NuMicro™ Mini51 Technical Reference Manual Bits Description as “1”, the controller start to transmit/receive data after the GO_BUSY bit active and the serial clock input. 0 = The controller is 4-wire bi-direction interface. Note: In no slave select signal mode, the SS_LTRIG, SPI_SSR[4] shall be set as “1”. [7:1] Reserved Clock Divider Fixed Divide one Register...

  • Page 251: Timer Controller

    NuMicro™ Mini51 Technical Reference Manual 5.12 Timer Controller 5.12.1 Overview The timer module includes two channels, TIMER0~TIMER1, which allow user to easily implement a timer control for applications. The timer can perform functions like frequency measurement, interval measurement, clock generation, delay timing, and so on. The timer can generate an interrupt signal upon time-out, or provide the current value of count during operation.

  • Page 252: Block Diagram

    NuMicro™ Mini51 Technical Reference Manual 5.12.3 Block Diagram Each channel is equipped with an 8-bit pre-scale counter, a 24-bit up-timer, a 24-bit compare register and an interrupt request signal. Refer to Figure 5.12-1. There are five options of clock sources for each channel. Figure 5.12-2 illustrates the clock source control function. TCSR[CRST] Reset Counter 24-Bit TCMPR...

  • Page 253: Functional Description

    NuMicro™ Mini51 Technical Reference Manual 5.12.4 Functional Description A Timer controller provides one-shot, periodic, toggle and continuous counting operation modes. It also provides the event counting function to count the event from the external pin and input capture function to capture or reset timer counter value. Each operating function mode is shown as follows: 5.12.4.1 One-Shot Mode If the timer is operated at one-shot mode and CEN (TCSR[30] timer enable bit) is set to “1”, the...

  • Page 254: Figure 5.12-3 Continuous Counting Mode

    NuMicro™ Mini51 Technical Reference Manual signal is generated depending on TDR = TCMPR if IE is enabled. User can change different TCMPR value immediately without disabling timer counting and restarting timer counting. For example, TCMPR is set as 80, first. (The TCMPR should be less than 2 -1 and be greater than 1).

  • Page 255: Table 5.12-1 Input Capture Mode Operation

    NuMicro™ Mini51 Technical Reference Manual 5.12.4.7 Free-Counting Capture Mode If CAP_MODE is cleared to “0”, TEXEN (TEXCON[3]) is set to “1” and RSTCAPN is set to “0”, the TDR will be captured into TCAP register when TEX (Timer External Pin) pin trigger condition occurred. The TEX trigger edge can be chosen by TEX_EDGE.
  • Page 256 NuMicro™ Mini51 Technical Reference Manual Capture Mode External Input Pin is detected to reset TDR as “0” and then starts counting, while the 2nd high to zero transition stops counting Rising Edge Trigger: The 1st zero to high transition on Timer External Input Pin is detected to reset TDR as “0”...

  • Page 257: Register Map

    NuMicro™ Mini51 Technical Reference Manual 5.12.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value TMR_BA = 0x4001_0000 TCSR0 TMR_BA+0x00 Timer0 Control and Status Register 0x0000_0005 TCMPR0 TMR_BA+0x04 Timer0 Compare Register 0x0000_0000 TISR0 TMR_BA+0x08...

  • Page 258: Register Description

    NuMicro™ Mini51 Technical Reference Manual 5.12.6 Register Description Timer Control Register (TCSR) Register Offset Description Reset Value TCSR0 TMR_BA+0x00 Timer0 Control and Status Register 0x0000_0005 TCSR1 TMR_BA+0x20 Timer1 Control and Status Register 0x0000_0005 DBGACK_TMR MODE CRST CACT WAKE_EN TDR_EN PRESCALE Bits Description ICE Debug Mode Acknowledge Disable (Write-protection Bit)
  • Page 259 NuMicro™ Mini51 Technical Reference Manual Bits Description automatically cleared by hardware. The timer is operating in Periodic mode. The associated interrupt signal is generated periodically (if IE is enabled). The timer is operating in Toggle mode. The interrupt signal is generated periodically (if IE is enabled).
  • Page 260 NuMicro™ Mini51 Technical Reference Manual Timer Compare Register (TCMPR) Register Offset Description Reset Value TCMPR0 TMR_BA+0x04 Timer0 Compare Register 0x0000_0000 TCMPR1 TMR_BA+0x24 Timer1 Compare Register 0x0000_0000 TCMP TCMP TCMP Bits Description [31:24] Reserved Timer Compared Value TCMP is a 24-bit compared register. When the internal 24-bit up-timer counts and its value is equal to TCMP value, a Timer Interrupt is requested if the timer interrupt is enabled with TCSR.IE[29] = “1”.
  • Page 261 NuMicro™ Mini51 Technical Reference Manual Timer Interrupt Status Register (TISR) Register Offset Description Reset Value TISR0 TMR_BA+0x08 Timer0 Interrupt Status Register 0x0000_0000 TISR1 TMR_BA+0x28 Timer1 Interrupt Status Register 0x0000_0000 Bits Description Reserved [31:2] Timer Wake-up Flag If timer causes CPU wakes up from power-down mode, this bit will be set to high. It must be cleared by software with writing “1”...
  • Page 262 NuMicro™ Mini51 Technical Reference Manual Timer Data Register (TDR) Register Offset Description Reset Value TDR0 TMR_BA+0x0C Timer0 Data Register 0x0000_0000 TDR1 TMR_BA+0x2C Timer1 Data Register 0x0000_0000 Bits Description Reserved [31:24] Timer Data Register [23:0] TDR[23:0] This field indicates the current count value. Feb 9, 2012 Page 262 of 342 Revision V1.03...
  • Page 263 NuMicro™ Mini51 Technical Reference Manual Timer Capture Data Register (TCAP) Register Offset Description Reset Value TCAP0 TMR_BA+0x10 Timer0 Capture Data Register 0x0000_0000 TCAP1 TMR_BA+0x30 Timer1 Capture Data Register 0x0000_0000 TCAP TCAP TCAP Bits Description Reserved [31:24] Timer Capture Data Register When TEXEN (TEXCON[3]) is set, RSTCAPN (TEXCON[4]) is “0”, and the transition TCAP[23:0] [23:0]...
  • Page 264 NuMicro™ Mini51 Technical Reference Manual Timer External Control Register (TEXCON) Register Offset Description Reset Value TEXCON0 TMR_BA+0x14 Timer0 External Control Register 0x0000_0000 TEXCON1 TMR_BA+0x34 Timer1 External Control Register 0x0000_0000 CAP_MODE TCDB TEXDB TEXIEN RSTCAPN TEXEN TEX_EDGE TX_PHASE Bits Description [31:9] Reserved Capture Mode Selection CAP_MODE...
  • Page 265 NuMicro™ Mini51 Technical Reference Manual Bits Description 1 = TEX transition is used as the timer counter reset function. 0 = TEX transition is used as the timer capture function. Timer External Pin Enable This bit enables the reset/capture function on the TEX pin. TEXEN 1 = The transition detected on the TEX pin will result in capture or reset of timer counter.
  • Page 266 NuMicro™ Mini51 Technical Reference Manual Timer External Interrupt Status Register (TEXISR) Register Offset Description Reset Value TEXISR0 TMR_BA+0x18 Timer0 External Interrupt Status Register 0x0000_0000 TEXISR1 TMR_BA+0x38 Timer1 External Interrupt Status Register 0x0000_0000 TEXIF Bits Description Reserved [31:1] Timer External Interrupt Flag This bit indicates the external interrupt status of the timer.

  • Page 267: Uart Interface Controller

    NuMicro™ Mini51 Technical Reference Manual 5.13 UART Interface Controller NuMicro Mini51 series provides channel Universal Asynchronous Receiver/Transmitters (UART). UART performs Normal Speed UART, and support flow control function. 5.13.1 Overview The Universal Asynchronous Receiver/Transmitter (UART) performs a serial-to-parallel conversion on data received from the peripheral, and a parallel-to-serial conversion on data transmitted from the CPU.
  • Page 268 NuMicro™ Mini51 Technical Reference Manual A=14, B=11 A=22, B=15 57600 A=22 A=382 A=30, B=11 A=62, B=8 38400 A=34 A=46, B=11 A=574 A=34, B=15 A=126, B=8 19200 A=70 A=94, B=11 A=1150 A=70, B=15 A=254, B=8 9600 A=142 A=190, B=11 A=2302 A=142, B=15 A=510, B=8 4800 A=286...

  • Page 269: Features

    NuMicro™ Mini51 Technical Reference Manual 5.13.2 Features  Full duplex, asynchronous communications  Separates receive/transmit 16 bytes entry FIFO for data payloads  Supports hardware auto flow control/flow control function (CTSn, RTSn) and programmable RTSn flow control trigger level  Programmable receiver buffer trigger level ...

  • Page 270: Block Diagram

    NuMicro™ Mini51 Technical Reference Manual 5.13.3 Block Diagram The UART clock control and block diagram are shown as follows. UART_S (CLKSEL1[25:24]) Reserved 22.1184 MHz 1/(UART_N+1) Reserved UART_CLK UART_N (CLKDIV[11:8]) 12 MHz UART0_EN (APBCLK[16]) Clock Controller Figure 5.13-1 UART Clock Control Diagram Feb 9, 2012 Page 270 of 342 Revision V1.03...

  • Page 271: Figure 5.13-2 Uart Block Diagram

    NuMicro™ Mini51 Technical Reference Manual APB_BUS Status & Control Status & Control Control and Status TX_FIFO RX_FIFO Registers TX Shift Register RX Shift Register Baud Rate Baud Out Baud Out Generator Serial Data Out Serial Data In UART_CLK IrDA Encode IrDA Decode UART / IrDA / RS-485 Device or Transceiver Figure 5.13-2 UART Block Diagram...
  • Page 272 NuMicro™ Mini51 Technical Reference Manual IrDA Decode This block is IrDA decode control block. Control and Status Register This field is a register set which includes the FIFO control registers (UA_FCR), FIFO status registers (UA_FSR), and line control register (UA_LCR) for transmitter and receiver. The time-out control register (UA_TOR) identifies the condition of time-out interrupt.

  • Page 273: Functional Description

    NuMicro™ Mini51 Technical Reference Manual 5.13.4 Functional Description 5.13.4.1 Auto-flow Control The following diagram demonstrates the auto-flow control block diagram. Parallel to Serial TX FIFO CTSn Flow Control APB BUS Serial to Parallel RX FIFO RTSn Flow Control Figure 5.13-3 Auto Flow Control Block Diagram 5.13.4.2 IrDA Mode The UART supports IrDA SIR (Serial Infrared) Transmit Encoder and Receive Decoder, and IrDA mode is selected by setting the IrDA_EN bit in UA_FUN_SEL register.

  • Page 274: Figure 5.13-4 Irda Block Diagram

    NuMicro™ Mini51 Technical Reference Manual TX Pin SOUT Emit Infra Red Ray IR_SOUT IrDA UART Transceiver RX Pin Detect Infra Red Ray IR_SIN BAUDOUT IrDA_enable TX_select IRCR INT_TX INT_RX Figure 5.13-4 IrDA Block Diagram IrDA SIR Transmit Encoder The IrDA SIR Transmit Encoder modulates Non-Return-to Zero (NRZ) transmit bit stream output from UART.

  • Page 275: Figure 5.13-5 Irda Tx/Rx Timing Diagram

    NuMicro™ Mini51 Technical Reference Manual STOP START SOUT (From UART TX) Timing IR_ SOUT (Encoder Output) 3/16 Bit Width IR_ SIN (Decorder Input) 3/16 Bit Width Timing (To UART RX) STOP START Bit Pulse Width Figure 5.13-5 IrDA TX/RX Timing Diagram 5.13.4.3 RS-485 Function Mode The UART support RS-485 9-bit mode function.
  • Page 276 NuMicro™ Mini51 Technical Reference Manual detected (bit9 = “1”), an interrupt will be generated to CPU and software can decide whether the receiver will be enabled or disabled to accept the following data byte by setting UA_ALT_CSR[RX_DIS]. If the receiver is enabled, all received byte data will be accepted and stored in the RX-FIFO;...

  • Page 277: Figure 5.13-6 Structure Of Rs-485 Frame

    NuMicro™ Mini51 Technical Reference Manual Differenitial Bus UART/RS-485 Controller RS-485 Transceiver Drive Enable STOP Drive Enable Figure 5.13-6 Structure of RS-485 Frame Feb 9, 2012 Page 277 of 342 Revision V1.03...

  • Page 278: Registers Map

    NuMicro™ Mini51 Technical Reference Manual 5.13.5 Registers Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value UART_BA = 0x4005_0000 UA_RBR UART_BA+0x00 UART Receive Buffer Register Undefined UA_THR UART_BA+0x00 UART Transmit Holding Register Undefined UA_IER UART_BA+0x04...

  • Page 279: Register Description

    NuMicro™ Mini51 Technical Reference Manual 5.13.6 Register Description Receive Buffer Register (UA_RBR) Register Offset Description Reset Value UA_RBR UART_BA+0x00 UART Receive Buffer Register Undefined Bits Description [31:8] Reserved Receive Buffer Register (Read Only) [7:0] RBR[7:0] By reading this register, the UART will return a 8-bit data received from RX pin (LSB first).
  • Page 280 NuMicro™ Mini51 Technical Reference Manual Transmit Holding Register (UA_THR) Register Offset Description Reset Value UA_THR UART_BA+0x00 UART Transmit Holding Register Undefined Bits Description [31:8] Reserved Transmit Holding Register [7:0] THR[7:0] By writing to this register, the UART sends out an 8-bit data through the TX pin (LSB first).
  • Page 281 NuMicro™ Mini51 Technical Reference Manual Interrupt Enable Register (UA_IER) Register Offset Description Reset Value UA_IER UART_BA+0x04 UART Interrupt Enable Register 0x0000_0000 AUTO_RTS_ AUTO_CTS_EN TIME_OUT_EN WAKE_EN BUF_ERR_IEN RTO_IEN MODEM_IEN RLS_IEN THRE_IEN RDA_IEN Bits Description [31:14] Reserved CTS Auto Flow Control Enable 1 = CTSn auto flow control Enabled.
  • Page 282 NuMicro™ Mini51 Technical Reference Manual Bits Description RX Time-out Interrupt Enable RTO_IEN 1 = INT_TOUT Enabled. 0 = INT_TOUT Masked off. Modem Status Interrupt Enable MODEM_IEN 1 = INT_MODEM Enabled. 0 = INT_MODEM Masked off. Receive Line Status Interrupt Enable RLS_IEN 1 = INT_RLS Enabled.
  • Page 283 NuMicro™ Mini51 Technical Reference Manual FIFO Control Register (UA_FCR) Register Offset Description Reset Value UA_FCR UART_BA+0x08 UART FIFO Control Register 0x0000_0000 RTS_TRI_LEV RX_DIS RFITL Bits Description [31:20] Reserved RTSn Trigger Level (for Auto-flow Control Use) RTS_TRI_LEV Trigger Level (Bytes) 0000 0001 RTS_TRI_LEV [19:16]...
  • Page 284 NuMicro™ Mini51 Technical Reference Manual Bits Description 0001 0010 0011 Others Reserved TX Field Software Reset When TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared. 1 = The TX internal state machine and pointers reset. 0 = No effect.
  • Page 285 NuMicro™ Mini51 Technical Reference Manual Line Control Register (UA_LCR) Register Offset Description Reset Value UA_LCR UART_BA+0x0C UART Line Control Register 0x0000_0000 Bits Description Reserved [31:7] Break Control Bit When this bit is set to logic “1”, the serial data output (TX) is forced to the Spacing State (logic “0”).
  • Page 286 NuMicro™ Mini51 Technical Reference Manual Bits Description 5 bits 6 bits 7 bits 8 bits Feb 9, 2012 Page 286 of 342 Revision V1.03...
  • Page 287 NuMicro™ Mini51 Technical Reference Manual MODEM Control Register (UA_MCR) Register Offset Description Reset Value UA_MCR UART_BA+0x10 UART Modem Control Register 0x0000_0000 RTS_ST LEV_RTS RTSn Bits Description Reserved [31:14] RTSn Pin State (Read Only) [13] RTS_ST This bit is the output pin status of RTSn. [12:10] Reserved RTSn Trigger Level...
  • Page 288 NuMicro™ Mini51 Technical Reference Manual Bits Description RS-485 Mode : MCR[LEV_RTS] = “0” Start MCR [RTS_ST] RS-485 Mode : MCR[LEV_RTS] = “1” Start MCR [RTS_ST] Reserved [8:2] RTSn (Request-to-Send) Signal LEV_RTS RTSn RTS_ST 0 (Low Level Trigger) RTSn 0 (Low Level Trigger) 1 (High Level Trigger) 1 (High Level Trigger) Reserved...
  • Page 289 NuMicro™ Mini51 Technical Reference Manual Modem Status Register (UA_MSR) Register Offset Description Reset Value UA_MSR UART_BA+0x14 UART Modem Status Register 0x0000_0000 LEV_CTS CTS_ST DCTSF Bits Description Reserved [31:9] CTSn Trigger Level This bit can change the CTSn trigger level. LEV_CTS 1 = High level triggered.
  • Page 290 NuMicro™ Mini51 Technical Reference Manual FIFO Status Register (UA_FSR) Register Offset Description Reset Value UA_FSR UART_BA+0x18 UART FIFO Status Register 0x1040_4000 TE_FLAG TX_OVER_IF TX_FULL TX_EMPTY TX_POINTER RX_FULL RX_EMPTY RX_POINTER RS-485_ RX_OVER_IF ADD_DETF Bits Description Reserved [31:29] Transmitter Empty Flag (Read Only) Bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last [28] TE_FLAG...
  • Page 291 NuMicro™ Mini51 Technical Reference Manual Bits Description Receiver FIFO Full (Read Only) [15] RX_FULL This bit initiates RX FIFO full or not. This bit is set when RX_POINTER is equal to 16; otherwise, it is cleared by hardware. Receiver FIFO Empty (Read Only) This bit initiates RX FIFO empty (or not).
  • Page 292 NuMicro™ Mini51 Technical Reference Manual Interrupt Status Control Register (UA_ISR) Register Offset Description Reset Value UA_ISR UART_BA+0x1C UART Interrupt Status Register 0x0000_0002 BUF_ERR_INT TOUT_INT MODEM_INT RLS_INT THRE_INT RDA_INT BUF_ERR_IF TOUT_IF MODEM_IF RLS_IF THRE_IF RDA_IF Bits Description [31:14] Reserved Buffer Error Interrupt Indicator to Interrupt Controller (Read Only) [13] BUF_ERR_INT An AND output with inputs of BUF_ERR_IEN and BUF_ERR_IF.
  • Page 293 NuMicro™ Mini51 Technical Reference Manual Bits Description 0 = No RDA interrupt generated. Reserved [7:6] Buffer Error Interrupt Flag (Read Only) This bit is set when the TX or RX FIFO overflows or Break Interrupt Flag or Parity BUF_ERR_IF Error Flag or Frame Error Flag (TX_OVER_IF or RX_OVER_IF or BIF or PEF or FEF ) is set.

  • Page 294: Table 5.13-3 Uart Interrupt Sources And Flags Table In Software Mode

    NuMicro™ Mini51 Technical Reference Manual Table 5.13-3 UART Interrupt Sources and Flags Table In Software Mode Interrupt Indicator to UART Interrupt Source Interrupt Enable Bit Interrupt Flag Flag Clear Interrupt Controller Write „1‟ to HW_BUF_ERR_IF = Buffer Error Interrupt (TX_OVER_IF or TX_OVER_IF/ BUF_ERR_IEN BUF_ERR_INT...
  • Page 295 NuMicro™ Mini51 Technical Reference Manual Time-out Register (UA_TOR) Register Offset Description Reset Value UA_TOR UART_BA+0x20 UART Time-out Register 0x0000_0000 TOIC Bits Description [31:16] Reserved TX Delay Time Value This field is used to program the transfer delay time between the last stop bit and next start bit [15:8] DLY[7:0]...
  • Page 296 NuMicro™ Mini51 Technical Reference Manual Baud Rate Divider Register (UA_BAUD) Register Offset Description Reset Value UA_BAUD UART_BA+0x24 UART Baud Rate Divisor Register 0x0F00_0000 DIV_X_EN DIV_X_ONE DIVIDER_X Bits Description Reserved [31:30] Divider X Enable The BRD = baud rate divider, and the baud rate equation is:Baud Rate = Clock / [M * (BRD + 2)], The default value of M is 16.

  • Page 297: Table 5.13-4 Uart Baud Rate Setting Table

    NuMicro™ Mini51 Technical Reference Manual Table 5.13-4 UART Baud Rate Setting Table Mode DIV_X_EN DIV_X_ONE Divider X Baud Rate Equation UART_CLK / [16 * (A+2)] UART_CLK / [(B+1) * (A+2)] , B must >= 8 Don‟t care UART_CLK / (A+2), A must >=3 Feb 9, 2012 Page 297 of 342 Revision V1.03...
  • Page 298 NuMicro™ Mini51 Technical Reference Manual IrDA Control Register (IRCR) Register Offset Description Reset Value UA_IRCR UART_BA+0x28 UART IrDA Control Register 0x0000_0040 INV_RX INV_TX TX_SELECT Bits Description [31:7] Reserved INV_RX INV_RX 1 = RX input signal inversed. 0 = No inversion. INV_TX INV_TX 1 = TX output signal inversed.
  • Page 299 NuMicro™ Mini51 Technical Reference Manual UART Alternate Control/Status Register (UA_ALT_CSR) Register Offset Description Reset Value UA_ALT_CSR UART_BA+0x2C UART Alternate Control/Status Register 0x0000_0000 ADDR_MATCH RS485_ADD_ RS485_AUD RS485_AAD RS485_NMM Bits Description Address Match Value Register ADDR_MATCH [31:24] This field contains the RS-485 address match values. [7:0] Note: This field is used for Auto RS-485 Address Detection mode.
  • Page 300 NuMicro™ Mini51 Technical Reference Manual Bits Description [7:0] Reserved Feb 9, 2012 Page 300 of 342 Revision V1.03...
  • Page 301 NuMicro™ Mini51 Technical Reference Manual UART Function Select Register (UA_FUN_SEL) Register Offset Description Reset Value UA_FUN_SEL UART_BA+0x30 UART Function Select Register 0x0000_0000 FUN_SEL Bits Description [31:2] Reserved Function Select Enable Description FUN_SEL UART Function [1:0] FUN_SEL[1:0] Reserved. Enable IrDA Function Enable RS-485 Function Feb 9, 2012 Page 301 of 342...

  • Page 302: Watchdog Timer

    NuMicro™ Mini51 Technical Reference Manual 5.14 Watchdog Timer 5.14.1 Overview The purpose of Watchdog Timer (WDT) is to perform a system reset after software runs into a problem. This prevents system from hanging for an infinite period of time. Besides, the Watchdog Timer supports another function to wake up CPU from Power-down mode.

  • Page 303: Features

    NuMicro™ Mini51 Technical Reference Manual 1024 * T Minimum T 63 * T Maximum T  : Watchdog Engine Clock Time Period  : Watchdog Timeout Interval Selection Period  : Watchdog Interrupt Period  : Watchdog Reset Period  : Watchdog Timeout Interval Period Figure 5.14-1 Timing of Interrupt and Reset Signal 5.14.2 Features...

  • Page 304: Figure 5.14-3 Watchdog Timer Block Diagram

    NuMicro™ Mini51 Technical Reference Manual WTR(WDTCR[0]) Watchdog Reset WDT WTIF Counter Interrupt 18-bit WDT Counter (WTCR[3]) WTIE …... (WTCR[6]) Delay Watchdog Time- 1024 Reset select WTRE clocks (WTCR[1]) WDT_CLK WTRF (WTCR[2]) (WTCR[7]) WDTCR. WTIS[10:8] Wakeup CPU from Power-down mode Note: WTWKE 1.

  • Page 305: Watchdog Timer Control Registers Map

    NuMicro™ Mini51 Technical Reference Manual 5.14.4 Watchdog Timer Control Registers Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value WDT_BA = 0x4000_4000 WTCR WDT_BA+0x00 Watchdog Timer Control Register 0x0000_0700 Feb 9, 2012 Page 305 of 342 Revision V1.03...

  • Page 306: Register Description

    NuMicro™ Mini51 Technical Reference Manual 5.14.5 Register Description Watchdog Timer Control Register (WTCR) Register Offset Description Reset Value WTCR WDT_BA+0x00 Watchdog Timer Control Register 0x0000_0700 Note: All bits in this register are write-protected. To program it, an open lock sequence is needed, by sequentially writing 0x59, 0x16, and 0x88 to register RegLockAddr at address GCR_BA + 0x100.
  • Page 307 NuMicro™ Mini51 Technical Reference Manual Bits Description Watchdog Timer Interval Selection These three bits select the time-out interval for the Watchdog timer. Time-out Interval WTR Time-out Interval WTIS Interrupt Period Selection (WDT_CLK=10 kHz) 24 * TWDT (24 + 1024) * TWDT 1.6 ms ~ 104 ms 26 * TWDT (26 + 1024) * TWDT...
  • Page 308 NuMicro™ Mini51 Technical Reference Manual Bits Description Watchdog Timer Reset Flag When the Watchdog timer initiates a reset, the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing “1”...

  • Page 309: Arm ® Cortex™-M0 Core

    NuMicro™ Mini51 Technical Reference Manual ® CORTEX™-M0 CORE Overview The Cortex™-M0 processor is a configurable, multistage, 32-bit RISC processor which has an AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug functionality. The processor can execute Thumb code and is compatible with other Cortex-M profile processors.

  • Page 310: Features

    NuMicro™ Mini51 Technical Reference Manual Features  A low gate count processor ®  ARMv6-M Thumb instruction set  Thumb-2 technology  ARMv6-M compliant 24-bit SysTick timer  A 32-bit hardware multiplier  Supports little-endian data accesses  Deterministic, fixed-latency, interrupt handling ...

  • Page 311: System Timer (Systick)

    NuMicro™ Mini51 Technical Reference Manual System Timer (SysTick) The Cortex-M0 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter. When system timer is enabled, it will count down from the value in the SysTick Current Value Register (SYST_CVR) to zero, and reload (wrap) to the value in the SysTick Reload Value Register (SYST_RVR) on the next clock edge, and then decrement on subsequent clocks.

  • Page 312: System Timer Control Register Map

    NuMicro™ Mini51 Technical Reference Manual 6.3.1 System Timer Control Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value SCS_BA = 0xE000_E000 SYST_CSR SCS_BA+0x10 SysTick Control and Status 0x0000_0000 SYST_RVR SCS_BA+0x14 SysTick Reload value 0x00XX_XXXX SYST_CVR SCS_BA+0x18...

  • Page 313: System Timer Control Register

    NuMicro™ Mini51 Technical Reference Manual 6.3.2 System Timer Control Register SysTick Control and Status (SYST_CSR) Register Offset Description Reset Value SYST_CSR SCS_BA+0x10 SysTick Control and Status 0x0000_0000 COUNTFLAG CLKSRC TICKINT ENABLE Bits Description [31:17] Reserved Returns “1” if timer counted to 0 since this register was read last time. COUNTFLAG [16] COUNTFLAG is set by a count transition from 1 to 0.
  • Page 314 NuMicro™ Mini51 Technical Reference Manual SysTick Reload Value Register (SYST_RVR) Register Offset Description Reset Value SYST_RVR SCS_BA+0x14 SysTick Reload Value Register 0x00XX_XXXX RELOAD RELOAD RELOAD Bits Description [31:24] Reserved [23:0] RELOAD[23:0] Value to load into the Current Value register when the counter reaches 0. Feb 9, 2012 Page 314 of 342 Revision V1.03...
  • Page 315 NuMicro™ Mini51 Technical Reference Manual SysTick Current Value Register (SYST_CVR) Register Offset Description Reset Value SYST_CVR SCS _BA+0x18 SysTick Current Value Register 0x00XX_XXXX CURRENT CURRENT CURRENT Bits Description [31:24] Reserved Current counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection.

  • Page 316: System Control Registers

    NuMicro™ Mini51 Technical Reference Manual System Control Registers Cortex-M0 status and operation mode control are managed System Control Registers. Including CPUID, Cortex-M0 interrupt priority and Cortex-M0 power management can be controlled through these system control registers. ® For more detailed information, please refer to the “ARM Cortex™-M0 Technical Reference ®...

  • Page 317: System Control Register

    NuMicro™ Mini51 Technical Reference Manual 6.4.2 System Control Register CPUID Base Register (CPUID) Register Offset Description Reset Value CPUID SCS_BA+0xD00 CPUID Base Register 0x410C_C200 IMPLEMENTER PART PARTNO PARTNO REVISION Bits Description IMPLEMENTER [31:24] Implementer code assigned by ARM. (ARM = 0x41). [7:0] [23:20] Reserved...
  • Page 318 NuMicro™ Mini51 Technical Reference Manual Interrupt Control State Register (ICSR) Register Offset Description Reset Value ICSR SCS_BA+0xD04 Interrupt Control State Register 0x0000_0000 NMIPENDSE PENDSVSET PENDSVCLR PENDSTSET PENDSTCLR ISRPREEMP ISRPENDING VECTPENDING VECTPENDING VECTACTIVE VECTACTIVE Bits Description NMI Set-pending Bit Write: 0 = No effect. 1 = NMI exception state changed to pending.
  • Page 319 NuMicro™ Mini51 Technical Reference Manual Bits Description PendSV Clear-pending Bit (Write Only) Write: [27] PENDSVCLR 0 = No effect. 1 = The pending state removed from the PendSV exception. SysTick Exception Set-pending Bit Write: 0 = No effect. [26] PENDSTSET 1 = SysTick exception state changed to pending.
  • Page 320 NuMicro™ Mini51 Technical Reference Manual Application Interrupt and Reset Control Register (AIRCR) Register Offset Description Reset Value AIRCR SCS_BA+0xD0C Application Interrupt and Reset Control Register 0xFA05_0000 VECTORKEY VECTORKEY SYSRESETR VECTCLKAC TIVE Bits Description VECTORKEY When writing this register, this field should be 0x05FA; otherwise, the write action will [31:16] [15:0] be unpredictable.
  • Page 321 NuMicro™ Mini51 Technical Reference Manual System Control Register (SCR) Register Offset Description Reset Value SCS_BA+0xD10 System Control Register 0x0000_0000 SEVONPEND SLEEPDEEP SLEEPONEXIT Bits Description [31:5] Reserved Send Event on Pending Bit 0 = Only the enabled interrupts or events can wake up the processor, disabled interrupts are excluded.
  • Page 322 NuMicro™ Mini51 Technical Reference Manual System Handler Priority Register 2 (SHPR2) Register Offset Description Reset Value SHPR2 SCS_BA+0xD1C System Handler Priority Register 2 0x0000_0000 PRI_11 Bits Description Priority of System Handler 11 – SVCall [31:30] PRI_11[1:0] “0” denotes the highest priority and “3” denotes the lowest priority. [29:0] Reserved Feb 9, 2012...
  • Page 323 NuMicro™ Mini51 Technical Reference Manual System Handler Priority Register 3 (SHPR3) Register Offset Description Reset Value SHPR3 SCS_BA+0xD20 System Handler Priority Register 3 0x0000_0000 PRI_15 PRI_14 Bits Description Priority of System Handler 15 – SysTick [31:30] PRI_15[1:0] “0” denotes the highest priority and “3” denotes the lowest priority. [29:24] Reserved Priority of System Handler 14 –...

  • Page 324: Application Circuit

    NuMicro™ Mini51 Technical Reference Manual APPLICATION CIRCUIT DAVDD R0603 0.1uF C0603 TICERST PUSH BOTTOM 10uF/10V TANT-A Reset Circuit From ICE Bridge's USB Power PIN1 PIN36 PIN2 PIN35 CPP0/AIN5/P1.5 P0.4/SPISS/PWM5 TICERST PIN3 TICEDAT PIN34 P0.5/MOSI PIN4 TICECLK PIN33 CPN1/AIN6/P3.0 P0.6/MISO TICERST PIN5 PIN32 AVSS...

  • Page 325: Electrical Characteristics

    NuMicro™ Mini51 Technical Reference Manual ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings SYMBOL PARAMETER UNIT V DC power supply -0.3 +7.0 Input voltage -0.3 +0.3 Oscillator frequency CLCL C Operating temperature C Storage temperature +150 Maximum current into VDD Maximum current out of VSS Maximum current sunk by a I/O pin Maximum current sourced by a I/O pin Maximum current sunk by total I/O pins...

  • Page 326: Dc Electrical Characteristics

    NuMicro™ Mini51 Technical Reference Manual DC Electrical Characteristics (VDD-VSS = 5.0 V, TA = 25C, FOSC = 24 MHz unless otherwise specified.) Specification PARAMETER Sym. TEST CONDITIONS Min. TYP. Max. Unit Operation voltage = 2.5 V ~ 5.5 V up to 24 MHz rise rate to ensure internal operation 0.05...
  • Page 327 NuMicro™ Mini51 Technical Reference Manual Specification PARAMETER Sym. TEST CONDITIONS Min. TYP. Max. Unit = 5.5V at 32.768 KHz, A DD17 all IP Enabled = 5.5V at 32.768 KHz, Operating current A DD18 all IP Disabled Normal run mode = 3.3V at 32.768 KHz, at 32.768 KHz crystal A DD19...
  • Page 328 NuMicro™ Mini51 Technical Reference Manual Specification PARAMETER Sym. TEST CONDITIONS Min. TYP. Max. Unit = 3.3V at 22.1184 MHz, IDLE16 all IP Disabled = 5.5V at 32.768 KHz, A IDLE17 all IP Enabled = 5.5V at 32.768 KHz, Operating current A IDLE18 all IP Disabled...
  • Page 329 NuMicro™ Mini51 Technical Reference Manual Specification PARAMETER Sym. TEST CONDITIONS Min. TYP. Max. Unit P0~P5 (TTL input) -0.3 = 2.5 V = 5.5V +0.2 Input high voltage P0~P5 (TTL input) = 3.0V +0.2 Input low voltage P0~P5, (Schmitt input) Input high voltage P0~P5, (Schmitt input) Hysteresis voltage of P0~P5 (Schmitt input)
  • Page 330 NuMicro™ Mini51 Technical Reference Manual Crystal Input is a CMOS input. Pins of P0~P5 can source a transition current when they are being externally driven from 1 to 0. In the condition of =5.5V, the transition current reaches its maximum value when V approximates to 2V.

  • Page 331: Ac Electrical Characteristics

    NuMicro™ Mini51 Technical Reference Manual AC Electrical Characteristics 8.3.1 External Input Clock Specification PARAMETER Sym. TEST CONDITIONS Min. TYP. Max. Unit Clock high time CHCX Clock low time CLCX Clock rise time CLCH Clock fall time CHCL t CLCL t CLCH t CLCX t CHCL t CHCX...

  • Page 332: External 32.768 Khz Xtal Oscillator

    NuMicro™ Mini51 Technical Reference Manual Figure 8.3-1 Typical Crystal Application Circuit 8.3.4 External 32.768 KHz XTAL Oscillator Specification PARAMETER Sym. TEST CONDITIONS Min. TYP. Max. Unit Oscillator frequency 32.768 KHz V = 2.5V ~ 5.5V XTAL Temperature XTAL A Operating current = 5.0V HXTAL 8.3.5...

  • Page 333: Internal 10 Khz Rc Oscillator

    NuMicro™ Mini51 Technical Reference Manual 8.3.6 Internal 10 KHz RC Oscillator Specification PARAMETER Sym. TEST CONDITIONS Min. TYP. Max. Unit Supply voltage KHz 25 C, V = 5V Center frequency KHz -40 C = ~+85 C, V = 2.5V~5.5V A Operating current = 5V Note: Internal operation voltage comes from LDO.

  • Page 334: Analog Characteristics

    NuMicro™ Mini51 Technical Reference Manual Analog Characteristics = 5.0V, TA = 25C, FOSC = 24 MHz unless otherwise specified.) 8.4.1 Brown-Out Reset (BOD) Specification PARAMETER Sym. TEST CONDITIONS Min. TYP. Max. Unit Operating voltage = 5V A Operating current BOD27 and BOD38 Enabled BOD38 detection level B38dt BOD27 detection level...

  • Page 335: Analog Comparator Reference Voltage (Crv)

    NuMicro™ Mini51 Technical Reference Manual Specification PARAMETER Sym. TEST CONDITIONS Min. TYP. Max. Unit Stable time S CPPx = 1.3V and CPNX = 1.2V STBL 8.4.4 Analog Comparator Reference Voltage (CRV) Specification PARAMETER Sym. TEST CONDITIONS Min. TYP. Max. Unit Operating voltage VDD = 5V, CRV step size...
  • Page 336 NuMicro™ Mini51 Technical Reference Manual Specification PARAMETER Sym. TEST CONDITIONS Min. TYP. Max. Unit Bang-gap voltage 1.27 1.35 1.44 C ~ +85 Feb 9, 2012 Page 336 of 342 Revision V1.03...

  • Page 337: Flash Memory Characteristics

    NuMicro™ Mini51 Technical Reference Manual 8.4.6 Flash Memory Characteristics Specification PARAMETER Sym. TEST CONDITIONS Min. TYP. Max. Unit Cycling (erase/write) K cycle Program memory Data retention years = +85 Erase time of ISP mode Erase time for one page ERASE Programming time for one S Program time of ISP mode...

  • Page 338: Package Dimension

    NuMicro™ Mini51 Technical Reference Manual PACKAGE DIMENSION 48-pin LQFP  C o n t r o l l i n g d i m e n s i o n : M i l l i m e t e r s Dimension in inch Dimension in mm Symbol...

  • Page 339: 33-Pin Qfn (4Mm X 4Mm)

    NuMicro™ Mini51 Technical Reference Manual 33-pin QFN (4mm x 4mm) Feb 9, 2012 Page 339 of 342 Revision V1.03...

  • Page 340: 33-Pin Qfn (5Mm X 5Mm)

    NuMicro™ Mini51 Technical Reference Manual 33-pin QFN (5mm x 5mm) Feb 9, 2012 Page 340 of 342 Revision V1.03...

  • Page 341: Revision History

    NuMicro™ Mini51 Technical Reference Manual 10 REVISION HISTORY Date Revision Changes Sep 6, 2011 1.00 Initial release 1. Changed electrical characteristics of comparator, 22 MHz RC oscillator, ADC and band-gap. 2. Added electrical characteristics of Flash memory. 3. Changed maximum SPI frequency as 12MHz. Oct 20, 2011 1.01 4.
  • Page 342 NuMicro™ Mini51 Technical Reference Manual Important Notice Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”.

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