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Nuvoton NuMicro NUC126 Series Technical Reference Manual

Nuvoton NuMicro NUC126 Series Technical Reference Manual

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NUC126

®

ARM CORTEX

-M

32-BIT MICROCONTROLLER

®

NuMicro

Family

NUC126 Series

Technical Reference Manual

The information described in this document is the exclusive intellectual property of

Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.

Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based

system design. Nuvoton assumes no responsibility for errors or omissions.

All data and specifications are subject to change without notice.

For additional information or questions, please contact: Nuvoton Technology Corporation.

www.nuvoton.com

Aug. 08, 2018

Page 1 of 943

Rev 1.03

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Page 1 The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions.
Page 2: Table Of Contents
NUC126 TABLE OF CONTENTS 1 GENERAL DESCRIPTION ................19 1.1 Key Feature and Application ..................19 2 FEATURES.....................20 ® 2.1 NuMicro NUC126 Features ..................20 3 ABBREVIATIONS ..................28 3.1 Abbreviations ........................ 28 4 PARTS INFORMATION LIST AND PIN CONFIGURATION ......30 ® 4.1 NuMicro NUC126 Selection Guide ................
Page 3 NUC126 6.2.15 System Control ......................161 6.3 Clock Controller ......................169 6.3.1 Overview ........................169 6.3.2 System Clock and SysTick Clock ................172 6.3.3 Peripherals Clock ......................173 6.3.4 Power-down Mode Clock .................... 174 6.3.5 Clock Output ......................... 174 6.3.6 Register Map ........................ 176 6.3.7 Register Description ....................
Page 4 NUC126 6.8.1 Overview ........................298 6.8.2 Features ........................298 6.8.3 Block Diagram ......................299 6.8.4 Basic Configuration ...................... 299 6.8.5 Functional Description ....................300 6.8.6 Register Map ........................ 308 6.8.7 Register Description ....................309 6.9 General Purpose I/O (GPIO) ..................313 6.9.1 Overview ........................
Page 5 NUC126 6.13.2 Features ........................413 6.13.3 Block Diagram ......................415 6.13.4 Basic Configuration ...................... 418 6.13.5 Functional Description ....................419 6.13.6 Register Map ........................ 450 6.13.7 Register Description ....................454 6.14 Real Time Clock (RTC) ..................518 6.14.1 Overview ........................518 6.14.2 Features ........................
Page 6 NUC126 6.18.1 Overview ........................703 6.18.2 Features ........................703 6.18.3 Block Diagram ......................704 6.18.4 Basic Configuration ...................... 704 6.18.5 Functional Description ....................704 6.18.6 Register Map ........................ 710 6.18.7 Register Description ....................712 6.19 USCI - Universal Serial Control Interface Controller ........731 6.19.1 Overview ........................
Page 7 NUC126 6.23.5 Functional Description ....................860 6.23.6 Register Map ........................ 884 6.23.7 Register Description ....................886 6.24 Watchdog Timer (WDT) ..................919 6.24.1 Overview ........................919 6.24.2 Features ........................919 6.24.3 Block Diagram ......................919 6.24.4 Basic Configuration ...................... 919 6.24.5 Functional Description ....................
Page 8 NUC126 LIST OF FIGURES ® Figure 4.2-1 NuMicro NUC126 USB Series QFN 48-pin Diagram ..........32 ® Figure 4.2-2 NuMicro NUC126 USB Series LQFP 48-pin Diagram ..........33 ® Figure 4.2-3 NuMicro NUC126 USB Series LQFP 64-pin Diagram ..........34 ®...
Page 9 NUC126 Figure 6.4-13 Firmware in SRAM for Multi-word Programming ........... 224 Figure 6.4-14 Multi-word Programming Flow ................225 Figure 6.4-15 CRC-32 Checksum Calculation ................226 Figure 6.4-16 CRC-32 Checksum Calculation Flow ..............227 Figure 6.4-17 All-One Verification Flow ..................228 Figure 6.5-1 Analog Comparator Block Diagram .................
Page 10 NUC126 Figure 6.11-2 I C Bus Timing ....................... 346 Figure 6.11-3 I C Protocol ......................347 Figure 6.11-4 START and STOP Conditions................347 Figure 6.11-5 Bit Transfer on the I C Bus ..................348 Figure 6.11-6 Acknowledge on the I C Bus ..................
Page 11 NUC126 Figure 6.13-9 PWM Up-Down Counter Type................421 Figure 6.13-10 PWM Compared point Events in Up-Down Counter Type ........422 Figure 6.13-11 PWM Double Buffering Illustration ............... 423 Figure 6.13-12 Period Loading in Up-Count Mode ............... 424 Figure 6.13-13 Immediately Loading in Up-Count Mode .............. 425 Figure 6.13-14 Window Loading in Up-Count Mode ..............
Page 12 NUC126 Figure 6.15-1 SC Clock Control Diagram ..................547 Figure 6.15-2 SC Controller Block Diagram ................. 547 Figure 6.15-3 SC Data Character ....................549 Figure 6.15-4 SC Activation Sequence ..................550 Figure 6.15-5 SC Warm Reset Sequence ..................551 Figure 6.15-6 SC Deactivation Sequence ..................552 Figure 6.15-7 Basic Operation Flow .....................
Page 13 NUC126 Figure 6.17-1 Timer Controller Block Diagram ................628 Figure 6.17-2 Clock Source of Timer Controller ................629 Figure 6.17-3 PWM Generator Overview Block Diagram ............. 630 Figure 6.17-4 PWM System Clock Source Control ..............630 Figure 6.17-5 PWM Counter Clock Source Control ..............631 Figure 6.17-6 PWM Independent Mode Architecture Diagram ............
Page 14 NUC126 Figure 6.18-2 WKIDLE Interrupt Operation Flow ................. 706 Figure 6.18-3 Endpoint SRAM Structure ..................707 Figure 6.18-4 Setup Transaction Followed by Data IN Transaction ..........707 Figure 6.18-5 Data Out Transfer ....................708 Figure 6.19-1 USCI Block Diagram ....................731 Figure 6.19-2 Input Conditioning for USCIx_DAT[1:0] and USCIx_CTL[1:0] .......
Page 15 NUC126 Figure 6.21-14 One Output Data Channel Half-duplex (SPI Master Mode) ......... 785 Figure 6.21-15 One Input Data Channel Half-duplex (SPI Master Mode) ........786 Figure 6.21-16 SPI Timing in Master Mode .................. 788 Figure 6.21-17 SPI Timing in Master Mode (Alternate Phase of Serial Bus Clock) ..... 788 Figure 6.21-18 SPI Timing in Slave Mode ..................
Page 16 NUC126 Figure 6.23-11 Auto-Flow Control Block Diagram ................ 870 Figure 6.23-12 UART nCTS Auto-Flow Control Enabled ............. 871 Figure 6.23-13 UART nRTS Auto-Flow Control Enabled ............. 871 Figure 6.23-14 UART nRTS Auto-Flow with Software Control............. 872 Figure 6.23-15 IrDA Control Block Diagram ................. 872 Figure 6.23-16 IrDA TX/RX Timing Diagram ................
Page 17 NUC126 List of Tables Table 1.1-1 Key Features Support Table ..................19 Table 3.1-1 List of Abbreviations ....................29 Table 4.3-1 NUC126 GPIO Multi-function Table ................68 Table 6.2-1 Reset Value of Registers ..................... 75 Table 6.2-2 Power Mode Difference Table ..................79 Table 6.2-3 Clocks in Power Modes ....................
Page 18 NUC126 Table 6.19-2 Output Signals for Different Protocols ..............733 Table 6.19-3 Data Transfer Events and Interrupt Handling............740 Table 6.19-4 Protocol-specific Events and Interrupt Handling ............. 741 Table 6.20-1 Input Signals for UART Protocols ................745 Table 6.20-2 Output Signals for Different Protocols ..............746 Table 6.21-1 SPI Communication Signals ..................
Page 19: General Description
NUC126 GENERAL DESCRIPTION ® ® ® The NuMicro NUC126 series microcontroller based on the ARM Cortex -M0 core operates at up to 72 MHz. With its crystal-less USB 2.0 FS interface, it is able to generate precise frequency required by USB protocol without the need of external crystal.
Page 20: Features
NUC126 FEATURES ® NuMicro NUC126 Features  Core ® ® – Cortex -M0 core running up to 72 MHz – One 24-bit system timer – Supports low power sleep mode – Single-cycle 32-bit hardware multiplier – NVIC for the 32 interrupt inputs, each with 4-levels of priority –...
Page 21 NUC126 – Built-in 22.1184 MHz high speed RC oscillator for system operation (Frequency variation < 2% at -40 C ~ +105 – Built-in 48 MHz internal high speed RC oscillator for USB device operation – Built-in 10 kHz low speed RC oscillator for Watchdog Timer and Wake-up operation –...
Page 22 NUC126  Supports 16-bit resolution PWM counter, each timer provides 1 PWM counter  Supports up, down and up/down counter operation type  Supports one-shot or Auto-reload counter operation mode  Supports mask function and tri-state enable for each PWM pin ...
Page 23 NUC126  PWM counter match zero, period value or compared value – Supports up to 12 capture input channels with 16-bit resolution – Supports rising or falling capture condition – Supports input rising/falling capture interrupt – Supports rising/falling capture with counter reload option ...
Page 24 NUC126 – Supports Auto-Baud Rate measurement and baud rate compensation function – Supports break error, frame error, parity error and receive/transmit buffer overflow detection function – Fully programmable serial-interface characteristics  Programmable number of data bit, 5-, 6-, 7-, 8- bit character ...
Page 25 NUC126 – Supports up to two SPI/I S controllers SPI Mode S Mode SPI_CLK I2S_BCLK SPI_SS I2S_LRCLK SPI_MOSI I2S_DO SPI_MISO I2S_DI I2S_MCLK – SPI Mode  Supports Master or Slave mode operation  Configurable bit length of a transfer word from 8 to 32-bit ...
Page 26 NUC126  ADC – Supports 12-bit SAR ADC – 12-bit resolution and 10-bit accuracy is guaranteed – Analog input voltage range: 0~ AV – Supports external V – Up to 20 single-end analog input channels – Maximum ADC peripheral clock frequency is 16 MHz –...
Page 27 NUC126  Brown-out detector – With 8 levels: 4.3 V/ 3.7V/ 2.7V/ 2.2V – Supports Brown-out Interrupt and Reset option  Low Voltage Reset – Threshold voltage levels: 2.0 V  Power consumption – Chip power down current < 10 uA with RAM data retention. –...
Page 28: Abbreviations
NUC126 ABBREVIATIONS Abbreviations Acronym Description ACMP Analog Comparator Controller Analog-to-Digital Converter Advanced Encryption Standard Advanced Peripheral Bus Advanced High-Performance Bus Brown-out Detection Debug Access Port Data Encryption Standard External Bus Interface EPWM Enhanced Pulse Width Modulation FIFO First In, First Out Flash Memory Controller Floating-point Unit GPIO...
Page 29: Table 3.1-1 List Of Abbreviations
NUC126 Serial Peripheral Interface Samples per Second TDES Triple Data Encryption Standard Timer Controller UART Universal Asynchronous Receiver/Transmitter UCID Unique Customer ID Universal Serial Bus Watchdog Timer WWDT Window Watchdog Timer Table 3.1-1 List of Abbreviations Aug. 08, 2018 Page 29 of 943 Rev 1.03...
Page 30: Parts Information List And Pin Configuration
NUC126 PARTS INFORMATION LIST AND PIN CONFIGURATION ® NuMicro NUC126 Selection Guide ® 4.1.1 NuMicro NUC126 Naming Rule ARM–Based NUC1 26 X X 4 X E 32-bit Microcontroller CPU core Temperature Corte ® E : -40 C ~ +105 Version Product Line Function 2X : USB Line SRAM Size...
Page 31: Numicro ® Nuc126 Usb Series (M452 Compatible) Selection Guide
NUC126 ® 4.1.2 NuMicro NUC126 USB Series (M452 Compatible) Selection Guide Connectivity Part Number √ √ √ √ NUC126NE4AE Conf* 9-ch QFN 48 √ √ √ √ NUC126LE4AE Conf* 9-ch LQFP 48 √ √ √ √ Conf* NUC126LG4AE 9-ch LQFP 48 √...
Page 32: Pin Configuration
NUC126 Pin Configuration ® 4.2.1 NuMicro NUC126 USB Series QFN48 Pin Diagram Corresponding Part Number: NUC126NE4AE PA.3 PE.0 PA.2 PC.4 PA.1 PC.3 PA.0 PC.2 PC.1 PC.0 QFN48 QFN 48 LDO_CAP PB.0 PB.1 PF.4 PB.2 PF.3 PB.3 PD.7 PB.4 PF.2 Top Transparent View power domain DDIO power domain...
Page 33: Numicro ® Nuc126 Usb Series Lqfp48 Pin Diagram
NUC126 ® 4.2.2 NuMicro NUC126 USB Series LQFP48 Pin Diagram Corresponding Part Number: NUC126LE4AE, NUC126LG4AE PA.3 PE.0 PA.2 PC.4 PA.1 PC.3 PA.0 PC.2 PC.1 LQFP48 PC.0 LDO_CAP PB.0 PB.1 PF.4 PB.2 PF.3 PB.3 PD.7 PB.4 PF.2 power domain DDIO power domain ®...
Page 34: Numicro ® Nuc126 Usb Series Lqfp64 Pin Diagram
NUC126 ® 4.2.3 NuMicro NUC126 USB Series LQFP64 Pin Diagram Corresponding Part Number: NUC126SE4AE, NUC126SG4AE PA.3 PC.5 PA.2 PC.4 PA.1 PC.3 PA.0 PC.2 PC.1 PC.0 LDO_CAP LQFP64 PB.0 PB.1 PF.4 PB.2 PF.3 PB.3 PD.7 PB.4 PD.15 PB.8 PD.14 PB.11 PD.13 PE.2 PD.12 power domain...
Page 35: Numicro ® Nuc126 Usb Series Lqfp100 Pin Diagram
NUC126 ® 4.2.4 NuMicro NUC126 USB Series LQFP100 Pin Diagram Corresponding Part Number: NUC126VG4AE PF.7 PC.5 USB_VDD33_CAP PE.0 PB.12 PC.4 PA.3 PC.3 PA.2 PC.2 PA.1 PC.1 PA.0 PC.0 PA.12 PC.14 PA.13 PC.13 PA.14 PC.12 PA.15 PC.11 PC.10 LQFP100 PC.9 LDO_CAP PB.0 PB.1 PF.4...
Page 36: Pin Description
NUC126 Pin Description 4.3.1 NUC126 USB Series Pin Description MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH) PA.0 MFP0 means SYS_GP0_MFPL[3:0]=0x0. PA.9 MFP5 means SYS_GP0_MFPH[7:4]=0x5. Pin Name Type Description 1 PB.13 MFP0 General purpose digital I/O pin. ADC0_CH10 MFP1 ADC0 channel 10 analog input.
Page 37 NUC126 Pin Name Type Description SPI1_CLK MFP3 SPI1 serial clock pin. USCI2_CTL1 MFP4 USCI2 control 1 pin. ACMP0_P0 MFP5 Analog comparator 0 positive input 0 pin. SC1_DAT MFP6 Smart Card 1 data pin. EBI_AD4 MFP7 EBI address/data bus bit 4. 7 nRESET MFP0 External reset input: active LOW, with an internal pull-...
Page 38 NUC126 Pin Name Type Description ACMP1_P3 MFP5 Analog comparator 1 positive input 3 pin. MFP6 Timer3 event counter input/toggle output pin. EBI_ALE MFP7 EBI address latch enable output pin. 10 15 PD.1 MFP0 General purpose digital I/O pin. ADC0_CH19 MFP1 ADC0 channel 19 analog input.
Page 39 NUC126 Pin Name Type Description UART2_nRTS MFP4 UART2 request to Send output pin. PWM0_BRAKE0 MFP5 PWM0 Brake 0 input pin. MFP6 Timer0 event counter input/toggle output pin. 19 PD.5 MFP0 General purpose digital I/O pin. CLKO MFP1 Clock Out SPI1_MISO MFP2 SPI1 MISO (Master In, Slave Out) pin.
Page 40 NUC126 Pin Name Type Description 13 16 25 PF.2 MFP0 General purpose digital I/O pin. USCI2_CLK MFP5 USCI2 clock pin. PWM1_BRAKE1 MFP6 PWM1 Brake 1 input pin. 26 PD.10 MFP0 General purpose digital I/O pin. MFP4 Timer2 event counter input/toggle output pin. USCI2_DAT0 MFP5 USCI2 data 0 pin.
Page 41 NUC126 Pin Name Type Description PWM1_CH3 MFP6 PWM1 channel 3 output/capture input. EBI_ADR19 MFP7 EBI address bus bit 19. 14 21 32 PD.7 MFP0 General purpose digital I/O pin. USCI1_CTL1 MFP1 USCI1 control 1 pin. SPI0_I2SMCLK MFP2 SPI0 I2S master clock output pin PWM0_SYNC_IN MFP3 PWM0 counter synchronous trigger input pin.
Page 42 NUC126 Pin Name Type Description USCI2_CLK MFP4 USCI2 clock pin. PWM1_CH2 MFP6 PWM1 channel 2 output/capture input. 41 PC.12 MFP0 General purpose digital I/O pin. SPI0_CLK MFP2 SPI0 serial clock pin. USCI2_CTL0 MFP4 USCI2 control 0 pin. PWM1_CH3 MFP6 PWM1 channel 3 output/capture input. 42 PC.13 MFP0 General purpose digital I/O pin.
Page 43 NUC126 Pin Name Type Description SPI0_SS MFP2 SPI0 slave select pin. UART2_TXD MFP3 UART2 data transmitter output pin. USCI0_CTL1 MFP4 USCI0 control 1 pin. ACMP1_O MFP5 Analog comparator 1 output pin. PWM0_CH2 MFP6 PWM0 channel 2 output/capture input. EBI_AD10 MFP7 EBI address/data bus bit 10.
Page 44 NUC126 Pin Name Type Description USCI0_DAT0 MFP4 USCI0 data 0 pin. PWM0_CH5 MFP6 PWM0 channel 5 output/capture input. EBI_AD13 MFP7 EBI address/data bus bit 13. 33 51 PC.6 MFP0 General purpose digital I/O pin. USCI0_DAT1 MFP4 USCI0 data 1 pin. ACMP1_O MFP5 Analog comparator 1 output pin.
Page 45 NUC126 Pin Name Type Description UART0_RXD MFP3 UART0 data receiver input pin. 26 36 56 PE.7 MFP0 General purpose digital I/O pin. ICE_DAT MFP1 Serial wired debugger data pin. I2C0_SDA MFP2 I2C0 data input/output pin. UART0_TXD MFP3 UART0 data transmitter output pin. 57 PA.8 MFP0 General purpose digital I/O pin.
Page 46 NUC126 Pin Name Type Description TM_BRAKE2 MFP6 TM_BRAKE2 I Timer Brake * input pin. EBI_AD6 MFP7 EBI address/data bus bit 6. 61 PA.5 MFP0 General purpose digital I/O pin. SPI1_MOSI MFP2 SPI1 MOSI (Master Out, Slave In) pin. TM2_EXT MFP3 Timer2 external capture input/toggle output pin.
Page 47 NUC126 Pin Name Type Description SC0_DAT MFP5 Smart Card 0 data pin. SPI1_CLK MFP6 SPI1 serial clock pin. EBI_AD7 MFP7 EBI address/data bus bit 7. TM0_EXT MFP8 Timer0 external capture input/toggle output pin. 28 40 69 PE.11 MFP0 General purpose digital I/O pin. SPI1_MOSI MFP1 SPI1 MOSI (Master Out, Slave In) pin.
Page 48 NUC126 Pin Name Type Description 34 46 75 USB_D+ MFP0 USB differential signal D+. 35 47 76 PF.7 MFP0 General purpose digital I/O pin. 36 48 77 USB_VDD33_CAP MFP0 Internal power regulator output 3.3V decoupling pin. 78 PB.12 MFP0 General purpose digital I/O pin. PWM1_CH1 MFP6 PWM1 channel 1 output/capture input.
Page 49 NUC126 Pin Name Type Description USCI1_CTL0 MFP4 USCI1 control 0 pin. SC0_CLK MFP5 Smart Card 0 clock pin. PWM1_CH5 MFP6 PWM1 channel 5 output/capture input. EBI_AD0 MFP7 EBI address/data bus bit 0. INT0 MFP8 External interrupt 0 input pin. 83 PA.12 MFP0 General purpose digital I/O pin.
Page 50 NUC126 Pin Name Type Description UART2_RXD MFP3 UART2 data receiver input pin. MFP4 Timer2 event counter input/toggle output pin. USCI1_DAT0 MFP6 USCI1 data 0 pin. EBI_nWRL MFP7 EBI low byte write enable output pin. INT1 MFP8 External interrupt 1 input pin. TM1_EXT MFP10 Timer1 external capture input/toggle output pin.
Page 51 NUC126 Pin Name Type Description EBI_ALE MFP7 EBI address latch enable output pin. USCI0_DAT1 MFP8 USCI0 data 1 pin. TM0_EXT MFP10 Timer0 external capture input/toggle output pin. 48 61 95 PB.4 MFP0 General purpose digital I/O pin. ADC0_CH4 MFP1 ADC0 channel 4 analog input. SPI0_SS MFP2 SPI0 slave select pin.
Page 52 NUC126 Pin Name Type Description PWM0_CH2 MFP6 PWM0 channel 2 output/capture input. USCI0_CTL0 MFP8 USCI0 control 0 pin. Aug. 08, 2018 Page 52 of 943 Rev 1.03...
Page 53: Gpio Multi-Function Pin Summary
NUC126 4.3.2 GPIO Multi-function Pin Summary MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH) PA.0 MFP0 means SYS_GP0_MFPL[3:0]=0x0. PA.9 MFP5 means SYS_GP0_MFPH[7:4]=0x5. Pin Name Type Description PA.0 MFP0 General purpose digital I/O pin. UART1_nCTS MFP1 UART1 clear to Send input pin. UART1_TXD MFP3 UART1 data transmitter output pin.
Page 54 NUC126 Pin Name Type Description PWM1_CH2 MFP6 PWM1 channel 2 output/capture input. EBI_AD3 MFP7 EBI address/data bus bit 3. USCI1_CLK MFP8 USCI1 clock pin. PA.4 MFP0 General purpose digital I/O pin. SPI1_SS MFP2 SPI1 slave select pin. PA.4 TM3_EXT MFP3 Timer3 external capture input/toggle output pin.
Page 55 NUC126 Pin Name Type Description SPI1_I2SMCLK MFP1 SPI1 I S master clock output pin I2C1_SDA MFP2 C1 data input/output pin. UART1_RXD MFP3 UART1 data receiver input pin. SC0_RST MFP4 Smart Card 0 reset pin. SC1_PWR MFP5 Smart Card 1 power pin. TM_BRAKE1 MFP6 TM_BRAKE1 I Timer Brake * input pin.
Page 56 NUC126 Pin Name Type Description ADC0_CH0 MFP1 ADC0 channel 0 analog input. VDET_P0 MFP2 Voltage detector positive input 0 pin. UART2_RXD MFP3 UART2 data receiver input pin. MFP4 Timer2 event counter input/toggle output pin. USCI1_DAT0 MFP6 USCI1 data 0 pin. EBI_nWRL MFP7 EBI low byte write enable output pin.
Page 57 NUC126 Pin Name Type Description TM_BRAKE1 MFP6 TM_BRAKE1 I Timer Brake * input pin. EBI_ALE MFP7 EBI address latch enable output pin. USCI0_DAT1 MFP8 USCI0 data 1 pin. TM0_EXT MFP10 Timer0 external capture input/toggle output pin. PB.4 MFP0 General purpose digital I/O pin. ADC0_CH4 MFP1 ADC0 channel 4 analog input.
Page 58 NUC126 Pin Name Type Description SPI0_CLK MFP2 SPI0 serial clock pin. SPI1_CLK MFP3 SPI1 serial clock pin. USCI2_CTL1 MFP4 USCI2 control 1 pin. ACMP0_P0 MFP5 Analog comparator 0 positive input 0 pin. SC1_DAT MFP6 Smart Card 1 data pin. EBI_AD4 MFP7 EBI address/data bus bit 4.
Page 59 NUC126 Pin Name Type Description UART2_nCTS MFP3 UART2 clear to Send input pin. USCI0_DAT0 MFP4 USCI0 data 0 pin. ACMP0_WLAT MFP5 Analog comparator 0 window latch input pin PWM0_CH0 MFP6 PWM0 channel 0 output/capture input. EBI_AD8 MFP7 EBI address/data bus bit 8. INT2 MFP8 External interrupt 2 input pin.
Page 60 NUC126 Pin Name Type Description I2C1_SCL MFP3 C1 clock pin. USCI0_CLK MFP5 USCI0 clock pin. PWM0_CH4 MFP6 PWM0 channel 4 output/capture input. EBI_AD12 MFP7 EBI address/data bus bit 12. PC.5 MFP0 General purpose digital I/O pin. SPI0_I2SMCLK MFP2 SPI0 I S master clock output pin I2C1_SDA MFP3...
Page 61 NUC126 Pin Name Type Description PC.11 MFP0 General purpose digital I/O pin. SPI0_MISO MFP2 SPI0 MISO (Master In, Slave Out) pin. PC.11 USCI2_CLK MFP4 USCI2 clock pin. PWM1_CH2 MFP6 PWM1 channel 2 output/capture input. PC.12 MFP0 General purpose digital I/O pin. SPI0_CLK MFP2 SPI0 serial clock pin.
Page 62 NUC126 Pin Name Type Description PD.2 MFP0 General purpose digital I/O pin. ADC0_ST MFP1 ADC0 external trigger input pin. TM0_EXT MFP3 Timer0 external capture input/toggle output pin. USCI2_DAT0 MFP4 USCI2 data 0 pin. PD.2 ACMP1_P1 MFP5 Analog comparator 1 positive input 1 pin. PWM0_BRAKE0 MFP6 PWM0 Brake 0 input pin.
Page 63 NUC126 Pin Name Type Description SPI1_SS MFP2 SPI1 slave select pin. UART0_RXD MFP3 UART0 data receiver input pin. UART2_TXD MFP4 UART2 data transmitter output pin. ACMP0_O MFP5 Analog comparator 0 output pin. PWM0_CH5 MFP6 PWM0 channel 5 output/capture input. EBI_nWR MFP7 EBI write enable output pin.
Page 64 NUC126 Pin Name Type Description USCI2_DAT1 MFP5 USCI2 data 1 pin. PD.12 MFP0 General purpose digital I/O pin. USCI1_CTL0 MFP1 USCI1 control 0 pin. SPI1_SS MFP2 SPI1 slave select pin. PD.12 UART0_TXD MFP3 UART0 data transmitter output pin. PWM1_CH0 MFP6 PWM1 channel 0 output/capture input.
Page 65 NUC126 Pin Name Type Description INT4 MFP8 External interrupt 4 input pin. PE.1 MFP0 General purpose digital I/O pin. TM3_EXT MFP3 Timer3 external capture input/toggle output pin. PE.1 SC0_nCD MFP5 Smart Card 0 card detect pin. PWM0_CH1 MFP6 PWM0 channel 1 output/capture input. PE.2 MFP0 General purpose digital I/O pin.
Page 66 NUC126 Pin Name Type Description ICE_CLK MFP1 Serial wired debugger clock pin. I2C0_SCL MFP2 C0 clock pin. UART0_RXD MFP3 UART0 data receiver input pin. PE.7 MFP0 General purpose digital I/O pin. ICE_DAT MFP1 Serial wired debugger data pin. PE.7 I2C0_SDA MFP2 C0 data input/output pin.
Page 67 NUC126 Pin Name Type Description TM1_EXT MFP8 Timer1 external capture input/toggle output pin. PE.12 MFP0 General purpose digital I/O pin. SPI1_SS MFP1 SPI1 slave select pin. SPI0_SS MFP2 SPI0 slave select pin. UART1_TXD MFP3 UART1 data transmitter output pin. PE.12 I2C0_SCL MFP4 C0 clock pin.
Page 68: Table 4.3-1 Nuc126 Gpio Multi-Function Table
NUC126 Pin Name Type Description XT1_IN MFP1 External 4~24 MHz (high speed) crystal input pin. I2C1_SDA MFP3 C1 data input/output pin. PF.5 MFP0 General purpose digital I/O pin. TM3_EXT MFP3 Timer3 external capture input/toggle output pin. PF.5 SC1_nCD MFP5 Smart Card 1 card detect pin. TM_BRAKE0 MFP6 TM_BRAKE0 I Timer Brake * input pin.
Page 69: Block Diagram
NUC126 BLOCK DIAGRAM ® NuMicro NUC126 Block Diagram Analog Interface RTC / PWM / Timer Memory Speed Up APROM LDROM RTC (V PDMA-5ch 256/128KB 4 KB 12-bit ADC 20-ch Watchdog Timer DataFlash SRAM Cortex-M0 Hard Divider Analog 72 MHz 20 KB Configurable Comparator x 2 Timer/PWM X4...
Page 70: Functional Description
NUC126 FUNCTIONAL DESCRIPTION ® ® Cortex -M0 Core ® The Cortex -M0 processor is a configurable, multistage, 32-bit RISC processor, which has an AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug ® functionality. The processor can execute Thumb code and is compatible with other Cortex -M profile processor.
Page 71 NUC126 Dedicated Non-maskable Interrupt (NMI) input – Supports for both level-sensitive and pulse-sensitive interrupt lines – Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power Sleep – mode  Debug support: Four hardware breakpoints – Two watchpoints – Program Counter Sampling Register (PCSR) for non-intrusive code profiling –...
Page 72: System Manager
NUC126 System Manager 6.2.1 Overview The system manager provides the functions of system control, power modes, wake-up sources, reset sources, system memory map, product ID and multi-function pin control. The following sections describe the functions for  System Reset  Power Modes and Wake-up Sources ...
Page 73: Figure 6.2-1 System Reset Sources
NUC126 Glitch Filter nRESET ~36 us ~50k ohm POROFF(SYS_PORCTL[15:0]) Power-on Reset LVREN(SYS_BODCTL[7]) Reset Pulse Width Low Voltage ~3.2ms Reset BODRSTEN(SYS_BODCTL[3]) Brown-out Reset System Reset WDT/WWDT Reset Pulse Width Reset Controller Reset 64 WDT clocks CPU Lockup Reset Pulse Width Reset 2 system clocks CHIP Reset CHIPRST(SYS_IPRST0[0])
Page 74 NUC126 ® There are a total of 9 reset sources in the NuMicro family. In general, CPU reset is used to reset ® ® Cortex -M0 only; the other reset sources will reset Cortex -M0 and all peripherals. However, there are small differences between each reset source and they are listed in Table 6.2-1.
Page 75: Table 6.2-1 Reset Value Of Registers
NUC126 WDT_CTL 0x0700 0x0700 0x0700 0x0700 0x0700 0x0700 except bit 1 and bit 7. WDT_ALTCTL 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 WWDT_RLDCNT 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 WWDT_CTL 0x3F0800 0x3F0800 0x3F0800 0x3F0800 0x3F0800 - 0x3F0800 WWDT_STATUS 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000...
Page 76: Figure 6.2-2 Nreset Reset Waveform
NUC126 Figure 6.2-2 nRESET Reset Waveform 6.2.2.2 Power-on Reset (POR) The Power-on reset (POR) is used to generate a stable system reset signal and forces the system to be reset when power-on to avoid unexpected behavior of MCU. When applying the power to MCU, the POR module will detect the rising voltage and generate reset signal to system until the voltage is ready for MCU operation.
Page 77: Figure 6.2-4 Low Voltage Reset (Lvr) Waveform
NUC126 ( < LVRDGSEL) ( =LVRDGSEL) ( =LVRDGSEL) Low Voltage Reset 200 us Delay for LVR stable LVREN Figure 6.2-4 Low Voltage Reset (LVR) Waveform 6.2.2.4 Brown-out Detector Reset (BOD Reset) If the Brown-out Detector (BOD) function is enabled by setting the Brown-out Detector Enable Bit BODEN (SYS_BODCTL[0]), Brown-out Detector function will detect AV during system operation.
Page 78: Figure 6.2-5 Brown-Out Detector (Bod) Waveform
NUC126 BODH Hysteresis BODL (< BODDGSEL) (= BODDGSEL) BODOUT (= BODDGSEL) BODRSTEN Brown-out Reset Figure 6.2-5 Brown-out Detector (BOD) Waveform 6.2.2.5 Watchdog Timer Reset (WDT) In most industrial applications, system reliability is very important. To automatically recover the MCU from failure status is one way to improve system reliability. The watchdog timer(WDT) is widely used to check if the system works fine.
Page 79: Power Modes And Wake-Up Sources
NUC126 reloaded from CONFIG0 setting and keep its original software setting for booting from APROM or LDROM. User can set the SYSRESETREQ(AIRCR[2]) to 1 to assert the MCU Reset. 6.2.3 Power Modes and Wake-up Sources There are several wake-up sources in Idle mode and Power-down mode. Table 6.2-2 lists the available clocks for each power mode.
Page 80: Figure 6.2-6 Numicro ® Nuc126 Power Mode State Machine
NUC126 System reset released Normal Mode CPU Clock ON HXT, HIRC, HIRC48, LXT, LIRC, HCLK, PCLK ON Flash ON CPU executes WFI Interrupts occur 1. SLEEPDEEP(SCR[2]) = 1 Wake-up events 2. PDEN(CLK_PWRCTL[7]) = 1 occur 3. CPU executes WFI Idle Mode Power-down Mode CPU Clock OFF CPU Clock OFF...
Page 81: Table 6.2-3 Clocks In Power Modes
NUC126 WWDT Halt ON/OFF UART ON/OFF Halt USCI Halt Halt Halt USBD Halt Halt ACMP Halt Table 6.2-3 Clocks in Power Modes Wake-up sources in Power-down mode: RTC, WDT, I²C, Timer, UART, USCI, BOD, EBOD, GPIO, USBD, and ACMP. After chip enters power down, the following wake-up sources can wake chip up to normal mode. Table 6.2-4 lists the condition about how to enter Power-down mode again for each peripheral.
Page 82: System Power Distribution
NUC126 After software writes 1 to clear WKAKDONE (UI2C_PROTSTS[16], then writes 1 Address match to clear WKF (UI2C_WKSTS[0]). USCI SPI SS Toggle After software writes 1 to clear WKF (USPI_WKSTS[0]). After software writes 1 to clear WKAKDONE (I2C_WKSTS[1]). Then software Address match wake-up writes 1 to clear WKIF(I2C_WKSTS[0]).
Page 83: Figure 6.2-7 Numicro ® Nuc126 Power Distribution Diagram
NUC126 Internal 32.768 kHz USB_D+ Reference IO Cell crystal USB_D- Transceiver Voltage oscillator 12-bit ADC USB_VDD33_CAP Analog 3.3V 1.8V Comparator Brown- to 1.8V 5V to 3.3V Low Voltage Reset Detector Temperature SRAM Flash Digital Logic Sensor IO Cell PE.8~PE.13 LDO_CAP 1.8V 48 MHz 22.1184 MHz...
Page 84: System Memory Map
NUC126 6.2.5 System Memory Map The NUC126 series provides 4G-byte addressing space. The memory locations assigned to each on- chip controllers are shown in Table 6.2-5. The detailed register definition, memory space, and programming will be described in the following sections for each on-chip peripheral. The NUC126 series only supports little-endian data format.
Page 85: Table 6.2-5 Address Space Assignments For On-Chip Controllers
NUC126 0x4007_4000 – 0x4007_7FFF USCI2_BA USCI2 Control Registers 0x400D_0000 – 0x400D_3FFF ACMP01_BA Analog Comparator Control Registers 0x400D_4000 – 0x400D_7FFF Reserved Reserved 0x400E_0000 – 0x400E_FFFF ADC_BA Analog-Digital-Converter (ADC) Control Registers 0x4010_0000 – 0x4010_3FFF Reserved Reserved 0x4011_0000 – 0x4011_3FFF TMR23_BA Timer2/Timer3 Control Registers 0x4012_0000 –...
Page 86: Sram Memory Orginization
NUC126 6.2.6 SRAM Memory Orginization The NUC126 supports embedded SRAM with total 20 Kbytes size in one bank.  Supports total 20 Kbytes SRAM  Supports byte / half word / word write  Supports oversize response error AHB interface SRAM decoder SRAM bank controller...
Page 87: Register Lock
NUC126 0x3FFF_FFFF Reserved 0x2000_5000 0x2000_4FFF 20K byte SRAM bank0 0x2000_0000 20K byte device Figure 6.2-9 SRAM Memory Organization 6.2.7 Register Lock Some of the system control registers need to be protected to avoid inadvertent write and disturb the chip operation. These system control registers are protected after the power-on reset till user to disable register protection.
Page 88: Uart1_Txd Modulation With Pwm
NUC126 according to the accurate external 32.768 kHz crystal oscillator or internal USB synchronous mode, automatically gets accurate HIRC output frequency, 0.25 % deviation within all temperature ranges. For instance, the system needs an accurate 22.1184 MHz clock. In such case, if users do not want to use PLL as the system clock source, they need to solder 32.768 kHz crystal in system, and set FREQSEL (SYS_IRCTCTL0[1:0] trim frequency selection) to “01”, set REFCKSEL (SYS_IRCTCTL0[9] reference clock selection) to “0”, and the auto-trim function will be enabled.
Page 89: Voltage Detector (Vdet)
NUC126 6.2.10 Voltage Detector (VDET) This chip supports low power comparator to detect external voltage. User can control Bandgap active interval and comparator active interval to achieve low power detection purpose. There is no debounce function in Power-down mode since no HCLK available in Power-down mode. VDETPINSEL(SYS_BODCTL[17]) VDET_ VDET_...
Page 90: Register Map
NUC126 6.2.11 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value SYS Base Address: SYS_BA = 0x5000_0000 0xXXXX_XXXX SYS_PDID SYS_BA+0x00 R Part Device Identification Number Register SYS_RSTSTS SYS_BA+0x04 R/W System Reset Status Register 0x0000_004B SYS_IPRST0 SYS_BA+0x08 R/W Peripheral Reset Control Register 0...
Page 91 NUC126 SYS_IRCTCTL1 SYS_BA+0x90 R/W HIRC1 Trim Control Register 0x0000_0400 SYS_REGLCTL SYS_BA+0x100 R/W Register Lock Control Register 0x0000_0000 SYS_TSOFFSET SYS_BA+0x114 R Temperature Sensor Offset Register 0x0000_0XXX Aug. 08, 2018 Page 91 of 943 Rev 1.03...
Page 92: Register Description
NUC126 6.2.12 Register Description Part Device Identification Number Register (SYS_PDID) Register Offset Description Reset Value 0xXXXX_XXXX SYS_PDID SYS_BA+0x00 Part Device Identification Number Register [1] Every part number has a unique default reset value. PDID [31:24] PDID [23:16] PDID [15:8] PDID [7:0] Bits Description Part Device Identification Number (Read Only)
Page 93 NUC126 System Reset Status Register (SYS_RSTSTS) This register provides specific information for software to identify this chip’s reset source from last operation. Register Offset Description Reset Value SYS_RSTSTS SYS_BA+0x04 System Reset Status Register 0x0000_004B Reserved Reserved Reserved CPULKRF CPURF Reserved MCURF BODRF LVRF...
Page 94 NUC126 Bits Description BOD Reset Flag The BOD reset flag is set by the “Reset Signal” from the Brown-out Detector to indicate the previous reset source. BODRF 0 = No reset from BOD. 1 = The BOD had issued the reset signal to reset the system. Note: This bit can be cleared by software writing ‘1’.
Page 95 NUC126 Peripheral Reset Control Register 0 (SYS_IPRST0) Register Offset Description Reset Value Peripheral Reset Control Register 0 SYS_IPRST0 SYS_BA+0x08 0x0000_0000 Reserved Reserved Reserved CRCRST Reserved HDIVRST EBIRST PDMARST CPURST CHIPRST Bits Description [31:8] Reserved Reserved. CRC Calculation Controller Reset (Write Protect) Set this bit to 1 will generate a reset signal to the CRC calculation controller.
Page 96 NUC126 this bit will automatically return to 0 after the 2 clock cycles. 0 = Processor core normal operation. 1 = Processor core one-shot reset. Note: This bit is write protected. Refer to the SYS_REGLCTL register. Chip One-shot Reset (Write Protect) Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.
Page 97 NUC126 Peripheral Reset Control Register 1 (SYS_IPRST1) Setting these bits 1 will generate asynchronous reset signals to the corresponding module controller. Users need to set these bits to 0 to release corresponding module controller from reset state. Register Offset Description Reset Value SYS_IPRST1 SYS_BA+0x0C...
Page 98 NUC126 1 = UART1 controller reset. UART0 Controller Reset [16] UART0RST 0 = UART0 controller normal operation. 1 = UART0 controller reset. Reserved [15:14] Reserved. SPI1 Controller Reset [13] SPI1RST 0 = SPI1 controller normal operation. 1 = SPI1 controller reset. SPI0 Controller Reset [12] SPI0RST...
Page 99 NUC126 Peripheral Reset Control Register 2 (SYS_IPRST2) Setting these bits to 1 will generate asynchronous reset signals to the corresponding module controller. Users need to set these bits to 0 to release corresponding module controller from reset state. Register Offset Description Reset Value SYS_IPRST2...
Page 100 NUC126 Brown-out Detector Control Register (SYS_BODCTL) Partial of the SYS_BODCTL control registers values are initiated by the flash configuration and partial bits are write-protected bit. Register Offset Description Reset Value SYS_BODCTL SYS_BA+0x18 Brown-out Detector Control Register 0x0000_038X Reserved VDETDGSEL VDETDOUT VDETBGSEL VDETDTSEL VDETIF...
Page 101 NUC126 Bits Description Voltage Detector Interrupt Enable Bit [18] VDETIEN 0 = VDET interrupt Disabled. 1 = VDET interrupt Enabled. Voltage Detector External Input Voltage Pin Selection 0 = The input voltage is from VDET_P0 (PB.0). 1 = The input voltage is from VDET_P1 (PB.1). [17] VDETPINSEL Note1: If VDET_P0 is selected, multi-function pin must be selected correctly in PB0MFP...
Page 102 NUC126 Bits Description Low Voltage Reset Enable Bit (Write Protect) The LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default. 0 = Low Voltage Reset function Disabled. LVREN 1 = Low Voltage Reset function Enabled.
Page 103 NUC126 Bits Description Brown-out Detector Enable Bit (Write Protect) The default value is set by flash controller user configuration register CBODEN (CONFIG0 [23]). BODEN 0 = Brown-out Detector function Disabled. 1 = Brown-out Detector function Enabled. Note: This bit is write protected. Refer to the SYS_REGLCTL register. Aug.
Page 104 NUC126 Internal Voltage Source Control Register (SYS_IVSCTL) Register Offset Description Reset Value SYS_IVSCTL SYS_BA+0x1C Internal Voltage Source Control Register 0x0000_0000 Reserved Reserved Reserved Reserved VBATUGEN VTEMPEN Bits Description [31:2] Reserved Reserved. VBAT Unity Gain Buffer Enable Bit This bit is used to enable/disable VBAT unity gain buffer function. 0 = VBAT unity gain buffer function Disabled (default).
Page 105 NUC126 Power-on Reset Controller Register (SYS_PORCTL) Register Offset Description Reset Value SYS_PORCTL SYS_BA+0x24 Power-on Reset Controller Register 0x0000_0000 Reserved Reserved POROFF[15:8] POROFF[7:0] Bits Description [31:16] Reserved Reserved. Power-on Reset Enable Bit (Write Protect) When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again.
Page 106 NUC126 Control Register (SYS_VREFCTL) Register Offset Description Reset Value SYS_VREFCTL SYS_BA+0x28 Control Register 0x0000_0000 Reserved Reserved Reserved Reserved VREFCTL Bits Description [31:5] Reserved Reserved. Int_V Control Bits (Write Protect) 00000 = From V pin. 00011 = V is internal 2.56V. 00111 = V is internal 2.048V.
Page 107 NUC126 GPIOA Low Byte Multiple Function Control Register (SYS_GPA_MFPL) Register Offset R/W Description Reset Value SYS_GPA_MFPL SYS_BA+0x30 R/W GPIOA Low Byte Multiple Function Control Register 0x0000_0000 PA7MFP PA6MFP PA5MFP PA4MFP PA3MFP PA2MFP PA1MFP PA0MFP Bits Description [31:28] PA7MFP PA.7 Multi-function Pin Selection [27:24] PA6MFP PA.6 Multi-function Pin Selection...
Page 108 NUC126 GPIOA High Byte Multiple Function Control Register (SYS_GPA_MFPH) Register Offset R/W Description Reset Value SYS_GPA_MFPH SYS_BA+0x34 R/W GPIOA High Byte Multiple Function Control Register 0x0000_0000 PA15MFP PA14MFP PA13MFP PA12MFP PA11MFP PA10MFP PA9MFP PA8MFP Bits Description [31:28] PA15MFP PA.15 Multi-function Pin Selection [27:24] PA14MFP PA.14 Multi-function Pin Selection...
Page 109 NUC126 GPIOB Low Byte Multiple Function Control Register (SYS_GPB_MFPL) Register Offset Description Reset Value SYS_GPB_MFPL SYS_BA+0x38 R/W GPIOB Low Byte Multiple Function Control Register 0x0000_0000 PB7MFP PB6MFP PB5MFP PB4MFP PB3MFP PB2MFP PB1MFP PB0MFP Bits Description [31:28] PB7MFP PB.7 Multi-function Pin Selection [27:24] PB6MFP PB.6 Multi-function Pin Selection...
Page 110 NUC126 GPIOB High Byte Multiple Function Control Register (SYS_GPB_MFPH) Register Offset R/W Description Reset Value SYS_GPB_MFPH SYS_BA+0x3C R/W GPIOB High Byte Multiple Function Control Register 0x0000_0000 PB15MFP PB14MFP PB13MFP PB12MFP PB11MFP PB10MFP PB9MFP PB8MFP Bits Description [31:28] PB15MFP PB.15 Multi-function Pin Selection [27:24] PB14MFP PB.14 Multi-function Pin Selection...
Page 111 NUC126 GPIOC Low Byte Multiple Function Control Register (SYS_GPC_MFPL) Register Offset Description Reset Value SYS_GPC_MFPL SYS_BA+0x40 R/W GPIOC Low Byte Multiple Function Control Register 0x0000_0000 PC7MFP PC6MFP PC5MFP PC4MFP PC3MFP PC2MFP PC1MFP PC0MFP Bits Description [31:28] PC7MFP PC.7 Multi-function Pin Selection [27:24] PC6MFP PC.6 Multi-function Pin Selection...
Page 112 NUC126 GPIOC High Byte Multiple Function Control Register (SYS_GPC_MFPH) Register Offset Description Reset Value SYS_GPC_MFPH SYS_BA+0x44 R/W GPIOC High Byte Multiple Function Control Register 0x0000_0000 PC15MFP PC14MFP PC13MFP PC12MFP PC11MFP PC10MFP PC9MFP PC8MFP Bits Description [31:28] PC15MFP PC15 Multi-function Pin Selection [27:24] PC14MFP PC14 Multi-function Pin Selection...
Page 113 NUC126 GPIOD Low Byte Multiple Function Control Register (SYS_GPD_MFPL) Register Offset Description Reset Value SYS_GPD_MFPL SYS_BA+0x48 GPIOD Low Byte Multiple Function Control Register 0x0000_0000 PD7MFP PD6MFP PD5MFP PD4MFP PD3MFP PD2MFP PD1MFP PD0MFP Bits Description [31:28] PD7MFP PD.7 Multi-function Pin Selection [27:24] PD6MFP PD.6 Multi-function Pin Selection...
Page 114 NUC126 GPIOD High Byte Multiple Function Control Register (SYS_GPD_MFPH) Register Offset R/W Description Reset Value SYS_GPD_MFPH SYS_BA+0x4C R/W GPIOD High Byte Multiple Function Control Register 0x0000_0000 PD15MFP PD14MFP PD13MFP PD12MFP PD11MFP PD10MFP PD9MFP PD8MFP Bits Description [31:28] PD15MFP PD.15 Multi-function Pin Selection [27:24] PD14MFP PD.14 Multi-function Pin Selection...
Page 115 NUC126 GPIOE Low Byte Multiple Function Control Register (SYS_GPE_MFPL) Register Offset Description Reset Value SYS_GPE_MFPL SYS_BA+0x50 GPIOE Low Byte Multiple Function Control Register 0x1100_0000 PE7MFP PE6MFP PE5MFP PE4MFP PE3MFP PE2MFP PE1MFP PE0MFP Bits Description [31:28] PE7MFP PE.7 Multi-function Pin Selection [27:24] PE6MFP PE.6 Multi-function Pin Selection...
Page 116 NUC126 GPIOE High Byte Multiple Function Control Register (SYS_GPE_MFPH) Register Offset R/W Description Reset Value SYS_GPE_MFPH SYS_BA+0x54 R/W GPIOE High Byte Multiple Function Control Register 0x0000_0000 Reserved PE13MFP PE12MFP PE11MFP PE10MFP PE9MFP PE8MFP Bits Description [31:24] Reserved Reserved. [23:20] PE13MFP PE.13 Multi-function Pin Selection [19:16] PE12MFP...
Page 117 NUC126 GPIOF Low Byte Multiple Function Control Register (SYS_GPF_MFPL) Register Offset Description Reset Value SYS_GPF_MFPL SYS_BA+0x58 GPIOF Low Byte Multiple Function Control Register 0x000X_X000 PF7MFP PF6MFP PF5MFP PF4MFP PF3MFP PF2MFP PF1MFP PF0MFP Bits Description [31:28] PF7MFP PF.7 Multi-function Pin Selection [27:24] PF6MFP PF.6 Multi-function Pin Selection...
Page 118 NUC126 Modulation Control Register (SYS_MODCTL) Register Offset Description Reset Value SYS_MODCTL SYS_BA+0xC0 Modulation Control Register 0x0000_0000 Reserved Reserved Reserved Reserved MODPWMSEL Reserved MODH MODEN Bits Description [31:7] Reserved Reserved. PWM0 Channel Select for Modulation Select the PWM0 channel to modulate with the UART1_TXD. 000 = PWM0 channel 0 modulate with UART1_TXD.
Page 119 NUC126 System SRAM BIST Test Control Register (SYS_SRAM_BISTCTL) Register Offset Description Reset Value SYS_SRAM_BIS SYS_BA+0xD0 System SRAM BIST Test Control Register 0x0000_0000 TCTL Reserved Reserved Reserved Reserved USBBIST Reserved CRBIST Reserved SRBIST Bits Description [31:5] Reserved Reserved. USB BIST Enable Bit (Write Protect) This bit enables BIST test for USB RAM USBBIST 0 = System USB BIST Disabled.
Page 120 NUC126 System SRAM BIST Test Status Register (SYS_SRAM_BISTSTS) Register Offset Description Reset Value SYS_SRAM_BIS SYS_BA+0xD4 System SRAM BIST Test Status Register 0x00XX_00XX TSTS Reserved Reserved USBBEND Reserved CRBEND Reserved SRBEND Reserved Reserved USBBEF Reserved CRBISTEF Reserved SRBISTEF Bits Description [31:21] Reserved Reserved.
Page 121 NUC126 HIRC0 Trim Control Register (SYS_IRCTCTL0) Register Offset Description Reset Value SYS_IRCTCTL0 SYS_BA+0x80 HIRC0 Trim Control Register 0x0000_0000 Reserved Reserved Reserved REFCKSEL Reserved CESTOPEN RETRYCNT LOOPSEL Reserved FREQSEL Bits Description [31:10] Reserved Reserved. Reference Clock Selection [10] REFCKSEL 0 = HIRC trim reference clock is from external 32.768 kHz crystal oscillator . 1 = HIRC trim reference clock is from internal USB synchronous mode.
Page 122 NUC126 [3:2] Reserved Reserved. Trim Frequency Selection This field indicates the target frequency of internal high speed RC oscillator 0 (HIRC0) auto trim. During auto trim operation, if clock error detected with CESTOPEN(SYS_IRCTCTL0[8]) is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. [1:0] FREQSEL 00 = Disable HIRC0 auto trim function.
Page 123 NUC126 HIRC Trim Interrupt Enable Register (SYS_IRCTIEN) Register Offset Description Reset Value SYS_IRCTIEN SYS_BA+0x84 HIRC Trim Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved CLKEIEN1 TFAILIEN1 Reserved Reserved CLKEIEN TFAILIEN Reserved Bits Description [31:11] Reserved Reserved. HIRC1 Clock Error Interrupt Enable Bit This bit controls if CPU would get an interrupt while HIRC1 clock is inaccuracy during auto trim operation.
Page 124 NUC126 interrupt will be triggered to notify that HIRC0 trim value update limitation count was reached. 0 = Disable TFAILIF(SYS_IRCTSTS0[1]) status to trigger an interrupt to CPU. 1 = Enable TFAILIF(SYS_IRCTSTS0[1]) status to trigger an interrupt to CPU. Reserved Reserved. Aug.
Page 125 NUC126 HIRC Trim Interrupt Status Register (SYS_IRCTISTS) Register Offset Description Reset Value SYS_IRCTISTS SYS_BA+0x88 HIRC Trim Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved CLKERRIF1 TFAILIF1 FREQLOCK1 Reserved CLKERRIF TFAILIF FREQLOCK Bits Description [31:11] Reserved Reserved. HIRC1 Clock Error Interrupt Status When the frequency of internal USB synchronous or 48 MHz internal high speed RC oscillator 1 (HIRC1) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy...
Page 126 NUC126 Once this auto trim operation stopped FREQSEL(SYS_IRCTCL0[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL0[8]) is set to 1. If this bit is set and CLKEIEN(SYS_IRCTIEN0[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0. 0 = Clock frequency is accuracy.
Page 127 NUC126 HIRC1 Trim Control Register (SYS_IRCTCTL1) Register Offset Description Reset Value SYS_IRCTCTL1 SYS_BA+0x90 HIRC1 Trim Control Register 0x0000_0400 Reserved Reserved Reserved REFCKSEL Reserved CESTOPEN RETRYCNT LOOPSEL Reserved FREQSEL Bits Description [31:11] Reserved Reserved. Reference Clock Selection [10] REFCKSEL 0 = HIRC trim reference clock is from external 32.768 kHz crystal oscillator. 1 = HIRC trim reference clock is from internal USB synchronous mode.
Page 128 NUC126 [3:2] Reserved Reserved. Trim Frequency Selection This field indicates the target frequency of internal high speed RC oscillator 1 (HIRC 1) auto trim. During auto trim operation, if clock error detected with CESTOPEN(SYS_IRCTCTL1[8]) is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. [1:0] FREQSEL 00 = Disable HIRC1 auto trim function.
Page 129 NUC126 Register Lock Control Register (SYS_REGLCTL) Register Offset Description Reset Value SYS_REGLCTL SYS_BA+0x100 Register Lock Control Register 0x0000_0000 Reserved Reserved Reserved REGLCTL REGLCTL[0] REGLCTL Bits Description [31:8] Reserved Reserved. Register Lock Control Code (Write Only) Some registers have write-protection function. Writing these registers have to disable the [7:1] REGLCTL protected function by writing the sequence value “59h”, “16h”, “88h”...
Page 130 NUC126 CLK_CLKSEL1 [1:0]: address 0x5000_0214 (for watchdog clock source select) CLK_CLKSEL3[8]: address 0x5000_0234 (USBD Clock Source Selection) CLK_CLKDSTS: address 0x5000_0274 FMC_ISPCTL: address 0x5000_C000 (Flash ISP Control register) FMC_ISPTRG: address 0x5000_C010 (ISP Trigger Control register) FMC_ISPSTS: address 0x5000_C040 WDT_CTL: address 0x4000_4000 FMC_FTCTL: address 0x5000_C018 PWM0_CTL: address 0x4004_0000 PWM1_CTL: address 0x4014_0000...
Page 131 NUC126 TIMER3_PWMINTSTS1: address 0x4011_018C Aug. 08, 2018 Page 131 of 943 Rev 1.03...
Page 132 NUC126 Temperature Sensor Offset Register (SYS_TSOFFSET) Register Offset Description Reset Value SYS_TSOFFSE SYS_BA+0x114 Temperature Sensor Offset Register 0x0000_0XXX Reserved Reserved Reserved VTEMP[11:0] VTEMP[7:0] Bits Description [31:12] Reserved Reserved. Temperature Sensor Offset Value [11:0] VTEMP This field reflects temperature sensor output voltage offset at 25 C from flash.
Page 133: System Timer (Systick)
NUC126 6.2.13 System Timer (SysTick) ® The Cortex -M0 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear- on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter. When system timer is enabled, it will count down from the value in the SysTick Current Value Register (SYST_CVR) to 0, and reload (wrap) to the value in the SysTick Reload Value Register (SYST_RVR) on the next clock cycle, then decrement on subsequent clocks.
Page 134 NUC126 6.2.13.1 System Timer Control Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value SYST Base Address: SCS_BA = 0xE000_E000 SYST_CSR SCS_BA+0x10 SysTick Control and Status Register 0x0000_0000 SYST_RVR SCS_BA+0x14 SysTick Reload Value Register 0xXXXX_XXXX SYST_CVR SCS_BA+0x18...
Page 135 NUC126 6.2.13.2 System Timer Control Register Description SysTick Control and Status Register (SYST_CSR) Register Offset Description Reset Value SYST_CSR SCS_BA+0x10 SysTick Control and Status Register 0x0000_0000 Reserved Reserved COUNTFLAG Reserved Reserved CLKSRC TICKINT ENABLE Bits Description [31:17] Reserved Reserved. System Tick Counter Flag Returns 1 if timer counted to 0 since last time this register was read.
Page 136 NUC126 SysTick Reload Value Register (SYST_RVR) Register Offset Description Reset Value SYST_RVR SCS_BA+0x14 SysTick Reload Value Register 0xXXXX_XXXX Reserved RELOAD[23:16] RELOAD[15:8] RELOAD[7:0] Bits Description [31:24] Reserved Reserved. System Tick Reload Value [23:0] RELOAD Value to load into the Current Value register when the counter reaches 0. Aug.
Page 137 NUC126 SysTick Current Value Register (SYST_CVR) Register Offset Description Reset Value SYST_CVR SCS_BA+0x18 SysTick Current Value Register 0xXXXX_XXXX Reserved CURRENT [23:16] CURRENT [15:8] CURRENT[7:0] Bits Description [31:24] Reserved Reserved. System Tick Current Value Current counter value. This is the value of the counter at the time it is sampled. The [23:0] CURRENT counter does not provide read-modify-write protection.
Page 138: Nested Vectored Interrupt Controller (Nvic)
NUC126 6.2.14 Nested Vectored Interrupt Controller (NVIC) ® The Cortex -M0 provides an interrupt controller as an integral part of the exception mode, named as “Nested Vectored Interrupt Controller (NVIC)”, which is closely coupled to the processor kernel and provides following features: ...
Page 139: Table 6.2-6 Exception Model
NUC126 (Vector Number)*4 Table 6.2-6 Exception Model Interrupt Number Vector Interrupt Name Interrupt Description (Bit Interrupt Number Registers) 0 ~ 15 System exceptions BOD_INT Brown-out low voltage detected interrupt WDT_INT Window Watchdog Timer interrupt EINT024 External interrupt from PA.0/PC.0/PD.2/PE.0/PE.4 pin EINT135 External interrupt from PB.0/PC.0/ PD.0/PD.3/PE.5/PF.0 pin GPAB_INT...
Page 140: Table 6.2-7 Interrupt Number Table
NUC126 ADC_INT ADC interrupt Clock fail detect and IRC TRIM interrupt CLKDIRC_INT RTC_INT Real Time Clock interrupt Table 6.2-7 Interrupt Number Table 6.2.14.2 Operation Description NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-Enable or Interrupt Clear-Enable register bit-field.
Page 141 NUC126 6.2.14.3 NVIC Control Registers R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value NVIC Base Address: SCS_BA = 0xE000_E000 NVIC_ISER SCS_BA+0x100 IRQ0 ~ IRQ31 Set-Enable Control Register 0x0000_0000 NVIC_ICER SCS_BA+0x180 IRQ0 ~ IRQ31 Clear-Enable Control Register 0x0000_0000 NVIC_ISPR SCS_BA+0x200...
Page 142 NUC126 IRQ0 ~ IRQ31 Set-Enable Control Register (NVIC_ISER) Register Offset Description Reset Value NVIC_ISER SCS_BA+0x100 IRQ0 ~ IRQ31 Set-Enable Control Register 0x0000_0000 SETENA SETENA SETENA SETENA Bits Description Interrupt Enable Register Enable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).
Page 143 NUC126 IRQ0 ~ IRQ31 Clear-Enable Control Register (NVIC_ICER) Register Offset Description Reset Value NVIC_ICER SCS_BA+0x180 IRQ0 ~ IRQ31 Clear-Enable Control Register 0x0000_0000 CLRENA CLRENA CLRENA CLRENA Bits Description Interrupt Disable Bits Disable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).
Page 144 NUC126 IRQ0 ~ IRQ31 Set-Pending Control Register (NVIC_ISPR) Register Offset Description Reset Value NVIC_ISPR SCS_BA+0x200 IRQ0 ~ IRQ31 Set-Pending Control Register 0x0000_0000 SETPEND SETPEN SETPEND SETPEND Bits Description Set Interrupt Pending Bits Write Operation: 0 = No effect. 1 = Write 1 to set pending state. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).
Page 145 NUC126 IRQ0 ~ IRQ31 Clear-Pending Control Register (NVIC_ICPR) Register Offset Description Reset Value NVIC_ICPR SCS_BA+0x280 IRQ0 ~ IRQ31 Clear-Pending Control Register 0x0000_0000 CLRPEND CLRPEND CLRPEND CLRPEND Bits Description Clear Interrupt Pending Bits Write Operation: 0 = No effect. 1 = Write 1 to clear pending state. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).
Page 146 NUC126 IRQ0 ~ IRQ3 Priority Register (NVIC_IPR0) Register Offset Description Reset Value NVIC_IPR0 SCS_BA+0x400 IRQ0 ~ IRQ3 Priority Control Register 0x0000_0000 PRI_3 Reserved PRI_2 Reserved PRI_1 Reserved PRI_0 Reserved Bits Description Priority of IRQ3 [31:30] PRI_3 “0” denotes the highest priority and “3” denotes the lowest priority. Reserved [29:24] Reserved.
Page 147 NUC126 IRQ4 ~ IRQ7 Priority Register (NVIC_IPR1) Register Offset Description Reset Value NVIC_IPR1 SCS_BA+0x404 IRQ4 ~ IRQ7 Priority Control Register 0x0000_0000 PRI_7 Reserved PRI_6 Reserved PRI_5 Reserved PRI_4 Reserved Bits Description Priority of IRQ7 [31:30] PRI_7 “0” denotes the highest priority and “3” denotes the lowest priority. Reserved [29:24] Reserved.
Page 148 NUC126 IRQ8 ~ IRQ11 Priority Register (NVIC_IPR2) Register Offset Description Reset Value NVIC_IPR2 SCS_BA+0x408 IRQ8 ~ IRQ11 Priority Control Register 0x0000_0000 PRI_11 Reserved PRI_10 Reserved PRI_9 Reserved PRI_8 Reserved Bits Description Priority of IRQ11 [31:30] PRI_11 “0” denotes the highest priority and “3” denotes the lowest priority. [29:24] Reserved Reserved.
Page 149 NUC126 IRQ12 ~ IRQ15 Priority Register (NVIC_IPR3) Register Offset Description Reset Value NVIC_IPR3 SCS_BA+0x40C IRQ12 ~ IRQ15 Priority Control Register 0x0000_0000 PRI_15 Reserved PRI_14 Reserved PRI_13 Reserved PRI_12 Reserved Bits Description Priority of IRQ15 [31:30] PRI_15 “0” denotes the highest priority and “3” denotes the lowest priority. [29:24] Reserved Reserved.
Page 150 NUC126 IRQ16 ~ IRQ19 Priority Register (NVIC_IPR4) Register Offset Description Reset Value NVIC_IPR4 SCS_BA+0x410 IRQ16 ~ IRQ19 Priority Control Register 0x0000_0000 PRI_19 Reserved PRI_18 Reserved PRI_17 Reserved PRI_16 Reserved Bits Description Priority of IRQ19 [31:30] PRI_19 “0” denotes the highest priority and “3” denotes the lowest priority. [29:24] Reserved Reserved.
Page 151 NUC126 IRQ20 ~ IRQ23 Priority Register (NVIC_IPR5) Register Offset Description Reset Value NVIC_IPR5 SCS_BA+0x414 IRQ20 ~ IRQ23 Priority Control Register 0x0000_0000 PRI_23 Reserved PRI_22 Reserved PRI_21 Reserved PRI_20 Reserved Bits Description Priority of IRQ23 [31:30] PRI_23 “0” denotes the highest priority and “3” denotes the lowest priority. [29:24] Reserved Reserved.
Page 152 NUC126 IRQ24 ~ IRQ27 Priority Register (NVIC_IPR6) Register Offset Description Reset Value NVIC_IPR6 SCS_BA+0x418 IRQ24 ~ IRQ27 Priority Control Register 0x0000_0000 PRI_27 Reserved PRI_26 Reserved PRI_25 Reserved PRI_24 Reserved Bits Description Priority of IRQ27 [31:30] PRI_27 “0” denotes the highest priority and “3” denotes the lowest priority. [29:24] Reserved Reserved.
Page 153 NUC126 IRQ28 ~ IRQ31 Priority Register (NVIC_IPR7) Register Offset Description Reset Value NVIC_IPR7 SCS_BA+0x41C IRQ28 ~ IRQ31 Priority Control Register 0x0000_0000 PRI_31 Reserved PRI_30 Reserved PRI_29 Reserved PRI_28 Reserved Bits Description Priority of IRQ31 [31:30] PRI_31 “0” denotes the highest priority and “3” denotes the lowest priority. [29:24] Reserved Reserved.
Page 154 NUC126 6.2.14.4 Interrupt Source Register Map Besides the interrupt control registers associated with the NVIC, the NUC126 series also implement some specific control registers to facilitate the interrupt functions, including “interrupt source identification”, ”NMI source selection” and “interrupt test mode”, which are described below. R: read only, W: write only, R/W: both read and write Register Offset...
Page 155 NUC126 IRQ25_SRC INT_BA+0x64 IRQ25 (ACMP) Interrupt Source Identity 0xXXXX_XXXX IRQ26_SRC INT_BA+0x68 IRQ26 (PDMA) Interrupt Source Identity 0xXXXX_XXXX IRQ27_SRC INT_BA+0x6C Reserved 0xXXXX_XXXX IRQ28_SRC INT_BA+0x70 IRQ28 (PWRWU) Interrupt Source Identity 0xXXXX_XXXX IRQ29_SRC INT_BA+0x74 IRQ29 (ADC) Interrupt Source Identity 0xXXXX_XXXX IRQ30_SRC INT_BA+0x78 IRQ30 (IRC/CLKD) Interrupt Source Identity 0xXXXX_XXXX IRQ31_SRC INT_BA+0x7C...
Page 156 NUC126 6.2.14.5 Interrupt Source Register Description Interrupt Source Identity Register (IRQn_SRC) Register Offset Description Reset Value IRQ0_SRC INT_BA+0x00 IRQ0 (BOD) Interrupt Source Identity 0xXXXX_XXXX IRQ1_SRC INT_BA+0x04 IRQ1 (WDT) Interrupt Source Identity 0xXXXX_XXXX IRQ2_SRC INT_BA+0x08 IRQ2 (EINT0/2/4) Interrupt Source Identity 0xXXXX_XXXX IRQ3_SRC INT_BA+0x0C IRQ3 (EINT1/3/5) Interrupt Source Identity...
Page 157 NUC126 IRQ28_SRC INT_BA+0x70 IRQ28 (PWRWU) Interrupt Source Identity 0xXXXX_XXXX IRQ29_SRC INT_BA+0x74 IRQ29 (ADC) Interrupt Source Identity 0xXXXX_XXXX IRQ30_SRC INT_BA+0x78 IRQ30 (IRC/CLKD) Interrupt Source Identity 0xXXXX_XXXX IRQ31_SRC INT_BA+0x7C IRQ31 (RTC) Interrupt Source Identity 0xXXXX_XXXX Reserved Reserved Reserved Reserved INT_SRC Bits Description [31:4] Reserved Reserved.
Page 158 NUC126 Bit0: GPC_INT Bit2: 0 [3:0] INT_BA+0x18 Bit1: BRAKE0_INT Bit0: PWM0_INT Bit2: 0 [2:0] INT_BA+0x1C Bit1: BRAKE1_INT Bit0: PWM1_INT Bit2: 0 [2:0] INT_BA+0x20 Bit1: 0 Bit0: TMR0_INT Bit2: 0 [2:0] INT_BA+0x24 Bit1: 0 Bit0: TMR1_INT Bit2: 0 [2:0] INT_BA+0x28 Bit1: 0 Bit0: TMR2_INT Bit2: 0 [2:0]...
Page 159 NUC126 Bit1: 0 Bit0: USBD_INT Bit2: 0 [2:0] INT_BA+0x60 Bit1: SMC1_INT Bit0: SMC0_INT Bit2: 0 [2:0] INT_BA+0x64 Bit1: 0 Bit0: ACMP_INT Bit2: 0 [2:0] INT_BA+0x68 Bit1: 0 Bit0: PDMA_INT [2:0] INT_BA+0x6C Reserved Bit2: 0 [2:0] INT_BA+0x70 Bit1: 0 Bit0: PWRWU_INT Bit2: 0 Bit1: 0 [2:0]...
Page 160 NUC126 NMI Source Interrupt Select Control Register (NMI_SEL) Register Offset Description Reset Value NMI_SEL INT_BA+0x80 NMI Source Interrupt Select Control Register 0x0000_0000 Reserved Reserved Reserved NMI_EN Reserved NMI_SEL Bits Description [31:8] Reserved Reserved. NMI Interrupt Enable Bit (Write Protect) 0 = NMI interrupt Disabled. NMI_EN 1 = NMI interrupt Enabled.
Page 161: System Control
NUC126 6.2.15 System Control ® The Cortex -M0 status and operating mode control are managed by System Control Registers. ® ® Including CPUID, Cortex -M0 interrupt priority and Cortex -M0 power management can be controlled through these system control registers. ®...
Page 162 NUC126 6.2.15.2 System Control Register Description CPUID Register (CPUID) Register Offset Description Reset Value CPUID SCS_BA+0xD00 CPUID Register 0x410C_C200 IMPLEMENTER[7:0] Reserved PART[3:0] PARTNO[11:4] PARTNO[3:0] REVISION[3:0] Bits Description Implementer Code Assigned by ARM IMPLEMENTER [31:24] Implementer code assigned by ARM. (ARM = 0x41). [23:20] Reserved Reserved.
Page 163 NUC126 Interrupt Control State Register (ICSR) Register Offset Description Reset Value ICSR SCS_BA+0xD04 Interrupt Control and State Register 0x0000_0000 NMIPENDSET Reserved PENDSVSET PENDSVCLR PENDSTSET PENDSTCLR Reserved ISRPREEMPT ISRPENDING Reserved VECTPENDING[5:4] VECTPENDING[3:0] Reserved Reserved VECTACTIVE[5:0] Bits Description NMI Set-pending Bit Write Operation: 0 = No effect.
Page 164 NUC126 0 = No effect. 1 = Changes SysTick exception state to pending. Read Operation: 0 = SysTick exception is not pending. 1 = SysTick exception is pending. SysTick Exception Clear-pending Bit Write Operation: 0 = No effect. PENDSTCLR [25] 1 = Removes the pending state from the SysTick exception.
Page 165 NUC126 Application Interrupt and Reset Control Register (AIRCR) Register Offset Description Reset Value AIRCR SCS_BA+0xD0C Application Interrupt and Reset Control Register 0xFA05_0000 VECTORKEY[15:8] VECTORKEY[7:0] Reserved Reserved SYSRESETRE VECTCLRAC Reserved TIVE Bits Description Register Access Key Write Operation: When writing to this register, the VECTORKEY field need to be set to 0x05FA, otherwise [31:16] VECTORKEY the write operation would be ignored.
Page 166 NUC126 System Control Register (SCR) Register Offset Description Reset Value SCS_BA+0xD10 System Control Register 0x0000_0000 Reserved Reserved Reserved Reserved SEVONPEND Reserved SLEEPDEEP SLEEPONEXIT Reserved Bits Description [31:5] Reserved Reserved. Send Event on Pending Bit 0 = Only enabled interrupts or events can wake-up the processor, disabled interrupts are excluded.
Page 167 NUC126 System Handler Priority Register 2 (SHPR2) Register Offset Description Reset Value SHPR2 SCS_BA+0xD1C System Handler Priority Register 2 0x0000_0000 PRI_11 Reserved Reserved Reserved Reserved Bits Description Priority of System Handler 11 – SVCall [31:30] PRI_11 “0” denotes the highest priority and “3” denotes the lowest priority [29:0] Reserved Reserved.
Page 168 NUC126 System Handler Priority Register 3 (SHPR3) Register Offset Description Reset Value SHPR3 SCS_BA+0xD20 System Handler Priority Register 3 0x0000_0000 PRI_15 Reserved PRI_14 Reserved Reserved Reserved Bits Description Priority of System Handler 15 – SysTick [31:30] PRI_15 “0” denotes the highest priority and “3” denotes the lowest priority [29:24] Reserved Reserved.
Page 169: Clock Controller
NUC126 Clock Controller 6.3.1 Overview The clock controller generates clocks for the whole chip, including system clocks and all peripheral clocks. The clock controller also implements the power control function with the individually clock ON/OFF control, clock source selection and a clock divider. The chip will not enter Power-down mode ®...
Page 170: Figure 6.3-1 Clock Generator Block Diagram
NUC126 LXTEN (CLK_PWRCTL[1]) X32_IN External 32.768 kHz Crystal (LXT) X32_OUT HXTEN (CLK_PWRCTL[0]) XT1_IN External 4~24 PLLSRC (CLK_PLLCTL[19]) MHz Crystal (HXT) XT1_OUT PLL FOUT HIRCEN (CLK_PWRCTL[2]) Internal 22.1184 MHz Oscillator (HIRC) HIRC LIRCEN(CLK_PWRCTL[3]) Internal10 KHz LIRC Oscillator (LIRC) LIRCEN(CLK_PWRCTL[13]) Internal 48 MHz HIRC48 Oscillator (HIRC48)
Page 171: Figure 6.3-2 Clock Generator Global View Diagram
NUC126 48 MHz CPUCLK 48 MHz 48 MHz 22.1184 22.1184 MHz 22.1184 MHz 10 kHz 10 kHz 1/(HCLKDIV+1) PDMA HCLK 4~24 PLLFOUT PLLFOUT CLK_CLKSEL0[6] 32.768 kHz 32.768 kHz HDIV I2C0 32.768 4~24 MHz 4~24 MHz PCLK0 ACMP CLK_CLKSEL0[2:0] USCI0/2 USCI1 10 kHz I2C1 PCLK1...
Page 172: System Clock And Systick Clock
NUC126 6.3.2 System Clock and SysTick Clock The system clock has 6 clock sources, which were generated from clock generator block. The clock source switch depends on the register HCLKSEL (CLK_CLKSEL0 [2:0]). The block diagram is shown in Figure 6.3-3. HCLKSEL (CLK_CLKSEL0[2:0]) HIRC LIRC...
Page 173: Peripherals Clock
NUC126 Set HXTFDEN To enable HXT clock detector HXTFIF = 1? System clock source = System clock keep “HXT” or “PLL with original clock HXT” ? Switch system clock to HIRC Figure 6.3-4 HXT Stop Protect Procedure ® The clock source of SysTick in Cortex -M0 core can use CPU clock or external clock (SYST_CSR[2]).
Page 174: Power-Down Mode Clock
NUC126 6.3.4 Power-down Mode Clock When entering Power-down mode, system clocks, some clock sources, and some peripheral clocks are disabled. Some clock sources and peripherals clock are still active in Power-down mode. For theses clocks, which still keep active, are listed below: ...
Page 175: Figure 6.3-7 Clock Output Block Diagram
NUC126 CLKOEN (CLK_CLKOCTL[4]) Enable FREQSEL divide-by-2 counter 16 chained (CLK_CLKOCTL[3:0]) divide-by-2 counter DIV1EN CLKO_CLK (CLK_CLKOCTL[5]) …... CLK1HZEN 0000 (CLK_CLKOCTL[6]) 0001 16 to 1 1110 CLKO 1111 RTCSEL(CLK_CLKSEL2[18]) LIRC 1 Hz clock from RTC /32768 Figure 6.3-7 Clock Output Block Diagram Aug.
Page 176: Register Map
NUC126 6.3.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value CLK Base Address: CLK_BA = 0x5000_0200 CLK_PWRCTL CLK_BA+0x00 System Power-down Control Register 0x0000_1C1X CLK_AHBCLK CLK_BA+0x04 AHB Devices Clock Enable Control Register 0x003F_8004 CLK_APBCLK0 CLK_BA+0x08 APB Devices Clock Enable Control Register 0...
Page 177: Register Description
NUC126 6.3.7 Register Description System Power-down Control Register (CLK_PWRCTL) Register Offset Description Reset Value CLK_PWRCT CLK_BA+0x00 System Power-down Control Register 0x0000_1C1X Reserved Reserved Reserved HIRC48EN HXTSELTYP HXTGAIN Reserved PDEN PDWKIF PDWKIEN PDWKDLY LIRCEN HIRCEN LXTEN HXTEN Bits Description [31:14] Reserved Reserved.
Page 178 NUC126 In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC. 0 = Chip operating normally or chip in idle mode because of WFI command. 1 = Chip waits CPU sleep command WFI and then enters Power-down mode.
Page 179: Table 6.3-2 Power-Down Mode Control Table
NUC126 [7]) Normal operation All clocks are disabled by control register. Idle mode Only CPU clock is disabled. (CPU enter Sleep mode) Power-down mode Most clocks are disabled except LIRC/LXT, and only RTC/WDT/Timer/UART peripheral clocks (CPU enters Deep still enable if their clock sources are selected as Sleep mode) LIRC/LXT..
Page 180 NUC126 AHB Devices Clock Enable Control Register (CLK_AHBCLK) The bits in this register are used to enable/disable clock for system clock, AHB bus devices clock. Register Offset Description Reset Value CLK_AHBCL CLK_BA+0x04 AHB Devices Clock Enable Control Register 0x003F_8004 Reserved Reserved GPIOFCKEN GPIOECKEN...
Page 181 NUC126 CRC Generator Controller Clock Enable Bit CRCCKEN 0 = CRC peripheral clock Disabled. 1 = CRC peripheral clock Enabled. Reserved [6:5] Reserved. HDIVCKEN Hardware Divider Controller Clock Enable Bit 0 = Hardware divider peripheral clock Disabled. 1 = Hardware divider peripheral clock Enabled. EBI Controller Clock Enable Bit EBICKEN 0 = EBI peripheral clock Disabled.
Page 182 NUC126 APB Devices Clock Enable Control Register 0 (CLK_APBCLK0) The bits in this register are used to enable/disable clock for peripheral controller clocks. Register Offset Description Reset Value CLK_APBCLK0 CLK_BA+0x08 APB Devices Clock Enable Control Register 0 0x0000_0001 Reserved ACMP01CKE Reserved ADCCKEN USBDCKEN...
Page 183 NUC126 0 = UART1 clock Disabled. 1 = UART1 clock Enabled. UART0 Clock Enable Bit [16] UART0CKEN 0 = UART0 clock Disabled. 1 = UART0 clock Enabled. [15:14] Reserved Reserved. SPI1 Clock Enable Bit [13] SPI1CKEN 0 = SPI1 Clock Disabled. 1 = SPI1 Clock Enabled.
Page 184 NUC126 Note: This bit is write protected. Refer to the SYS_REGLCTL register. Aug. 08, 2018 Page 184 of 943 Rev 1.03...
Page 185 NUC126 APB Devices Clock Enable Control Register 1 (CLK_APBCLK1) The bits in this register are used to enable/disable clock for peripheral controller clocks. Register Offset Description Reset Value CLK_APBCL CLK_BA+0x30 APB Devices Clock Enable Control Register 1 0x0000_0000 Reserved Reserved Reserved USCI2CKEN USCI1CKEN...
Page 186 NUC126 Clock Source Select Control Register 0 (CLK_CLKSEL0) Register Offset Description Reset Value CLK_CLKSEL CLK_BA+0x10 Clock Source Select Control Register 0 0x0000_003X Reserved Reserved Reserved PCLK1SEL PCLK0SEL STCLKSEL HCLKSEL Bits Description [31:8] Reserved Reserved. PCLK1 Clock Source Selection (Write Protect) 0 = APB1 BUS clock source from HCLK.
Page 187 NUC126 011 = Clock source from LIRC. 100 = Clock source from HIRC48. 111= Clock source from HIRC clock. Other = Reserved. Note: These bits are write protected. Refer to the SYS_REGLCTL register. Aug. 08, 2018 Page 187 of 943 Rev 1.03...
Page 188 NUC126 Clock Source Select Control Register 1 (CLK_CLKSEL1) Before clock switching, the related clock sources (pre-selected and newly-selected) must be turned on. Register Offset Description Reset Value CLK_CLKSEL CLK_BA+0x14 Clock Source Select Control Register 1 0x3377_770F Reserved PWM1SEL PWM0SEL Reserved UARTSEL Reserved TMR3SEL...
Page 189 NUC126 [19] Reserved Reserved. TIMER2 Clock Source Selection 000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT) clock. 001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT) clock. 010 = Clock source from PCLK1. [18:16] TMR2SEL 011 = Clock source from external clock T2 pin.
Page 190 NUC126 Clock Source Select Control Register 2 (CLK_CLKSEL2) Before clock switching, the related clock sources (pre-select and new-select) must be turned on. Register Offset Description Reset Value CLK_CLKSEL CLK_BA+0x1C Clock Source Select Control Register 2 0x0002_0008 Reserved SPI1SEL SPI0SEL Reserved RTCSEL WWDTSEL Reserved...
Page 191 NUC126 011 = Clock source from 22.1184 MHz internal high speed RC oscillator (HIRC) clock. 101 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48) clock. Others = Reserved. [1:0] Reserved Reserved. Aug. 08, 2018 Page 191 of 943 Rev 1.03...
Page 192 NUC126 Clock Source Select Control Register 3 (CLK_CLKSEL3) Before clock switching, the related clock sources (pre-select and new-select) must be turned on. Register Offset Description Reset Value CLK_CLKSEL CLK_BA+0x34 Clock Source Select Control Register 3 0x0000_0000 Reserved Reserved Reserved USBDSEL Reserved SC1SEL SC0SEL...
Page 193 NUC126 Clock Divider Number Register 0 (CLK_CLKDIV0) Register Offset Description Reset Value CLK_CLKDIV0 CLK_BA+0x18 Clock Divider Number Register 0 0x0000_0000 Reserved ADCDIV Reserved UARTDIV USBDIV HCLKDIV Bits Description [31:24] Reserved Reserved. ADC Clock Divide Number From ADC Clock Source ADCDIV [23:16] ADC clock frequency = (ADC clock source frequency) / (ADCDIV + 1).
Page 194 NUC126 Clock Divider Number Register 1 (CLK_CLKDIV1) Register Offset Description Reset Value CLK_CLKDIV1 CLK_BA+0x38 Clock Divider Number Register 1 0x0000_0000 Reserved Reserved SC1DIV SC0DIV Bits Description [31:16] Reserved Reserved. SC1 Clock Divide Number From SC1 Clock Source SC1DIV [15:8] SC1 clock frequency = (SC1 clock source frequency ) / (SC1DIV + 1). SC0 Clock Divide Number From SC0 Clock Source [7:0] SC0DIV...
Page 195 NUC126 PLL Control Register (CLK_PLLCTL) The PLL reference clock input is from the 4~24 MHz external high speed crystal oscillator (HXT) clock input or from the 22.1184 MHz internal high speed RC oscillator (HIRC). This register is used to control the PLL output frequency and PLL operation mode.
Page 196 NUC126 Refer to the formulas below the table. PLL Feedback Divider Control [8:0] FBDIV Refer to the formulas below the table. Output Clock Frequency Setting    FOUT Constraint:         preferred Symbol Description FOUT Output Clock Frequency...
Page 197 NUC126 Clock Status Monitor Register (CLK_STATUS) The bits in this register are used to monitor if the chip clock source is stable or not, and whether the clock switch is failed. Register Offset Description Reset Value CLK_STATUS CLK_BA+0x0C R Clock Status Monitor Register 0x0000_00XX Reserved Reserved...
Page 198 NUC126 HXT Clock Source Stable Flag (Read Only) HXTSTB 0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled. 1 = 4~24 MHz external high speed crystal oscillator (HXT)clock is stable and enabled. Aug. 08, 2018 Page 198 of 943 Rev 1.03...
Page 199 NUC126 Clock Output Control Register (CLK_CLKOCTL) Register Offset Description Reset Value CLK_CLKOC CLK_BA+0x24 Clock Output Control Register 0x0000_0000 Reserved Reserved Reserved Reserved CLK1HZEN DIV1EN CLKOEN FREQSEL Bits Description [31:7] Reserved Reserved. Clock Output 1Hz Enable Bit 0 = 1 Hz clock output for 32.768 kHz external low speed crystal oscillator (LXT) frequency CLK1HZEN compensation Disabled.
Page 200 NUC126 Clock Source Select for BOD Control Register (CLK_BODCLK) Register Offset Description Reset Value CLK_BODCL CLK_BA+0x40 Clock Source Select for BOD Control Register 0x0000_0000 Reserved Reserved Reserved Reserved VDETCKSEL Bits Description [31:1] Reserved Reserved. Clock Source Selection for Voltage Detector The Voltage Detector clock source for detecting external input voltage is defined by VDETCKSEL.
Page 201 NUC126 Clock Fail Detector Control Register (CLK_CLKDCTL) Register Offset Description Reset Value CLK_CLKDCTL CLK_BA+0x70 Clock Fail Detector Control Register 0x0000_0000 Reserved Reserved HXTFQIEN HXTFQDEN Reserved LXTFIEN LXTFDEN Reserved Reserved HXTFIEN HXTFDEN Reserved Bits Description [31:18] Reserved Reserved. HXT Clock Frequency Monitor Interrupt Enable Bit 0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail [17] HXTFQIEN...
Page 202 NUC126 Clock Fail Detector Status Register (CLK_CLKDSTS) Register Offset Description Reset Value CLK_CLKDST CLK_BA+0x74 Clock Fail Detector Status Register 0x0000_0000 Reserved Reserved Reserved HXTFQIF Reserved LXTFIF HXTFIF Bits Description Reserved [31:9] Reserved. HXT Clock Frequency Monitor Interrupt Flag (Write Protect) 0 = 4~24 MHz external high speed crystal oscillator (HXT) clock normal.
Page 203 NUC126 Clock Frequency Detector Upper Boundary Register (CLK_CDUPB) Register Offset Description Reset Value CLK_CDUPB CLK_BA+0x78 Clock Frequency Detector Upper Boundary Register 0x0000_0000 Reserved Reserved Reserved UPERBD UPERBD Bits Description [31:10] Reserved Reserved. HXT Clock Frequency Detector Upper Boundary The bits define the high value of frequency monitor window. [9:0] UPERBD When HXT frequency monitor value higher than this register, the HXT frequency detect fail...
Page 204 NUC126 Clock Frequency Detector Low Boundary Register (CLK_CDLOWB) Register Offset Description Reset Value CLK_CDLOWB CLK_BA+0x7c Clock Frequency Detector Low Boundary Register 0x0000_0000 Reserved Reserved Reserved LOWERBD[9:8] LOWERBD Bits Description [31:10] Reserved Reserved. HXT Clock Frequency Detector Low Boundary The bits define the low value of frequency monitor window. [9:0] LOWERBD When HXT frequency monitor value lower than this register, the HXT frequency detect fail...
Page 205: Flash Memeory Controller (Fmc)
NUC126 Flash Memeory Controller (FMC) 6.4.1 Overview The NUC126 series is equipped with 128/256 Kbytes on-chip embedded flash for application and configurable Data Flash to store some application dependent data. A User Configuration block provides for system initiation. A 4 Kbytes loader ROM (LDROM) is used for In-System-Programming (ISP) function.
Page 206: Block Diagram
NUC126 6.4.3 Block Diagram The flash memory controller (FMC) consists of AHB slave interface, cache memory controller, flash control registers, flash initialization controller, flash operation control and embedded flash memory. The block diagram of flash memory controller is shown as follows. Cortex-M0 AHB-BUS Flash Memory Controller AHB Slave Interface...
Page 207: Functional Description
NUC126 All of ISP control and status registers are in the flash control registers. The detail registers description is in the Register Description section Flash Initialization Controller When chip is powered on or active from reset, the flash initialization controller will start to access flash automatically and check the flash stability, and also reload User Configuration content to the flash control registers for system initiation.
Page 208: Figure 6.4-2 Data Flash
NUC126 0x0003_FFFF Data Flash DFBA 0x0001_FFFF Data Flash ApplicationROM DFBA (APROM) ApplicationROM (APROM) 0x0000_0000 APROM 128KB APROM 256KB Device Device Figure 6.4-2 Data Flash Aug. 08, 2018 Page 208 of 943 Rev 1.03...
Page 209 NUC126 User Configuration Block User Configuration block is internal programmable configuration area for boot options, such as flash security lock, boot select, brown-out voltage level, and Data Flash base address. It works like a fuse for power on setting. It is loaded from flash memory to its corresponding control registers during chip power on.
Page 210 NUC126 PF[4:3] Multi-Function Select If user don’t need HXT in his application, he can use CFGXT1 to change PF[4:3] power on default to GPIO to avoid the effect of crystal oscillator circuite. [27] CFGXT1 0 = PF[4:3] pins are configured as GPIO pins. 1 = PF[4:3] pins are configured as external 4~24 MHz external high speed crystal oscillator (HXT) pins.
Page 211 NUC126 Chip Booting Selection When CBS[0] = 0, the LDROM base address is mapping to 0x100000 and APROM base address is mapping to 0x0. User could access both APROM and LDROM without boot switching. In other words, if IAP mode is supported, the code in LDROM and APROM can be called by each other.
Page 212 NUC126 CONFIG1 (Address = 0x0030_0004) Reserved Reserved DFBA DFBA DFBA Bits Descriptions [31:20] Reserved Reserved. Data Flash Base Address This register works only when DFEN (CONFIG0[0])set to 0. If DFEN (CONFIG0[0]) is set [19:0] DFBA to 0, the Data Flash base address is defined by user. Since on-chip flash erase unit is 2 Kbytes, it is mandatory to keep bit 10-0 as 0.
Page 213: Figure 6.4-3 Sprom Security Mode
NUC126 Security Protection Memory (SPROM) The security protection memory (SPROM) is a special flash memory area for security applications. It supports independent lock machnism which is different to sercurity function of LOCK (CONFIG0[1]). In other words, user can lock SPROM without lock whole flash memory. This make it is possible for user to only protect their security key or key function in SPROM without lock all flash memory.
Page 214: Figure 6.4-4 Flash Memory Map
NUC126 0x0. User cannot debug code in secred mode because it is forbidden to set breakpoint or step into SPROM. However, the code in SPROM still could work as usual by free running. The SCODE (FMC_ISPSTS[31]) is SPROM secured flag. If the flag is 1, it means SPROM is in secured mode or debug mode.
Page 215: Figure 6.4-5 System Memory Map With Iap Mode
NUC126 System Memory Map with IAP Mode The system memory map is used by CPU to fetch code or data from flash memory. In IAP mode, CPU can read and execute the code from APROM and LDROM. It also supports to call the funcitons in LDROM from APROM or call the funciton in APROM from LDROM.
Page 216: Figure 6.4-6 Aprom/Ldrom Boot With Iap Mode
NUC126 reset, the stack pointer and reset hander in LDROM vector table are used to reboot the system. This is so called boot from LDROM. LDROM LDROM LDROM 0x0010_0000 Application ROM Application ROM Application ROM (APROM) (APROM) (APROM) 0x0000_0200 Vector Table of APROM Vector Table of LDROM Vector Map Space (0 ~ 0x1FF)
Page 217: Figure 6.4-8 System Memory Map Without Iap Mode
NUC126 System Memory Map without IAP mode In system memory map without IAP mode, the system memory vector mapping is not supported. There are two kinds of system memory map without IAP mode when chip booting. One is LDROM without IAP, the other one is APROM without IAP.
Page 218: Table 6.4-1 Boot Source Selection Table
NUC126 APROM without IAP Table 6.4-1 Boot Source Selection Table 6.4.4.3 In-Application-Programming (IAP) The NUC126 Series provides In-Application-Programming (IAP) mode for user to switch the code executing between APROM, LDROM and SPROM. User can enable the IAP mode by booting chip and setting the chip boot selection bits in CBS (CONFIG0[7:6]) as 10 or 00.
Page 219: Table 6.4-2 Isp Command List
NUC126 FMC_ISPDAT: N/A FMC_MPDAT0: 1’st Programming Data FMC_MPDAT1: 2’nd Valid address of flash memory organization. It must FLASH Multi-Word Program 0x27 Programming Data be 64-bit alignment. FMC_MPDAT2: 3’rd Programming Data FMC_MPDAT3: 4’th Programming Data FMC_ISPDAT: Return Data Valid address of flash memory organization. It must FLASH 32-bit Read 0x00 FMC_MPDAT0~FMC_MPDAT3:...
Page 220: Figure 6.4-9 Isp Procedure Example
NUC126 control bits of FMC control register are write-protected, thus it is necessary to unlock before setting. After unlocking the protected register bits, user needs to set the FMC_ISPCTL control register to decide to update LDROM, APROM, SPROM or user configuration block, and then set ISPEN (FMC_ISPCTL[0]) to enable ISP function.
Page 221: Figure 6.4-10 Example For Accelerating Interrupt By Vecmap
NUC126 ISB (Instruction Synchronization Barrier) instruction next to the instruction in which ISPGO (FMC_ISPTRG[0]) bit is set 1 to ensure correct execution of the instructions following ISP operation. 6.4.4.5 VECMAP for Interrupt and Memory Programming Accelerate Interrupt by VECMAP In IAP mode, VECMAP function could be used to map 512 bytes SRAM to vector map space. It means it is possible to store all exception vectors to SRAM.
Page 222: Figure 6.4-11 Isp 32-Bit Programming Procedure
NUC126 FMC_ISPCMD ISP CMD Register 0x21 0x61 0x27    FMC_ISPTRG ISP Trigger Register   FMC_ISPSTS ISP Status Register   FMC_MPDAT0 ISP Data0 Register   FMC_MPDAT1 ISP Data1 Register  FMC_MPDAT2 ISP Data2 Register  FMC_MPDAT3 ISP Data3 Register ...
Page 223: Figure 6.4-12 Isp 64-Bit Programming Procedure
NUC126 Start Enable ISPEN Write FMC_ISPADDR Write FMC_ISPCMD End of Flash Operation Write FMC_MPDAT0 Write FMC_MPDAT1 Check ISPFF = 1? Set ISPGO = 1 Add ISB instruction End of ISP Operation Check ISPGO = 0 Stop Figure 6.4-12 ISP 64-bit Programming Procedure Multi-word Programming The NUC126 series supports multi-word programming function to speed up flash updated procedure.
Page 224: Figure 6.4-13 Firmware In Sram For Multi-Word Programming
NUC126 SRAM Multi-Word Programming Code Vector Table 0x2000_0000 Program APROM Remap vector map to avoid flash access by exceptions when doing ISP APROM Programming Space 0x0000_01FF Vector Map Space 0x0000_0000 Figure 6.4-13 Firmware in SRAM for Multi-word Programming The multi-word programming flow is shown as bellow. The starting ISP address (FMC_ISPADDR) has to be 8-byte align.
Page 225: Figure 6.4-14 Multi-Word Programming Flow
NUC126 Start Enable ISPEN Write FMC_ISPADDR Write FMC_MPDAT0 Write FMC_MPDAT1 Write FMC_MPDAT2 Write FMC_MPDAT3 Set ISPGO = 1 Programming Finish? Read FMC_MPSTS Read FMC_MPSTS Read FMC_MPADDR Check MPBUSY==0? (D1,D0)=00? MPBUSY == 0? Write FMC_MPDAT0 Write FMC_MPDAT1 End of ISP Operation? Read FMC_MPSTS Multi-Word Programming...
Page 226: Figure 6.4-15 Crc-32 Checksum Calculation
NUC126 6.4.4.7 CRC-32 Checksum Calculation The NUC126 series supports the Cyclic Redundancy Check (CRC) generator to perform CRC-32 checksum calculation, and help user quickly check the memory content includes APROM, LDROM and SPROM. The CRC-32 polynomial is CRC-32: X + X + 1 With seed = 0xFFFF_FFFF Din[31:0] Din[0]...
Page 227: Figure 6.4-16 Crc-32 Checksum Calculation Flow
NUC126 Checksum Calculation Start Step 1 Step 2 Enable ISPEN Write FMC_ISPADDR Write FMC_ISPDAT Write FMC_ISPCMD (0x0D) Write FMC_ISPCMD (0x2D) Set ISPGO = 1 Set ISPGO = 1 Add ISB instruction Add ISB instruction Check ISPGO = 0 Check ISPGO = 0 Step 3 Read Checksum from FMC_ISPDAT...
Page 228: Figure 6.4-17 All-One Verification Flow
NUC126 6.4.4.8 Flash All-One Verification The NUC126 series supports the flash all one verification function to help user quickly check a memory block content blanking for APROM, LDROM, and SPROM after flash erase operation. Two steps complete this flash all-one verification. Step 1: perform ISP “Run Flash All One Verification”...
Page 229: Register Map
NUC126 6.4.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value FMC Base Address FMC_BA = 0x5000_C000 FMC_ISPCTL FMC_BA+0x00 ISP Control Register 0x0000_0000 FMC_ISPADDR FMC_BA+0x04 ISP Address Register 0x0000_0000 FMC_ISPDAT FMC_BA+0x08 ISP Data Register 0x0000_0000 FMC_ISPCMD...
Page 230: Register Description
NUC126 6.4.6 Register Description ISP Control Register (FMC_ISPCTL) Register Offset Description Reset Value FMC_ISPCTL FMC_BA+0x00 ISP Control Register 0x0000_0000 Reserved Reserved Reserved Reserved ISPFF LDUEN CFGUEN APUEN SPUEN ISPEN Bits Description [31:15] Reserved Reserved. [14:12] Reserved To be 000, Reserved Reserved [11] Reserved.
Page 231 NUC126 CONFIG Update Enable Bit (Write Protect) 0 = CONFIG cannot be updated. CFGUEN 1 = CONFIG can be updated. Note: This bit is write-protected. Refer to the SYS_REGLCTL register. APROM Update Enable Bit (Write Protect) 0 = APROM cannot be updated when the chip runs in APROM. APUEN 1 = APROM can be updated when the chip runs in APROM.
Page 232 NUC126 ISP Address (FMC_ISPADDR) Register Offset Description Reset Value FMC_ISPADDR FMC_BA+0x04 ISP Address Register 0x0000_0000 ISPADDR ISPADDR ISPADDR ISPADDR Bits Description [31:0] ISPADDR ISP Address ® The NuMicro NUC126 series is equipped with embedded flash. ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. ISPADDR[2:0] must be kept 000 for ISP 64-bit operation. For Checksum Calculation command, this field is the flash starting address for checksum calculation, 512 bytes alignment is necessary for checksum calculation.
Page 233 NUC126 ISP Data Register (FMC_ISPDAT) Register Offset Description Reset Value FMC_ISPDAT FMC_BA+0x08 ISP Data Register 0x0000_0000 ISPDAT ISPDAT ISPDAT ISPDAT Bits Description [31:0] ISPDAT ISP Data Write data to this register before ISP program operation. Read data from this register after ISP read operation. For Run Checksum Calculation command, ISPDAT is the memory size (byte) and 512 bytes alignment.
Page 234 NUC126 ISP CMD (FMC_ISPCMD) Register Offset Description Reset Value FMC_ISPCMD FMC_BA+0x0C ISP CMD Register 0x0000_0000 Reserved Reserved Reserved Reserved Bits Description [31:7] Reserved Reserved. [6:0] ISP CMD ISP command table is shown below: 0x00= FLASH Read. 0x40= FLASH 64-bit Read. 0x04= Read Unique ID.
Page 235 NUC126 ISP Trigger Control Register (FMC_ISPTRG) Register Offset Description Reset Value FMC_ISPTRG FMC_BA+0x10 ISP Trigger Control Register 0x0000_0000 Reserved Reserved Reserved Reserved ISPGO Bits Description [31:1] Reserved Reserved. ISP Start Trigger (Write Protect) ISPGO Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
Page 236 NUC126 Data Flash Base Address Register (FMC_DFBA) Register Offset Description Reset Value FMC_DFBA FMC_BA+0x14 Data Flash Base Address 0xXXXX_XXXX DFBA DFBA DFBA DFBA Bits Description [31:0] DFBA Data Flash Base Address This register indicates Data Flash start address. It is a read only register. The Data Flash is shared with APROM.
Page 237 NUC126 Flash Access Time Control Register (FMC_FTCTL) Register Offset Description Reset Value FMC_FTCTL FMC_BA+0x18 Flash Access Time Control Register 0x0000_0000 Reserved Reserved Reserved MFPSOFF CACHEOFF FATS FPSEN Bits Description [31:8] Reserved Reserved. Flash Cache Disable Bit (Write Protect) 0 = Flash Cache function Enabled (default). CACHEOFF 1 = Flash Cache function Disabled.
Page 238 NUC126 ISP Status Register (FMC_ISPSTS) Register Offset Description Reset Value FMC_ISPSTS FMC_BA+0x40 ISP Status Register 0xX000_000X SCODE Reserved VECMAP VECMAP VECMAP Reserved ALLONE ISPFF Reserved ISPBUSY Bits Description Security Code Active Flag This bit is set by hardware when detecting SPROM secured code is active at flash initiation, or software writes 1 to this bit to make secured code active;...
Page 239 NUC126 ISP Fail Flag (Write Protect) This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions: (1) APROM writes to itself if APUEN is set to 0.
Page 240 NUC126 ISP Data 0 Register (FMC_MPDAT0) Register Offset Description Reset Value FMC_MPDAT0 FMC_BA+0x80 ISP Data0 Register 0x0000_0000 ISPDAT0 ISPDAT0 ISPDAT0 ISPDAT0 Bits Description [31:0] ISPDAT0 ISP Data 0 This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data.
Page 241 NUC126 ISP Data 1 Register (FMC_MPDAT1) Register Offset Description Reset Value FMC_MPDAT1 FMC_BA+0x84 ISP Data1 Register 0x0000_0000 ISPDAT1 ISPDAT1 ISPDAT1 ISPDAT1 Bits Description [31:0] ISPDAT1 ISP Data 1 This register is the second 32-bit data for 64-bit/multi-word programming. Aug. 08, 2018 Page 241 of 943 Rev 1.03...
Page 242 NUC126 ISP Data 2 Register (FMC_MPDAT2) Register Offset Description Reset Value FMC_MPDAT2 FMC_BA+0x88 ISP Data2 Register 0x0000_0000 ISPDAT2 ISPDAT2 ISPDAT2 ISPDAT2 Bits Description [31:0] ISPDAT2 ISP Data 2 This register is the third 32-bit data for multi-word programming. Aug. 08, 2018 Page 242 of 943 Rev 1.03...
Page 243 NUC126 ISP Data 3 Register (FMC_MPDAT3) Register Offset Description Reset Value FMC_MPDAT3 FMC_BA+0x8C ISP Data3 Register 0x0000_0000 ISPDAT3 ISPDAT3 ISPDAT3 ISPDAT3 Bits Description [31:0] ISPDAT3 ISP Data 3 This register is the fourth 32-bit data for multi-word programming. Aug. 08, 2018 Page 243 of 943 Rev 1.03...
Page 244 NUC126 ISP Multi-Program Status Register (FMC_MPSTS) Register Offset Description Reset Value FMC_MPSTS FMC_BA+0xC0 ISP Multi-Program Status Register 0x0000_0000 Reserved Reserved Reserved Reserved ISPFF PPGO MPBUSY Bits Description [31:8] Reserved Reserved. ISP DATA 3 Flag (Read Only) This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete.
Page 245 NUC126 ISP Fail Flag (Read Only) This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions: (1) APROM writes to itself if APUEN is set to 0.
Page 246 NUC126 ISP Multi-Word Program Address Register (FMC_MPADDR) Register Offset Description Reset Value FMC_MPADDR FMC_BA+0xC4 ISP Multi-Program Address Register 0x0000_0000 MPADDR MPADDR MPADDR MPADDR Bits Description [31:0] MPADDR ISP Multi-word Program Address MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1. MPADDR will keep the final ISP address when ISP multi-word program is complete.
Page 247: Analog Comparator Controller (Acmp)
NUC126 Analog Comparator Controller (ACMP) 6.5.1 Overview NUC126 contains two analog comparators. The comparator output is logic 1 when positive input is greater than negative input; otherwise, the output is 0. Each comparator can be configured to generate an interrupt when the comparator output state changes. 6.5.2 Features ...
Page 248: Block Diagram
NUC126 6.5.3 Block Diagram POSSEL ACMPS0 ACMP_CTL0[7:6] (ACMP_STATUS[12]) HYSEN ACMP0_P0 ACMPO0 (ACMP_CTL0[2]) (ACMP_STATUS[4]) ACMP0_WLA ACMP0_P1 ACMPEN ACMPOINV (ACMP_CTL0[0]) OUTSEL ACMP0_P2 (ACMP_CTL0[3] (ACMP_CTL0[12]) WLATOUT0 ACMP0_P3 ACMP0 ACMP0_O ACMP0_N Filter Window Block Latch PWM/Timer Brake CRVSSEL ACMP_VREF[6] WCMPSEL ACMPIF0 FILTSEL (ACMP_CTL0[18]) (ACMP_STATUS[0]) (ACMP_CTL0[15:13] NEGSEL WKIF0...
Page 249: Basic Configuration
NUC126 6.5.4 Basic Configuration  Clock Source Configuration Enable ACMP peripheral clock in ACMP01CKEN (CLK_APBCLK0[30]). –  Reset Configuration Reset ACMP controller in ACMP01RST (SYS_IPRST1[22]). –  Pin Configuration Group Pin Name GPIO ACMP0_N PB.4 MFP5 ACMP0_O PD.6, PD.7 MFP5 ACMP0_P0 PB.7 MFP5...
Page 250: Figure 6.5-2 Comparator Hysteresis Function Of Acmp0
NUC126 High threshold voltage ACMP0_N Low threshold voltage ACMP0_P ACMP0_O Figure 6.5-2 Comparator Hysteresis Function of ACMP0 6.5.5.2 Window Latch Function Figure 6.5-3 shows the comparator operation of window latch function. Window latch function can be enabled by setting WLATEN (ACMP_CTL0/1[17]) to 1. When window latch function enabled, ACMP0/1_WLAT pin is used to control the output WLATOUT0/1 .When ACMP0/1_WLAT pin is high, ACMPO0/1 passes through to WLATOUT0/1.
Page 251: Figure 6.5-4 Filter Function Example
NUC126 Comparing Result Comparing Result ACMP0_N ACMP0_P ACMPO0 PCLK Figure 6.5-4 Filter Function Example 6.5.5.4 Interrupt The outputs of ACMP0 and ACMP1 are reflected at ACMPO0 (ACMP_STATUS[4]) and ACMPO1 (ACMP_STATUS[5]) respectively. Then they are processed by window latch and filter functions. Finally, the output signal could be utilized to assert interrupts.
Page 252: Figure 6.5-6 Comparator Reference Voltage Block Diagram
NUC126 CRVSSEL (ACMP_VREF[6]) INT_VREF CRVCTL (ACMP_VREF[3:0]) 1111 1110 CRV output 1101 0010 0001 0000 Figure 6.5-6 Comparator Reference Voltage Block Diagram 6.5.5.6 Window Compare Mode The NUC126 comparator provides window compare mode. When window compare mode is enabled by setting WCMPSEL (ACMP_CTL0/1[18]) to 1, user can monitor a specific analog voltage source with a designated range.
Page 253: Figure 6.5-7 Example Connection Of Window Compare Mode
NUC126 Voltage source ACMP0 Voltage of ACMPS0 lower bound ACMPWO ACMPS1 ACMP1 Voltage of upper bound Figure 6.5-7 Example Connection of Window Compare Mode The comparator window output, ACMPW0 (ACMP_STATUS[16]), is come from ACMPS0 XOR ACMPS1. Voltage of upper bound ACMP1_N ACMP0/1_P Voltage of lower bound...
Page 254: Register Map
NUC126 6.5.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value ACMP Base Address: ACMP01_BA = 0x400D_0000 ACMP_CTL0 ACMP01_BA+0x00 R/W Analog Comparator 0 Control Register 0x0000_0000 ACMP_CTL1 ACMP01_BA+0x04 R/W Analog Comparator 1 Control Register 0x0000_0000 ACMP_STATUS ACMP01_BA+0x08...
Page 255: Register Description
NUC126 6.5.7 Register Description Analog Comparator 0 Control Register (ACMP_CTL0) Register Offset R/W Description Reset Value ACMP_CTL0 ACMP01_BA+0x00 R/W Analog Comparator 0 Control Register 0x0000_0000 Reserved Reserved WCMPSEL WLATEN WKEN FILTSEL OUTSEL Reserved INTPOL POSSEL NEGSEL ACMPOINV HYSEN ACMPIE ACMPEN Bits Description Reserved...
Page 256 NUC126 00 = Rising edge or falling edge. 01 = Rising edge. 10 = Falling edge. 11 = Reserved. Comparator Positive Input Selection 00 = Input from ACMP0_P0. [7:6] POSSEL 01 = Input from ACMP0_P1. 10 = Input from ACMP0_P2. 11 = Input from ACMP0_P3.
Page 257 NUC126 Analog Comparator 1 Control Register (ACMP_CTL1) Register Offset R/W Description Reset Value ACMP_CTL1 ACMP01_BA+0x04 R/W Analog Comparator 1 Control Register 0x0000_0000 Reserved Reserved WCMPSEL WLATEN WKEN FILTSEL OUTSEL Reserved INTPOL POSSEL NEGSEL ACMPOINV HYSEN ACMPIE ACMPEN Bits Description [31:19] Reserved Reserved.
Page 258 NUC126 Bits Description 00 = Rising edge or falling edge. 01 = Rising edge. 10 = Falling edge. 11 = Reserved. Comparator Positive Input Selection 00 = Input from ACMP1_P0. [7:6] POSSEL 01 = Input from ACMP1_P1. 10 = Input from ACMP1_P2. 11 = Input from ACMP1_P3.
Page 259 NUC126 Analog Comparator Status Register (ACMP_STATUS) Register Offset Description Reset Value ACMP_STATUS ACMP01_BA+0x08 Analog Comparator Status Register 0x0000_0000 Reserved Reserved ACMPWO Reserved ACMPS1 ACMPS0 Reserved WKIF1 WKIF0 Reserved ACMPO1 ACMPO0 Reserved ACMPIF1 ACMPIF0 Bits Description Reserved [31:17] Reserved. Comparator Window Output This bit shows the output status of window compare mode ACMPWO [16]...
Page 260 NUC126 Bits Description is disabled, i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0. Comparator 0 Output ACMPO0 Synchronized to the PCLK to allow reading by software. Cleared when the comparator 0 is disabled, i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0. [3:2] Reserved Reserved.
Page 261 NUC126 ACMP Reference Voltage Control Register (ACMP_VREF) Register Offset R/W Description Reset Value ACMP_VREF ACMP01_BA+0x0C R/W Analog Comparator Reference Voltage Control Register 0x0000_0000 Reserved Reserved Reserved Reserved CRVSSEL Reserved CRVCTL Bits Description [31:7] Reserved Reserved. CRV Source Voltage Selection 0 = AV is selected as CRV voltage source.
Page 262: Analog-To-Digital Converter (Adc)
NUC126 Analog-to-Digital Converter (ADC) 6.6.1 Overview The NUC126 series contains one 12-bit successive approximation analog-to-digital converter (SAR A/D converter) with twenty input channels. The A/D converter supports four operation modes: Single, Burst, Single-cycle Scan and Continuous Scan mode. The A/D converter can be started by software, external pin (STADC/PD.2), timer0~3 overflow pulse trigger and PWM trigger.
Page 263: Block Diagram
NUC126 6.6.3 Block Diagram VALID & OVERRUN PDMA request Digital Control Logic STADC & ADC_INT PWM_TRG ADC Clock Generator TIMER_TRG A/D conversion result INT_VREF Successive Approximations SYS_VREFCTL[4:0] Register 12-bit DAC AIN0 ADC0_CH0 AIN1 ADC0_CH1 AIN19 Analog Control ADC0_CH19 Logic VTEMPEN (SYS_IVSCTL[0]) Comparator TEMP...
Page 264: Functional Description
NUC126 ADC0_CH1 PB.1 MFP1 ADC0_CH2 PB.2 MFP1 ADC0_CH3 PB.3 MFP1 ADC0_CH4 PB.4 MFP1 ADC0_CH5 PB.8 MFP1 ADC0_CH6 PB.9 MFP1 ADC0_CH7 PB.10 MFP1 ADC0_CH8 PB.11 MFP1 ADC0_CH9 PE.2 MFP1 ADC0_CH10 PB.13 MFP1 ADC0_CH11 PB.14 MFP1 ADC0_CH12 PB.15 MFP1 ADC0_CH13 PB.5 MFP1 ADC0_CH14 PB.6 MFP1...
Page 265: Figure 6.6-2 Adc Peripheral Clock Control
NUC126 ADCSEL (CLKSEL1[3:2]) ADCCKEN(APBCLK0[28]) 22.1184 MHz HIRC ADCCLK HCLK 1/(ADCDIV + 1) PLL FOUT Legend: ADCDIV(CLKDIV0[23:16]) HXT = High-Speed External clock signal 4~24 MHz HXT HIRC = High-Speed Internal clock signal Figure 6.6-2 ADC Peripheral Clock Control 6.6.5.2 Single Mode In Single mode, A/D conversion is performed only once on the specified single channel.
Page 266: Figure 6.6-3 Single Mode Conversion Timing Diagram
NUC126 ADCCLK ADST SAMPLE Valid data ADDRx Note: SAMPLE is an internal signal indicates sample stage x = the selected channel Figure 6.6-3 Single Mode Conversion Timing Diagram 6.6.5.3 Burst Mode In Burst mode, A/D converter samples and converts the specified single channel and sequentially stores the result into FIFO (up to 16 samples).
Page 267: Figure 6.6-4 Burst Mode Conversion Timing Diagram
NUC126 ADST A/D converter channel select SAMPLE ADC analog DAT0 DAT1 DAT2 DAT15 macro output FIFO_0 DAT0 FIFO_1 DAT1 FIFO_2 DAT2 FIFO_15 DAT15 Note: x = the smallest channel selection SAMPLE is an internal signal indicates sample stage Figure 6.6-4 Burst Mode Conversion Timing Diagram Note1: If software enables more than one channel in Burst mode, only the channel with the smallest number is converted and other enabled channels will be ignored.
Page 268: Figure 6.6-5 Single-Cycle Scan Mode On Enabled Channels Timing Diagram
NUC126 ADST A/D converter channel select SAMPLE ADC analog macro output ADDR0 ADDR2 ADDR3 ADDR7 Single-cycle scan on channel 0, 2, 3 and 7 Note: SAMPLE is an internal signal indicates sample stage Figure 6.6-5 Single-Cycle Scan Mode on Enabled Channels Timing Diagram 6.6.5.5 Continuous Scan Mode In Continuous Scan mode, A/D conversion is performed sequentially on the specified channels that...
Page 269: Figure 6.6-6 Continuous Scan Mode On Enabled Channels Timing Diagram
NUC126 ADST Software clear ADST A/D converter channel select SAMPLE ADDR0 ADDR2 ADDR3 ADDR7 Continuous scan on channel 0, 2, 3 and 7 Note: SAMPLE is an internal signal indicates sample stage Figure 6.6-6 Continuous Scan Mode on Enabled Channels Timing Diagram 6.6.5.6 External Trigger Input In Single-cycle Scan mode, A/D conversion can be triggered by external pin request.
Page 270: Figure 6.6-7 A/D Conversion Result Monitor Logic Diagram
NUC126 6.6.5.9 Conversion Result Monitor by Compare Mode Function The NUC126 series ADC controller provides two compare registers, ADCMPRx(x=0,1), to monitor maximum two specified channels. Software can select which channel to be monitored by setting CMPCH (ADCMPRx[7:3]). CMPCOND (ADCMPRx[2]) bit is used to determine the compare condition. If CMPCOND bit is cleared to 0, the internal match counter will increase one when the conversion result is less than the value specified in CMPD (ADCMPRx[27:16]);...
Page 271: Figure 6.6-8 A/D Controller Interrupt
NUC126 6.6.5.12 Interrupt Sources There are three interrupt sources of ADC interrupt. When an ADC operation mode finishes its conversion, the A/D conversion end flag, ADF(ADSR0[0]), will be set to 1. The CMPF0(ADSR0[1]) and CMPF1(ADSR0[2]) are the compare flags of compare function. When the conversion result meets the settings of ADCMPR0/1 registers, the corresponding flag will be set to 1.
Page 272: Register Map
NUC126 6.6.6 Register Map R: read only, W: write only, R/W: both read and write. Register Offset Description Reset Value ADC Base Address: ADC_BA = 0x400E_0000 ADC_ADDR0 ADC_BA+0x00 ADC Data Register 0 0x0000_0000 ADC_ADDR1 ADC_BA+0x04 ADC Data Register 1 0x0000_0000 ADC_ADDR2 ADC_BA+0x08 ADC Data Register 2...
Page 273 NUC126 ADC_ADSR0 ADC_BA+0x90 ADC Status Register0 0x0000_0000 ADC_ADSR1 ADC_BA+0x94 ADC Status Register1 0x0000_0000 ADC_ADSR2 ADC_BA+0x98 ADC Status Register2 0x0000_0000 ADC_ADTDCR ADC_BA+0x9C ADC Trigger Delay Control Register 0x0000_0000 ADC_ADPDMA ADC_BA+0x100 ADC PDMA Current Transfer Data Register 0x0000_0000 Aug. 08, 2018 Page 273 of 943 Rev 1.03...
Page 274: Register Description
NUC126 6.6.7 Register Description ADC Data Registers (ADC_ADDRx x = 0~19, 29~31) Register Offset Description Reset Value ADC_ADDR0 ADC_BA+0x00 ADC Data Register 0 0x0000_0000 ADC_ADDR1 ADC_BA+0x04 ADC Data Register 1 0x0000_0000 ADC_ADDR2 ADC_BA+0x08 ADC Data Register 2 0x0000_0000 ADC_ADDR3 ADC_BA+0x0C ADC Data Register 3 0x0000_0000 ADC_ADDR4...
Page 275: Figure 6.6-9 Conversion Result Mapping Diagram Of Adc Single-End Input
NUC126 Reserved Reserved VALID OVERRUN RSLT RSLT Bits Description [31:18] Reserved Reserved. Valid Flag (Read Only) This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read. [17] VALID 0 = Data in RSLT bits is not valid.
Page 276: Figure 6.6-10 Conversion Result Mapping Diagram Of Adc Differential Input
NUC126 ADC result in ADC result in RSLT[11:0] RSLT[15:0] Note: Vref voltage comes from VREF(AV Note: Vref voltage comes from VREF(AV (DMOF = 0) (DMOF = 1) 1111_1111_1111 0000_0111_1111_1111 1111_1111_1110 0000_0111_1111_1110 1111_1111_1101 0000_0111_1111_1101 1000_0000_0001 0000_0000_0000_0001 1000_0000_0000 0000_0000_0000_0000 0111_1111_1111 1111_1111_1111_1111 1 LSB = Vref/4096 1 LSB = Vref/4096 0000_0000_0010 1111_1000_0000_0010...
Page 277 NUC126 ADC Control Register (ADC_ADCR) Register Offset Description Reset Value ADC_ADCR ADC_BA+0x80 ADC Control Register 0x0005_0000 DMOF Reserved Reserved SMPTSEL Reserved ADST DIFFEN PTEN TRGEN TRGCOND TRGS ADMD ADIE ADEN Bits Description Differential Input Mode Output Format If user enables differential input mode, the conversion result can be expressed with binary straight format (unsigned format) or 2’s complement format (signed format).
Page 278 NUC126 where V is the analog input; V is the inverted analog input. plus minus The V of differential input paired channel x is from ADC0_CHy pin; V is from plus minus ADC0_CHz pin, x=0,1..9, y=2*x, z=y+1. 0 = Single-end analog input mode. 1 = Differential analog input mode.
Page 279 NUC126 0 = A/D converter Disabled. 1 = A/D converter Enabled. Note: Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit to save power consumption. Aug. 08, 2018 Page 279 of 943 Rev 1.03...
Page 280 NUC126 ADC Channel Enable Register (ADC_ADCHER) Register Offset Description Reset Value ADC_ADCHER ADC_BA+0x84 ADC Channel Enable Register 0x0000_0000 CHEN CHEN CHEN CHEN Bits Description Analog Input Channel Enable Control Set ADCHER[19:0] bits to enable the corresponding analog input channel 19 ~ 0. If DIFFEN bit is set to 1, only the even number channel needs to be enabled.
Page 281 NUC126 ADC Compare Register 0/1 (ADC_ADCMPR0/1) Register Offset Description Reset Value ADC_ADCMPR0 ADC_BA+0x88 ADC Compare Register 0 0x0000_0000 ADC_ADCMPR1 ADC_BA+0x8C ADC Compare Register 1 0x0000_0000 Reserved CMPD CMPD CMPWEN Reserved CMPMATCNT CMPCH CMPCOND CMPIE CMPEN Bits Description [31:28] Reserved Reserved. Comparison Data CMPD The 12-bit data is used to compare with conversion result of specified channel.
Page 282 NUC126 01010 = Channel 10 conversion result is selected to be compared. 01011 = Channel 11 conversion result is selected to be compared. 01100 = Channel 12 conversion result is selected to be compared. 01101 = Channel 13 conversion result is selected to be compared. 01110 = Channel 14 conversion result is selected to be compared.
Page 283 NUC126 ADC Status Register0 (ADC_ADSR0) Register Offset Description Reset Value ADC_ADSR0 ADC_BA+0x90 ADC Status Register0 0x0000_0000 CHANNEL Reserved Reserved OVERRUNF Reserved VALIDF BUSY Reserved CMPF1 CMPF0 Bits Description Current Conversion Channel (Read Only) [31:27] CHANNEL When BUSY=1, this filed reflects current conversion channel. When BUSY=0, it shows the number of the next converted channel.
Page 284 NUC126 A/D Conversion End Flag A status flag that indicates the end of A/D conversion. Software can write 1 to clear this bit. ADF bit is set to 1 at the following three conditions: When A/D conversion ends in Single mode. When A/D conversion ends on all specified channels in Single-cycle Scan mode and Continuous Scan mode.
Page 285 NUC126 ADC Status Register1 (ADC_ADSR1) Register Offset Description Reset Value ADC_ADSR1 ADC_BA+0x94 ADC Status Register1 0x0000_0000 VALID VALID VALID VALID Bits Description Data Valid Flag (Read Only) VALID[31:29, 19:0] are the mirror of the VALID bits in ADDR31[17] ~ ADDR29[17], VALID [31:0] ADDR19[17]~ ADDR0[17].
Page 286 NUC126 ADC Status Register2 (ADC_ADSR2) Register Offset Description Reset Value ADC_ADSR2 ADC_BA+0x98 ADC Status Register2 0x0000_0000 OVERRUN OVERRUN OVERRUN OVERRUN Bits Description Overrun Flag (Read Only) OVERRUN[31:29, 19:0] are the mirror of the OVERRUN bit in ADDR31[16] [31:0] OVERRUN ~ADDR29[16], ADDR19[16] ~ ADDR0[16]. The other bits are reserved. Note: When ADC is in burst mode and the FIFO is overrun, OVERRUN[31:29, 19:0] will be set to 1.
Page 287 NUC126 ADC Trigger Delay Control Register (ADC_ADTDCR) Register Offset Description Reset Value ADC_ADTDCR ADC_BA+0x9C ADC Trigger Delay Control Register 0x0000_0000 Reserved Reserved Reserved PTDT Bits Description [31:8] Reserved Reserved. PWM Trigger Delay Time [7:0] PTDT Set this field will delay ADC start conversion time after PWM trigger. PWM trigger delay time is (4 * PTDT) * system clock Aug.
Page 288 NUC126 ADC PDMA Current Transfer Data Register (ADC_ADPDMA) Register Offset Description Reset Value ADC_ADPDMA ADC_BA+0x100 ADC PDMA Current Transfer Data Register 0x0000_0000 Reserved Reserved CURDAT CURDAT CURDAT Bits Description Reserved [31:18] Reserved. ADC PDMA Current Transfer Data Register (Read Only) When PDMA transferring, read this register can monitor current PDMA transfer data.
Page 289: Crc Controller (Crc)
NUC126 CRC Controller (CRC) 6.7.1 Overview The Cyclic Redundancy Check (CRC) generator can perform CRC calculation with four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32 settings. 6.7.2 Features  Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32 CRC-CCITT: X –...
Page 290: Basic Configuration
NUC126 6.7.4 Basic Configuration  Clock Source Configuration Enable CRC peripheral clock in CRCCKEN (CLK_AHBCLK[7]). –  Reset Configuration Reset CRC in CRCRST (SYS_IPRST0[7]). – User can start to program DATA (CRC_DAT[31:0]) to calculate CRC checksum result in CHECKSUM (CRC_CHECKSUM[31:0]). 6.7.5 Functional Description The CRC generator can perform CRC calculation with four common polynomial settings which...
Page 291: Figure 6.7-3 Write Data Bit Order Reverse Functional Block
NUC126 …… BIT24 BIT31 BIT30 …… … … … BIT7 BIT6 BIT0 Bit Order Reverse Bit Order Reverse … … … per byte per byte …… BIT31 … … … …… BIT24 BIT25 BIT0 BIT1 BIT7 Figure 6.7-3 Write Data Bit Order Reverse Functional Block Aug.
Page 292: Register Map
NUC126 6.7.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value CRC Base Address: CRC_BA = 0x5001_8000 CRC_CTL CRC_BA+0x00 CRC Control Register 0x2000_0000 CRC_DAT CRC_BA+0x04 CRC Write Data Register 0x0000_0000 CRC_SEED CRC_BA+0x08 CRC Seed Register 0xFFFF_FFFF...
Page 293: Register Description
NUC126 6.7.7 Register Description CRC Control Register (CRC_CTL) Register Offset Description Reset Value CRC_CTL CRC_BA+0x00 CRC Control Register 0x2000_0000 CRCMODE DATLEN CHKSFMT DATFMT CHKSREV DATREV Reserved Reserved Reserved CHKSINIT CRCEN Bits Description CRC Polynomial Mode This field indicates the CRC operation polynomial mode. 00 = CRC-CCITT Polynomial mode.
Page 294 NUC126 Checksum Bit Order Reverse Enable Bit This bit is used to enable the bit order reverse function for checksum result CHECKSUM (CRC_CHECKSUM[31:0]). CHKSREV 0 = Bit order reverse for CRC CHECKSUM Disabled. [25] 1 = Bit order reverse for CRC CHECKSUM Enabled. Note: If the checksum result is 0xDD7B0F2E, the bit order reverse result for CRC checksum is 0x74F0DEBB.
Page 295 NUC126 CRC Write Data Register (CRC_DAT) Register Offset Description Reset Value CRC_DAT CRC_BA+0x04 CRC Write Data Register 0x0000_0000 DATA DATA DATA DATA Bits Description CRC Write Data Bits User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
Page 296 NUC126 CRC Seed Register (CRC_SEED) Register Offset Description Reset Value CRC_SEED CRC_BA+0x08 CRC Seed Register 0xFFFF_FFFF SEED SEED SEED SEED Bits Description CRC Seed Value This field indicates the CRC seed value. [31:0] SEED Note1: This SEED value will be loaded to checksum initial value CHECKSUM (CRC_CHECKSUM[31:0]) after set CHKSINIT (CRC_CTL[1]) to 1.
Page 297 NUC126 CRC Checksum Register (CRC_CHECKSUM) Register Offset Description Reset Value CRC_CHECKSUM CRC_BA+0x0C CRC Checksum Register 0xFFFF_FFFF CHECKSUM CHECKSUM CHECKSUM CHECKSUM Bits Description CRC Checksum Results This field indicates the CRC checksum result. CHECKSUM [31:0] Note: The valid bits of CRC_CHECKSUM[31:0] is correlated to CRCMODE (CRC_CTL[31:30]).
Page 298: External Bus Interface (Ebi)
NUC126 External Bus Interface (EBI) 6.8.1 Overview The NUC126 series is equipped with an external bus interface (EBI) for external device used. To save the connections between external device and the NUC126, EBI operating at address bus and data bus multiplex mode.
Page 299: Block Diagram
NUC126 6.8.3 Block Diagram HCLK EBI_MCLK MCLK Divider MCLKDIV Idle Cycle Timing Controller CACCESS RAHDOFF WAHDOFF EBI_ADR[19:16] TACC EBI State EBI_AD[15:0] TAHD Machine EBI Signal TALE Timing EBI_nCSx Controller Register Controller Output EBI_nRD DW16 Controller CSPOLINV EBI_nWR EBI_nWRL EBI request EBI_nWRH Address Hit EBI_ALE...
Page 300: Functional Description
NUC126 EBI_AD5 PA.5, PB.6, PE.12 MFP7 EBI_AD6 PA.6, PB.5, PE.11 MFP7 EBI_AD7 PA.7, PB.4, PE.10 MFP7 EBI_AD8 PC.0 MFP7 EBI_AD9 PC.1 MFP7 EBI_AD10 PC.2 MFP7 EBI_AD11 PC.3 MFP7 EBI_AD12 PC.4 MFP7 EBI_AD13 PC.5 MFP7 EBI_AD14 PC.6 MFP7 EBI_AD15 PC.7 MFP7 EBI_ADR16 PD.12 MFP7...
Page 301: Figure 6.8-2 Connection Of 16-Bit Device With 16-Bit Ebi Data Width
NUC126 To map the whole EBI memory space, it requires 20-bit address for 8-bit data width device and 19-bit address for 16-bit data width device. For device package that output less than 20-bit address, EBI will map device to mirror space. For example, the external device with 18-bit EBI address on bank0, EBI control will mapped external device to memory address 0x6000_0000 ~ 0x6003_FFFF, 0x6004_0000 ~ 0x6007_FFFF, 0x6008_0000 ~ 0x600B_FFFF and 0x600C_0000 ~ 0x600F_FFFF simultaneously.
Page 302: Figure 6.8-3 Connection Of 8-Bit Device With 8-Bit Ebi Data Width
NUC126 External Bus Interface 1M x 8-bit SRAM EBI_ADR[19:16] Addr[19:16] EBI_AD[15:8] Addr[15:8] Address latch device EBI_AD[7:0] Addr[7:0] EBI_ALE EBI_nCSx EBI_nRD EBI_nWR EBI_AD[7:0] EBI_AD[7:0] Data[7:0] Note: x = 0 or 1 Figure 6.8-3 Connection of 8-bit Device with 8-bit EBI Data Width When system access data width is larger than EBI data width setting, EBI controller will finish a system access command by operating EBI access with data width setting more than once.
Page 303: Table 6.8-2 Ebi Timing Control Setting Table
NUC126 6.8.5.3 EBI Operating Control MCLK Control In the chip, all EBI signals will be synchronized by EBI_MCLK when EBI is operating. When chip connects to the external device with slower operating frequency, the EBI_MCLK can divide most to HCLK/128 by setting MCLKDIV (EBI_CTLx[10:8]). Therefore, chip can suitable for a wide frequency range of EBI device.
Page 304: Figure 6.8-4 Timing Control Waveform For 16-Bit Data Width
NUC126 Figure 6.8-4 shows an example of setting 16-bit data width by 16-bit read/write access commands. In this example, EBI_AD[15:0] bus is used for being Address output[15:0] and Data[15:0]. When EBI_ALE assert to high, EBI_AD is address output. After address is latched, EBI_ALE asserts to low and the EBI_AD bus change to high impedance to wait device output data in read access operation, or it is used for being write data output.
Page 305: Figure 6.8-5 Timing Control Waveform For 8-Bit Data Width
NUC126 tASU tALE tLHD tA2D tACC tAHD EBI_MCLK EBI_nCSx EBI_ALE EBI_nRD RData EBI_AD[7:0] Address output[7:0] input EBI_AD[15:8] Address output[15:8] EBI_ADR[19:16] Address output[19:16] EBI_nWR EBI_AD[7:0] Address output[7:0] WData output[7:0] EBI_AD[15:8] Address output[15:8] EBI_ADR[19:16] Address output[19:16] Note1: TALE is 1, TACC is 2, TAHD is 1 and access command width is 8-bit read and write. Note2: x = 0 or 1.
Page 306: Figure 6.8-6 Timing Control Waveform For Insert Idle Cycle
NUC126 Insert Idle Cycle When EBI accessing continuously, there may occur bus conflict if the device access time is much slow with system operating. EBI controller supply additional idle cycle as shown in Figure 6.8-6 to solve this problem. During idle cycle, all control signals of EBI are inactive. There are two conditions that EBI controller can insert idle cycle by timing control after write access, W2X (EBI_TCTLx[15:12]) and after read access and before next read access, R2R (EBI_TCTLx[27:24]).
Page 307: Figure 6.8-7 Timing Control Waveform For Continuous Data Access Mode
NUC126 Idle tA2D tACC tAHD tA2D tACC tAHD tA2D tACC tAHD cycle EBI_MCLK EBI_nCSx EBI_nRD RData RData RData EBI_AD[15:0] input input input EBI_nWR EBI_AD[15:0] Wdata output[15:0] Wdata output[15:0] Wdata output[15:0] Note1: TACC is 1, TAHD is 1, CACCESS is enabled and access command width is 32-bit read and write. Note2: x = 0 or 1.
Page 308: Register Map
NUC126 6.8.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value EBI Base Address: EBI_BA = 0x5001_0000 EBI_CTL0 EBI_BA+0x00 External Bus Interface Bank0 Control Register 0x0000_0000 EBI_TCTL0 EBI_BA+0x04 External Bus Interface Bank0 Timing Control Register 0x0000_0000 EBI_CTL1 EBI_BA+0x10...
Page 309: Register Description
NUC126 6.8.7 Register Description External Bus Interface Control Register (EBI_CTLx) Register Offset Description Reset Value EBI_CTL0 EBI_BA+0x00 External Bus Interface Bank0 Control Register 0x0000_0000 EBI_CTL1 EBI_BA+0x10 External Bus Interface Bank1 Control Register 0x0000_0000 Reversed Reserved Reversed TALE Reversed MCLKDIV Reversed CACCESS Reversed CSPOLINV...
Page 310 NUC126 Chip Select Pin Polar Inverse This bit defines the active level of EBI chip select pin (EBI_nCSx), x = 0 or 1. CSPOLINV 0 = Chip select pin (EBI_nCSx) is active low. 1 = Chip select pin (EBI_nCSx) is active high. EBI Data Width 16-bit Select This bit defines if the EBI data width is 8-bit or 16-bit.
Page 311 NUC126 External Bus Interface Timing Control Register (EBI_TCTLx) Register Offset Description Reset Value EBI_TCTL0 EBI_BA+0x04 External Bus Interface Bank0 Timing Control Register 0x0000_0000 EBI_TCTL1 EBI_BA+0x14 External Bus Interface Bank1 Timing Control Register 0x0000_0000 Reserved WAHDOFF RAHDOFF Reserved Reversed TAHD TACC Reserved Bits Description...
Page 312 NUC126 tACC = (TACC + 1) * EBI_MCLK. [2:0] Reserved Reserved. Aug. 08, 2018 Page 312 of 943 Rev 1.03...
Page 313: General Purpose I/O (Gpio)
NUC126 General Purpose I/O (GPIO) 6.9.1 Overview The NUC126 series has up to 86 General Purpose I/O pins to be shared with other function pins depending on the chip configuration. These 86 pins are arranged in 6 ports named as PA, PB, PC, PD, PE and PF.
Page 314: Block Diagram
NUC126 6.9.3 Block Diagram Control Registers PA[15:0] PF[7:0] Control Register Control Register PA[15:0] PB[15:0] PB[15:0] Control Register PC[15:0] PC[15:0] Control Register PD[15:0] PE[15:0] PD[15:0] Control Register PF[7:0] PE[15:0] Control Register Interrupt, Wake-up Event De-bounce Control Register Detector GPIO_INT Figure 6.9-1 GPIO Controller Block Diagram Note: The PE.14/PE.15 pin is ignored.
Page 315: Basic Configuration
NUC126 HCLKSEL (CLK_CLKSEL0[2:0]) ÷ (HCLKDIV + 1) LIRC HCLKDIV HIRC48 (CLK_CLKDIV0[3:0]) HIRC GPIOA_CLK GPIOACKEN (CLK_AHBCLK[16]) GPIOB_CLK GPIOBCKEN (CLK_AHBCLK[17]) GPIOC_CLK GPIOCCKEN (CLK_AHBCLK[18]) GPIOD_CLK GPIODCKEN (CLK_AHBCLK[19]) GPIOE_CLK GPIOECKEN (CLK_AHBCLK[20]) GPIOF_CLK GPIOFCKEN (CLK_AHBCLK[21]) Note: Legend: HXT: External 4~24 MHz High Speed Crystal Before clock switching, both the pre-selected and newly LXT: External 32.768 KHz Low Speed Crystal selected clock sources must be turned on and stable.
Page 316 NUC126 DOUT (Px_DOUT[n]) is driven on the pin. Port Pin Port Pin Port Latch Data Port Latch Data Input Data Input Data Figure 6.9-2 Push-Pull Output 6.9.5.3 Open-drain Mode Set MODEn (Px_MODE[2n+1:2n]) to 10 the Px.n pin is in Open-drain mode and the digital output function of I/O pin supports only sink current capability, an external pull-up register is needed for driving high state.
Page 317 NUC126 uA for V is form 5.0 V to 2.5 V. 2 CPU Very Very Weak Strong Weak Strong Weak Clock Delay Weak Port Pin Port Pin Port Latch Data Port Latch Data Input Data Input Data Figure 6.9-4 Quasi-Bidirectional I/O Mode 6.9.5.5 GPIO Interrupt and Wake-up Function Each GPIO pin can be set as chip interrupt source by setting correlative RHIEN (Px_INTEN[n+16])/...
Page 318: Register Map
NUC126 6.9.6 Register Map R: read only, W: write only, R/W: both read and write. Register Offset Description Reset Value GPIO Base Address: GPIO_BA = 0x5000_4000 PA_MODE GPIO_BA+0x000 PA I/O Mode Control 0xXXXX_XXXX PA_DINOFF GPIO_BA+0x004 PA Digital Input Path Disable Control 0x0000_0000 PA_DOUT GPIO_BA+0x008...
Page 319 NUC126 PC_DBEN GPIO_BA+0x094 PC De-Bounce Enable Control 0x0000_0000 PC_INTTYPE GPIO_BA+0x098 PC Interrupt Trigger Type Control 0x0000_0000 PC_INTEN GPIO_BA+0x09C PC Interrupt Enable Control 0x0000_0000 PC_INTSRC GPIO_BA+0x0A0 PC Interrupt Source Flag 0x0000_XXXX PC_SMTEN GPIO_BA+0x0A4 PC Input Schmitt Trigger Enable 0x0000_0000 PC_SLEWCTL GPIO_BA+0x0A8 PC High Slew Rate Control 0x0000_0000 PD_MODE...
Page 320 NUC126 PF_DOUT GPIO_BA+0x148 PF Data Output Value 0x0000_00FF PF_DATMSK GPIO_BA+0x14C PF Data Output Write Mask 0x0000_0000 PF_PIN GPIO_BA+0x150 PF Pin Value 0x0000_00XX PF_DBEN GPIO_BA+0x154 PF De-Bounce Enable Control 0x0000_0000 PF_INTTYPE GPIO_BA+0x158 PF Interrupt Trigger Type Control 0x0000_0000 PF_INTEN GPIO_BA+0x15C PF Interrupt Enable Control 0x0000_0000 PF_INTSRC GPIO_BA+0x160...
Page 321: Register Description
NUC126 6.9.7 Register Description Port A-F I/O Mode Control (Px_MODE) Register Offset Description Reset Value PA_MODE GPIO_BA+0x000 PA I/O Mode Control 0xXXXX_XXXX PB_MODE GPIO_BA+0x040 PB I/O Mode Control 0xXXXX_XXXX PC_MODE GPIO_BA+0x080 PC I/O Mode Control 0xXXXX_XXXX PD_MODE GPIO_BA+0x0C0 PD I/O Mode Control 0xXXXX_XXXX PE_MODE GPIO_BA+0x100...
Page 322 NUC126 Port A-F Digital Input Path Disable Control (Px_DINOFF) Register Offset Description Reset Value PA_DINOFF GPIO_BA+0x004 PA Digital Input Path Disable Control 0x0000_0000 PB_DINOFF GPIO_BA+0x044 PB Digital Input Path Disable Control 0x0000_0000 PC_DINOFF GPIO_BA+0x084 PC Digital Input Path Disable Control 0x0000_0000 PD_DINOFF GPIO_BA+0x0C4...
Page 323 NUC126 Port A-F Data Output Value (Px_DOUT) Register Offset Description Reset Value PA_DOUT GPIO_BA+0x008 PA Data Output Value 0x0000_FFFF PB_DOUT GPIO_BA+0x048 PB Data Output Value 0x0000_FFFF PC_DOUT GPIO_BA+0x088 PC Data Output Value 0x0000_FFFF PD_DOUT GPIO_BA+0x0C8 PD Data Output Value 0x0000_FFFF PE_DOUT GPIO_BA+0x108 PE Data Output Value...
Page 324 NUC126 Port A-F Data Output Write Mask (Px_DATMSK) Register Offset Description Reset Value PA_DATMSK GPIO_BA+0x00C PA Data Output Write Mask 0x0000_0000 PB_DATMSK GPIO_BA+0x04C PB Data Output Write Mask 0x0000_0000 PC_DATMSK GPIO_BA+0x08C PC Data Output Write Mask 0x0000_0000 PD_DATMSK GPIO_BA+0x0CC PD Data Output Write Mask 0x0000_0000 PE_DATMSK GPIO_BA+0x10C...
Page 325 NUC126 Port A-F Pin Value (Px_PIN) Register Offset Description Reset Value PA_PIN GPIO_BA+0x010 PA Pin Value 0x0000_XXXX PB_PIN GPIO_BA+0x050 PB Pin Value 0x0000_XXXX PC_PIN GPIO_BA+0x090 PC Pin Value 0x0000_XXXX PD_PIN GPIO_BA+0x0D0 PD Pin Value 0x0000_XXXX PE_PIN GPIO_BA+0x110 PE Pin Value 0x0000_XXXX PF_PIN GPIO_BA+0x150...
Page 326 NUC126 Port A-F De-Bounce Enable Control (Px_DBEN) Register Offset Description Reset Value PA_DBEN GPIO_BA+0x014 PA De-Bounce Enable Control 0x0000_0000 PB_DBEN GPIO_BA+0x054 PB De-Bounce Enable Control 0x0000_0000 PC_DBEN GPIO_BA+0x094 PC De-Bounce Enable Control 0x0000_0000 PD_DBEN GPIO_BA+0x0D4 PD De-Bounce Enable Control 0x0000_0000 PE_DBEN GPIO_BA+0x114 PE De-Bounce Enable Control...
Page 327 NUC126 Port A-F Interrupt Type Control (Px_INTTYPE) Register Offset Description Reset Value PA_INTTYPE GPIO_BA+0x018 PA Interrupt Trigger Type Control 0x0000_0000 PB_INTTYPE GPIO_BA+0x058 PB Interrupt Trigger Type Control 0x0000_0000 PC_INTTYPE GPIO_BA+0x098 PC Interrupt Trigger Type Control 0x0000_0000 PD_INTTYPE GPIO_BA+0x0D8 PD Interrupt Trigger Type Control 0x0000_0000 PE_INTTYPE GPIO_BA+0x118...
Page 328 NUC126 Port A-F Interrupt Enable Control (Px_INTEN) Register Offset Description Reset Value PA_INTEN GPIO_BA+0x01C PA Interrupt Enable Control 0x0000_0000 PB_INTEN GPIO_BA+0x05C PB Interrupt Enable Control 0x0000_0000 PC_INTEN GPIO_BA+0x09C PC Interrupt Enable Control 0x0000_0000 PD_INTEN GPIO_BA+0x0DC PD Interrupt Enable Control 0x0000_0000 PE_INTEN GPIO_BA+0x11C PE Interrupt Enable Control...
Page 329 NUC126 0 = Px.n level low or high to low interrupt Disabled. 1 = Px.n level low or high to low interrupt Enabled. Note1: Max. n=15 for port A/B/C/D/E. Max. n=7 for port F. Note2: The PE.14/PE.15 pin is ignored. Aug.
Page 330 NUC126 Port A-F Interrupt Source Flag (Px_INTSRC) Register Offset Description Reset Value PA_INTSRC GPIO_BA+0x020 PA Interrupt Source Flag 0x0000_XXXX PB_INTSRC GPIO_BA+0x060 PB Interrupt Source Flag 0x0000_XXXX PC_INTSRC GPIO_BA+0x0A0 PC Interrupt Source Flag 0x0000_XXXX PD_INTSRC GPIO_BA+0x0E0 PD Interrupt Source Flag 0x0000_XXXX PE_INTSRC GPIO_BA+0x120 PE Interrupt Source Flag...
Page 331 NUC126 Port A-F Input Schmitt Trigger Enable (Px_SMTEN) Register Offset Description Reset Value PA_SMTEN GPIO_BA+0x024 PA Input Schmitt Trigger Enable 0x0000_0000 PB_SMTEN GPIO_BA+0x064 PB Input Schmitt Trigger Enable 0x0000_0000 PC_SMTEN GPIO_BA+0x0A4 PC Input Schmitt Trigger Enable 0x0000_0000 PD_SMTEN GPIO_BA+0x0E4 PD Input Schmitt Trigger Enable 0x0000_0000 PE_SMTEN GPIO_BA+0x124...
Page 332 NUC126 Port A-F High Slew Rate Control (Px_SLEWCTL) Register Offset Description Reset Value PA_SLEWCTL GPIO_BA+0x028 PA High Slew Rate Control 0x0000_0000 PB_SLEWCTL GPIO_BA+0x068 PB High Slew Rate Control 0x0000_0000 PC_SLEWCTL GPIO_BA+0x0A8 PC High Slew Rate Control 0x0000_0000 PD_SLEWCTL GPIO_BA+0x0E8 PD High Slew Rate Control 0x0000_0000 PE_SLEWCTL GPIO_BA+0x128 PE High Slew Rate Control...
Page 333 NUC126 Port E High Drive Strength Control (Px_DRVCTL) Register Offset Description Reset Value PE_DRVCTL GPIO_BA+0x12C PE High Drive Strength Control 0x0000_0000 Reserved Reserved Reserved HDRVEN[n] Reserved Bits Description [31:14] Reserved Reserved. Port E Pin[n] Driving Strength Control 0 = Px.n output with basic driving strength. HDRVEN[n] 1 = Px.n output with high driving strength.
Page 334 NUC126 Interrupt De-bounce Control (GPIO_DBCTL) Register Offset Description Reset Value GPIO_DBCTL GPIO_BA+0x180 Interrupt De-bounce Control 0x0000_0020 Reserved Reserved Reserved Reserved ICLKON DBCLKSRC DBCLKSEL Bits Description [31:6] Reserved Reserved. Interrupt Clock on Mode 0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1.
Page 335 NUC126 GPIO Px.n Pin Data Input/Outut (Pxn_PDIO) Register Offset Description Reset Value PAn_PDIO GPIO_BA+0x200+(0x04 * n) GPIO PA.n Pin Data Input/Output 0x0000_000X n=0,1..15 PBn_PDIO GPIO_BA+0x240+(0x04 * n) GPIO PB.n Pin Data Input/Output 0x0000_000X n=0,1..15 PCn_PDIO GPIO_BA+0x280+(0x04 * n) GPIO PC.n Pin Data Input/Output 0x0000_000X n=0,1..15 PDn_PDIO...
Page 336: Hardware Divider (Hdiv)
NUC126 6.10 Hardware Divider (HDIV) 6.10.1 Overview The hardware divider (HDIV) is useful to the high performance application. The hardware divider is a signed, integer divider with both quotient and remainder outputs. 6.10.2 Features  Signed (two’s complement) integer calculation ...
Page 337 NUC126 To use hardware divider, it needs to set dividend first. Then set divisor and the hardware divider will trigger calculation automatically after divisor written. The calculation results including the quotient and remainder could be got by reading DIVQUO and DIVREM register. If CPU reads DIVQUO or DIVREM before hardware divider calculation finishing, CPU will be held until hardware divider finishing the calculation.
Page 338: Register Map
NUC126 6.10.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value HDIV Base Address: HDIV_BA = 0x5001_4000 HDIV_DIVIDEND HDIV_BA+0x00 R/W Dividend Source Register 0x0000_0000 HDIV_DIVISOR HDIV_BA+0x04 R/W Divisor Source Resister 0x0000_FFFF HDIV_DIVQUO HDIV_BA+0x08...
Page 339: Register Description
NUC126 6.10.7 Register Description Dividend Source Register (HDIV_DIVIDEND) Register Offset Description Reset Value HDIV_DIVIDEND HDIV_BA+0x00 Dividend Source Register 0x0000_0000 DIVIDEND DIVIDEND DIVIDEND DIVIDEND Bits Description Dividend Source [31:0] DIVIDEND This register is given the dividend of divider before calculation starting. Aug.
Page 340 NUC126 Divisor Source Register (HDIV_DIVISOR) Register Offset Description Reset Value HDIV_DIVISOR HDIV_BA+0x04 Divisor Source Resister 0x0000_FFFF Reserved Reserved DIVISOR DIVISOR Bits Description [31:16] Reserved Reserved. Divisor Source [15:0] DIVISOR This register is given the divisor of divider before calculation starts. Note: When this register is written, hardware divider will start calculate.
Page 341 NUC126 Quotient Result Register (HDIV_DIVQUO) Register Offset Description Reset Value HDIV_DIVQUO HDIV_BA+0x08 Quotient Result Resister 0x0000_0000 QUOTIENT QUOTIENT QUOTIENT QUOTIENT Bits Description Quotient Result [31:0] QUOTIENT This register holds the quotient result of divider after calculation complete. Aug. 08, 2018 Page 341 of 943 Rev 1.03...
Page 342 NUC126 Remainder Result Register (HDIV_DIVREM) Register Offset Description Reset Value HDIV_DIVREM HDIV_BA+0x0C Remainder Result Register 0x0000_0000 REMAINDER REMAINDER REMAINDER REMAINDER Bits Description Remainder Result The remainder of hardware divider is 16-bit sign integer (REMAINDER[15:0]), which [31:0] REMAINDER holds the remainder result of divider after calculation complete. The remainder of hardware divider with sign extension (REMAINDER[31:16]) to 32-bit integer.
Page 343 NUC126 Divider Status Register (HDIV_DIVSTS) Register Offset Description Reset Value HDIV_DIVSTS HDIV_BA+0x10 Divider Status Register 0x0000_0001 Reserved Reserved Reserved Reserved DIV0 FINISH Bits Description [31:2] Reserved Reserved. Divisor Zero Warning 0 = The divisor is not 0. DIV0 1 = The divisor is 0. Note: The DIV0 flag is used to indicate divide-by-zero situation and updated whenever DIVISOR is written.
Page 344: C Serial Interface Controller (I C)
NUC126 6.11 I C Serial Interface Controller (I 6.11.1 Overview C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. The I C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously.
Page 345: Block Diagram
NUC126 6.11.3 Block Diagram APB Interface Wakeup Control PDMA Control Register Bus Protocol Bus Clock Interface Control Control Figure 6.11-1 I C Controller Block Diagram 6.11.4 Basic Configuration 6.11.4.1 Basic Configuration of I2C0  Clock Source Configuration Enable I2C0 peripheral clock in I2C0CKEN (CLK_APBCLK0[8]). –...
Page 346: Functional Description
NUC126 Reset I2C1 controller in I2C1RST (SYS_IPRST1[9]]). –  Pin Configuration Group Pin Name GPIO PA.8 MFP2 I2C1_SCL PC.4, PC.9, PE.4, PF.3 MFP3 PE.8 MFP4 I2C1 PA.9 MFP2 I2C1_SDA PC.5, PC.10, PE.0, PE.5, PF.4 MFP3 PE.9 MFP4 6.11.5 Functional Description On I C bus, data is transferred between a Master and a Slave.
Page 347: Figure 6.11-3 I 2 C Protocol
NUC126  Slave address and R/W bit transfer  Data transfer  STOP signal generation ADDRESS DATA DATA Figure 6.11-3 I C Protocol START or Repeated START Signal When the bus is free/idle, which means no master device is engaging the bus (both SCL and SDA lines are high), a master can initiate a transfer by sending a START signal.
Page 348: Figure 6.11-5 Bit Transfer On The I C Bus
NUC126 Data Transfer When a slave receives a correct address with an R/W bit, the data will follow R/W bit specified to transfer. Each transferred byte is followed by an acknowledge bit on the 9th SCL clock cycle. If the slave signals a Not Acknowledge (NACK), the master can generate a STOP signal to abort the data transfer or generate a Repeated START signal and start a new transfer cycle.
Page 349: Figure 6.11-7 Master Transmits Data To Slave By 7-Bit
NUC126 SLAVE ADDRESS DATA DATA data transfer ‘0’ : write (n bytes + acknowlegde) from master to slave A = acknowledge (SDA low) A = not acknowledge (SDA high) S = START condition from slave to master P = STOP condition Figure 6.11-7 Master Transmits Data to Slave by 7-bit Figure 6.11-8 shows a master read data from slave by 7-bit.
Page 350: Figure 6.11-9 Control I C Bus According To The Current I C Status
NUC126 Updated Status Last Status STATUS=0x18 STATUS=0x08 I2C_DAT (SLA+W) Register Control I2C_DAT=SLA+W Master to Slave (STA,STO,SI,AA)=(0,0,1,x) Slave to Master Figure 6.11-9 Control I C Bus according to the current I C Status Master Mode In Figure 6.11-10, all possible protocols for I C master are shown.
Page 351: Figure 6.11-11 Master Receiver Mode Control Flow
NUC126 STATUS=0x08 STATUS=0x40 STATUS=0x50 I2C_DAT I2C_DAT (SLA+R) (Data) (STA,STO,SI,AA)=(1,0,1,x) I2C_DAT=SLA+R (STA,STO,SI,AA)=(0,0,1,1) (STA,STO,SI,AA)=(0,0,1,x) (Arbitration Lost) ACK STATUS=0x38 I2C_DAT (Data) (STA,STO,SI,AA)=(0,0,1,0) STATUS=0x58 I2C_DAT (Data) (STA,STO,SI,AA)=(0,0,1,0) STATUS=0x48 STATUS=0x08 (STA,STO,SI,AA)=(1,1,1,x) (Arbitration Lost) STATUS=0x38 STATUS=0xF8 I2C_DAT ACK/ (SLA+R) I2C_DAT=SLA+R (STA,STO,SI,AA)=(0,0,1,X) (STA,STO,SI,AA)=(0,1,1,x) (Arbitration Lost) ACK STATUS=0x10 STATUS= 0x68, 0x78, 0xB0 I2C_DAT (SLA+R)
Page 352: Figure 6.11-12 Slave Mode Control Flow
NUC126 Switch to not addressed mode STATUS=0x60 STATUS=0x80 Own SLA will be recognized I2C_DAT I2C_DAT (Data) (SLA+W) STATUS=0x88 (STA,STO,SI,AA)=(0,0,1,1) (STA,STO,SI,AA)=(0,0,1,1) (Arbitration Lost) STATUS=0x68 I2C_DAT I2C_DAT (Data) (SLA+W) (STA,STO,SI,AA)=(0,0,1,0) STATUS=0xA8 STATUS=0xA0 I2C_DAT (SLA+R) (STA,STO,SI,AA)=(0,0,1,X) (Arbitration Lost) STATUS=0xA0 STATUS=0xB0 I2C_DAT (SLA+R) (STA,STO,SI,AA)=(0,0,1,1) (STA,STO,SI,AA)=(0,0,1,X) STATUS=0xB8 Switch to not addressed mode...
Page 353: Figure 6.11-13 Gc Mode
NUC126 Switch to not addressed mode Address 0x0 will be recognized STATUS=0x70 STATUS=0x90 I2C_DAT I2C_DAT (SLA+W=0x00) (Data) (STA,STO,SI,AA)=(0,0,1,1) GC=1 (STA,STO,SI,AA)=(0,0,1,1) (Arbitration Lost) STATUS=0x78 STATUS=0x98 I2C_DAT I2C_DAT (SLA+W=0x00) (Data) (STA,STO,SI,AA)=(0,0,1,0) STATUS=0xA0 (STA,STO,SI,AA)=(0,0,1,X) STATUS=0xA0 (STA,STO,SI,AA)=(0,0,1,X) (STA,STO,SI,AA)=(0,0,1,1) Switch to not addressed mode Own SLA will be recognized Send START when bus free Become I C Master...
Page 354: Figure 6.11-14 Arbitration Lost
NUC126 SDA signal while the SCL signal is high. Each master checks if the SDA signal on the bus corresponds to the generated SDA signal. If the SDA signal on the bus is low but it should be high, then this master has lost arbitration.
Page 355: Figure 6.11-15 Timing Of Two-Level Buffer Transmit In Master Write
NUC126 empty. 6.11.5.4 Two-level Buffer Mode on I2C bus Set to enable the two-level buffer for I C transmitted or received buffer. It is used to improve the performance of the I C bus. If this TWOBUFEN bit is set = 1, the control bit of STA for repeat start or STO bit should be set as normal operation.
Page 356: Figure 6.11-17 Setup Time Wrong Adjustment
NUC126 C Baud Rate 100k 200k 400k 800k 1200k PCLK 12MHz 24MHz 48MHz 72MHz Table 6.11-1 Relationship between I C Baud Rate and PCLK For setup time wrong adjustment example, we assume one SCL cycle contains 5 PCLKs and set STCTL [5:0] (I2C_TMCTL[5:0]) to 3 that stretch three PCLKs for setup time setting.
Page 357: Figure 6.11-19 I 2 C Data Shifting Direction
NUC126 I2C_ADDRMSKn (address mask registers, n=0~3), I2C_CLKDIV (clock civided register), I2C_TOCTL (Time-out control register), I2C_WKCTL(wake up control register) and I2C_WKSTS(wake up status register). Address Registers (I2C_ADDR) The I C port is equipped with four slave address registers, I2C_ADDRn (n=0~3). The contents of the register irrelevant when...
Page 358: Table 6.11-2 I 2 C Status Code Description
NUC126 I2C_STATUS [7:0] is an 8-bit read-only register. The bit field I2C_STATUS [7:0] contains the status code and there are 26 possible status codes. All states are listed in Table 6.11-2. When I2C_STATUS [7:0] is F8H, no serial interrupt is requested. All other I2C_STATUS [7:0] values correspond to the defined I C states.
Page 359: Figure 6.11-20 I 2 C Time-Out Count Block Diagram
NUC126 counter is enabled, the counter starts up counting until it overflows (TOIF=1) and generates I interrupt to CPU or stops counting by clearing TOCEN to 0. When time-out counter is enabled, writing 1 to the SI flag will reset counter and re-start up counting after SI is cleared. If I C bus hangs up, it causes the I2C_STATUS and flag SI are not updated for a period, the 14-bit time-out counter may overflow and acknowledge CPU the I...
Page 360: Figure 6.11-21 I 2 C Wake-Up Related Signals Waveform
NUC126 PDEN (CLK_PWRCTL[7])=1 CPU Run WFI Instruction WKUPIF WR_STATUS WKACDONE Figure 6.11-21 I C Wake-Up Related Signals Waveform C Control Register 1 (I2C_CTL1) For the TWOBUFEN (I2C_CTL1[5]) bit , it is used to enable the two-level buffer for I C transmitted or received buffer.
Page 361: Figure 6.11-22 Eeprom Random Read
NUC126 ROM ADDRRSS ROM ADDRRSS SLA+W SLA+R DATA BYTE HIGH BYTE LOW BYTE 1 0 1 0 X X X 1 0 1 0 LINE Figure 6.11-22 EEPROM Random Read Figure 6.11-23 shows how to use I C controller to implement the protocol of EEPROM random read. STATUS=0x08 STATUS=0x18 I2C_DAT...
Page 362: Register Map
NUC126 6.11.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value C Base Address: I2Cx_BA = 0x4002_0000 + (0x10_0000 *x) x= 0,1 I2C_CTL I2Cx_BA+0x00 R/W I C Control Register 0 0x0000_0000 I2C_ADDR0 I2Cx_BA+0x04...
Page 363: Register Description
NUC126 6.11.7 Register Description C Control Register (I2C_CTL) Register Offset Description Reset Value I2C_CTL I2Cx_BA+0x00 C Control Register 0 0x0000_0000 Reserved Reserved Reserved INTEN I2CEN Reserved Bits Description [31:8] Reserved Reserved. Enable Interrupt INTEN 0 = I C interrupt Disabled. 1 = I C interrupt Enabled.
Page 364 NUC126 C Data Register (I2C_DAT) Register Offset Description Reset Value I2C_DAT I2Cx_BA+0x08 C Data Register 0x0000_0000 Reserved Reserved Reserved Bits Description [31:8] Reserved Reserved. C Data [7:0] Bit [7:0] is located with the 8-bit transferred/received data of I C serial port. Aug.
Page 365 NUC126 C Status Register (I2C_STATUS) Register Offset Description Reset Value I2C_STATUS I2Cx_BA+0x0C C Status Register 0 0x0000_00F8 Reserved Reserved Reserved STATUS Bits Description [31:8] Reserved Reserved. C Status The three least significant bits are always 0. The five most significant bits contain the status code.
Page 366 NUC126 C Clock Divided Register (I2C_CLKDIV) Register Offset Description Reset Value I2C_CLKDIV I2Cx_BA+0x10 C Clock Divided Register 0x0000_0000 Reserved Reserved Reserved DIVIDER Bits Description [31:8] Reserved Reserved. C Clock Divided Indicates the I C clock rate: Data Baud Rate of I C = (system clock) / (4x [7:0] DIVIDER...
Page 367 NUC126 C Time-out Control Register (I2C_TOCTL) Register Offset Description Reset Value I2C_TOCTL I2Cx_BA+0x14 C Time-out Control Register 0x0000_0000 Reserved Reserved Reserved Reserved TOCEN TOCDIV4 TOIF Bits Description [31:3] Reserved Reserved. Time-out Counter Enable Bit When Enabled, the 14-bit time-out counter will start counting when SI is clear. Setting flag SI to ‘1’...
Page 368 NUC126 C Slave Address Register (ADDRx) Register Offset Description Reset Value I2C_ADDR0 I2Cx_BA+0x04 C Slave Address Register0 0x0000_0000 I2C_ADDR1 I2Cx_BA+0x18 C Slave Address Register1 0x0000_0000 I2C_ADDR2 I2Cx_BA+0x1C C Slave Address Register2 0x0000_0000 I2C_ADDR3 I2Cx_BA+0x20 C Slave Address Register3 0x0000_0000 Reserved Reserved Reserved ADDR...
Page 369 NUC126 C Slave Address Mask Register (ADDRMSKx) Register Offset Description Reset Value I2C_ADDRMSK0 I2Cx_BA+0x24 C Slave Address Mask Register0 0x0000_0000 I2C_ADDRMSK1 I2Cx_BA+0x28 C Slave Address Mask Register1 0x0000_0000 I2C_ADDRMSK2 I2Cx_BA+0x2C C Slave Address Mask Register2 0x0000_0000 I2C_ADDRMSK3 I2Cx_BA+0x30 C Slave Address Mask Register3 0x0000_0000 Reserved Reserved...
Page 370 NUC126 C Wake-up Control Register (I2C_WKCTL) Register Offset Description Reset Value I2C_WKCTL I2Cx_BA+0x3C C Wake-up Control Register 0x0000_0000 Reserved Reserved Reserved NHDBUSEN Reserved WKEN Bits Description [31:8] Reserved Reserved. C No Hold BUS Enable Bit C don’t hold bus after wake-up disable. 0 = I C don’t hold bus after wake-up enable.
Page 371 NUC126 C Wake-up Status Register (I2C_WKSTS) Register Offset Description Reset Value I2C_WKSTS I2Cx_BA+0x40 C Wake-up Status Register 0x0000_0000 Reserved Reserved Reserved Reserved WRSTSWK WKAKDONE WKIF Bits Description [31:3] Reserved Reserved. Read/Write Status Bit in Address Wakeup Frame 0 = Write command be record on the address match wakeup frame. WRSTSWK 1 = Read command be record on the address match wakeup frame.
Page 372 NUC126 C Control Register 1 (I2C_CTL1) Register Offset Description Reset Value I2C_CTL1 I2Cx_BA+0x44 C Control Register 1 0x0000_0000 Reserved Reserved Reserved PDMASTR NSTRETCH TWOBUFRST TWOBUFEN UDRIEN OVRIEN PDMARST RXPDMAEN TXPDMAEN Bits Description [31:9] Reserved Reserved. PDMA Stretch Bit 0 = I C sends STOP automatically after PDMA transfer done.
Page 373 NUC126 PDMA Reset PDMARST 0 = No effect. 1 = Reset the PDMA control logic. This bit will be cleared to 0 automatically. PDMA Receive Channel Available RXPDMAEN 0 = Receive PDMA function Disabled. 1 = Receive PDMA function Enabled. PDMA Transmit Channel Available TXPDMAEN 0 = Transmit PDMA function Disabled.
Page 374 NUC126 C Status Register 1 (I2C_STATUS1) Register Offset Description Reset Value I2C_STATUS1 I2Cx_BA+0x48 C Status Register 1 0x0000_0000 Reserved Reserved Reserved ONBUSY EMPTY FULL Reserved Bits Description [31:9] Reserved Reserved. on Bus Busy Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected.
Page 375 NUC126 C Timing Configure Control Register (I2C_TMCTL) Register Offset Description Reset Value I2C_TMCTL I2Cx_BA+0x4C C Timing Configure Control Register 0x0000_0000 Reserved Reserved Reserved HTCTL HTCTL STCTL Bits Description [31:12] Reserved Reserved. Hold Time Configure Control Register This field is used to generate the delay timing between SCL falling edge and SDA rising [11:6] HTCTL edge in transmission mode.
Page 376: Pdma Controller (Pdma)
NUC126 6.12 PDMA Controller (PDMA) 6.12.1 Overview The peripheral direct memory access (PDMA) controller is used to provide high-speed data transfer. The PDMA controller can transfer data from one address to another without CPU intervention. This has the benefit of reducing the workload of CPU and keeps CPU resources free for other applications. The PDMA controller has a total of 5 channels and each channel can perform transfer between memory and peripherals or between memory and memory.
Page 377: Functional Description
NUC126 6.12.5 Functional Description The PDMA controller transfers data from one address to another without CPU intervention. The PDMA controller supports 5 independent channels and serves only one channel at one time, as the result, PDMA controller supports two level channel priorities: fixed and round-robin priority, PDMA controller serves channel in order from highest to lowest priority channel.
Page 378: Figure 6.12-3 Descriptor Table Operation In Basic Mode
NUC126 6.12.5.2 PDMA Operation Mode The PDMA controller supports two operation modes including Basic mode and Scatter-Gather mode. Basic Mode Basic mode is used to perform one descriptor table transfer mode that shown as Figure 6.12-3. This mode can be used to transfer data between memory and memory or peripherals and memory. PDMA controller operation mode can be set from OPMODE (PDMA_DSCTn_CTL[1:0], n denotes PDMA channel).
Page 379 NUC126 Transfer State OPMODE (PDMA_DSCTn_CTL[1:0]) = 0x1 Next Request Transfer done Idle State OPMODE (PDMA_DSCTn_CTL[1:0]) = 0x0 Figure 6.12-4 Basic Mode Finite State Machine Scatter-Gather Mode Scatter-Gather mode is a complex mode and can perform sophisticated transfer through the use of the description link list table as shown in Figure 6.12-4 Descriptor Table Link List Structure.
Page 380: Figure 6.12-4 Descriptor Table Link List Structure
NUC126 PDMA_SCATBA MSB 16 bits LSB 16 bits 0x2000 0x0100 DSCT_FIRST DSCT_DA DSCT_NEXT 0x2000_020C DSCT_SA DSCT_DA 0x2000_0208 DSCT_CTL Current DSCT4 Entry DSCT_SA 0x2000_0204 DSCT_CTL 0x2000_0200 Next DSCT4 Entry LSB 16 bits 0x0200 DSCT_NEXT 0x2000_010C DSCT4 DSCT_DA 0x2000_0108 DSCT3 DSCT_SA 0x2000_0104 DSCT2 DSCT_CTL 0x2000_0100...
Page 381 NUC126 Through Scatter-Gather mode, user can perform peripheral wrapper-around, multiple PDMA tasks or can be used for data transfer between varied locations in system memory instead of a set of contiguous locations. The Ping-Pong audio buffer for I S can be implemented by the wrapper-around two link list tables. The audio buffer can be divide to two parts that assign to two link list tables for PDMA transfer, then PDMA controller can loop around two buffer for transferring audio data to I S TX buffer.
Page 382: Figure 6.12-6 Example Of Single Transfer Type And Burst Transfer Type In Basic Mode
NUC126 Execution Channel 1 Channel 0 Channel 1 Channel 0 Channel transferred transferred CH1 Request 1 byte data 1 byte data Transferred Transferred CH0 Request 128 words data 128 words data TXCNT (PDMA_DSCTn_CTL[29:16]) TXWIDTH (PDMA_DSCTn_CTL[13:12]) (1 byte) (1 word) BURSIZE Non-useful (PDMA_DSCTn_CTL[6:4]) (128 transfers)
Page 383: Figure 6.12-7 Example Of Pdma Channel 0 Time-Out Counter Operation
NUC126 Time-out clock (HCLK/2^8) TOUTPSC0 (PDMA_TOUTPSC[2:0]) TOC0 (PDMA_TOC0_1[15:0]) 0 1 2 3 0 1 2 3 4 5 0 1 2 3 Time-out counter TOUTEN0 (PDMA_TOUTEN[0]) Peripheral request REQTOF0 (PDMA_INTSTS[8]) Figure 6.12-7 Example of PDMA Channel 0 Time-out Counter Operation Aug.
Page 384: Register Map
NUC126 6.12.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value PDMA Base Address: PDMA_BA = 0x5000_8000 Descriptor Table Control Register of PDMA Channel PDMA_DSCT0_CTL PDMA_BA + 0x000 0xXXXX_XXXX PDMA_DSCT0_SA PDMA_BA + 0x004 R/W Source Address Register of PDMA Channel 0 0xXXXX_XXXX PDMA_DSCT0_DA PDMA_BA + 0x008...
Page 385 NUC126 Current Scatter-Gather Descriptor Table Address of PDMA_CURSCAT4 PDMA_BA + 0x060 0xXXXX_XXXX PDMA Channel 4 PDMA_CHCTL PDMA_BA + 0x400 R/W PDMA Channel Control Register 0x0000_0000 PDMA_PAUSE PDMA_BA + 0x404 PDMA Transfer Pause Control Register 0x0000_0000 PDMA_SWREQ PDMA_BA + 0x408 PDMA Software Request Register 0x0000_0000 PDMA_TRGSTS PDMA_BA + 0x40C...
Page 386: Register Description
NUC126 6.12.7 Register Description PDMA Descriptor Table Control Register (PDMA_DSCTn_CTL) Register Offset Description Reset Value PDMA_DSCT0_CTL PDMA_BA + 0x000 Descriptor Table Control Register of PDMA Channel 0 0xXXXX_XXXX PDMA_DSCT1_CTL PDMA_BA + 0x010 Descriptor Table Control Register of PDMA Channel 1 0xXXXX_XXXX PDMA_DSCT2_CTL PDMA_BA + 0x020 Descriptor Table Control Register of PDMA Channel 2 0xXXXX_XXXX...
Page 387 NUC126 Destination Address Increment This field is used to set the destination address increment size. [11:10] DAINC 11 = No increment (fixed address). Others = Increment and size is depended on TXWIDTH selection. Source Address Increment This Field Is Used To Set The Source Address Increment Size. [9:8] SAINC 11 = No Increment (Fixed Address).
Page 388 NUC126 Source Address Register (PDMA_DSCTn_SA) Register Offset R/W Description Reset Value PDMA_DSCT0_SA PDMA_BA + 0x004 R/W Source Address Register of PDMA Channel 0 0xXXXX_XXXX PDMA_DSCT1_SA PDMA_BA + 0x014 R/W Source Address Register of PDMA Channel 1 0xXXXX_XXXX PDMA_DSCT2_SA PDMA_BA + 0x024 R/W Source Address Register of PDMA Channel 2 0xXXXX_XXXX PDMA_DSCT3_SA...
Page 389 NUC126 Destination Address Register (PDMA_DSCTn_DA) Register Offset R/W Description Reset Value PDMA_DSCT0_DA PDMA_BA + 0x008 R/W Destination Address Register of PDMA Channel 0 0xXXXX_XXXX PDMA_DSCT1_DA PDMA_BA + 0x018 R/W Destination Address Register of PDMA Channel 1 0xXXXX_XXXX PDMA_DSCT2_DA PDMA_BA + 0x028 R/W Destination Address Register of PDMA Channel 2 0xXXXX_XXXX PDMA_DSCT3_DA...
Page 390 NUC126 First Scatter-Gather Descriptor Table Offset (PDMA_DSCTn_FIRST) Register Offset R/W Description Reset Value First Scatter-Gather Descriptor Table Offset of PDMA PDMA_DSCT0_FIRST PDMA_BA + 0x00C 0xXXXX_XXXX Channel 0 First Scatter-Gather Descriptor Table Offset of PDMA PDMA_DSCT1_FIRST PDMA_BA + 0x01C 0xXXXX_XXXX Channel 1 First Scatter-Gather Descriptor Table Offset of PDMA PDMA_DSCT2_FIRST PDMA_BA + 0x02C...
Page 391 NUC126 Current Scatter-Gather Descriptor Table Address (PDMA_CURSCATn) Register Offset R/W Description Reset Value Current Scatter-Gather Descriptor Table Address of PDMA_CURSCAT0 PDMA_BA + 0x050 0xXXXX_XXXX PDMA Channel 0 Current Scatter-Gather Descriptor Table Address of PDMA_CURSCAT1 PDMA_BA + 0x054 0xXXXX_XXXX PDMA Channel 1 Current Scatter-Gather Descriptor Table Address of PDMA_CURSCAT2 PDMA_BA + 0x058 0xXXXX_XXXX...
Page 392 NUC126 Channel Control Register (PDMA_CHCTL) Register Offset R/W Description Reset Value PDMA_CHCTL PDMA_BA + 0x400 R/W PDMA Channel Control Register 0x0000_0000 Reserved Reserved Reserved Reserved CHEN4 CHEN3 CHEN2 CHEN1 CHEN0 Bits Description [31:5] Reserved Reserved. PDMA Channel N Enable Bit Set this bit to 1 to enable PDMAn operation.
Page 393 NUC126 PDMA Transfer Pause Control Register (PDMA_PAUSE) Register Offset R/W Description Reset Value PDMA_PAUSE PDMA_BA + 0x404 PDMA Transfer Pause Control Register 0x0000_0000 Reserved Reserved Reserved Reserved PAUSE4 PAUSE3 PAUSE2 PAUSE1 PAUSE0 Bits Description [31:5] Reserved Reserved. PDMA Channel N Transfer Pause Control Register (Write Only) User can set PAUSEn bit field to pause the PDMA transfer.
Page 394 NUC126 PDMA Software Request Register (PDMA_SWREQ) Register Offset R/W Description Reset Value PDMA_SWREQ PDMA_BA + 0x408 PDMA Software Request Register 0x0000_0000 Reserved Reserved Reserved Reserved SWREQ4 SWREQ3 SWREQ2 SWREQ1 SWREQ0 Bits Description [31:5] Reserved Reserved. PDMA Channel N Software Request Register (Write Only) Set this bit to 1 to generate a software request to PDMA [n].
Page 395 NUC126 PDMA Channel Request Status Register (PDMA_TRGSTS) Register Offset R/W Description Reset Value PDMA_TRGSTS PDMA_BA + 0x40C PDMA Channel Request Status Register 0x0000_0000 Reserved Reserved Reserved Reserved REQSTS4 REQSTS3 REQSTS2 REQSTS1 REQSTS0 Bits Description [31:5] Reserved Reserved. PDMA Channel N Request Status (Read Only) This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral.
Page 396 NUC126 PDMA Fixed Priority Setting Register (PDMA_PRISET) Register Offset R/W Description Reset Value PDMA_PRISET PDMA_BA + 0x410 R/W PDMA Fixed Priority Setting Register 0x0000_0000 Reserved Reserved Reserved Reserved FPRISET4 FPRISET3 FPRISET2 FPRISET1 FPRISET0 Bits Description [31:5] Reserved Reserved. PDMA Channel N Fixed Priority Setting Register Set this bit to 1 to enable fixed priority level.
Page 397 NUC126 PDMA Fixed Priority Clear Register (PDMA_PRICLR) Register Offset R/W Description Reset Value PDMA_PRICLR PDMA_BA + 0x414 PDMA Fixed Priority Clear Register 0x0000_0000 Reserved Reserved Reserved Reserved FPRICLR4 FPRICLR3 FPRICLR2 FPRICLR1 FPRICLR0 Bits Description [31:5] Reserved Reserved. PDMA Channel N Fixed Priority Clear Register (Write Only) Set this bit to 1 to clear fixed priority level.
Page 398 NUC126 PDMA Interrupt Enable Register (PDMA_INTEN) Register Offset R/W Description Reset Value PDMA_INTEN PDMA_BA + 0x418 R/W PDMA Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved INTEN4 INTEN3 INTEN2 INTEN1 INTEN0 Bits Description [31:12] Reserved Reserved. PDMA Channel N Interrupt Enable Register This field is used for enabling PDMA channel[n] interrupt.
Page 399 NUC126 PDMA Interrupt Status Register (PDMA_INTSTS) Register Offset R/W Description Reset Value PDMA_INTSTS PDMA_BA + 0x41C R/W PDMA Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved REQTOF1 REQTOF0 Reserved TEIF TDIF ABTIF Bits Description [31:13] Reserved Reserved. PDMA Channel N Request Time-out Flag This flag indicates that PDMA controller has waited peripheral request for a period [n+8] defined by PDMA_TOCn, user can write 1 to clear these bits.
Page 400 NUC126 PDMA Channel Read/Write Target Abort Flag Register (PDMA_ABTSTS) Register Offset R/W Description Reset Value PDMA Channel Read/Write Target Abort Flag PDMA_ABTSTS PDMA_BA + 0x420 0x0000_0000 Register Reserved Reserved Reserved Reserved ABTIF4 ABTIF3 ABTIF2 ABTIF1 ABTIF0 Bits Description [31:5] Reserved Reserved.
Page 401 NUC126 PDMA Channel Transfer Done Flag Register (PDMA_TDSTS) Register Offset R/W Description Reset Value PDMA_TDSTS PDMA_BA + 0x424 R/W PDMA Channel Transfer Done Flag Register 0x0000_0000 Reserved Reserved Reserved Reserved TDIF4 TDIF3 TDIF2 TDIF1 TDIF0 Bits Description [31:5] Reserved Reserved. PDMA Channel N Transfer Done Flag Register This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
Page 402 NUC126 PDMA Scatter-Gather Table Empty Status Register (PDMA_SCATSTS) Register Offset R/W Description Reset Value PDMA_SCATSTS PDMA_BA + 0x428 R/W PDMA Scatter-Gather Table Empty Status Register 0x0000_0000 Reserved Reserved Reserved Reserved TEMPTYF4 TEMPTYF3 TEMPTYF2 TEMPTYF1 TEMPTYF0 Bits Description [31:5] Reserved Reserved. Table Empty Flag Register T This bit indicates which PDMA channel table is empty when channel have a request , no matter request from software or peripheral, but operation mode of channel descriptor...
Page 403 NUC126 PDMA Transfer Active Flag Register (PDMA_TACTSTS) Register Offset R/W Description Reset Value PDMA_TACTSTS PDMA_BA + 0x42C PDMA Transfer Active Flag Register 0x0000_0000 Reserved Reserved Reserved Reserved TXACTF4 TXACTF3 TXACTF2 TXACTF1 TXACTF0 Bits Description [31:5] Reserved Reserved. PDMA Channel N Transfer on Active Flag Register (Read Only) This bit indicates which PDMA channel is in active.
Page 404 NUC126 PDMA Time-out Prescaler Register (PDMA_TOUTPSC) Register Offset R/W Description Reset Value PDMA_TOUTPSC PDMA_BA + 0x430 R/W PDMA Time-out Prescaler Register 0x0000_0000 Reserved Reserved Reserved Reserved TOUTPSC1 Reserved TOUTPSC0 Bits Description [31:7] Reserved Reserved. PDMA Channel 1 Time-out Clock Source Prescaler Bits 000 = PDMA channel 1 time-out clock source is HCLK/2 001 = PDMA channel 1 time-out clock source is HCLK/2 010 = PDMA channel 1 time-out clock source is HCLK/2...
Page 405 NUC126 PDMA Time-out Enable Register (PDMA_TOUTEN) Register Offset R/W Description Reset Value PDMA_TOUTEN PDMA_BA + 0x434 R/W PDMA Time-out Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved TOUTEN1 TOUTEN0 Bits Description [31:2] Reserved Reserved. PDMA Channel N Time-out Enable Bit TOUTENn 0 = PDMA Channel n time-out function Disabled.
Page 406 NUC126 PDMA Time-out Interrupt Enable Register (PDMA_TOUTIEN) Register Offset R/W Description Reset Value PDMA_TOUTIEN PDMA_BA + 0x438 R/W PDMA Time-out Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved TOUTIEN1 TOUTIEN0 Bits Description [31:2] Reserved Reserved. PDMA Channel N Time-out Interrupt Enable Bit TOUTIENn 0 = PDMA Channel n time-out interrupt Disabled.
Page 407 NUC126 PDMA Scatter-Gather Descriptor Table Base Address Register (PDMA_SCATBA) Register Offset R/W Description Reset Value PDMA Scatter-Gather Descriptor Table Base Address PDMA_SCATBA PDMA_BA + 0x43C 0x2000_0000 Register SCATBA SCATBA Reserved Reserved Bits Description PDMA Scatter-gather Descriptor Table Address Register In Scatter-Gather mode, this is the base address for calculating the next link - list address.
Page 408 NUC126 PDMA Channel 0 and Channel 1 Time-out Counter Register (PDMA_TOC0_1) Register Offset R/W Description Reset Value PDMA Channel 0 and Channel 1 Time-out Counter PDMA_TOC0_1 PDMA_BA + 0x440 0x0000_0000 Register TOC1 TOC1 TOC0 TOC0 Bits Description Time-out Counter for Channel 1 This controls the period of time-out function for channel 1.
Page 409 NUC126 PDMA Channel Reset Control Register (PDMA_RESET) Register Offset R/W Description Reset Value PDMA_RESET PDMA_BA + 0x460 R/W PDMA Channel Reset Control Register 0x0000_0000 Reserved Reserved Reserved Reserved RESET4 RESET3 RESET2 RESET1 RESET0 Bits Description [31:5] Reserved Reserved. PDMA Channel N Reset Control Register User can set this bit field to reset the PDMA channel.
Page 410 NUC126 PDMA Channel 0 to Channel 3 Request Source Select Register (PDMA_REQSEL0_3) Register Offset R/W Description Reset Value PDMA Channel 0 to Channel 3 Request Source PDMA_REQSEL0_3 PDMA_BA + 0x480 0x0000_0000 Select Register Reserved REQSRC3 Reserved REQSRC2 Reserved REQSRC1 Reserved REQSRC0 Bits Description...
Page 411 NUC126 Bits Description 5 = Channel connects to UART0_RX. 6 = Channel connects to UART1_TX. 7 = Channel connects to UART1_RX. 8 = Channel connects to UART2_TX. 9 = Channel connects to UART2_RX. 16 =Channel connects to SPI0_TX. 17 = Channel connects to SPI0_RX. 18 = Channel connects to SPI1_TX.
Page 412 NUC126 PDMA Channel 4 Request Source Select Register (PDMA_REQSEL4) Register Offset R/W Description Reset Value PDMA_REQSEL4 PDMA_BA + 0x484 R/W PDMA Channel 4 Request Source Select Register 0x0000_0000 Reserved Reserved Reserved Reserved REQSRC4 Bits Description [31:6] Reserved Reserved. Channel 4 Request Source Selection This filed defines which peripheral is connected to PDMA channel 4.
Page 413: Pwm Generator And Capture Timer (Pwm)
NUC126 6.13 PWM Generator and Capture Timer (PWM) 6.13.1 Overview The NUC126 provides two PWM generator: PWM0 and PWM1 as Figure 6.13-1. Each PWM supports 6 channels of PWM output or input capture. There is a 12-bit prescaler to support flexible clock to the 16-bit PWM counter with 16-bit comparator.
Page 414 NUC126  Supports interrupt on the following events: PWM zero point, period point, up-count compared or down-count compared point – events Brake condition happened –  Supports trigger ADC on the following events: PWM zero point, period point, zero or period point, up-count compared point, down- –...
Page 415: Block Diagram
NUC126 6.13.3 Block Diagram PWM0_SYNC_OUT PWM0_SYNC_IN PWM0_BRAKE0 BK0SRC(PWM_BNF[16]) SYNC_IN NVIC_MUX PWM0_CH0 PWM0_BRAKE1 BK1SRC(PWM_BNF[24]) PWM0 CLOCK PWM0_CH5 CONTROLLER TIMER0 PDMA TIMER1 SYNC_OUT TIMER2 TIMER3 ACMP Clock Fail Brown-Out Detect SYNC_IN SYNC_IN ADC result monitor PWM1_CH0 CPU Lockup Brake Source PWM1 PWM1_BRAKE0 BK0SRC(PWM_BNF[16]) PWM1_CH5 PWM1_BRAKE1...
Page 416: Figure 6.13-3 Pwm Clock Source Control
NUC126 PWM System Clock/HCLK HCLKSEL HCLKDIV PWM0SEL Frequency Ratio (CLK_CLKSEL0[2:0]) (CLK_CLKDIV0[3:0]) (CLK_CLKSEL2[0] Don’t care Don’t care Table 6.13-1 PWM System Clock Source Control Registers Setting Table ECLKSRC0 (PWM_CLKSRC[2:0]) ECLKSRC2 (PWM_CLKSRC[10:8]) ECLKSRC4 (PWM_CLKSRC[18:16]) PWMx system clock TMR0_INT TRGPWM(TIMER0_TRGCTL[1]) PWMx_CLK0 TMR1_INT PWMx_CLK2 PWMx_CLK4 TRGPWM(TIMER1_TRGCTL[1]) TMR2_INT...
Page 417: Figure 6.13-4 Pwm Independent Mode Architecture Diagram
NUC126 PWM0_BRAKE0 Interrupt Interrupt events IRQ_MUX Generator Trigger Trigger events Generator PWM0_BRAKE1 PWM0_CLK0 Prescaler0 Counter0 PWM0_CH0 Pulse Output 12bits 16bits Generator0 Control0 Comparator0 PWM0_BRAKE0 16bits PWM0_BRAKE1 Counter1 PWM0_CH1 Pulse Output 16bits Generator1 Control1 Comparator1 PWM0_BRAKE0 16bits PWM0_BRAKE1 PWM0_CLK2 Prescaler2 Counter2 PWM0_CH2 Pulse Output...
Page 418: Basic Configuration
NUC126 PWM0_BRAKE0 Interrupt Events Interrupt IRQ_MUX Generator PWM0_BRAKE1 Trigger Events Trigger Generator Free Trigger Comparator0 PWM0_SYNC_IN PWM0_CH0 Comparator0 PWM0_CLK0 Prescaler0 Pulse Output Counter0 12bits Generator0 Control0 PWM0_CH1 Comparator1 PWM0_BRAKE0 Free Trigger PWM0_BRAKE1 Comparator2 PWM0_CH2 Comparator2 PWM0_CLK2 Prescaler2 Pulse Output Counter2 12bits Generator2 Control2...
Page 419: Functional Description
NUC126 PWM0_CH0 PC.0, PE.0 MFP6 PWM0_CH1 PC.1, PE.1 MFP6 PWM0_CH2 PB.8, PC.2, PE.2 MFP6 PWM0_CH3 PC.3, PE.3 MFP6 PWM0_CH4 PC.4 MFP6 PWM0_CH5 PC.5, PD.6, PD.7 MFP6 PD.1 MFP2 PWM0_SYNC_IN PD.7 MFP3 PWM0_SYNC_OUT PB.1 MFP6 6.13.4.2 Basic Configuration of PWM1  Clock source Configuration Select the source of PWM1 peripheral clock on PWM1SEL (CLK_CLKSEL1[29]).
Page 420: Figure 6.13-6 Pwm0_Ch0 Prescaler Waveform In Up Counter Type
NUC126 PWM0_CLK CLKPSC (PWM_CLKPSC0_1[11:0]) CNTEN0 (PWM_CNTEN[0]) 5 4 3 2 1 3 2 1 0 4 3 2 1 0 4 3 2 1 0 4 3 2 1 0 Prescale counter (PWM_CNT0[15:0]) Figure 6.13-6 PWM0_CH0 Prescaler Waveform in Up Counter Type 6.13.5.2 PWM Counter PWM supports 3 counter types operation: Up Counter, Down Counter and Up-Down Counter types.
Page 421: Figure 6.13-8 Pwm Down Counter Type
NUC126 PERIOD = 5 PERIOD = 8 PERIOD = 8 (PWM_CNTn[15:0]) PWM Period PWM Period PWM Period CNTENn (PWM_CNTEN[n]) zero point event period point event Note: n denotes channel 0,1..5 Figure 6.13-8 PWM Down Counter Type 6.13.5.5 Up-Down Counter Type When PWM counter is set to up-down count type, CNTTYPEn (PWM_CTL1[2n+1:2n], n = 0,1..5) is 0x2, it starts counting-up from zero to PERIOD and then starts counting down to zero to complete a PWM period.
Page 422: Figure 6.13-10 Pwm Compared Point Events In Up-Down Counter Type
NUC126 0,2,4, m = 1,3,5) registers are continuously compared to the complementary even channel’s counter value, because of odd channel’s counter is useless. For example, channel 0 and channel 1 are complementary channels, in Complementary mode, channel 1’s comparator is continuously compared to channel 0’s counter, but not channel 1’s.
Page 423: Figure 6.13-11 Pwm Double Buffering Illustration
NUC126 Load from PERIOD to PBUF, from FTCMPDAT to FTCMPBUF Initialize Load from CMPDAT start S/W Write CMPDAT S/W Write PERIOD to CMPBUF PERIOD PBUF CMPDAT CMPBUF FTCMPDAT FTCMPBUF S/W Write FTCMPDAT CMPU CMPD FTCMPU FTCMPD Figure 6.13-11 PWM Double Buffering Illustration 6.13.5.8 Period Loading Mode When immediately loading mode, window loading mode and center loading mode are disabled that IMMLDENn bits, WINLDENn bits and CTRLDn bits of PWM_CTL0 register are set to 0, PWM operates...
Page 424: Figure 6.13-12 Period Loading In Up-Count Mode
NUC126 point 1 point 2 point 3 point 4 point 5 point 6 PERIOD PERIOD DATA0 PERIOD DATA1 PERIOD DATA2 PBUF PERIOD DATA0 PERIOD DATA1 PERIOD DATA2 CMPDAT CMPDAT DATA1 CMPDAT DATA1 CMPBUF PERIOD DATA1 PERIOD DATA0 PERIOD DATA2 CMPDAT DATA1 CMPDAT DATA0 CMPU Note:...
Page 425: Figure 6.13-13 Immediately Loading In Up-Count Mode
NUC126 point 1 point 2 point 3 PERIOD PERIOD DATA0 PERIOD DATA1 PERIOD DATA2 PBUF PERIOD DATA0 PERIOD DATA1 PERIOD DATA2 CMPDAT CMPDAT DATA1 CMPBUF CMPDAT DATA1 CNT wraparound 0xFFFF PERIOD DATA1 PERIOD DATA0 CMPDAT DATA1 PERIOD DATA2 CMPDAT DATA0 CMPU Note: Write...
Page 426: Figure 6.13-14 Window Loading In Up-Count Mode
NUC126 point 3 point 7 point 1 point 2 point 4 point 5 point 6 point 8 point 9 PERIOD PERIOD DATA0 PERIOD DATA 3 PERIOD DATA2 PERIOD DATA1 PBUF PERIOD DATA0 PERIOD DATA1 PERIOD DATA2 PERIOD DATA3 CMPDAT CMPDAT DATA1 CMPBUF CMPDAT DATA0 CMPDAT DATA1...
Page 427: Figure 6.13-15 Center Loading In Up-Down-Count Mode
NUC126 point 1 point 2 point 3 point 4 point 5 point 6 point 7 point 8 PERIOD PERIOD DATA0 PERIOD DATA1 PERIOD DATA2 PBUF PERIOD DATA0 PERIOD DATA1 PERIOD DATA2 CMPDAT CMPDAT DATA1 CMPDAT DATA2 CMPBUF CMPDAT DATA0 CMPDAT DATA1 CMPDAT DATA2 PERIOD DATA1 PERIOD DATA0...
Page 428: Figure 6.13-16 Pwm One-Shot Mode Output Waveform
NUC126 point 1 point 2 point 3 point 4 point 5 point 6 PERIOD DATA1 Continuous one- One-shot shot PERIOD DATA0 CMPDAT DATA3 CMPDAT DATA0 PWM OUT Note: Write Load Figure 6.13-16 PWM One-shot Mode Output Waveform In Auto-reload mode, CMPDAT and PERIOD registers should be written first and then the CNTENn(PWM_CNTEN[n]) bit is set to 1 to enable PWM prescaler and start to run counter.
Page 429: Figure 6.13-17 Pwm Pulse Generation
NUC126 Center Center CMPDATm CMPDATm CMPDATn CMPDATn Zero Zero PWM OUT PWM OUT PWM period PWM period Note: 1. Zero = L Note: 1. Zero = H 2. CMPUn = X 2. CMPUn = T 3. CMPUm = H 3. CMPUm = H 4.
Page 430: Figure 6.13-19 Pwm Independent Mode Waveform
NUC126 Priority Down Event 1 (Highest) Zero event (CNT = zero) Compare down event of odd channel (CNT = CMPDm) Compare down event of even channel (CNT = CMPDn) 4 (Lowest) Period event (CNT = PERIOD) Table 6.13-3 PWM Pulse Generation Event Priority for Down-Counter Priority Up Event Down Event...
Page 431: Figure 6.13-20 Pwm Complementary Mode Waveform
NUC126 6.13.5.16 Complementary Mode Complementary mode enabled when pair channel corresponding PWMMODEn (PWM_CTL1[26:24]) bit set to 1. In this mode there are 3 PWM generators utilized for complementary mode, with total of 3 PWM output paired pins in this module. In Complimentary modes, the internal odd PWM signal must always be the complement of the corresponding even PWM signal.
Page 432: Figure 6.13-21 Pwm Group Function Waveform
NUC126 Setting: GROUPEN (PWMx_CTL0[24]) = 0x1 Setting: OUTMODE0 (PWMx_CTL1[24]) = 0x1 PWMx_CH0 PWMx_CH1 Setting: OUTMODE2 (PWMx_CTL1[25]) = 0x1 PWMx_CH2 PWMx_CH3 Setting: OUTMODE4 (PWMx_CTL1[26]) = 0x1 PWMx_CH4 PWMx_CH5 Figure 6.13-21 PWM Group Function Waveform 6.13.5.19 Synchronous function Synchronous function can only be enabled when complementary mode is enabled. Figure 6.13-23 is counter synchronous function block diagram.
Page 433: Figure 6.13-23 Pwm Counter Synchronous Function Block Diagram
NUC126 The SINSRCn (PWM_SYNC[13:8]) bits can be used to select the synchronize source. When SINSRCn bits is set to 0, PWM0_SYNC_IN pin “OR” set SWSYNCn (PWM_SWSYNC[2:0]) to 1 can generate SYNC_IN signal for the next counter’s synchronization . Synchronizing source can also be selected as CNT = 0 or CNT = PWM_CMPDATm register (if being the up-down counter type, it will synchronize twice in a PWM period) to trigger a sync event or to disable SYNC_OUT signal.
Page 434: Figure 6.13-24 Pwm Synchronous Function With Synchronize Source From Sync_In Signal
NUC126 PERIOD = 900 (PWM_PERIOD0[15:0]) CMP = 600 (PWM_CMPDAT0[15:0]) PHSDIR0 = 1 (PWM_SYNC[24]) PHS = 0 (PWM_PHS0_1) PWM SYNC input PWMx_CH0 PERIOD = 900 PWM period PWM period PWM period (PWM_PERIOD2[15:0]) CMP = 600 (CMPDAT2[15:0]) PHSDIR2 = 0 (PWM_SYNC[25]) PHS = 600 (PWM_PHS2_3) PWMx_CH2 PERIOD = 900...
Page 435: Figure 6.13-26 Pwmx_Ch0 And Pwmx_Ch1 Output Control In Complementary Mode
NUC126 Complementary Mode Dead Time Insertion Control PWMx_CH0 Independent Mode Pulse Dead Time Four Steps Generation 12-bits PWMx_CH1 Dead Time Independent Mode 12-bits Four Steps DTEN (PWM_DTCTL0_1[16]) DTCNT (PWM_DTCTL0_1[11:0]) Figure 6.13-26 PWMx_CH0 and PWMx_CH1 Output Control in Complementary Mode 6.13.5.21 Dead-Time Insertion In the complementary application, the complement channels may drive the external devices like power switches.
Page 436: Figure 6.13-28 Illustration Of Mask Control Waveform
NUC126 these settings, the PWM channel outputs can be assigned to specified logic states independent of the duty cycle comparison units. The PWM mask bits are useful when controlling various types of Electrically Commutated Motor (ECM) like a BLDC motor. The PWM_MSKEN register contains six bits, MSKENn(PWM_MSKEN[5:0]).
Page 437: Figure 6.13-29 Brake Noise Filter Block Diagram
NUC126 BRKxNFSEL (PWM_BNF[3:1] for BKP0) (PWM_BNF[11:9] for BKP1) BRKxFCNT HCLK BRKxPINV (PWM_BNF[6:4] for BKP0) HCLK/2 (PWM_BNF[7] for BKP0) (PWM_BNF[14:12] for BKP1) HCLK/4 (PWM_BNF[15] for BKP1) HCLK/8 Sampling Clock HCLK/16 Brake Source HCLK/32 Noise filter HCLK/64 counter 3-bits HCLK/128 PWMx_BRAKEy BRKxNFEN (PWM_BNF[0] for BKP0) Note: x,y denotes 0 or 1 (PWM_BNF[8] for BKP1)
Page 438: Figure 6.13-30 Brake Block Diagram For Pwmx_Ch0 And Pwmx_Ch1 Pair
NUC126 BRKEIF0 or BRKEIF1 (PWM_INTSTS1[1:0]) Edge Detect Edge Detect Brake Interrupt Brake Source BRKEIEN0_1 (PWM_INTEN1[0]) BRK_INT BRKLIF0 or BRKLIF1 (PWM_INTSTS1[9:8]) Level Detect Brake Interrupt BRKLIEN0_1 (PWM_INTEN1[8]) BRKLSTS0 (PWM_INTSTS1[24]) BRKAEVEN BRKESTS0 (PWM_BRKCTL0_1[17:16]) (PWM_INTSTS1[16]) PWMx_CH0 Level Detect Low level Brake Source detection PWMx_CH1 BRKAODD BRKESTS1(PWM_INTSTS1[17])
Page 439: Figure 6.13-31 Edge Detector Waveform For Pwmx_Ch0 And Pwmx_Ch1 Pair
NUC126 Setting: BRKAEVEN = 3 (High) BRKAODD = 2 (Low) Edge Detect Brake Source BRKEIF0 s/w clear PWM_INTSTS1[0] BRKEIF1 s/w clear PWM_INTSTS1[1] BRKESTS0 PWM_INTSTS1[16] BRKESTS1 PWM_INTSTS1[17] PWMx_CH0 PWMx_CH1 PWMx_CH0 signals resume at the next PWMx_CH1 signals resume at the next start of PWM period after BRKEIF0 is start of PWM period after BRKEIF1 is cleared...
Page 440: Figure 6.13-33 Brake Source Block Diagram
NUC126 specified to several different system fail conditions. These conditions include clock fail, Brown-out ® detect and Cortex -M0 lockup. Figure 6.13-34 shows that by setting corresponding enable bits, the enabled system fail condition can be one of the sources to issue the Brake system fail to the PWM brake.
Page 441: Figure 6.13-35 Pwm Leb Function Waveform
NUC126 from LEBCNT+1 to 0, the counter clock base is ECLK. If new trigger event occur, blanking counter will reset to LEBCNT and down count again. LEB trigger edge can be rising, falling or both rising and falling edge by setting TRGTYPE (PWM_LEBCTL[17:16]) bits. Figure 6.13-35 shows that LEB will blank leading edge caused by PWMx_CH0 and PWMx_CH4.
Page 442: Figure 6.13-36 Initial State And Polarity Control With Rising Edge Dead-Time Insertion
NUC126 Initial State PWM Starts PWMx_CH0 PWMx_CH1 PWMx_CH0 (PINV0=0) PWMx_CH1 (PINV1=0) PWMx_CH0 (PINV0=1) PWMx_CH1 (PINV1=0) PWMx_CH0 (PINV0=0) PWMx_CH1 (PINV1=1) (PINV0=1) PWMx_CH0 (PINV1=1) PWMx_CH1 Dead-time insertion; It is only effective in complementary mode Note: PINVx: Negative Polarity control bits; It controls the PWM output initial state and polarity, x denotes 0 or 1.
Page 443: Figure 6.13-37 Pwmx_Ch0 And Pwmx_Ch1 Pair Accumulate Interrupt Waveform
NUC126 PERIOD (PWM_PERIOD0[15:0]) IFAEN0_1 (PWM_IFA[7]) IFCNT0_1 (PWM_IFA[3:0]) IFSEL0_1 (PWM_IFA[6:4]) (PWM_CNT0[15:0]) zero point event IFAIF0_1 (PWM_INTSTS0[7]) Figure 6.13-37 PWMx_CH0 and PWMx_CH1 Pair Accumulate Interrupt Waveform The 2 interrupt is the capture interrupt (CAP_INT). It shares the PWM_INT vector in NVIC. The CAP_INT can be generated when the CRLIFn (PWM_CAPIF[5:0]) flag is triggered and the Capture Rising Interrupt Enable bit CAPRIENn (PWM_CAPIEN[5:0]) is set to 1.
Page 444: Figure 6.13-38 Pwmx_Ch0 And Pwmx_Ch1 Pair Interrupt Architecture Diagram
NUC126 ZIF0 (PWM_INTSTS0[0]) ZIEN0 (PWM_INTEN0[0]) PIF0 (PWM_INTSTS0[8]) PIEN0 (PWM_INTEN0[8]) CMPUIF0 (PWM_INTSTS0[16]) CMPUIEN0 (PWM_INTEN0[16]) CMPDIF0 (PWM_INTSTS0[24]) CMPDIEN0 (PWM_INTEN0[24]) ZIF1 (PWM_INTSTS0[1]) ZIEN1 (PWM_INTEN0[1]) PIF1 (PWM_INTSTS0[9]) PIEN1 (PWM_INTEN0[9]) CMPUIF1 (PWM_INTSTS0[17]) CMPUIEN1 (PWM_INTEN0[17]) IFAEN0_1 (PWM_IFA[7]) CMPDIF1 (PWM_INTSTS0[25]) CMPDIEN1 (PWM_INTEN0[25]) PWM_INT IFSEL0_1 (PWM_IFA[6:4]) PWM_CH0 zero point IFAIEN0_1 (PWM_INTEN0[7]) PWM_CH0 period point...
Page 445: Figure 6.13-39 Pwmx_Ch0 And Pwmx_Ch1 Pair Trigger Adc Block Diagram
NUC126 6.13.5.27 PWM Trigger ADC Generator PWM can be one of the ADC conversion trigger source. Each PWM pair channels share the same trigger source. Setting TRGSELn bit of PWM_ADCTS0 and PWM_ADCTS1 registers is to select the trigger sources, where TRGSELn bit is TRGSEL0, TRGSEL1, …, and TRGSEL5, which are located in PWM_ADCTS0[3:0], PWM_ADCTS0[11:8], PWM_ADCTS0[19:16],...
Page 446: Figure 6.13-40 Pwm Trigger Adc In Up-Down Counter Type Timing Waveform
NUC126 PWM_PERIODn PWM_CMPDATn PWM_FTCMPDATn PWM_CNTn zero point trigger period point trigger CMPU point trigger CMPD point trigger FTCMPU point trigger FTCMPD point trigger Figure 6.13-40 PWM Trigger ADC in Up-Down Counter Type Timing Waveform 6.13.5.28 Capture Operation The channels of the capture input and the PWM output share the same pin and counter. The counter can operate in up or down counter type.
Page 447: Figure 6.13-41 Pwmx_Ch0 Capture Block Diagram
NUC126 PERIOD (PWM_PERIOD0) RCRLDEN0 (PWM_CAPCTL[16]) DIRF FCRLDEN0 16-bits PWM (PWM_CNT0[16]) (PWM_CAPCTL[24]) up/down counter (PWM_CNT0[15:0]) Rising Latch RCAPPAT (PWM_RCAPDAT0[15:0]) Falling Latch FCAPDAT (PWM_FCAPDAT0[15:0]) PWMx_CH0 CAPINEN0 (PWM_CAPINEN[0]) CAPEN0 CAPINV0 (PWM_CAPCTL[0]) (PWM_CAPCTL[8]) Note: denotes rising edge detect denotes falling edge detect Figure 6.13-41 PWMx_CH0 Capture Block Diagram Figure 6.13-42 illustrates the capture function timing.
Page 448: Figure 6.13-42 Capture Operation Waveform
NUC126 PWM counter Reload (PERIOD = 8) Reload Capture Input Falling Latch Falling Latch CAPINENn Rising Latch PWM_FCAPDATn PWM_RCAPDATn FCRLDENn RCRLDENn CAPFIENn CAPRIENn CFLIFn Clear by S/W CRLIFn Clear by S/W Capture interrupt Note: n denotes 0 to 5 Figure 6.13-42 Capture Operation Waveform The capture pulse width can be calculated according to the following formula: For the negative pulse case, the channel low pulse width is calculated as (PWM_PERIODn + 1 - PWM_RCAPDATn).
Page 449: Figure 6.13-43 Capture Pdma Operation Waveform Of Channel 0
NUC126 order of the transferred data (falling edge captured is first or rising edge captured first). The complement pair channels share a PDMA channel. Therefore, a selection bit CHSELn_m (CHSEL0_1 (PWM_PDMACTL[4]), CHSEL2_3 (PWM_PDMACTL[12]) and CHSEL4_5 (PWM_PDMACTL[20])) bit is used to decide either channel n or channel m can be serviced by the PDMA channel. Figure 6.13-43 is capture PDMA waveform.
Page 450: Register Map
NUC126 6.13.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value PWM Base Address: PWMx_BA = 0x4004_0000 + (0x10_0000 * x) x=0,1 PWM_CTL0 PWMx_BA+0x00 PWM Control Register 0 0x0000_0000 PWM_CTL1 PWMx_BA+0x04 PWM Control Register 1 0x0000_0000...
Page 451 NUC126 PWM_PHS0_1 PWMx_BA+0x80 PWM Counter Phase Register 0/1 0x0000_0000 PWM_PHS2_3 PWMx_BA+0x84 PWM Counter Phase Register 2/3 0x0000_0000 PWM_PHS4_5 PWMx_BA+0x88 PWM Counter Phase Register 4/5 0x0000_0000 PWM_CNT0 PWMx_BA+0x90 PWM Counter Register 0 0x0000_0000 PWM_CNT1 PWMx_BA+0x94 PWM Counter Register 1 0x0000_0000 PWM_CNT2 PWMx_BA+0x98 PWM Counter Register 2 0x0000_0000...
Page 452 NUC126 PWM_SSCTL PWMx_BA+0x110 R/W PWM Synchronous Start Control Register 0x0000_0000 PWM_SSTRG PWMx_BA+0x114 W PWM Synchronous Start Trigger Register 0x0000_0000 PWM_LEBCTL PWMx_BA+0x118 R/W PWM Leading Edge Blanking Control Register 0x0000_0000 PWM_LEBCNT PWMx_BA+0x11C R/W PWM Leading Edge Blanking Counter Register 0x0000_0000 PWM_STATUS PWMx_BA+0x120 R/W PWM Status Register 0x0000_0000...
Page 453 NUC126 PWM_PBUF5 PWMx_BA+0x318 R PWM PERIOD5 Buffer 0x0000_0000 PWM_CMPBUF0 PWMx_BA+0x31C R PWM CMPDAT0 Buffer 0x0000_0000 PWM_CMPBUF1 PWMx_BA+0x320 R PWM CMPDAT1 Buffer 0x0000_0000 PWM_CMPBUF2 PWMx_BA+0x324 R PWM CMPDAT2 Buffer 0x0000_0000 PWM_CMPBUF3 PWMx_BA+0x328 R PWM CMPDAT3 Buffer 0x0000_0000 PWM_CMPBUF4 PWMx_BA+0x32C R PWM CMPDAT4 Buffer 0x0000_0000 PWM_CMPBUF5 PWMx_BA+0x330 R...
Page 454: Register Description
NUC126 6.13.7 Register Description PWM Control Register 0 (PWM_CTL0) Register Offset Description Reset Value PWM_CTL0 PWMx_BA+0x00 PWM Control Register 0 0x0000_0000 DBGTRIOFF DBGHALT Reserved GROUPEN Reserved IMMLDEN5 IMMLDEN4 IMMLDEN3 IMMLDEN2 IMMLDEN1 IMMLDEN0 Reserved WINLDEN5 WINLDEN4 WINLDEN3 WINLDEN2 WINLDEN1 WINLDEN0 Reserved CTRLD5 CTRLD4 CTRLD3...
Page 455 NUC126 [15:14] Reserved Reserved. Window Load Enable Bits Each bit n controls the corresponding PWM channel n. 0 = PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each [n+8] WINLDENn period by setting CTRLDn bit.
Page 456 NUC126 PWM Control Register 1 (PWM_CTL1) Register Offset Description Reset Value PWM_CTL1 PWMx_BA+0x04 PWM Control Register 1 0x0000_0000 Reserved OUTMODE4 OUTMODE2 OUTMODE0 Reserved CNTMODE5 CNTMODE4 CNTMODE3 CNTMODE2 CNTMODE1 CNTMODE0 Reserved CNTTYPE5 CNTTYPE4 CNTTYPE3 CNTTYPE2 CNTTYPE1 CNTTYPE0 Bits Description [31:27] Reserved Reserved.
Page 457 NUC126 PWM Synchronization Register (PWM_SYNC) Register Offset Description Reset Value PWM_SYNC PWMx_BA+0x08 PWM Synchronization Register 0x0000_0000 Reserved PHSDIR4 PHSDIR2 PHSDIR0 SINPINV SFLTCNT SFLTCSEL SNFLTEN Reserved SINSRC4 SINSRC2 SINSRC0 Reserved PHSEN4 PHSEN2 PHSEN0 Bits Description [31:27] Reserved Reserved. PWM Phase Direction Control [n/2+24] Each bit n controls corresponding PWM channel n.
Page 458 NUC126 00 = Synchronize source from SYNC_IN or SWSYNC. 01 = Counter equal to 0. 10 = Counter equal to PWM_CMPDATm, m denotes 1, 3, 5. 11 = SYNC_OUT signal will not be generated. [7:3] Reserved Reserved. SYNC Phase Enable Bits [n/2] n denotes PWM channel 0,2,4 and m denotes channel 1,3,5.
Page 459 NUC126 PWM Software Control Synchronization Register (PWM_SWSYNC) Register Offset Description Reset Value PWM_SWSYNC PWMx_BA+0x0C PWM Software Control Synchronization Register 0x0000_0000 Reserved Reserved Reserved Reserved SWSYNC4 SWSYNC2 SWSYNC0 Bits Description [31:3] Reserved Reserved. Software SYNC Function [n/2] Each bit n controls corresponding PWM channel n. SWSYNCn n=0,2,4 When SINSRCn (PWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from...
Page 460 NUC126 PWM Clock Source Register (PWM_CLKSRC) Register Offset Description Reset Value PWM_CLKSR PWMx_BA+0x10 PWM Clock Source Register 0x0000_0000 Reserved Reserved ECLKSRC4 Reserved ECLKSRC2 Reserved ECLKSRC0 Bits Description [31:19] Reserved Reserved. PWMx_CH4/5 External Clock Source Select 000 = PWMx_CLK, x denotes 0 or 1. 001 = TIMER0 time-out event.
Page 461 NUC126 PWM Clock Pre-Scale Register 0_1, 2_3, 4_5 (PWM_CLKPSC0_1, 2_3, 4_5) Register Offset Description Reset Value PWM_CLKPS PWMx_BA+0x14 PWM Clock Pre-scale Register 0/1 0x0000_0000 C0_1 PWM_CLKPS PWMx_BA+0x18 PWM Clock Pre-scale Register 2/3 0x0000_0000 C2_3 PWM_CLKPS PWMx_BA+0x1C PWM Clock Pre-scale Register 4/5 0x0000_0000 C4_5 Reserved...
Page 462 NUC126 PWM Counter Enable Register (PWM_CNTEN) Register Offset Description Reset Value PWM_CNTEN PWMx_BA+0x20 PWM Counter Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved CNTEN5 CNTEN4 CNTEN3 CNTEN2 CNTEN1 CNTEN0 Bits Description [31:6] Reserved Reserved. PWM Counter Enable Bits Each bit n controls the corresponding PWM channel n. CNTENn n=0,1..5 0 = PWM Counter and clock prescaler Stop Running.
Page 463 NUC126 PWM Clear Counter Register (PWM_CNTCLR) Register Offset Description Reset Value PWM_CNTCL PWMx_BA+0x24 PWM Clear Counter Register 0x0000_0000 Reserved Reserved Reserved Reserved CNTCLR5 CNTCLR4 CNTCLR3 CNTCLR2 CNTCLR1 CNTCLR0 Bits Description [31:6] Reserved Reserved. Clear PWM Counter Control Bit It is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n.
Page 464 NUC126 PWM Load Register (PWM_LOAD) Register Offset Description Reset Value PWM_LOAD PWMx_BA+0x28 PWM Load Register 0x0000_0000 Reserved Reserved Reserved Reserved LOAD5 LOAD4 LOAD3 LOAD2 LOAD1 LOAD0 Bits Description [31:6] Reserved Reserved. Re-load PWM Comparator Register (CMPDAT) Control Bit This bit is software write, and hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n.
Page 465 NUC126 PWM Period Register 0~5 (PWM_PERIOD0~5) Register Offset Description Reset Value PWM_PERIO PWMx_BA+0x30 PWM Period Register 0 0x0000_0000 PWM_PERIO PWMx_BA+0x34 PWM Period Register 1 0x0000_0000 PWM_PERIO PWMx_BA+0x38 PWM Period Register 2 0x0000_0000 PWM_PERIO PWMx_BA+0x3C PWM Period Register 3 0x0000_0000 PWM_PERIO PWMx_BA+0x40 PWM Period Register 4 0x0000_0000...
Page 466 NUC126 PWM Comparator Register 0~5 (PWM_CMPDAT0~5) Register Offset Description Reset Value PWM_CMPDA PWMx_BA+0x50 PWM Comparator Register 0 0x0000_0000 PWM_CMPDA PWMx_BA+0x54 PWM Comparator Register 1 0x0000_0000 PWM_CMPDA PWMx_BA+0x58 PWM Comparator Register 2 0x0000_0000 PWM_CMPDA PWMx_BA+0x5C PWM Comparator Register 3 0x0000_0000 PWM_CMPDA PWMx_BA+0x60 PWM Comparator Register 4 0x0000_0000...
Page 467 NUC126 PWM Dead-Time Control Register 0_1, 2_3, 4_5 (PWM_DTCTL0_1, 2_3, 4_5) Register Offset Description Reset Value PWM_DTCTL PWMx_BA+0x70 PWM Dead-Time Control Register 0/1 0x0000_0000 PWM_DTCTL PWMx_BA+0x74 PWM Dead-Time Control Register 2/3 0x0000_0000 PWM_DTCTL PWMx_BA+0x78 PWM Dead-Time Control Register 4/5 0x0000_0000 Reserved DTCKSEL Reserved...
Page 468 NUC126 PWM Counter Phase Register 0_1, 2_3, 4_5 (PWM_PHS0_1, 2_3, 4_5) Register Offset Description Reset Value PWM_PHS0_1 PWMx_BA+0x80 PWM Counter Phase Register 0/1 0x0000_0000 PWM_PHS2_3 PWMx_BA+0x84 PWM Counter Phase Register 2/3 0x0000_0000 PWM_PHS4_5 PWMx_BA+0x88 PWM Counter Phase Register 4/5 0x0000_0000 Reserved Reserved Bits...
Page 469 NUC126 PWM Counter Register 0~5 (PWM_CNT0~5) Register Offset Description Reset Value PWM_CNT0 PWMx_BA+0x90 PWM Counter Register 0 0x0000_0000 PWM_CNT1 PWMx_BA+0x94 PWM Counter Register 1 0x0000_0000 PWM_CNT2 PWMx_BA+0x98 PWM Counter Register 2 0x0000_0000 PWM_CNT3 PWMx_BA+0x9C PWM Counter Register 3 0x0000_0000 PWM_CNT4 PWMx_BA+0xA0 PWM Counter Register 4 0x0000_0000...
Page 470 NUC126 PWM Generation Register 0 (PWM_WGCTL0) Register Offset Description Reset Value PWM_WGCTL PWMx_BA+0xB0 PWM Generation Register 0 0x0000_0000 Reserved PRDPCTL5 PRDPCTL4 PRDPCTL3 PRDPCTL2 PRDPCTL1 PRDPCTL0 Reserved ZPCTL5 ZPCTL4 ZPCTL3 ZPCTL2 ZPCTL1 ZPCTL0 Bits Description [31:28] Reserved Reserved. PWM Period (Center) Point Control PWM can control output level on period(center) point event.
Page 471 NUC126 PWM Generation Register 1 (PWM_WGCTL1) Register Offset Description Reset Value PWM_WGCTL PWMx_BA+0xB4 PWM Generation Register 1 0x0000_0000 Reserved CMPDCTL5 CMPDCTL4 CMPDCTL3 CMPDCTL2 CMPDCTL1 CMPDCTL0 Reserved CMPUCTL5 CMPUCTL4 CMPUCTL3 CMPUCTL2 CMPUCTL1 CMPUCTL0 Bits Description [31:28] Reserved Reserved. PWM Compare Down Point Control PWM can control output level on compare down point event.
Page 472 NUC126 PWM Mask Enable Register (PWM_MSKEN) Register Offset Description Reset Value PWM_MSKEN PWMx_BA+0xB8 PWM Mask Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved MSKEN5 MSKEN4 MSKEN3 MSKEN2 MSKEN1 MSKEN0 Bits Description [31:6] Reserved Reserved. PWM Mask Enable Bits The PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
Page 473 NUC126 PWM Mask DATA Register (PWM_MSK) Register Offset Description Reset Value PWM_MSK PWMx_BA+0xBC PWM Mask Data Register 0x0000_0000 Reserved Reserved Reserved Reserved MSKDAT5 MSKDAT4 MSKDAT3 MSKDAT2 MSKDAT1 MSKDAT0 Bits Description [31:6] Reserved Reserved. PWM Mask Data Bit This data bit control the state of PWMx_CHn output pin, if corresponding mask function is enabled.
Page 474 NUC126 PWM Brake Noise Filter Register (PWM_BNF) Register Offset Description Reset Value PWM_BNF PWMx_BA+0xC0 PWM Brake Noise Filter Register 0x0000_0000 Reserved BK1SRC Reserved BK0SRC BRK1PINV BRK1FCNT BRK1NFSEL BRK1NFEN BRK0PINV BRK0FCNT BRK0NFSEL BRK0NFEN Bits Description [31:25] Reserved Reserved. Brake 1 Pin Source Select For PWM0 setting: 0 = Brake 1 pin source come from PWM0_BRAKE1.
Page 475 NUC126 010 = Filter clock = HCLK/4. 011 = Filter clock = HCLK/8. 100 = Filter clock = HCLK/16. 101 = Filter clock = HCLK/32. 110 = Filter clock = HCLK/64. 111 = Filter clock = HCLK/128. PWM Brake 1 Noise Filter Enable Bit BRK1NFEN 0 = Noise filter of PWM Brake 1 Disabled.
Page 476 NUC126 PWM System Fail Brake Control Register (PWM_FAILBRK) Register Offset Description Reset Value PWM_FAILBR PWMx_BA+0xC4 PWM System Fail Brake Control Register 0x0000_0000 Reserved Reserved Reserved Reserved CORBRKEN Reserved BODBRKEN CSSBRKEN Bits Description [31:4] Reserved Reserved. Core Lockup Detection Trigger PWM Brake Function Enable Bit CORBRKEN 0 = Brake Function triggered by Core lockup event Disabled.
Page 477 NUC126 PWM Brake Edge Detect Control Register 0_1, 2_3, 4_5 (PWM_BRKCTL0_1, 2_3, 4_5) Register Offset R/W Description Reset Value PWM_BRKCTL0_ PWMx_BA+0xC8 R/W PWM Brake Edge Detect Control Register 0/1 0x0000_0000 PWM_BRKCTL2_ PWMx_BA+0xCC R/W PWM Brake Edge Detect Control Register 2/3 0x0000_0000 PWM_BRKCTL4_ PWMx_BA+0xD0...
Page 478 NUC126 11 = PWM even channel output high level when PWMx brake event happened. Note: This register is write protected. Refer to SYS_REGLCTL register. Enable System Fail As Level-detect Brake Source (Write Protect) 0 = System Fail condition as level-detect brake source Disabled. [15] SYSLBEN 1 = System Fail condition as level-detect brake source Enabled.
Page 479 NUC126 1 = ACMP0_O as edge-detect brake source Enabled. Note: This register is write protected. Refer to SYS_REGLCTL register. Aug. 08, 2018 Page 479 of 943 Rev 1.03...
Page 480 NUC126 PWM Pin Polar Inverse Control (PWM_POLCTL) Register Offset Description Reset Value PWM_POLCT PWMx_BA+0xD4 PWM Pin Polar Inverse Register 0x0000_0000 Reserved Reserved Reserved Reserved PINV5 PINV4 PINV3 PINV2 PINV1 PINV0 Bits Description [31:6] Reserved Reserved. PWM PIN Polar Inverse Control The register controls polarity state of PWMx_CHn output pin.
Page 481 NUC126 PWM Output Enable Register (PWM_POEN) Register Offset Description Reset Value PWM_POEN PWMx_BA+0xD8 PWM Output Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved POEN5 POEN4 POEN3 POEN2 POEN1 POEN0 Bits Description [31:6] Reserved Reserved. PWMx_CHn Pin Output Enable Bits Each bit n controls the corresponding PWM channel n. POENn n=0,1..5 0 = PWMx_CHn pin at tri-state.
Page 482 NUC126 PWM Software Brake Control Register (PWM_SWBRK) Register Offset Description Reset Value PWM_SWBR PWMx_BA+0xDC PWM Software Brake Control Register 0x0000_0000 Reserved Reserved Reserved BRKLTRG4 BRKLTRG2 BRKLTRG0 Reserved BRKETRG4 BRKETRG2 BRKETRG0 Bits Description [31:11] Reserved Reserved. PWM Level Brake Software Trigger (Write Only) (Write Protect) [n/2+8] Write 1 to this bit will trigger level brake, and set BRKLIFn bits to 1 in BRKLTRGn...
Page 483 NUC126 PWM Interrupt Enable Register 0 (PWM_INTEN0) Register Offset Description Reset Value PWM_INTEN0 PWMx_BA+0xE0 PWM Interrupt Enable Register 0 0x0000_0000 Reserved CMPDIEN5 CMPDIEN4 CMPDIEN3 CMPDIEN2 CMPDIEN1 CMPDIEN0 IFAIEN4_5 Reserved CMPUIEN5 CMPUIEN4 CMPUIEN3 CMPUIEN2 CMPUIEN1 CMPUIEN0 IFAIEN2_3 Reserved PIEN5 PIEN4 PIEN3 PIEN2 PIEN1 PIEN0...
Page 484 NUC126 Note2: Odd channels will read always 0 at complementary mode. PWM Channel 0/1 Interrupt Flag Accumulator Interrupt Enable Bit IFAIEN0_1 0 = Interrupt Flag accumulator interrupt Disabled. 1 = Interrupt Flag accumulator interrupt Enabled. Reserved Reserved. PWM Zero Point Interrupt Enable Bits Each bit n controls the corresponding PWM channel n.
Page 485 NUC126 PWM Interrupt Enable Register 1 (PWM_INTEN1) Register Offset Description Reset Value PWM_INTEN1 PWMx_BA+0xE4 PWM Interrupt Enable Register 1 0x0000_0000 Reserved Reserved Reserved BRKLIEN4_5 BRKLIEN2_3 BRKLIEN0_1 Reserved BRKEIEN4_5 BRKEIEN2_3 BRKEIEN0_1 Bits Description [31:11] Reserved Reserved. PWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect) 0 = Level-detect Brake interrupt for channel4/5 Disabled.
Page 486 NUC126 Note: This register is write protected. Refer to SYS_REGLCTL register. Aug. 08, 2018 Page 486 of 943 Rev 1.03...
Page 487 NUC126 PWM Interrupt Flag Register 0 (PWM_INTSTS0) Register Offset Description Reset Value PWM_INTSTS PWMx_BA+0xE8 PWM Interrupt Flag Register 0 0x0000_0000 Reserved CMPDIF5 CMPDIF4 CMPDIF3 CMPDIF2 CMPDIF1 CMPDIF0 IFAIF4_5 Reserved CMPUIF5 CMPUIF4 CMPUIF3 CMPUIF2 CMPUIF1 CMPUIF0 IFAIF2_3 Reserved PIF5 PIF4 PIF3 PIF2 PIF1 PIF0...
Page 488 NUC126 Flag is set by hardware when condition match IFSEL0_1 bits in PWM_IFA register, software can clear this bit by writing 1 to it. Reserved Reserved. PWM Zero Point Interrupt Flag Each bit n controls the corresponding PWM channel n. ZIFn n=0,1..5 This bit is set by hardware when PWM counter reaches zero, software can write 1 to clear...
Page 489 NUC126 PWM Interrupt Flag Register 1 (PWM_INTSTS1) Register Offset Description Reset Value PWM_INTSTS PWMx_BA+0xEC PWM Interrupt Flag Register 1 0x0000_0000 Reserved BRKLSTS5 BRKLSTS4 BRKLSTS3 BRKLSTS2 BRKLSTS1 BRKLSTS0 Reserved BRKESTS5 BRKESTS4 BRKESTS3 BRKESTS2 BRKESTS1 BRKESTS0 Reserved BRKLIF5 BRKLIF4 BRKLIF3 BRKLIF2 BRKLIF1 BRKLIF0 Reserved BRKEIF5...
Page 490 NUC126 PWM Interrupt Flag Accumulator Register (PWM_IFA) Register Offset Description Reset Value PWM_IFA PWMx_BA+0xF0 PWM Interrupt Flag Accumulator Register 0x0000_0000 Reserved IFAEN4_5 IFSEL4_5 IFCNT4_5 IFAEN2_3 IFSEL2_3 IFCNT2_3 IFAEN0_1 IFSEL0_1 IFCNT0_1 Bits Description [31:24] Reserved Reserved. PWM Channel 4/5 Interrupt Flag Accumulator Enable Bit [23] IFAEN4_5 0 = PWM Channel 4/5 interrupt flag accumulator Disabled.
Page 491 NUC126 110 = CNT equal to CMPU in channel 3. 111 = CNT equal to CMPD in channel 3. PWM Channel 2/3 Interrupt Flag Counter The register sets the count number which defines how many times of PWM Channel 2/3 IFCNT2_3 [11:8] period occurs to set IFAIF2_3 bit to request the PWM period interrupt.
Page 492 NUC126 PWM Trigger ADC Source Select Register 0 (PWM_ADCTS0) Register Offset Description Reset Value PWM_ADCTS PWMx_BA+0xF8 PWM Trigger ADC Source Select Register 0 0x0000_0000 TRGEN3 Reserved TRGSEL3 TRGEN2 Reserved TRGSEL2 TRGEN1 Reserved TRGSEL1 TRGEN0 Reserved TRGSEL0 Bits Description [31] TRGEN3 PWM_CH3 Trigger ADC enable bit [30:28] Reserved...
Page 493 NUC126 0100 = PWM_CH2 down-count compared point. 0101 = PWM_CH3 zero point. 0110 = PWM_CH3 period point. 0111 = PWM_CH3 zero or period point. 1000 = PWM_CH3 up-count compared point. 1001 = PWM_CH3 down-count compared point. 1010 = PWM_CH0 up-count free trigger compared point. 1011 = PWM_CH0 down-count free trigger compared point.
Page 494 NUC126 1101 = PWM_CH2 down-count free trigger compared point. 1110 = PWM_CH4 up-count free trigger compared point. 1111 = PWM_CH4 down-count free trigger compared point. Aug. 08, 2018 Page 494 of 943 Rev 1.03...
Page 495 NUC126 PWM Trigger ADC Source Select Register 1 (PWM_ADCTS1) Register Offset Description Reset Value PWM_ADCTS PWMx_BA+0xFC PWM Trigger ADC Source Select Register 1 0x0000_0000 Reserved Reserved TRGEN5 Reserved TRGSEL5 TRGEN4 Reserved TRGSEL4 Bits Description [31:16] Reserved Reserved. [15] TRGEN5 PWM_CH5 Trigger ADC enable bit [14:12] Reserved Reserved.
Page 496 NUC126 0010 = PWM_CH4 zero or period point. 0011 = PWM_CH4 up-count compared point. 0100 = PWM_CH4 down-count compared point. 0101 = PWM_CH5 zero point. 0110 = PWM_CH5 period point. 0111 = PWM_CH5 zero or period point. 1000 = PWM_CH5 up-count compared point. 1001 = PWM_CH5 down-count compared point.
Page 497 NUC126 PWM Free Trigger Compare Register 0_1, 2_3, 4_5 (PWM_FTCMPDAT0_1, 2_3, 4_5) Register Offset Description Reset Value PWM_FTCMP PWMx_BA+0x100 R/W PWM Free Trigger Compare Register 0/1 0x0000_0000 DAT0_1 PWM_FTCMP PWMx_BA+0x104 R/W PWM Free Trigger Compare Register 2/3 0x0000_0000 DAT2_3 PWM_FTCMP PWMx_BA+0x108 R/W PWM Free Trigger Compare Register 4/5 0x0000_0000...
Page 498 NUC126 PWM Synchronous Start Control Register (PWM_SSCTL) Register Offset Description Reset Value PWMx_BA+0x11 PWM_SSCTL PWM Synchronous Start Control Register 0x0000_0000 Reserved Reserved Reserved SSRC Reserved SSEN5 SSEN4 SSEN3 SSEN2 SSEN1 SSEN0 Bits Description [31:9] Reserved Reserved. PWM Synchronous Start Source Select Bit SSRC 0 = Synchronous start source come from PWM0.
Page 499 NUC126 PWM Synchronous Start Trigger Register (PWM_SSTRG) Register Offset Description Reset Value PWMx_BA+0x11 PWM_SSTRG PWM Synchronous Start Trigger Register 0x0000_0000 Reserved Reserved Reserved Reserved CNTSEN Bits Description [31:1] Reserved Reserved. PWM Counter Synchronous Start Enable (Write Only) PMW counter synchronous enable function is used to make selected PWM channels CNTSEN (PWMx_CHn) start counting at the same time.
Page 500 NUC126 PWM Leading Edge Blanking Control Register (PWM_LEBCTL) Register Offset Description Reset Value PWMx_BA+0x11 PWM_LEBCTL PWM Leading Edge Blanking Control Register 0x0000_0000 Reserved Reserved TRGTYPE Reserved SRCEN4 SRCEN2 SRCEN0 Reserved LEBEN Bits Description [31:18] Reserved Reserved. PWM Leading Edge Blanking Trigger Type 00 = When detect leading edge blanking source rising edge, blanking counter start counting.
Page 501 NUC126 PWM Leading Edge Blanking Counter Register (PWM_LEBCNT) Register Offset Description Reset Value PWMx_BA+0x11 PWM_LEBCNT PWM Leading Edge Blanking Counter Register 0x0000_0000 Reserved Reserved Reserved LEBCNT LEBCNT Bits Description [31:9] Reserved Reserved. PWM Leading Edge Blanking Counter [8:0] LEBCNT This counter value decides leading edge blanking window size. Blanking window size = LEBCNT+1, and LEB counter clock base is ECLK.
Page 502 NUC126 PWM Status Register (PWM_STATUS) Register Offset Description Reset Value PWM_STATU PWMx_BA+0x120 R/W PWM Status Register 0x0000_0000 Reserved Reserved ADCTRGF5 ADCTRGF4 ADCTRGF3 ADCTRGF2 ADCTRGF1 ADCTRGF0 Reserved SYNCINF4 SYNCINF2 SYNCINF0 Reserved CNTMAXF5 CNTMAXF4 CNTMAXF3 CNTMAXF2 CNTMAXF1 CNTMAXF0 Bits Description [31:22] Reserved Reserved.
Page 503 NUC126 PWM Capture Input Enable Register (PWM_CAPINEN) Register Offset Description Reset Value PWM_CAPIN PWMx_BA+0x200 R/W PWM Capture Input Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved CAPINEN5 CAPINEN4 CAPINEN3 CAPINEN2 CAPINEN1 CAPINEN0 Bits Description [31:6] Reserved Reserved. Capture Input Enable Bits Each bit n controls the corresponding PWM channel n.
Page 504 NUC126 PWM Capture Control Register (PWM_CAPCTL) Register Offset Description Reset Value PWM_CAPCT PWMx_BA+0x204 R/W PWM Capture Control Register 0x0000_0000 Reserved FCRLDEN5 FCRLDEN4 FCRLDEN3 FCRLDEN2 FCRLDEN1 FCRLDEN0 Reserved RCRLDEN5 RCRLDEN4 RCRLDEN3 RCRLDEN2 RCRLDEN1 RCRLDEN0 Reserved CAPINV5 CAPINV4 CAPINV3 CAPINV2 CAPINV1 CAPINV0 Reserved CAPEN5 CAPEN4...
Page 505 NUC126 PWM Capture Status Register (PWM_CAPSTS) Register Offset Description Reset Value PWM_CAPST PWMx_BA+0x208 R PWM Capture Status Register 0x0000_0000 Reserved Reserved Reserved CFLIFOV5 CFLIFOV4 CFLIFOV3 CFLIFOV2 CFLIFOV1 CFLIFOV0 Reserved CRLIFOV5 CRLIFOV4 CRLIFOV3 CRLIFOV2 CRLIFOV1 CRLIFOV0 Bits Description [31:14] Reserved Reserved. Capture Falling Latch Interrupt Flag Overrun Status (Read Only) This flag...
Page 506 NUC126 PWM Rising Capture Data Register 0~5 (PWM_RCAPDAT 0~5) Register Offset Description Reset Value PWM_RCAPD PWMx_BA+0x20C R PWM Rising Capture Data Register 0 0x0000_0000 PWM_RCAPD PWMx_BA+0x214 R PWM Rising Capture Data Register 1 0x0000_0000 PWM_RCAPD PWMx_BA+0x21C R PWM Rising Capture Data Register 2 0x0000_0000 PWM_RCAPD PWMx_BA+0x224 R...
Page 507 NUC126 PWM Falling Capture Data Register 0~5 (PWM_FCAPDAT 0~5) Register Offset Description Reset Value PWM_FCAPD PWMx_BA+0x210 R PWM Falling Capture Data Register 0 0x0000_0000 PWM_FCAPD PWMx_BA+0x218 R PWM Falling Capture Data Register 1 0x0000_0000 PWM_FCAPD PWMx_BA+0x220 R PWM Falling Capture Data Register 2 0x0000_0000 PWM_FCAPD PWMx_BA+0x228 R...
Page 508 NUC126 PWM PDMA Control Register (PWM_PDMACTL) Register Offset Description Reset Value PWM_PDMAC PWMx_BA+0x23C R/W PWM PDMA Control Register 0x0000_0000 Reserved Reserved CHSEL4_5 CAPORD4_5 CAPMOD4_5 CHEN4_5 Reserved CHSEL2_3 CAPORD2_3 CAPMOD2_3 CHEN2_3 Reserved CHSEL0_1 CAPORD0_1 CAPMOD0_1 CHEN0_1 Bits Description [31:21] Reserved Reserved. Select Channel 4/5 to Do PDMA Transfer [20] CHSEL4_5...
Page 509 NUC126 CAPMOD2_3 bits are set to 0x3. 0 = PWM_FCAPDAT2/3 register is the first captured data to memory. 1 = PWM_RCAPDAT2/3 register is the first captured data to memory. [10:9] CAPMOD2_3 Select PWM_RCAPDAT2/3 or PWM_FCAODAT2/3 to Do PDMA Transfer 00 = Reserved. 01 = PWM_RCAPDAT2/3 register.
Page 510 NUC126 PWM Capture Channel 0_1, 2_3, 4_5 PDMA Register (PWM_PDMACAP 0_1, 2_3, 4_5) Register Offset Description Reset Value PWM_PDMAC PWMx_BA+0x240 R PWM Capture Channel 0/1 PDMA Register 0x0000_0000 AP0_1 PWM_PDMAC PWMx_BA+0x244 R PWM Capture Channel 2/3 PDMA Register 0x0000_0000 AP2_3 PWM_PDMAC PWMx_BA+0x248 R PWM Capture Channel 4/5 PDMA Register...
Page 511 NUC126 PWM Capture Interrupt Enable Register (PWM_CAPIEN) Register Offset Description Reset Value PWM_CAPIE PWMx_BA+0x250 R/W PWM Capture Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved CAPFIEN5 CAPFIEN4 CAPFIEN3 CAPFIEN2 CAPFIEN1 CAPFIEN0 Reserved CAPRIEN5 CAPRIEN4 CAPRIEN3 CAPRIEN2 CAPRIEN1 CAPRIEN0 Bits Description [31:14] Reserved Reserved.
Page 512 NUC126 PWM Capture Interrupt Flag Register (PWM_CAPIF) Register Offset Description Reset Value PWM_CAPIF PWMx_BA+0x254 R/W PWM Capture Interrupt Flag Register 0x0000_0000 Reserved Reserved Reserved CFLIF5 CFLIF4 CFLIF3 CFLIF2 CFLIF1 CFLIF0 Reserved CRLIF5 CRLIF4 CRLIF3 CRLIF2 CRLIF1 CRLIF0 Bits Description [31:14] Reserved Reserved.
Page 513 NUC126 PWM Period Register Buffer 0~5 (PWM_PBUF0~5) Register Offset Description Reset Value PWM_PBUF0 PWMx_BA+0x304 R PWM PERIOD0 Buffer 0x0000_0000 PWM_PBUF1 PWMx_BA+0x308 R PWM PERIOD1 Buffer 0x0000_0000 PWM_PBUF2 PWMx_BA+0x30C R PWM PERIOD2 Buffer 0x0000_0000 PWM_PBUF3 PWMx_BA+0x310 R PWM PERIOD3 Buffer 0x0000_0000 PWM_PBUF4 PWMx_BA+0x314 R PWM PERIOD4 Buffer 0x0000_0000...
Page 514 NUC126 PWM Comparator Register Buffer 0~5 (PWM_CMPBUF0~5) Register Offset Description Reset Value PWM_CMPBU PWMx_BA+0x31C R PWM CMPDAT0 Buffer 0x0000_0000 PWM_CMPBU PWMx_BA+0x320 R PWM CMPDAT1 Buffer 0x0000_0000 PWM_CMPBU PWMx_BA+0x324 R PWM CMPDAT2 Buffer 0x0000_0000 PWM_CMPBU PWMx_BA+0x328 R PWM CMPDAT3 Buffer 0x0000_0000 PWM_CMPBU PWMx_BA+0x32C R PWM CMPDAT4 Buffer...
Page 515 NUC126 PWM CLKPSC Buffer 0_1, 2_3, 4_5 (PWM_CPSCBUF0_1, 2_3, 4_5) Register Offset Description Reset Value PWM_CPSCB PWMx_BA+0x334 R PWM CLKPSC0_1 Buffer 0x0000_0000 UF0_1 PWM_CPSCB PWMx_BA+0x338 R PWM CLKPSC2_3 Buffer 0x0000_0000 UF2_3 PWM_CPSCB PWMx_BA+0x33C R PWM CLKPSC4_5 Buffer 0x0000_0000 UF4_5 Reserved Reserved Reserved CPSCBUF...
Page 516 NUC126 PWM_FTCMPDAT Buffer 0_1, 2_3, 4_5 (PWM_FTCBUF0_1,2_3,4_5) Register Offset Description Reset Value PWM_FTCBU PWMx_BA+0x340 R PWM FTCMPDAT0_1 Buffer 0x0000_0000 F0_1 PWM_FTCBU PWMx_BA+0x344 R PWM FTCMPDAT2_3 Buffer 0x0000_0000 F2_3 PWM_FTCBU PWMx_BA+0x348 R PWM FTCMPDAT4_5 Buffer 0x0000_0000 F4_5 Reserved Reserved FTCMPBUF FTCMPBUF Bits Description [31:16]...
Page 517 NUC126 PWM FTCMPDAT Indicator Register (PWM_FTCI) Register Offset Description Reset Value PWM_FTCI PWMx_BA+0x34C R/W PWM FTCMPDAT Indicator Register 0x0000_0000 Reserved Reserved Reserved FTCMD4 FTCMD2 FTCMD0 Reserved FTCMU4 FTCMU2 FTCMU0 Bits Description [31:11] Reserved Reserved. PWM FTCMPDAT Down Indicator [n/2+8] Indicator will be set to high when FTCMP(PWM_FTCMPDATn[15:0]) bits equal to FTCMDn n=0,2,4 PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 0, software can...
Page 518: Real Time Clock (Rtc)
NUC126 6.14 Real Time Clock (RTC) 6.14.1 Overview The Real Time Clock (RTC) controller provides the real time and calendar message. The RTC offers programmable time tick and alarm match interrupts. The data format of time and calendar messages are expressed in BCD format. A digital frequency compensation feature is available to compensate external crystal oscillator frequency accuracy.
Page 519: Basic Configuration
NUC126 Time Alarm Calendar Alarm Time Alarm Calendar Mask Register Mask Register Register Alarm Register (RTC_TAMSK) (RTC_CAMSK) (RTC_TALM) (RTC_CALM) ALMIEN (RTC_INTEN[0]) Calendar Time Loading Loading Alarm Interrupt Compare Register Register Operation (RTC_TIME) (RTC_CAL) ALMIF (RTC_INTSTS[0]) (sec) 1/128 change INIT INIT Wakeup CPU from 1/64 change RWEN...
Page 520: Table 6.14-1 Rtc Read/Write Access Attribute
NUC126 RTC_INIT available RTC_RWEN available available RTC_FREQADJ RTC_TIME Not available RTC_CAL Not available RTC_CLKFMT Not available RTC_WEEKDAY Not available RTC_TALM Not available RTC_CALM Not available RTC_LEAPYEAR Not available RTC_INTEN available RTC_INTSTS available RTC_TICK Not available RTC_TAMSK Not available RTC_CAMSK Not available RTC_LXTCTL available RTC_LXTOCTL...
Page 521: Table 6.14-212/24-Hour Time Scale Selection
NUC126 Hz clock output frequency based on compensated RTC clock source. 6.14.5.4 Time and Calendar Counter RTC_TIME and RTC_CAL are used to load the real time and calendar. RTC_TALM and RTC_CALM are used for setup alarm time and calendar. 6.14.5.5 12/24 hour Time Scale Selection The 12/24 hour time scale selection depends on 24HEN (RTC_CLKFMT[0]).
Page 522: Table 6.14-3 Registers Default Value After Powered On
NUC126 (RTC_INTSTS[0]) will be set to 1 and the RTC alarm interrupt signal assert if the alarm interrupt enable ALMIEN (RTC_INTEN[0]) is enabled. The RTC controller also provides alarm mask function which controlled in RTC_TAMSK and RTC_CAMSK registers. User can mask the specified digit and generate periodic interrupt without changing the alarm match condition in RTC_TALM and RTC_CALM registers in each alarm interrupt service routine.
Page 523: Table 6.14-4 Registers Power Domain
NUC126 TENHR (RTC_TIME[21:20]) is 0x3, HR (RTC_TIME[19:16]) is 0x2. RTC_TIME[14:8]: 0x59 TENMIN (RTC_TIME[14:12]) is 0x5, MIN (RTC_TIME[11:8]) is 0x9. RTC_TIME[6:0]: 0x30 TENSEC (RTC_TIME[6:4]) is 0x3, SEC (RTC_TIME[3:0]) is 0x0. 6. Registers in RTC battery power domain and registers in core power domain are shown in Table 6.14-4.
Page 524: Figure 6.14-2 Backup I/O Control Diagram
NUC126 Output GPIO PFx_MODE Enable Control RTC PFx_OPMODE Logic GPIO PFx_DOUT Output PF.x Buffer RTC PFx_DOUT Pull Up GPIO PFx_MODE Weak Pull-up Control RTC PFx_OPMODE Resistor Logic CTLSEL Pin input GPIO PFx_SMTEN x = 0, 1, 2 Figure 6.14-2 Backup I/O Control Diagram Aug.
Page 525: Register Map
NUC126 6.14.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value RTC Base Address: RTC_BA = 0x4000_8000 RTC_INIT RTC_BA+0x00 RTC Initiation Register 0x0000_0000 RTC_RWEN RTC_BA+0x04 RTC Access Enable Register 0x0000_0000 RTC_FREQADJ RTC_BA+0x08 RTC Frequency Compensation Register 0x0020_0000...
Page 526: Register Description
NUC126 6.14.7 Register Description RTC Initiation Register (RTC_INIT) Register Offset Description Reset Value RTC_INIT RTC_BA+0x00 RTC Initiation Register 0x0000_0000 INIT INIT INIT INIT INIT[0]/ACTIVE Bits Description RTC Initiation When RTC block is first powered on, RTC is at reset state. User has to write a special [31:1] INIT number 0xA5EB1357 to INIT to make RTC leaving reset state.
Page 527 NUC126 RTC Access Enable Register (RTC_RWEN) Register Offset Description Reset Value RTC_RWEN RTC_BA+0x04 RTC Access Enable Register 0x0000_0000 Reserved RTCBUSY Reserved RWENF RWEN RWEN Bits Description [31:25] Reserved Reserved. RTC Write Busy Flag This bit indicates RTC registers are writable or not. 0 = RTC register write Disabled.
Page 528 NUC126 RTC Frequency Compensation Register (RTC_FREQADJ) Register Offset Description Reset Value RTC_FREQA RTC_BA+0x08 RTC Frequency Compensation Register 0x0020_0000 Reserved Reserved FREQADJ FREQADJ FREQADJ Bits Description [31:22] Reserved Reserved. Frequency Compensation Value User has to get actual clock frequency of LXT, LXT frequency. [21:0] FREQADJ FCR = 0x200000 * (32768 / LXT frequency).
Page 529 NUC126 RTC Time Loading Register (RTC_TIME) Register Offset Description Reset Value RTC_TIME RTC_BA+0x0C RTC Time Loading Register 0x0000_0000 Reserved Reserved TENHR Reserved TENMIN Reserved TENSEC Bits Description [31:24] Reserved Reserved. 10-hour Time Digit (0~2) Note: When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR [21:20] TENHR[1:0]) means AM/PM indication, RTC_TIME[21] is 0 means AM hour and...
Page 530 NUC126 RTC Calendar Loading Register (RTC_CAL) Register Offset Description Reset Value RTC_CAL RTC_BA+0x10 RTC Calendar Loading Register 0x0015_0808 Reserved TENYEAR YEAR Reserved TENMON Reserved TENDAY Bits Description [31:24] Reserved Reserved. [23:20] TENYEAR 10-Year Calendar Digit (0~9) [19:16] YEAR 1-Year Calendar Digit (0~9) [15:13] Reserved Reserved.
Page 531 NUC126 RTC Time Scale Selection Register (RTC_CLKFMT) Register Offset Description Reset Value RTC_CLKFMT RTC_BA+0x14 RTC Time Scale Selection Register 0x0000_0001 Reserved Reserved Reserved Reserved 24HEN Bits Description [31:1] Reserved Reserved. 24-hour / 12-hour Time Scale Selection Indicates that RTC_TIME and RTC_TALM register are in 24-hour time scale or 12-hour time scale 24HEN 0 = 12-hour time scale with AM and PM indication selected.
Page 532 NUC126 RTC Day of the Week Register (RTC_WEEKDAY) Register Offset Description Reset Value RTC_WEEKD RTC_BA+0x18 RTC Day of the Week Register 0x0000_0006 Reserved Reserved Reserved Reserved WEEKDAY Bits Description [31:3] Reserved Reserved. Day of the Week Register 000 = Sunday. 001 = Monday.
Page 533 NUC126 RTC Time Alarm Register (RTC_TALM) Register Offset Description Reset Value RTC_TALM RTC_BA+0x1C RTC Time Alarm Register 0x0000_0000 Reserved Reserved TENHR Reserved TENMIN Reserved TENSEC Bits Description [31:24] Reserved Reserved. 10-Hour Time Digit Alarm Setting (0~2) [21:20] TENHR When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.) [19:16] 1-Hour Time Digit of Alarm Setting (0~9)
Page 534 NUC126 RTC Calendar Alarm Register (RTC_CALM) Register Offset Description Reset Value RTC_CALM RTC_BA+0x20 RTC Calendar Alarm Register 0x0000_0000 Reserved TENYEAR YEAR Reserved TENMON Reserved TENDAY Bits Description [31:24] Reserved Reserved. [23:20] TENYEAR 10-Year Calendar Digit of Alarm Setting (0~9) YEAR [19:16] 1-Year Calendar Digit of Alarm Setting (0~9) [15:13]...
Page 535 NUC126 RTC Leap Year Indication Register (RTC_LEAPYEAR) Register Offset Description Reset Value RTC_LEAPYE RTC_BA+0x24 RTC Leap Year Indicaton Register 0x0000_0000 Reserved Reserved Reserved Reserved LEAPYEAR Bits Description [31:1] Reserved Reserved. Leap Year Indication Register (Read Only) LEAPYEAR 0 = This year is not a leap year. 1 = This year is leap year.
Page 536 NUC126 RTC Interrupt Enable Register (RTC_INTEN) Register Offset Description Reset Value RTC_INTEN RTC_BA+0x28 RTC Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved TICKIEN ALMIEN Bits Description [31:2] Reserved Reserved. Time Tick Interrupt Enable Bit TICKIEN 0 = RTC time tick interrupt Disabled. 1 = RTC time tick interrupt Enabled.
Page 537 NUC126 RTC Interrupt Status Register (RTC_INTSTS) Register Offset Description Reset Value RTC_INTSTS RTC_BA+0x2C RTC Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved Reserved TICKIF ALMIF Bits Description [31:2] Reserved Reserved. RTC Time Tick Interrupt Flag When RTC time tick event happened, TICKIF will be set to 1 and a time tick interrupt signal will be generated if TICKIEN (RTC_INTEN[1]) is enabled.
Page 538 NUC126 RTC Time Tick Register (RTC_TICK) Register Offset Description Reset Value RTC_TICK RTC_BA+0x30 RTC Time Tick Register 0x0000_0000 Reserved Reserved Reserved Reserved TICK Bits Description [31:3] Reserved Reserved. Time Tick Register These bits are used to select RTC time tick period for periodic time tick interrupt request. 000 = Time tick is 1 second.
Page 539 NUC126 RTC Time Alarm Mask Register (RTC_TAMSK) Register Offset Description Reset Value RTC_TAMSK RTC_BA+0x34 RTC Time Alarm Mask Register 0x0000_0000 Reserved Reserved Reserved Reserved MTENHR MTENMIN MMIN MTENSEC MSEC Bits Description [31:6] Reserved Reserved. Mask 10-hour Time Digit of Alarm Setting (0~2) MTENHR Note: MTENHR function is only for 24-hour time scale mode.
Page 540 NUC126 RTC Calendar Alarm Mask Register (RTC_CAMSK) Register Offset Description Reset Value RTC_CAMSK RTC_BA+0x38 RTC Calendar Alarm Mask Register 0x0000_0000 Reserved Reserved Reserved Reserved MTENYEAR MYEAR MTENMON MMON MTENDAY MDAY Bits Description [31:6] Reserved Reserved. MTENYEAR Mask 10-Year Calendar Digit of alarm setting (0~9) MYEAR Mask 1-Year Calendar Digit of alarm setting (0~9) MTENMON...
Page 541 NUC126 RTC 32 kHz Oscillator Control Register (RTC_LXTCTL) Register Offset Description Reset Value RTC_LXTCTL RTC_BA+0x100 RTC 32 kHz Oscillator Control Register 0x0000_000E Reserved Reserved Reserved Reserved GAIN Reserved Bits Description [31:4] Reserved Reserved. Oscillator Gain Option User can select oscillator gain according to crystal external loading and operating temperature range.
Page 542 NUC126 RTC X32KO Pin Control Register (RTC_LXTOCTL) Register Offset Description Reset Value RTC_LXTOCT RTC_BA+0x104 RTC X32KO Pin Control Register 0x0000_0000 Reserved Reserved Reserved Reserved CTLSEL DOUT OPMODE Bits Description [31:4] Reserved Reserved. I/O Pin State Backup Selection When low speed 32 kHz oscillator (LXT) is disabled, X32KO pin can be used as GPIO PF.0 function.
Page 543 NUC126 RTC X32KI Pin Control Register (RTC_LXTICTL) Register Offset Description Reset Value RTC_LXTICTL RTC_BA+0x108 RTC X32KI Pin Control Register 0x0000_0000 Reserved Reserved Reserved Reserved CTLSEL DOUT OPMODE Bits Description [31:4] Reserved Reserved. I/O Pin State Backup Selection When low speed 32 kHz oscillator (LXT) is disabled, X32KO pin can be used as GPIO PF.1 function.
Page 544 NUC126 RTC PF2 Pin Control Register (RTC_PF2CTL) Register Offset Description Reset Value RTC_PF2CTL RTC_BA+0x10C RTC PF.2 Pin Control Register 0x0000_0000 Reserved Reserved Reserved Reserved CTLSEL DOUT OPMODE Bits Description Reserved [31:4] Reserved. I/O Pin State Backup Selection User can program CTLSEL to decide GPIO PF.2 I/O function is controlled by system power domain GPIO module or V power domain RTC_LXTICTL register.
Page 545 NUC126 RTC Daylight Saving Time Control Register (RTC_DSTCTL) Register Offset Description Reset Value RTC_DSTCTL RTC_BA+0x110 RTC Daylight Saving Time Control Register 0x0000_0000 Reserved Reserved Reserved Reserved DSBAK SUBHR ADDHR Bits Description [31:3] Reserved Reserved. Daylight Saving Back DSBAK 0= Daylight Saving Time function is not performed. 1= Daylight Saving Time function is performed.
Page 546: Smart Card Host Interface (Sc)
NUC126 6.15 Smart Card Host Interface (SC) 6.15.1 Overview The Smart Card Interface controller (SC controller) is based on ISO/IEC 7816-3 standard and fully compliant with PC/SC Specifications. It also provides status of card insertion/removal. 6.15.2 Features  ISO-7816-3 T = 0, T = 1 compliant ...
Page 547: Figure 6.15-1 Sc Clock Control Diagram
NUC126 Clock Controller SC Controller SC0CKEN CLKKEEP0 PCLK1 Engine Clock SC0 CLK HIRC 1/(SC0DIV+1) SC0SEL 1/(SC1DIV+1) Engine Clock SC1 CLK PCLK1 CLKKEEP1 HIRC SC1CKEN SC1SEL SC0SEL SC0DIV SC0CKEN CLKKEEP0 SC0_PINCTL[6] CLKSEL3[1:0] CLKDIV1[7:0] CLK_APBCLK1[0] SC1SEL SC1DIV SC1CKEN CLKKEEP1 SC1_PINCTL[6] CLKSEL3[3:2] CLKDIV1[15:8] CLK_APBCLK1[1] Figure 6.15-1 SC Clock Control Diagram RX_FIFO...
Page 548: Basic Configuration
NUC126 6.15.4 Basic Configuration The SC Host Controller Pin description is shown in Table 6.15-1. Type Description SC_DATA Bi-direction SC Host Controller DATA SC_CD Input SC Host Controller Card Detect SC_PWR Output SC Host Controller Power ON/OFF SC_CLK Output SC Host Controller Clock SC_RST Output SC Host Controller Reset...
Page 549: Functional Description
NUC126 PC.4 MFP1 SC0_nCD PB.2, PE.0, PE.1 MFP5 6.15.4.2 Basic Configuration of SC1  Clock Source Configuration Select the source of SC1 peripheral clock on SC1SEL (CLK_CLKSEL3[3:2]). – Select the clock divider number of SC1 peripheral clock on – SC1DIV(CLK_CLKDIV1[15:8]). Enable SC1 peripheral clock in SC1CKEN (CLK_APBCLK1[1]).
Page 550: Figure 6.15-4 Sc Activation Sequence
NUC126 1. Set SC_RST to low by programming SCRST (SC_PINCTL[1]) to ‘0’. 2. Set SC_PWR at high level by programming PWREN (SC_PINCTL[0]) to ‘1’ and SC_DATA at high level (reception mode) by programming SCDATA (SC_PINCTL[9]) to ‘1’. 3. Enable SC_CLK clock by programming CLKKEEP (SC_PINCTL[6]) to ‘1’. 4.
Page 551: Figure 6.15-5 Sc Warm Reset Sequence
NUC126 Warm Reset The warm reset sequence is shown in Figure 6.15-5. 1. Set SC_RST to low by programming SCRST (SC_PINCTL[1]) to ‘0’. 2. Set SC_DATA to high by programming SCDATA (SC_PINCTL[9]) to ‘1’. 3. Set SC_RST to high by programming SCRST (SC_PINCTL[1]) to ‘1’. The warm reset sequence can be controlled in two ways.
Page 552: Figure 6.15-6 Sc Deactivation Sequence
NUC126 1. Set SC_RST to low by programming SCRST (SC_PINCTL[1]) to ‘0’. 2. Stop SC_CLK by programming CLKKEEP (SC_PINCTL[6]) to ‘0’. 3. Set SC_DATA to low by programming SCDATA (SC_PINCTL[9]) to ‘0’. 4. Deactivate SC_PWR by programming PWREN (SC_PINCTL[0]) to ‘0’. The deactivation sequence can be controlled in two ways.
Page 553: Figure 6.15-7 Basic Operation Flow
NUC126 Start Init system clock Configure SC function pin Card inertion? Insert smart card Activation sequence Receive ATR? Check parameter ok? Warm reset In specific mode? Negotiabled transmission protocol Application Deactivation sequence Card removal Figure 6.15-7 Basic Operation Flow 6.15.5.3 Initial Character TS According to ISO 7816-3, the initial character TS has two possible patterns shown in Figure 6.15-8.
Page 554: Figure 6.15-8 Initial Character Ts
NUC126 Start Start Character T0 Direct Convention t = 12 ~ 9600 ETU Start Start Character T0 Inverse Convention t = 12 ~ 9600 ETU Direct Convention 0_ 1101_ 1100_ 1 (0x3B) 0_ 1100_ 0000_ 1 (0x3F) Inverse Convention Figure 6.15-8 Initial Character TS 6.15.5.4 Error Signal and Character Repetition According to ISO7816-3 T=0 mode description, as shown in Figure 6.15-8, if the receiver receives a wrong parity bit, it will pull the SC_DAT to low by 1.5 bit period to inform the transmitter parity error.
Page 555 NUC126 1. Enable counter by setting TMRSEL (SC_CTL[14:13]) to 11. 2. Select operation mode OPMODE (SC_TMRCTLx[27:24], x=0, 1, 2). 3. Give a count value CNT for Timer0, Timer1 and Timer2 by setting SC_TMRCTL0[23:0], SC_TMRCTL1[7:0] and SC_TMRCTL2[7:0]. 4. Set CNTEN0 (SC_ALTCTL[5]), CNTEN1 (SC_ALTCTL[6]) and CNTEN2 (SC_ALTCTL[7]) to start counting.
Page 556 NUC126 Start Start down counter counting when CNTENx (SC_ALTCTL[7:5]) enabled. Recount When ACTSTSx (SC_ALTCTL[15:13]) is 1, user can change CNT (SC_TMRCTL0[23:0], & reload SC_TMRCTL1[7:0], SC_TMRCTL2[7:0]) value at any time. It will reload the last value which is filled into the CNT(SC_TMRCTL0[23:0], SC_TMRCTL1[7:0], SC_TMRCTL2[7:0]) before the counter count to 0.
Page 557: Figure 6.15-10 Transmit Direction Block Guard Time Operation
NUC126 (SC_INTEN[5:3]) enabled. The time-out value will be CNT (SC_TMRCTL0[23:0], SC_TMRCTL1[7:0], SC_TMRCTL2[7:0]) + 1. The down counter stopped when user clears CNTENx (SC_ALTCTL[7:5]) bit. Start The down counter starts counting when user sets CNTENx (SC_ALTCTL[7:5]) bit and it will count to time-out. Reload Only when the next START bit is detected, counter will reload the new value of CNT &recount...
Page 558: Figure 6.15-12 Extra Guard Time Operation
NUC126 Start D1 D2 D3 D4 D5 D6 D7 D8 Start Stop bit Figure 6.15-12 Extra Guard Time Operation 6.15.5.7 UART Mode When the UARTEN (SC_UARTCTL[0]) bit is set, the Smart Card Interface controller can also be used as basic UART function. The following is the program example for UART mode. Programming example 1.
Page 559: Register Map
NUC126 6.15.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value SC Base Address: SCx_BA = 0x4019_0000 + (0x4000 * x) x= 0, 1 SC_DAT SCx_BA+0x00 SC Receive/Transmit Holding Buffer Register Undefined SC_CTL SCx_BA+0x04...
Page 560: Register Description
NUC126 6.15.7 Register Description SC Receive/Transmit Holding Buffer Register (SC_DAT) Register Offset R/W Description Reset Value SCx_BA+0x00 R/W SC Receive/Transmit Holding Buffer Register SC_DAT Undefined Reserved Reserved Reserved Bits Description [31:8] Reserved Reserved. Receive/Transmit Holding Buffer Write Operation: By writing data to DAT, the SC will send out an 8-bit data. [7:0] Read Operation: By reading DAT, the SC will return an 8-bit received data.
Page 561 NUC126 SC Control Register (SC_CTL) Register Offset Description Reset Value SC_CTL SCx_BA+0x04 SC Control Register 0x0000_0000 Reserved SYNC Reserved CDLV CDDBSEL TXRTYEN TXRTY RXRTYEN RXRTY TMRSEL RXTRGLV CONSEL AUTOCEN TXOFF RXOFF SCEN Bits Description [31] Reserved Reserved. SYNC Flag Indicator (Read Only) Due to synchronization, user should check this bit before writing a new value to RXRTY and TXRTY fields.
Page 562 NUC126 RX Error Retry Enable Bit This bit enables receiver retry function when parity error has occurred. [19] RXRTYEN 0 = RX error retry function Disabled. 1 = RX error retry function Enabled. Note: User must fill in the RXRTY value before enabling this bit. RX Error Retry Count Number This field indicates the maximum number of receiver retries that are allowed when parity error has occurred...
Page 563 NUC126 0 = Auto-convention Disabled. 1 = Auto-convention Enabled. Note1: If user enables auto convention function, the setting step must be done before Answer to Reset (ATR) state and the first data must be 0x3B or 0x3F. After hardware received first data and stored it at buffer, hardware will decided the convention and change the CONSEL (SC_CTL[5:4]) bits automatically when received first data is 0x3B or 0x3F.
Page 564 NUC126 SC Alternate Control Register (SC_ALTCTL) Register Offset Description Reset Value SC_ALTCTL SCx_BA+0x08 SC Alternate Control Register 0x0000_0000 SYNC Reserved Reserved ACTSTS2 ACTSTS1 ACTSTS0 RXBGTEN ADACEN Reserved INITSEL CNTEN2 CNTEN1 CNTEN0 WARSTEN ACTEN DACTEN RXRST TXRST Bits Description SYNC Flag Indicator (Read Only) Due to synchronization, user should check this bit when writing a new value to SC_ALTCTL register.
Page 565 NUC126 Auto Deactivation When Card Removal This bit is usde for enable hardware auto deactivation when smart card is removed. 0 = Auto deactivation Disabled. ADACEN [11] 1 = Auto deactivation Enabled. Note: When the card is removed, hardware will stop any process and then do deactivation sequence if this bit is set.
Page 566 NUC126 Note1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF (SC_INTSTS[8]) will be set to 1. Note2: This field will be cleared by set TXRST (SC_ALTCTL[0]) or RXRST (SC_ALTCTL[1]). Thus, do not fill in WARSTEN, TXRST or RXRST at the same time. Note3: If SCEN (SC_CTL[0]) is not enabled, this filed cannot be programmed.
Page 567 NUC126 SC Extra Guard Time Register (SC_EGT) Register Offset Description Reset Value SC_EGT SCx_BA+0x0C SC Extra Guard Time Register 0x0000_0000 Reserved Reserved Reserved Bits Description [31:8] Reserved Reserved. Extra Guard Time [7:0] This field indicates the extra guard time value. Note: The extra guard time unit is ETU base.
Page 568 NUC126 SC Receiver buffer Time-out Register (SC_RXTOUT) Register Offset Description Reset Value SC_RXTOUT SCx_BA+0x10 SC Receive Buffer Time-out Counter Register 0x0000_0000 Reserved Reserved Reserved RFTM RFTM Bits Description [31:9] Reserved Reserved. SC Receiver FIFO Time-out Counter The time-out down counter resets and starts counting whenever the Rx buffer received a new data.
Page 569 NUC126 SC Element Time Unit Control Register (SC_ETUCTL) Register Offset Description Reset Value SC_ETUCTL SCx_BA+0x14 SC Element Time Unit Control Register 0x0000_0173 Reserved Reserved Reserved ETURDIV ETURDIV Bits Description [31:12] Reserved Reserved. ETU Rate Divider The field is used for define ETU time unit. [11:0] ETURDIV The real ETU time unit is (ETURDIV + 1) * SC clock time.
Page 570 NUC126 SC Interrupt Enable Control Register (SC_INTEN) Register Offset Description Reset Value SC_INTEN SCx_BA+0x18 SC Interrupt Enable Control Register 0x0000_0000 Reserved Reserved Reserved ACERRIEN RXTOIEN INITIEN CDIEN BGTIEN TMR2IEN TMR1IEN TMR0IEN TERRIEN TXEIEN RDAIEN Bits Description [31:11] Reserved Reserved. Auto Convention Error Interrupt Enable Bit This field is used to enable auto-convention error interrupt.
Page 571 NUC126 This field is used to enable Timer2 interrupt function. 0 = Timer2 interrupt Disabled. 1 = Timer2 interrupt Enabled. Timer1 Interrupt Enable Bit This field is used to enable the Timer1 interrupt function. TMR1IEN 0 = Timer1 interrupt Disabled. 1 = Timer1 interrupt Enabled.
Page 572 NUC126 SC Interrupt Status Register (SC_INTSTS) Register Offset Description Reset Value SC_INTSTS SCx_BA+0x1C SC Interrupt Status Register 0x0000_0002 Reserved Reserved Reserved ACERRIF RXTOIF INITIF CDIF BGTIF TMR2IF TMR1IF TMR0IF TERRIF TXEIF RDAIF Bits Description [31:11] Reserved Reserved. Auto Convention Error Interrupt Status Flag This field indicates auto convention sequence error.
Page 573 NUC126 This field is used for indicate block guard time interrupt status flag in receive direction. 0 = Block guard time interrupt did not occur. 1 = Block guard time interrupt occurred. Note1: This bit is valid only when RXBGTEN (SC_ALTCTL[12]) is enabled. Note2: This bit can be cleared by writing 1 to it.
Page 574 NUC126 SC Transfer Status Register (SC_STATUS) Register Offset Description Reset Value SC_STATUS SCx_BA+0x20 SC Transfer Status Register 0x0000_x202 TXACT TXOVERR TXRTYERR Reserved TXPOINT RXACT RXOVERR RXRTYERR Reserved RXPOINT Reserved CDPINSTS CINSERT CREMOVE TXFULL TXEMPTY TXOV Reserved Reserved RXFULL RXEMPTY RXOV Bits Description Transmit in Active Status Flag (Read Only)
Page 575 NUC126 This bit is used for indicate receiver retry counts over than retry number limitation. 0 = Receiver retries counts is not over than RXRTY (SC_CTL[18:16]) + 1. 1 = Receiver retries counts over than RXRTY (SC_CTL[18:16]) + 1. Note1: This bit can be cleared by writing 1 to it. Note2: If user enables receiver retries function by setting RXRTYEN (SC_CTL[19]), the PEF (SC_STATUS[4]) bit will not set.
Page 576 NUC126 This bit is set when Tx buffer overflow. 0 = Tx buffer is not overflow. 1 = Tx buffer is overflow, it means an additional write operation to DAT (SC_DAT[7:0]) when Tx buffer is already full. Note: This bit can be cleared by writing 1 to it. Reserved Reserved.
Page 577 NUC126 SC Pin Control State Register (SC_PINCTL) Register Offset Description Reset Value SC_PINCTL SCx_BA+0x24 SC Pin Control State Register 0x0000_00x0 Reserved SYNC Reserved Reserved RSTSTS PWRSTS DATSTS Reserved PWRINV Reserved SCDATA Reserved Reserved CLKKEEP Reserved SCRST PWREN Bits Description Reserved [31] Reserved.
Page 578 NUC126 00 = SC_PWR pin is 0. 01 = SC_PWR pin is 1. 10 = SC_PWR pin is 1. 11 = SC_PWR pin is 0. Note: User must select PWRINV (SC_PINCTL[11]) before smart card is enabled by SCEN (SC_CTL[0]). Reserved [10] Reserved.
Page 579 NUC126 SC Timer0 Control Register (SC_TMRCTL0) Register Offset Description Reset Value SC_TMRCTL0 SCx_BA+0x28 SC Timer0 Control Register 0x0000_0000 SYNC Reserved OPMODE Bits Description SYNC Flag Indicator (Read Only) Due to synchronization, user should check this bit when writing a new value to SC_TMRCTL0 register.
Page 580 NUC126 SC Timer1 Control Register (SC_TMRCTL1) Register Offset Description Reset Value SC_TMRCTL1 SCx_BA+0x2C SC Timer1 Control Register 0x0000_0000 SYNC Reserved OPMODE Reserved Reserved Bits Description SYNC Flag Indicator (Read Only) Due to synchronization, user should check this bit when writing a new value to SC_TMRCTL1 register.
Page 581 NUC126 SC Timer2 Control Register (SC_TMRCTL2) Register Offset Description Reset Value SC_TMRCTL2 SCx_BA+0x30 SC Timer2 Control Register 0x0000_0000 SYNC Reserved OPMODE Reserved Reserved Bits Description SYNC Flag Indicator (Read Only) Due to synchronization, user should check this bit when writing a new value to SC_TMRCTL2 register.
Page 582 NUC126 SC UART Mode Control Register (SC_UARTCTL) Register Offset Description Reset Value SC_UARTCTL SCx_BA+0x34 SC UART Mode Control Register 0x0000_0000 Bits Description Reserved [31:8] Reserved. Odd Parity Enable Bit This is used for odd/even parity selection. 0 = Even number of logic 1’s are transmitted or check the data word and parity bits in receiving mode.
Page 583 NUC126 SC Timer0 Current Data Register (SC_TMRDAT0) Register Offset Description Reset Value SC_TMRDAT0 SCx_BA+0x38 SC Timer0 Current Data Register 0x0000_07FF Reserved CNT0 CNT0 CNT0 Bits Description [31:24] Reserved Reserved. Timer0 Current Data Value (Read Only) [23:0] CNT0 This field indicates the current counter values of Timer0. Aug.
Page 584 NUC126 SC Timer1/2 Current Data Register (SC_TMRDAT12) Register Offset Description Reset Value SC_TMRDAT12 SCx_BA+0x3C SC Timer1/2 Current Data Register 0x0000_7F7F Reserved Reserved CNT2 CNT1 Bits Description [31:16] Reserved Reserved. Timer2 Current Data Value (Read Only) CNT2 [15:8] This field indicates the current counter values of Timer2. Timer1 Current Data Value (Read Only) [7:0] CNT1...
Page 585 NUC126 Reserved [31:5] Reserved. T1 Extend Time of Hardware Activation This field provide the configurable cycles to extend the activation time T1 period. Please refer to SC activation sequence in Figure 6.15-4. The cycle scaling factor is 2048 and Extend cycles = (T1EXT * 2048) cycles. [4:0] T1EXT For example:...
Page 586: Serial Peripheral Interface (Spi)
NUC126 6.16 Serial Peripheral Interface (SPI) 6.16.1 Overview The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and allows full duplex transfer. Devices communicate in Master/Slave mode with the 4-wire bi-direction interface. The NUC126 series contains up to two sets of SPI controllers performing a serial-to-parallel conversion on data received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device.
Page 587: 6.16.3 Block Diagram
NUC126 6.16.3 Block Diagram SPIx_I2SMCLK Interface Control Core Logic SPIx_CLK (I2Sx_BCLK) Peripheral clock SPIx_SS (I2Sx_LRCLK) Status / Control Registers Interface SPIx_MOSI (I2Sx_DO) Control 4-Bit 4-Level TX TX Shift Skew FIFO Buffer Register Buffer 4-Bit SPIx_MISO (I2Sx_DI) 4-Level RX RX Shift Skew FIFO Buffer Register...
Page 588 NUC126 Enable SPI0 peripheral clock in SPI0CKEN (CLK_APBCLK0[12]). –  Reset Configuration Reset SPI0 controller in SPI0RST (SYS_IPRST1[12]). –  Pin Configuration Group Pin Name GPIO SPI0_CLK PB.2, PB.7, PC.0, PC.12, PE.0, PE.13 MFP2 PD.0 MFP1 SPI0_I2SMCLK PC.5, PC.9, PD.3, PD.7 MFP2 SPI0 SPI0_MISO...
Page 589: Functional Description
NUC126 PE.12 MFP1 PA.4, PD.6, PD.12 MFP2 SPI1_SS PB.4 MFP3 PE.13 MFP6 SPI/I S Interface Controller Pin description is shown as follows: SPI Mode S Mode left/right channel synchronization clock SPIx_SS SPI slave selection pin (I2Sx_LRCLK) SPIx_CLK SPI clock pin S bit clock pin (I2Sx_BCLK) SPIx_MISO SPI master input or slave output pin...
Page 590: Figure 6.16-3 Spi Full-Duplex Master Mode Application Block Diagram
NUC126 register. Master/Slave Mode This SPI controller can be set as Master or Slave mode by setting the SLAVE (SPIx_CTL[18]) to communicate with the off-chip SPI slave or master device. The HALFDPX (SPIx_CTL[14]) can be used to select the full-duplex or half-duplex in SPI transmission. The application block diagrams in Master and Slave mode are shown below.
Page 591: Figure 6.16-532-Bit In One Transaction
NUC126 edge of SPI clock. Note: The settings of TXNEG and RXNEG are mutual exclusive. In other words, do not transmit and receive data at the same clock edge. Transmit/Receive Bit Length The bit length of a transaction word is defined in DWIDTH (SPIx_CTL[12:8]) and can be configured up to 32-bit length in a transaction word for transmitting and receiving.
Page 592: Figure 6.16-6 Automatic Slave Selection (Ssactpol = 0, Suspitv > 0X2)
NUC126 (SPIx_SSCTL[0]) TXEMPTY (SPIx_STATUS[16]) The last transaction SPIx_SS 1 SPI clock 1.5 SPI clock SPIx_CLK Figure 6.16-6 Automatic Slave Selection (SSACTPOL = 0, SUSPITV > 0x2) (SPIx_SSCTL[0]) TXEMPTY (SPIx_STATUS[16]) SPIx_SS One transaction One transaction SPIx_CLK The last transaction Figure 6.16-7 Automatic Slave Selection (SSACTPOL = 0, SUSPITV < 0x3) 6.16.5.3 Byte Reorder and Suspend Function When the transfer is set as MSB first (LSB = 0) and the REORDER (SPIx_CTL[19]) is set to 1, the data stored in the TX buffer and RX buffer will be rearranged in the order as [Byte0, Byte1, Byte2,...
Page 593: Figure 6.16-8 Byte Reorder Function
NUC126 SPI_TX/SPI_RX TX/RX FIFO Buffer LSB = 0 (MSB first) MSB first MSB first & REORDER = 1 Byte3 Byte2 Byte1 Byte0 Byte0 Byte1 Byte2 Byte3 DWIDTH = 0 MSB first Byte0 Byte1 Byte2 DWIDTH = 24 MSB first Byte0 Byte1 DWIDTH = 16 x = unknown byte...
Page 594: Figure 6.16-10 Spi Half-Duplex Master Mode Application Block Diagram
NUC126 SPIx_CLK SPIx_CLK SPIx_MISO M0564 Series Slave SPI Master SPIx_DATA SPIx_MOSI SPIx_SS SPIx_SS Note: x = 0, 1 Figure 6.16-10 SPI Half-Duplex Master Mode Application Block Diagram SPIx_CLK SPIx_CLK SPIx_MISO M0564 Series Master SPI Slave SPIx_MOSI SPIx_DATA SPIx_SS SPIx_SS Note: x = 0, 1 Figure 6.16-11 SPI Half-Duplex Slave Mode Application Block Diagram 6.16.5.5 Receive-Only Mode In SPI Master device, it can communicate in receive-only mode by setting RXONLY (SPIx_CTL[15]).
Page 595: Figure 6.16-12 Fifo Threshold Comparator
NUC126 6.16.5.7 FIFO Buffer Operation The SPI controllers are equipped with four 32-bit wide transmit and receive FIFO buffers. The data stored in the transmit FIFO buffer will be read and sent out by the transmission control logic. If the transmit FIFO buffer is full, the TXFULL (SPIx_STATUS[17]) will be set to 1.
Page 596: Figure 6.16-13 Transmit Fifo Buffer Example
NUC126 TXFULL = 1. TX Skew Buffer TX Shift Register Data 0 Data 0 Example 1 DWIDTH =0 H/W load Shift H/W load TX LSB = 1 Write Register into Buffer into TX Buffer 1 Data Skew Buffer Shift Register Data 0 TXEMPTY = 1 TXEMPTY = 0...
Page 597: Figure 6.16-14 Receive Fifo Buffer Example
NUC126 RX Skew Buffer 1. H/W load Shift Register Example 1 …………….b0 …………..b32 RX Shift Register b31|b30...b1|b0 into RX Buffer DWIDTH =0 H/W Load 2. H/W Load H/W Load 32 Skew Buffer LSB = 1 Skew Buffer RX FIFO Buffer bits into into Shift into Shift...
Page 598: Figure 6.16-16 Slave Mode Bit Count Error
NUC126 follow-up data will be dropped (refer to the Receive FIFO Buffer Example figure). If the receive bit count mismatch with the DWIDTH (SPIx_CTL[12:8]) when the slave selection line goes to inactive state, the SLVBEIF (SPIx_STATUS[6]) will be set to 1. SPIx_SS (SSACTPOL = 0) SPIx_CLK...
Page 599: Figure 6.16-17 I 2 S Data Format Timing Diagram
NUC126 Slave TX Underrun Interrupt If the TX underflow event occurs, the SLVURIF (SPIx_STATUS[7]) will be set to 1 when SPIx_SS goes to inactive state. The SPI controller will issue a TX under run interrupt if the SLVURIEN (SPIx_SSCTL[9]) is set to 1. Receive Overrun Interrupt In Slave mode, if the receive FIFO buffer contains 4 unread data, the RXFULL (SPIx_STATUS[9]) will be set to 1 and the RXOVIF (SPIx_STATUS[11]) will be set to 1 if there is more serial data is received...
Page 600: Figure 6.16-18 Msb Justified Data Format Timing Diagram
NUC126 I2Sx_BCLK I2Sx_LRCLK I2Sx_DI / I2Sx_DO word N-1 word N word N+1 right channel left channel right channel Figure 6.16-18 MSB Justified Data Format Timing Diagram The I2Sx_LRCLK signal also supports PCM mode A and PCM mode B. The I2Sx_LRCLK signal in PCM mode indicates the beginning of an audio frame.
Page 601: Figure 6.16-21 Fifo Contents For Various I
NUC126 6.16.5.10 I S Mode FIFO operation Mono 8-bit data mode SPIx_I2SCTL Stereo 8-bit data mode, ORDER ( [7]) = 0 LEFT+1 RIGHT+1 LEFT RIGHT SPIx_I2SCTL Stereo 8-bit data mode, ORDER ( [7]) = 1 RIGHT+1 LEFT+1 RIGHT LEFT Mono 16-bit data mode SPIx_I2SCTL Stereo 16-bit data mode, ORDER ( [7]) = 0...
Page 602: Timing Diagram
NUC126 6.16.6 Timing Diagram The active state of slave selection signal can be defined by setting the SSACTPOL (SPIx_SSCTL[2]). The SPI clock which is in idle state can be configured as high or low state by setting the CLKPOL (SPIx_CTL[3]). It also provides the bit length of a transaction word in DWIDTH (SPIx_CTL[12:8]), and transmitting/receiving data from MSB or LSB first in LSB (SPIx_CTL[13]).
Page 603: Figure 6.16-24 Spi Timing In Slave Mode
NUC126 SSACTPOL=1 SPIx_SS SSACTPOL=0 CLKPOL=0 SPIx_CLK CLKPOL=1 SPIx_MISO TX[6] TX[0] TX[7] TX[6] TX[7] TX[0] SPIx_MOSI RX[6] RX[0] RX[7] RX[6] RX[7] RX[0] Slave Mode: SLVAE=1, LSB=0, DWIDTH=0x08 1. CLKPOL=0, TXNEG=1, RXNEG=0 or 2. CLKPOL=1, TXNEG=0, RXNEG=1 Figure 6.16-24 SPI Timing in Slave Mode SSACTPOL=1 SPIx_SS SSACTPOL=0...
Page 604: Programming Examples
NUC126 6.16.7 Programming Examples Example 1: The SPI controller is set as a full-duplex master to access an off-chip slave device with the following specifications:  Data bit is latched on positive edge of SPI bus clock.  Data bit is driven on negative edge of SPI bus clock. ...
Page 605 NUC126  SPI bus clock is idle at high state.  Only one byte of data to be transmitted/received in a transaction.  Slave selection signal is active high. The operation flow is as follows: Write the SPIx_SSCTL register a proper value for the related settings of Slave mode. Select high level for the input of slave selection signal by setting SSACTPOL (SPIx_SSCTL[2]) to 1.
Page 606: Register Map
NUC126 6.16.8 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value SPI Base Address: SPIx_BA = 0x4003_0000 + (0x0000_4000 * x) x=0, 1 SPIx_CTL SPIx_BA+0x00 R/W SPI Control Register 0x0000_0034 SPIx_CLKDIV SPIx_BA+0x04 R/W SPI Clock Divider Register 0x0000_0000...
Page 607: Register Description
NUC126 6.16.9 Register Description SPI Control Register (SPIx_CTL) Register Offset Description Reset Value SPIx_CTL SPIx_BA+0x00 SPI Control Register 0x0000_0034 Note: Not supported in I S mode. Reserved Reserved DATDIR REORDER SLAVE UNITIEN Reserved RXONLY HALFDPX DWIDTH SUSPITV CLKPOL TXNEG RXNEG SPIEN Bits Description...
Page 608 NUC126 0 = SPI operates in full-duplex transfer. 1 = SPI operates in half-duplex transfer. Send LSB First 0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first. [13] 1 = The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX).
Page 609 NUC126 SPI Clock Divider Register (SPIx_CLKDIV) Register Offset Description Reset Value SPIx_CLKDIV SPIx_BA+0x04 SPI Clock Divider Register 0x0000_0000 Reserved Reserved Reserved DIVIDER Bits Description [31:8] Reserved Reserved. Clock Divider The value in this field is the frequency divider for generating the peripheral clock, f spi_eclk and the SPI bus clock of SPI Master.
Page 610 NUC126 SPI Slave Select Control Register (SPIx_SSCTL) Register Offset Description Reset Value SPIx_SSCTL SPIx_BA+0x08 SPI Slave Select Control Register 0x0000_0000 Note: Not supported in I S mode. Reserved Reserved Reserved SSINAIEN SSACTIEN Reserved SLVURIEN SLVBEIEN Reserved AUTOSS SSACTPOL Reserved Bits Description [31:14] Reserved...
Page 611 NUC126 Slave Selection Control (Master Only) If AUTOSS bit is cleared to 0, 0 = set the SPIx_SS line to inactive state. 1 = set the SPIx_SS line to active state. If the AUTOSS bit is set to 1, 0 = Keep the SPIx_SS line at inactive state. 1 = SPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time.
Page 612 NUC126 SPI PDMA Control Register (SPIx_PDMACTL) Register Offset Description Reset Value SPIx_PDMACTL SPIx_BA+0x0C SPI PDMA Control Register 0x0000_0000 Reserved Reserved Reserved Reserved PDMARST RXPDMAEN TXPDMAEN Bits Description [31:3] Reserved Reserved. PDMA Reset 0 = No effect. PDMARST 1 = Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0.
Page 613 NUC126 SPI FIFO Control Register (SPIx_FIFOCTL) Register Offset Description Reset Value SPIx_FIFOCTL SPIx_BA+0x10 SPI FIFO Control Register 0x2200_0000 Reserved TXTH Reserved RXTH Reserved Reserved TXFBCLR RXFBCLR TXUFIEN TXUFPOL RXOVIEN RXTOIEN TXTHIEN RXTHIEN TXRST RXRST Bits Description [31:30] Reserved Reserved. Transmit FIFO Threshold TXTH [29:28] If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH...
Page 614 NUC126 Note: 1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active. 2. This bit should be set as 0 in I S mode. 3. When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward.
Page 615 NUC126 SPI Status Register (SPIx_STATUS) Register Offset Description Reset Value SPIx_STATUS SPIx_BA+0x14 SPI Status Register 0x0005_0110 Note: Not supported in I S mode. TXCNT RXCNT TXRXRST Reserved TXUFIF TXTHIF TXFULL TXEMPTY SPIENSTS Reserved RXTOIF RXOVIF RXTHIF RXFULL RXEMPTY SLVURIF SLVBEIF Reserved SSLINE SSINAIF...
Page 616 NUC126 1 = Transmit FIFO buffer is full. Transmit FIFO Buffer Empty Indicator (Read Only) [16] TXEMPTY 0 = Transmit FIFO buffer is not empty. 1 = Transmit FIFO buffer is empty. SPI Enable Status (Read Only) 0 = SPI controller Disabled. SPIENSTS [15] 1 = SPI controller Enabled.
Page 617 NUC126 Slave Select Line Bus Status (Read Only) 0 = The slave select line status is 0. SSLINE 1 = The slave select line status is 1. Note: This bit is only available in Slave mode. If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
Page 618 NUC126 SPI Data Transmit Register (SPIx_TX) Register Offset Description Reset Value SPIx_TX SPIx_BA+0x20 SPI Data Transmit Register 0x0000_0000 Bits Description Data Transmit Register The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I S mode.
Page 619 NUC126 SPI Data Receive Register (SPIx_RX) Register Offset Description Reset Value SPIx_RX SPIx_BA+0x30 SPI Data Receive Register 0x0000_0000 Bits Description Data Receive Register There are 4-level FIFO buffers in this controller. The data receive register holds the data [31:0] received from SPI data input pin. If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register.
Page 620 NUC126 S Control Register (SPIx_I2SCTL) Register Offset Description Reset Value SPIx_I2SCTL SPIx_BA+0x60 S Control Register 0x0000_0000 Note: Not supported in SPI mode. Reserved FORMAT Reserved LZCIEN RZCIEN RXLCH Reserved LZCEN RZCEN MCLKEN Reserved SLAVE ORDER MONO WDWIDTH MUTE RXEN TXEN I2SEN Bits Description...
Page 621 NUC126 Right Channel Zero Cross Detection Enable Bit If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in [16] RZCEN transmit operation.
Page 622 NUC126 S Clock Divider Control Register (SPIx_I2SCLK) Register Offset Description Reset Value SPIx_I2SCLK SPIx_BA+0x64 S Clock Divider Control Register 0x0000_0000 Note: Not supported in SPI mode. Reserved Reserved BCLKDIV BCLKDIV Reserved MCLKDIV Bits Description [31:17] Reserved Reserved. Bit Clock Divider The I S controller will generate bit clock in Master mode.
Page 623 NUC126 Note: User should set BCLKDIV carefully because the peripheral clock frequency must be slower than or equal to system frequency Aug. 08, 2018 Page 623 of 943 Rev 1.03...
Page 624 NUC126 S Status Register (SPIx_I2SSTS) Register Offset Description Reset Value SPIx_I2SSTS SPIx_BA+0x68 I2S Status Register 0x0005_0100 Note: Not supported in SPI mode. Reserved TXCNT Reserved RXCNT TXRXRST Reserved LZCIF RZCIF TXUFIF TXTHIF TXFULL TXEMPTY I2SENSTS Reserved RXTOIF RXOVIF RXTHIF RXFULL RXEMPTY Reserved RIGHT...
Page 625 NUC126 value of TXTH. Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI/I S controller will generate a SPI interrupt request. Transmit FIFO Buffer Full Indicator (Read Only) TXFULL [17] 0 = Transmit FIFO buffer is not full. 1 = Transmit FIFO buffer is full.
Page 626: Timer Controller (Tmr)
NUC126 6.17 Timer Controller (TMR) 6.17.1 Overview The Timer controller includes four 32-bit timers, Timer0 ~ Timer3, allowing user to easily implement a timer control for applications. The timer can perform functions, such as frequency measurement, delay timing, clock generation, and event counting by external input pins, and interval measurement by external capture pins.
Page 627 NUC126 Brown-out detection and CPU lockup) Brake pin noise filter control for brake source – Edge detect brake source to control brake state until brake interrupt cleared – Level detect brake source to auto recover function after brake condition removed –...
Page 628: Block Diagram
NUC126 6.17.3 Block Diagram The Timer Controller block diagram and clock control are shown as follows. WKEN 24 - bit CMPDAT (TIMERx_CTL[23]) (TIMERx_CMP[23:0]) Timer RSTCNT(TIMERx_CTL[26] TWKF Wakeup Reset counter (TIMERx_INTSTS[1]) CNTEN(TIMERx_CTL[30] (TIMERx_INTSTS[0]) TMRx_CLK 8 - bit 24 - bit up counter Prescale T0 ~ T3 EXTCNTEN...
Page 629: Figure 6.17-2 Clock Source Of Timer Controller
NUC126 TMR0SEL (CLK_CLKSEL1[10:8]) TMR1SEL (CLK_CLKSEL1[14:12]) TMR0CKEN (CLK_APBCLK0[2]) 22.1184 MHz (HIRC) TMR1CKEN (CLK_APBCLK0[3]) 10 kHz (LIRC) TMR0_CLK T0~T1 TMR1_CLK PCLK0 32.768 kHz (LXT) 4~24 MHz (HXT) TMR2SEL (CLK_CLKSEL1[18:16]) TMR3SEL (CLK_CLKSEL1[22:20]) 22.1184 MHz (HIRC) TMR2CKEN (CLK_APBCLK0[4]) TMR3CKEN (CLK_APBCLK0[5]) 10 kHz (LIRC) TMR2_CLK T2~T3 TMR3_CLK PCLK1...
Page 630: Figure 6.17-3 Pwm Generator Overview Block Diagram
NUC126 BKSRC (TIMERx_PWMBDB[17:16]) BRAKE0 BRAKE1 NVIC BRAKE2 TIMERx_ Tx, x=0~3 BRAKE3 (PWMx_CH0) Tx_EXT, x=0~3 PCLK0/1 (PWMx_CH1) TMR0 TMR1 TMR2 TMR3 Clock Fail Brown-Out Detect CPU Lockup System Brake Source Figure 6.17-3 PWM Generator Overview Block Diagram Set FUNMODE (TIMERx_ALTCTL[0]) 1 to enable PWM mode. The clock source of Timer0 ~ Timer3 in PWM mode can be enabled in TMRxCKEN (CLK_APBCLK0[5:2]).
Page 631: Figure 6.17-5 Pwm Counter Clock Source Control
NUC126 CLKSRC (TIMERx_PWMCLKSRC[2:0]) TMRx_CLK TMR0_INT TMRx_PWMCLK TMR1_INT TMR2_INT TMR3_INT Figure 6.17-5 PWM Counter Clock Source Control Figure 6.17-6 and Figure 6.17-7 illustrate the architecture of PWM independent mode and complementary mode. Both independent mode and complementary mode supports PWMx_CH0 and PWMx_CH1 output channels in each PWM generator.
Page 632: Basic Configuration
NUC126 Interrupt Interrupt events NVIC Generator Trigger events Trigger Generator (PWMx_CH0) Comparator TMRx_PWMCLK Pulse Output Prescale Counter Generator Control Tx_EXT (PWMx_CH1) BKSRC (TIMERx_PWMBDB[17:16]) BRAKE0 BRAKE1 BRAKE2 BRAKE3 denotes interrupt events Note: denotes trigger events denotes interrupt, trigger and pulse generate events Figure 6.17-7 PWM Complementary Mode Architecture Diagram 6.17.4 Basic Configuration...
Page 633: Timer Functional Description
NUC126 PD.7 MFP4 PD.5 MFP6 PA.8 MFP8 PA.6, PD.3 MFP3 TM1_EXT PE.11 MFP8 PB.0, PB.4 MFP10 6.17.4.2 Basic Configuration of TIMER23  Clock Source Configuration Select the source of TIMER23 peripheral clock on TMR2SEL (CLK_CLKSEL1[18:16]) – for Timer2 and TMR3SEL (CLK_CLKSEL1[22:20]) for Timer3. Enable TIMER23 peripheral clock in TMR2CKEN (CLK_APBCLK0[4]) and –...
Page 634 NUC126 6.17.5.2 Timer Counting Mode The timer controller provides four timer counting modes: one-shot, periodic, toggle-output and continuous counting operation modes: 6.17.5.3 One–shot Mode If the timer controller is configured at one-shot mode (TIMERx_CTL[28:27] is 00) and CNTEN (TIMERx_CTL[30]) is set, the timer counter starts up counting. Once the CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value, the TIF (TIMERx_INTSTS[0]) will be set to 1, CNT value and CNTEN bit is cleared automatically by timer controller then timer counting operation stops.
Page 635: Figure 6.17-8 Continuous Counting Mode
NUC126 TIF = 1 and TIF = 1 and TIF = 1 and Interrupt Interrupt Interrupt Generation Generation Generation Clear TIF as 0 Clear TIF as 0 Clear TIF as 0 CMPDAT = 80 and Set and Set and Set CMPDAT = 200 CMPDAT = 500 CMPDAT = 80...
Page 636: Figure 6.17-9 External Capture Mode
NUC126 TIMERx_CNT Tx_EXT (CAPEDGE=0x02) Clear by software CAPIF TIMERx_CAP Figure 6.17-9 External Capture Mode 6.17.5.9 External Reset Counter Mode The timer controller also provides reset counter function to reset CNT (TIMERx_CNT[23:0]) value while edge transition detected on Tx_EXT (x= 0~3). In this mode, most the settings are the same as event capture mode except CAPFUNCS (TIMERx_EXTCTL[4]) should be as 1 for select Tx_EXT transition is using to trigger reset counter value.
Page 637: Figure 6.17-11 Internal Timer Trigger
NUC126 TRGPWM (TIMERx_TRGCTL[1]) Trigger PWM time-out interrupt signal capture interrupt signal TRGSSEL (TIMERx_TRGCTL[0]) TRGADC (TIMERx_TRGCTL[2]) Trigger ADC time-out interrupt signal capture interrupt signal TRGSSEL (TIMERx_TRGCTL[0]) TRGPDMA (TIMERx_TRGCTL[4]) Trigger PDMA time-out interrupt signal capture interrupt signal TRGSSEL (TIMERx_TRGCTL[0]) Figure 6.17-11 Internal Timer Trigger 6.17.5.11 Inter-Timer Trigger Capture Mode In this mode, the Timer0/2 will be forced in event counting mode, counting with external event, and will generate an internal signal (INTR_TMR_TRG) to trigger Timer1/3 start or stop counting.
Page 638: Pwm Functional Description
NUC126 counting mode and Timer1 as trigger-counting capture mode. T0 pin TIMER0_CTL. INTRGEN TIMER0_CTL. EXTCNTEN TIMER0_CNT. TIMER0_CMP. CMPDAT INTR_TMR_TRG TIMER1_CNT. TIMER1_CMP. CAPDAT TIMER1_EINTSTS. CAPIF Figure 6.17-12 Inter-Timer Trigger Capture Timing 6.17.5.12 Internal Capture Trigger from ACMP The external capture function can also be triggered by internal output signal transition on ACMP0, or ACMP1 output.
Page 639: Figure 6.17-14 Pwm Up Count Type
NUC126 6.17.6.2 PWM Counter PWM supports three counter types operation: up count, down count and up-down count types. 6.17.6.3 Up Count Type When the PWM counter is set to up count type, CNTTYPE (TIMERx_PWMCTL[2:1]) is 0x0, it starts up-counting from zero to PERIOD (TIMERx_PWMPERIOD[15:0]). The current counter value can be read from the CNT (TIMERx_PWMCNT[15:0]).
Page 640: Figure 6.17-16 Pwm Up-Down Count Type
NUC126 6.17.6.5 Up-Down Count Type When the PWM counter is set to up-down count type, CNTTYPE (TIMERx_PWMCTL[2:1]) is 0x2, it starts counting up from zero to PERIOD and then starts counting down to zero. The current counter value can be read from CNT (TIMERx_PWMCNT[15:0]). PWM generates a zero point event when both counter and prescale counts to 0.
Page 641: Figure 6.17-17 Pwm Comparator Events In Up-Down Count Type
NUC126 PERIOD = 7 PERIOD = 4 PERIOD = 5 CMPDAT = 4 CMPDAT = 5 CMPDAT= 0 (TIMERx_PWMCNT[15:0]) DIRF (TIMERx_PWMCNT[16]) PWM Period PWM Period Up-count compared point event (CMPU) Down-count compared point event (CMPD) Note: No CMPU event occurred when CMPDAT equals to PERIOD. Figure 6.17-17 PWM Comparator Events in Up-Down Count Type 6.17.6.8 Period Loading Mode When the IMMLDEN (TIMERx_PWMCTL[9]) bit set to 0, PWM operates at period loading mode.
Page 642: Figure 6.17-18 Period Loading Mode With Up Count Type
NUC126 point 1 point 2 point 3 point 4 point 5 point 6 PERIOD PERIOD DATA0 PERIOD DATA1 PERIOD DATA2 PBUF PERIOD DATA0 PERIOD DATA1 PERIOD DATA2 CMPDAT CMPDAT DATA1 CMPDAT DATA1 CMPBUF PERIOD DATA1 PERIOD DATA0 PERIOD DATA2 CMPDAT DATA1 CMPDAT DATA0 0x10000 CMPU...
Page 643: Figure 6.17-19 Immediately Loading Mode With Up Count Type
NUC126 point 1 point 2 point 3 PERIOD PERIOD DATA0 PERIOD DATA1 PERIOD DATA2 PBUF PERIOD DATA0 PERIOD DATA1 PERIOD DATA2 CMPDAT CMPDAT DATA1 CMPBUF CMPDAT DATA1 CNT wraparound 0x1FFFF PERIOD DATA1 PERIOD DATA0 CMPDAT DATA1 PERIOD DATA2 CMPDAT DATA0 0x10000 CMPU Note:...
Page 644: Figure 6.17-21 Pwm 0% To 100% Duty Cycle In Up Count Type And Up-Down Count Type
NUC126 Priority Zero And CMPU Point Event PWM Output (CMP = 0) 1 (High) Compare up event 2 (Low) Zero event High Table 6.17-1 PWM Pulse Generation Event Priority in Up Count Type Priority Zero And CMPD Point Event PWM Output (CMP = 0) 1 (High) Zero event...
Page 645: Figure 6.17-22 Pwm Independent Mode Output Waveform
NUC126 6.17.6.11 PWM Output Mode The PWM supports two output modes: independent mode which may be applied to DC motor system, complementary mode with dead-time insertion which may be used in the application of AC induction motor and permanent magnet synchronous motor. 6.17.6.12 Independent mode When OUTMODE (TIMERx_PWMCTL[16]) bit is set to 0, PWM output operates in independent mode.
Page 646: Figure 6.17-25 Pwmx_Ch0 And Pwmx_Ch1 Output Control In Complementary Mode
NUC126 complementary control dead-time insertion control (PWMx_CH0) Independent Mode Dead-Time Pulse Four Steps 12-bits Generator Tx_EXT (PWMx_CH1) Independent Mode Dead-Time Four Steps 12-bits DTEN DTCNT (TIMERx_PWMDTCTL[16]) (TIMERx_PWMDTCTL[11:0]) DTCKSEL (TIMERx_PWMDTCTL[24]) Figure 6.17-25 PWMx_CH0 and PWMx_CH1 Output Control in Complementary Mode 6.17.6.15 Dead-Time Insertion Control In the complementary application, the complement channels may drive the external devices like power switches.
Page 647: Figure 6.17-27 Pwm Output Mask Control Waveform
NUC126 PWMx_CH1. MSKEN1/0 0x2 (mask channel 1) 0x1 (mask channel 0) (TIMERx_PWMMSKEN[1:0]) MSKDAT1/0 (TIMERx_PWMMSK[1:0]) PWMx_CH0 PWMx_CH1 Figure 6.17-27 PWM Output Mask Control Waveform 6.17.6.17 PWM Brake Control Each PWM generator supports one external input brake pin as PWM brake event source. User can select active brake pin source in BKPINSRC (TIMERx_PWMBNF[17:16]), TM_BRAKEx (x=0~3).
Page 648: Figure 6.17-29 Brake Event Block Diagram For Pwmx_Ch0 And Pwmx_Ch1
NUC126 BRKEIF1/0 (TIMERx_PWMINTSTS1[1:0]) Edge Detect Edge Detect Brake Interrupt Brake Source BRKEIEN (TIMERx_PWMINTEN1[0]) BRKx_INT BRKLIF1/0 (TIMERx_PWMINTSTS1[9:8]) Level Detect BRKLIEN Brake Interrupt (TIMERx_PWMINTEN1[8]) BRKLSTS0 (TIMERx_PWMINTSTS1[24]) BRKESTS0 BRKACT0 (TIMERx_PWMBRKCTL[17:16]) (TIMERx_PWMINTSTS1[16]) PWMx_CH0 Level Detect Low level Brake Source detection PWMx_CH1 BRKESTS1 BRKACT1 (TIMERx_PWMBRKCTL[19:18]) (TIMERx_PWMINTSTS1[17]) BRKLSTS1 (TIMERx_PWMINTSTS1[25])
Page 649: Figure 6.17-30 Edge Detector Brake Waveform For Pwmx_Ch0 And Pwmx_Ch1
NUC126 (TIMERx_PWMCNT[15:0]) Edge Detect Brake Source BRKEIF0 s/w clear (TIMERx_PWMINTSTS1[0]) BRKEIF1 s/w clear (TIMERx_PWMINTSTS1[1]) BRKESTS0 (TIMERx_PWMINTSTS1[16]) BRKESTS1 TIMERx_PWMINTSTS1[17]) PWMx_CH0 PWMx_CH1 PWMx_CH0 resume at next start of PWMx_CH1 resume at next start of PWM period after BRKEIF0 is cleared PWM period after BRKEIF1 is cleared Note1: BRKACT0: 0x11, output high at brake condition BRKACT1: 0x10, output low at brake condition Note2:...
Page 650: Figure 6.17-31 Level Detector Brake Waveform For Pwmx_Ch0 And Pwmx_Ch1
NUC126 (TIMERx_PWMCNT[15:0]) Level Detect Brake Source BRKLIF0 s/w clear (TIMERx_PWMINTSTS1[0]) BRKLIF1 s/w clear (TIMERx_PWMINTSTS1[1]) BRKLSTS0 (TIMERx_PWMINTSTS1[16]) BRKLSTS1 (TIMERx_PWMINTSTS1[17]) PWMx_CH0 PWMx_CH1 No matter BRKLIF0 or BRKLIF1 clear or not, while level brake condition released, both PWMx_CH0 and PWMx_CH1 resume at next start of PWM period Note1: BRKACT0: 0x11, output high at brake condition BRKACT1: 0x10, output low at brake condition Note2:...
Page 651: Figure 6.17-32 Brake Source Block Diagram
NUC126 TM_BRAKEx (x=0~3) Brake Pin De-Bounce BKPEBEN (TIMERx_PWMBRKCTL[4]) Edge Detect ACMP0_O Brake Source CPO0EBEN (TIMERx_PWMBRKCTL[0]) Brake Control ACMP1_O CPO1EBEN (TIMERx_PWMBRKCTL[1]) System Fail Brake SYSEBEN (TIMERx_PWMBRKCTL[7]) BRKETRG (TIMERx_PWMSWBRK[0]) Brake Pin De-Bounce BKPLBEN (TIMERx_PWMBRKCTL[12]) Level Detect ACMP0_O Brake Source CPO0LBEN (TIMERx_PWMBRKCTL[8]) Brake Control ACMP1_O CPO1LBEN (TIMERx_PWMBRKCTL[9]) System Fail Brake...
Page 652: Figure 6.17-34 Pwmx_Ch0 And Pwmx_Ch1 Polarity Control With Dead-Time Insertion
NUC126 (TIMERx_PWMPOLCTL[0]) and PWMx_CH1 on PINV1 (TIMERx_PWMPOLCTL[1]). Figure 6.17-34 shows the PWMx_CH0 and PWMx_CH1 output with polarity control and dead-time insertion. Initial State PWM Starts PWMx_CH0 PWMx_CH1 PWMx_CH0 (PINV0=0) PWMx_CH1 (PINV1=0) PWMx_CH0 (PINV0=1) PWMx_CH1 (PINV1=0) PWMx_CH0 (PINV0=0) PWMx_CH1 (PINV1=1) (PINV0=1) PWMx_CH0 (PINV1=1) PWMx_CH1...
Page 653: Figure 6.17-35 Pwm Interrupt Architecture Diagram
NUC126 ZIF (TIMERx_PWMINTSTS0[0]) ZIEN (TIMERx_PWMINTEN0[0]) PIF (TIMERx_PWMINTSTS0[1]) PIEN (TIMERx_PWMINTEN0[1]) CMPUIF (TIMERx_PWMINTSTS0[2]) CMPUIEN (TIMERx_PWMINTEN0[2]) PWMx_INT CMPDIF (TIMERx_PWMINTSTS0[3]) TMRx_INT CMPDIEN (TIMERx_PWMINTEN0[3]) BRKEIF0 (TIMERx_PWMINTSTS1[0]) BRKEIF1 (TIMERx_PWMINTSTS1[1]) BRKEIEN (TIMERx_PWMINTEN1[0]) BRKLIF0 (TIMERx_PWMINTSTS1[8]) BRKx_INT BRKLIF1 (TIMERx_PWMINTSTS1[9]) BRKLIEN (TIMERx_PWMINTEN1[8]) Figure 6.17-35 PWM Interrupt Architecture Diagram 6.17.6.20 PWM Trigger ADC Generator The PWM counter event can be one of the ADC conversion trigger source.
Page 654: 6.17.7 Register Map
NUC126 6.17.7 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value TIMER Base Address: TMR01_BA = 0x4001_0000 TMR23_BA = 0x4011_0000 TIMER0_CTL TMR01_BA+0x00 Timer0 Control Register 0x0000_0005 TIMER0_CMP TMR01_BA+0x04 Timer0 Comparator Register 0x0000_0000 TIMER0_INTS TMR01_BA+0x08...
Page 655 NUC126 TIMER0_PWM TMR01_BA+0x70 Timer0 PWM Brake Control Register 0x0000_0000 BRKCTL TIMER0_PWM TMR01_BA+0x74 Timer0 PWM Pin Output Polar Control Register 0x0000_0000 POLCTL TIMER0_PWM TMR01_BA+0x78 Timer0 PWM Pin Output Enable Register 0x0000_0000 POEN TIMER0_PWM TMR01_BA+0x7C W Timer0 PWM Software Trigger Brake Control Register 0x0000_0000 SWBRK TIMER0_PWM...
Page 656 NUC126 CLKSRC TIMER1_PWM TMR01_BA+0x148 R/W Timer1 PWM Counter Clock Pre-scale Register 0x0000_0000 CLKPSC TIMER1_PWM TMR01_BA+0x14C R/W Timer1 PWM Clear Counter Register 0x0000_0000 CNTCLR TIMER1_PWM TMR01_BA+0x150 R/W Timer1 PWM Period Register 0x0000_0000 PERIOD TIMER1_PWM TMR01_BA+0x154 R/W Timer1 PWM Comparator Register 0x0000_0000 CMPDAT TIMER1_PWM TMR01_BA+0x158 R/W...
Page 657 NUC126 TIMER1_PWM TMR01_BA+0x1A4 R Timer1 PWM Comparator Buffer Register 0x0000_0000 CMPBUF TIMER2_CTL TMR23_BA+0x00 Timer2 Control Register 0x0000_0005 TIMER2_CMP TMR23_BA+0x04 Timer2 Comparator Register 0x0000_0000 TIMER2_INTS TMR23_BA+0x08 Timer2 Interrupt Status Register 0x0000_0000 TIMER2_CNT TMR23_BA+0x0C R/W Timer2 Data Register 0x0000_0000 TIMER2_CAP TMR23_BA+0x10 Timer2 Capture Data Register 0x0000_0000 TIMER2_EXT TMR23_BA+0x14...
Page 658 NUC126 POEN TIMER2_PWM TMR23_BA+0x7C W Timer2 PWM Software Trigger Brake Control Register 0x0000_0000 SWBRK TIMER2_PWM TMR23_BA+0x80 Timer2 PWM Interrupt Enable Register 0 0x0000_0000 INTEN0 TIMER2_PWM TMR23_BA+0x84 Timer2 PWM Interrupt Enable Register 1 0x0000_0000 INTEN1 TIMER2_PWM TMR23_BA+0x88 Timer2 PWM Interrupt Status Register 0 0x0000_0000 INTSTS0 TIMER2_PWM...
Page 659: Register Description
NUC126 TIMER3_PWM TMR23_BA+0x150 R/W Timer3 PWM Period Register 0x0000_0000 PERIOD TIMER3_PWM TMR23_BA+0x154 R/W Timer3 PWM Comparator Register 0x0000_0000 CMPDAT TIMER3_PWM TMR23_BA+0x158 R/W Timer3 PWM Dead-Time Control Register 0x0000_0000 DTCTL TIMER3_PWM TMR23_BA+0x15C R Timer3 PWM Counter Register 0x0000_0000 TIMER3_PWM TMR23_BA+0x160 R/W Timer3 PWM Output Mask Enable Register 0x0000_0000 MSKEN...
Page 660 NUC126 Timer Control Register (TIMERx_CTL) Register Offset Description Reset Value TIMER0_CTL TMR01_BA+0x00 Timer0 Control Register 0x0000_0005 TIMER1_CTL TMR01_BA+0x100 R/W Timer1 Control Register 0x0000_0005 TIMER2_CTL TMR23_BA+0x00 Timer2 Control Register 0x0000_0005 TIMER3_CTL TMR23_BA+0x100 R/W Timer3 Control Register 0x0000_0005 ICEDEBUG CNTEN INTEN OPMODE Reserved ACTSTS EXTCNTEN...
Page 661 NUC126 10 = The Timer controller is operated in Toggle-output mode. 11 = The Timer controller is operated in Continuous Counting mode. [26] Reserved Reserved. Timer Active Status Bit (Read Only) This bit indicates the 24-bit up counter status. [25] ACTSTS 0 = 24-bit up counter is not active.
Page 662 NUC126 Prescale Counter Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up [7:0] counter. If this field is 0 (PSC = 0), then there is no scaling. Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value.
Page 663 NUC126 Timer Comparator Register (TIMERx_CMP) Register Offset Description Reset Value TIMER0_CMP TMR01_BA+0x04 Timer0 Comparator Register 0x0000_0000 TIMER1_CMP TMR01_BA+0x104 R/W Timer1 Comparator Register 0x0000_0000 TIMER2_CMP TMR23_BA+0x04 Timer2 Comparator Register 0x0000_0000 TIMER3_CMP TMR23_BA+0x104 R/W Timer3 Comparator Register 0x0000_0000 Reserved CMPDAT CMPDAT CMPDAT Bits Description [31:24]...
Page 664 NUC126 Timer Interrupt Status Register (TIMERx_INTSTS) Register Offset Description Reset Value TIMER0_INTS TMR01_BA+0x08 Timer0 Interrupt Status Register 0x0000_0000 TIMER1_INTS TMR01_BA+0x108 R/W Timer1 Interrupt Status Register 0x0000_0000 TIMER2_INTS TMR23_BA+0x08 Timer2 Interrupt Status Register 0x0000_0000 TIMER3_INTS TMR23_BA+0x108 R/W Timer3 Interrupt Status Register 0x0000_0000 Reserved Reserved...
Page 665 NUC126 Timer Data Register (TIMERx_CNT) Register Offset Description Reset Value TIMER0_CNT TMR01_BA+0x0C R/W Timer0 Data Register 0x0000_0000 TIMER1_CNT TMR01_BA+0x10C R/W Timer1 Data Register 0x0000_0000 TIMER2_CNT TMR23_BA+0x0C R/W Timer2 Data Register 0x0000_0000 TIMER3_CNT TMR23_BA+0x10C R/W Timer3 Data Register 0x0000_0000 RSTACT Reserved Bits Description Timer Data Register Reset Active (Read Only)
Page 666 NUC126 Timer Capture Data Register (TIMERx_CAP) Register Offset Description Reset Value TIMER0_CAP TMR01_BA+0x10 Timer0 Capture Data Register 0x0000_0000 TIMER1_CAP TMR01_BA+0x110 R Timer1 Capture Data Register 0x0000_0000 TIMER2_CAP TMR23_BA+0x10 Timer2 Capture Data Register 0x0000_0000 TIMER3_CAP TMR23_BA+0x110 R Timer3 Capture Data Register 0x0000_0000 Reserved CAPDAT...
Page 667 NUC126 Timer External Control Register (TIMERx_EXTCTL) Register Offset Description Reset Value TIMER0_EXT TMR01_BA+0x14 Timer0 External Control Register 0x0000_0000 TIMER1_EXT TMR01_BA+0x114 R/W Timer1 External Control Register 0x0000_0000 TIMER2_EXT TMR23_BA+0x14 Timer2 External Control Register 0x0000_0000 TIMER3_EXT TMR23_BA+0x114 R/W Timer3 External Control Register 0x0000_0000 Reserved Reserved...
Page 668 NUC126 ACMP Source Selection to Trigger Capture Function 0 = Capture Function source is from internal ACMP0 output signal. ACMPSSEL 1 = Capture Function source is from internal ACMP1 output signal. Note: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1. Timer Counter Pin De-bounce Enable Bit 0 = Tx (x= 0~3) pin de-bounce Disabled.
Page 669 NUC126 Timer External Interrupt Status Register (TIMERx_EINTSTS) Register Offset Description Reset Value TIMER0_EINT TMR01_BA+0x18 Timer0 External Interrupt Status Register 0x0000_0000 TIMER1_EINT TMR01_BA+0x118 R/W Timer1 External Interrupt Status Register 0x0000_0000 TIMER2_EINT TMR23_BA+0x18 Timer2 External Interrupt Status Register 0x0000_0000 TIMER3_EINT TMR23_BA+0x118 R/W Timer3 External Interrupt Status Register 0x0000_0000 Reserved...
Page 670 NUC126 Timer Trigger Control Register (TIMERx_TRGCTL) Register Offset Description Reset Value TIMER0_TRG TMR01_BA+0x1C R/W Timer0 Trigger Control Register 0x0000_0000 TIMER1_TRG TMR01_BA+0x11C R/W Timer1 Trigger Control Register 0x0000_0000 TIMER2_TRG TMR23_BA+0x1C R/W Timer2 Trigger Control Register 0x0000_0000 TIMER3_TRG TMR23_BA+0x11C R/W Timer3 Trigger Control Register 0x0000_0000 Reserved Reserved...
Page 671 NUC126 clock source. 0 = Timer interrupt trigger PWM Disabled. 1 = Timer interrupt trigger PWM Enabled. Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal as PWM counter clock source. If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal as PWM counter clock source.
Page 672 NUC126 Timer Alternative Control Register (TIMERx_ALTCTL) Register Offset Description Reset Value TIMER0_ALT TMR01_BA+0x20 Timer0 Alternative Control Register 0x0000_0000 TIMER1_ALT TMR01_BA+0x120 R/W Timer1 Alternative Control Register 0x0000_0000 TIMER2_ALT TMR23_BA+0x20 Timer2 Alternative Control Register 0x0000_0000 TIMER3_ALT TMR23_BA+0x120 R/W Timer3 Alternative Control Register 0x0000_0000 Reserved Reserved...
Page 673 NUC126 Timer PWM Control Register (TIMERx_PWMCTL) Register Offset Description Reset Value TIMER0_PWM TMR01_BA+0x40 Timer0 PWM Control Register 0x0000_0000 TIMER1_PWM TMR01_BA+0x140 R/W Timer1 PWM Control Register 0x0000_0000 TIMER2_PWM TMR23_BA+0x40 Timer2 PWM Control Register 0x0000_0000 TIMER3_PWM TMR23_BA+0x140 R/W Timer3 PWM Control Register 0x0000_0000 DBGTRIOFF DBGHALT...
Page 674 NUC126 is enabled/disabled. If CTRLD is disabled, CMP will load to CMPBUF when current PWM period is completed; if CTRLD is enabled in up-down count type, CMP will load to CMPBUF at the center point of current period. 1 = PERIOD/CMP will load to PBUF/CMPBUF immediately when user update PERIOD/CMP.
Page 675 NUC126 Timer PWM Counter Clock Source Register (TIMERx PWMCLKSRC) Register Offset Description Reset Value TIMER0_PWM TMR01_BA+0x44 Timer0 PWM Counter Clock Source Register 0x0000_0000 CLKSRC TIMER1_PWM TMR01_BA+0x144 R/W Timer1 PWM Counter Clock Source Register 0x0000_0000 CLKSRC TIMER2_PWM TMR23_BA+0x44 Timer2 PWM Counter Clock Source Register 0x0000_0000 CLKSRC TIMER3_PWM...
Page 676 NUC126 Timer PWM Counter Clock Pre-scale Register (TIMERx PWMCLKPSC) Register Offset Description Reset Value TIMER0_PWM TMR01_BA+0x48 Timer0 PWM Counter Clock Pre-scale Register 0x0000_0000 CLKPSC TIMER1_PWM TMR01_BA+0x148 R/W Timer1 PWM Counter Clock Pre-scale Register 0x0000_0000 CLKPSC TIMER2_PWM TMR23_BA+0x48 Timer2 PWM Counter Clock Pre-scale Register 0x0000_0000 CLKPSC TIMER3_PWM...
Page 677 NUC126 Timer PWM Clear Counter Register (TIMERx PWMCNTCLR) Register Offset Description Reset Value TIMER0_PWM TMR01_BA+0x4C R/W Timer0 PWM Clear Counter Register 0x0000_0000 CNTCLR TIMER1_PWM TMR01_BA+0x14C R/W Timer1 PWM Clear Counter Register 0x0000_0000 CNTCLR TIMER2_PWM TMR23_BA+0x4C R/W Timer2 PWM Clear Counter Register 0x0000_0000 CNTCLR TIMER3_PWM...
Page 678 NUC126 Timer PWM Period Register (TIMERx PWMPERIOD) Register Offset Description Reset Value TIMER0_PWM TMR01_BA+0x50 Timer0 PWM Period Register 0x0000_0000 PERIOD TIMER1_PWM TMR01_BA+0x150 R/W Timer1 PWM Period Register 0x0000_0000 PERIOD TIMER2_PWM TMR23_BA+0x50 Timer2 PWM Period Register 0x0000_0000 PERIOD TIMER3_PWM TMR23_BA+0x150 R/W Timer3 PWM Period Register 0x0000_0000 PERIOD...
Page 679 NUC126 Timer PWM Comparator Register (TIMERx PWMCMPDAT) Register Offset Description Reset Value TIMER0_PWM TMR01_BA+0x54 Timer0 PWM Comparator Register 0x0000_0000 CMPDAT TIMER1_PWM TMR01_BA+0x154 R/W Timer1 PWM Comparator Register 0x0000_0000 CMPDAT TIMER2_PWM TMR23_BA+0x54 Timer2 PWM Comparator Register 0x0000_0000 CMPDAT TIMER3_PWM TMR23_BA+0x154 R/W Timer3 PWM Comparator Register 0x0000_0000 CMPDAT...
Page 680 NUC126 Timer PWM Dead-time Control Register (TIMERx PWMDTCTL) Register Offset Description Reset Value TIMER0_PWM TMR01_BA+0x58 Timer0 PWM Dead-Time Control Register 0x0000_0000 DTCTL TIMER1_PWM TMR01_BA+0x158 R/W Timer1 PWM Dead-Time Control Register 0x0000_0000 DTCTL TIMER2_PWM TMR23_BA+0x58 Timer2 PWM Dead-Time Control Register 0x0000_0000 DTCTL TIMER3_PWM TMR23_BA+0x158 R/W...
Page 681 NUC126 Timer PWM Counter Register (TIMERx PWMCNT) Register Offset Description Reset Value TIMER0_PWM TMR01_BA+0x5C Timer0 PWM Counter Register 0x0000_0000 TIMER1_PWM TMR01_BA+0x15C R Timer1 PWM Counter Register 0x0000_0000 TIMER2_PWM TMR23_BA+0x5C Timer2 PWM Counter Register 0x0000_0000 TIMER3_PWM TMR23_BA+0x15C R Timer3 PWM Counter Register 0x0000_0000 Reserved Reserved...
Page 682 NUC126 Timer PWM Output Mask Enable Register (TIMERx PWMMSKEN) Register Offset Description Reset Value TIMER0_PWM TMR01_BA+0x60 Timer0 PWM Output Mask Enable Register 0x0000_0000 MSKEN TIMER1_PWM TMR01_BA+0x160 R/W Timer1 PWM Output Mask Enable Register 0x0000_0000 MSKEN TIMER2_PWM TMR23_BA+0x60 Timer2 PWM Output Mask Enable Register 0x0000_0000 MSKEN TIMER3_PWM...
Page 683 NUC126 Timer PWM Output Mask Data Control Register (TIMERx PWMMSK) Register Offset Description Reset Value TIMER0_PWM TMR01_BA+0x64 Timer0 PWM Output Mask Data Control Register 0x0000_0000 TIMER1_PWM TMR01_BA+0x164 R/W Timer1 PWM Output Mask Data Control Register 0x0000_0000 TIMER2_PWM TMR23_BA+0x64 Timer2 PWM Output Mask Data Control Register 0x0000_0000 TIMER3_PWM TMR23_BA+0x164 R/W...
Page 684 NUC126 Timer PWM Brake Pin Noise Filter Register (TIMERx PWMBNF) Register Offset Description Reset Value TIMER0_PWM TMR01_BA+0x68 Timer0 PWM Brake Pin Noise Filter Register 0x0000_0000 TIMER1_PWM TMR01_BA+0x168 R/W Timer1 PWM Brake Pin Noise Filter Register 0x0000_0000 TIMER2_PWM TMR23_BA+0x68 Timer2 PWM Brake Pin Noise Filter Register 0x0000_0000 TIMER3_PWM TMR23_BA+0x168 R/W...
Page 685 NUC126 101 = Noise filter clock is PCLKx/32. 110 = Noise filter clock is PCLKx/64. 111 = Noise filter clock is PCLKx/128. Brake Pin Noise Filter Enable Bit BRKNFEN 0 = Pin noise filter detect of TM_BRAKEx Disabled. 1 = Pin noise filter detect of TM_BRAKEx Enabled. Aug.
Page 686 NUC126 Timer PWM System Fail Brake Control Register (TIMERx PWMFAILBRK) Register Offset Description Reset Value TIMER0_PWM TMR01_BA+0x6C R/W Timer0 PWM System Fail Brake Control Register 0x0000_0000 FAILBRK TIMER1_PWM TMR01_BA+0x16C R/W Timer1 PWM System Fail Brake Control Register 0x0000_0000 FAILBRK TIMER2_PWM TMR23_BA+0x6C R/W Timer2 PWM System Fail Brake Control Register 0x0000_0000...
Page 687 NUC126 Timer PWM Brake Control Register (TIMERx PWMBRKCTL) Register Offset R/W Description Reset Value TIMER0_PWMBR TMR01_BA+0x70 R/W Timer0 PWM Brake Control Register 0x0000_0000 KCTL TIMER1_PWMBR TMR01_BA+0x170 R/W Timer1 PWM Brake Control Register 0x0000_0000 KCTL TIMER2_PWMBR TMR23_BA+0x70 R/W Timer2 PWM Brake Control Register 0x0000_0000 KCTL TIMER3_PWMBR...
Page 688 NUC126 1 = TM_BRAKEx pin event as level-detect brake source Enabled. Note: This register is write protected. Refer to SYS_REGLCTL register. [11:10] Reserved Reserved. Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect) 0 = Internal ACMP1_O signal as level-detect brake source Disabled. CPO1LBEN 1 = Internal ACMP1_O signal as level-detect brake source Enabled.
Page 689 NUC126 Timer PWM Pin Output Polar Control Register (TIMERx PWMPOLCTL) Register Offset Description Reset Value TIMER0_PWM TMR01_BA+0x74 Timer0 PWM Pin Output Polar Control Register 0x0000_0000 POLCTL TIMER1_PWM TMR01_BA+0x174 R/W Timer1 PWM Pin Output Polar Control Register 0x0000_0000 POLCTL TIMER2_PWM TMR23_BA+0x74 Timer2 PWM Pin Output Polar Control Register 0x0000_0000 POLCTL...
Page 690 NUC126 Timer PWM Pin Output Enable Register (TIMERx PWMPOEN) Register Offset Description Reset Value TIMER0_PWM TMR01_BA+0x78 Timer0 PWM Pin Output Enable Register 0x0000_0000 POEN TIMER1_PWM TMR01_BA+0x178 R/W Timer1 PWM Pin Output Enable Register 0x0000_0000 POEN TIMER2_PWM TMR23_BA+0x78 Timer2 PWM Pin Output Enable Register 0x0000_0000 POEN TIMER3_PWM...
Page 691 NUC126 Timer PWM Software Trigger Brake Control Register (TIMERx PWMSWBRK) Register Offset Description Reset Value TIMER0_PWM TMR01_BA+0x7C W Timer0 PWM Software Trigger Brake Control Register 0x0000_0000 SWBRK TIMER1_PWM TMR01_BA+0x17C W Timer1 PWM Software Trigger Brake Control Register 0x0000_0000 SWBRK TIMER2_PWM TMR23_BA+0x7C W Timer2 PWM Software Trigger Brake Control Register 0x0000_0000...
Page 692 NUC126 Timer PWM Interrupt Enable Register 0 (TIMERx PWMINTEN0) Register Offset Description Reset Value TIMER0_PWM TMR01_BA+0x80 Timer0 PWM Interrupt Enable Register 0 0x0000_0000 INTEN0 TIMER1_PWM TMR01_BA+0x180 R/W Timer1 PWM Interrupt Enable Register 0 0x0000_0000 INTEN0 TIMER2_PWM TMR23_BA+0x80 Timer2 PWM Interrupt Enable Register 0 0x0000_0000 INTEN0 TIMER3_PWM...
Page 693 NUC126 Timer PWM Interrupt Enable Register 1 (TIMERx PWMINTEN1) Register Offset Description Reset Value TIMER0_PWM TMR01_BA+0x84 Timer0 PWM Interrupt Enable Register 1 0x0000_0000 INTEN1 TIMER1_PWM TMR01_BA+0x184 R/W Timer1 PWM Interrupt Enable Register 1 0x0000_0000 INTEN1 TIMER2_PWM TMR23_BA+0x84 Timer2 PWM Interrupt Enable Register 1 0x0000_0000 INTEN1 TIMER3_PWM...
Page 694 NUC126 Timer PWM Interrupt Status Register 0 (TIMERx PWMINTSTS0) Register Offset Description Reset Value TIMER0_PWM TMR01_BA+0x88 Timer0 PWM Interrupt Status Register 0 0x0000_0000 INTSTS0 TIMER1_PWM TMR01_BA+0x188 R/W Timer1 PWM Interrupt Status Register 0 0x0000_0000 INTSTS0 TIMER2_PWM TMR23_BA+0x88 Timer2 PWM Interrupt Status Register 0 0x0000_0000 INTSTS0 TIMER3_PWM...
Page 695 NUC126 Timer PWM Interrupt Status Register 1 (TIMERx PWMINTSTS1) Register Offset Description Reset Value TIMER0_PWM TMR01_BA+0x8C R/W Timer0 PWM Interrupt Status Register 1 0x0000_0000 INTSTS1 TIMER1_PWM TMR01_BA+0x18C R/W Timer1 PWM Interrupt Status Register 1 0x0000_0000 INTSTS1 TIMER2_PWM TMR23_BA+0x8C R/W Timer2 PWM Interrupt Status Register 1 0x0000_0000 INTSTS1 TIMER3_PWM...
Page 696 NUC126 1 = PWMx_CH0 at edge-detect brake state. Note: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period. [15:10] Reserved Reserved.
Page 697 NUC126 Timer PWM ADC Trigger Control Register (TIMERx PWMADCTS) Register Offset Description Reset Value TIMER0_PWM TMR01_BA+0x90 Timer0 PWM ADC Trigger Source Select Register 0x0000_0000 ADCTS TIMER1_PWM TMR01_BA+0x190 R/W Timer1 PWM ADC Trigger Source Select Register 0x0000_0000 ADCTS TIMER2_PWM TMR23_BA+0x90 Timer2 PWM ADC Trigger Source Select Register 0x0000_0000 ADCTS TIMER3_PWM...
Page 698 NUC126 Timer PWM Synchronous Control Register (TIMERx PWMSCTL) Register Offset Description Reset Value TIMER0_PWMS TMR01_BA+0x94 R/W Timer0 PWM Synchronous Control Register 0x0000_0000 TIMER1_PWMS TMR01_BA+0x19 Timer1 PWM Synchronous Control Register 0x0000_0000 TIMER2_PWMS TMR23_BA+0x94 R/W Timer2 PWM Synchronous Control Register 0x0000_0000 TIMER3_PWMS TMR23_BA+0x19 Timer3 PWM Synchronous Control Register 0x0000_0000...
Page 699 NUC126 Timer PWM Synchronous Trigger Register (TIMERx PWMSTRG) Register Offset Description Reset Value TIMER0_PWMS TMR01_BA+0x98 W Timer0 PWM Synchronous Trigger Register 0x0000_0000 TIMER2_PWMS TMR23_BA+0x98 W Timer2 PWM Synchronous Trigger Register 0x0000_0000 Reserved Reserved Reserved Reserved STRGEN Bits Description [31:1] Reserved Reserved.
Page 700 NUC126 Timer PWM Status Register (TIMERx PWMSTATUS) Register Offset Description Reset Value TIMER0_PWM TMR01_BA+0x9C R/W Timer0 PWM Status Register 0x0000_0000 STATUS TIMER1_PWM TMR01_BA+0x19C R/W Timer1 PWM Status Register 0x0000_0000 STATUS TIMER2_PWM TMR23_BA+0x9C R/W Timer2 PWM Status Register 0x0000_0000 STATUS TIMER3_PWM TMR23_BA+0x19C R/W Timer3 PWM Status Register 0x0000_0000...
Page 701 NUC126 Timer PWM Period Buffer Register (TIMERx PWMPBUF) Register Offset Description Reset Value TIMER0_PWM TMR01_BA+0xA0 R Timer0 PWM Period Buffer Register 0x0000_0000 PBUF TIMER1_PWM TMR01_BA+0x1A0 R Timer1 PWM Period Buffer Register 0x0000_0000 PBUF TIMER2_PWM TMR23_BA+0xA0 R Timer2 PWM Period Buffer Register 0x0000_0000 PBUF TIMER3_PWM...
Page 702 NUC126 Timer PWM Comparator Buffer Register (TIMERx PWMCMPBUF) Register Offset Description Reset Value TIMER0_PWM TMR01_BA+0xA4 R Timer0 PWM Comparator Buffer Register 0x0000_0000 CMPBUF TIMER1_PWM TMR01_BA+0x1A4 R Timer1 PWM Comparator Buffer Register 0x0000_0000 CMPBUF TIMER2_PWM TMR23_BA+0xA4 R Timer2 PWM Comparator Buffer Register 0x0000_0000 CMPBUF TIMER3_PWM...
Page 703: Usb Device Controller (Usbd)
NUC126 6.18 USB Device Controller (USBD) 6.18.1 Overview There is one set of USB 2.0 full-speed device controller and transceiver in this device. It is compliant with USB 2.0 full-speed device specification and supports control/bulk/interrupt/isochronous transfer types. It implements a full-speed (12 Mbit/s) function interface with added support for USB 2.0 Link Power Management.
Page 704: Block Diagram
NUC126 6.18.3 Block Diagram Clock NVIC Generator VBUS VBUS Detection Interrupt Detection DPLL control control De-bouncing status registers USB_D+ APB Bus RXDP Endpoint USB_D- RXDM Control SRAM Buffer (512 USB_VBUS Control Bytes) Transceiver Figure 6.18-1 USB Block Diagram 6.18.4 Basic Configuration User has to set the PLL related configurations before USB device controller is enabled.
Page 705 NUC126  Serial-Parallel/Parallel-Serial conversion 6.18.5.2 Endpoint Control This controller supports 8 endpoints. Each of the endpoint can be configured as Control, Bulk, Interrupt, or Isochronous transfer type. All the operations including Control, Bulk, Interrupt and Isochronous transfer are implemented in this block. It is also used to manage the data sequential synchronization, endpoint state control, current endpoint start address, current transaction status, and data buffer status in each endpoint.
Page 706: Figure 6.18-2 Wkidle Interrupt Operation Flow
NUC126 Wake Up Enable System Power Down System Wake-up Wait 20ms WKIDLE Interrupt Figure 6.18-2 WKIDLE Interrupt Operation Flow The USB interrupt is used to notify users of any USB event on the bus, and user can read EPSTS (USBD_EPSTS[31:8]) and EPEVT7~0 (USBD_INTSTS[23:16]) to take necessary responses. Same as USB interrupt, BUS interrupt notifies users of some bus events, like USB reset, suspend, time-out, and resume.
Page 707: Figure 6.18-3 Endpoint Sram Structure
NUC126 USBD_SRAM = USBD_BA + 0x0100 USB SRAM Start Address Setup Token Buffer: 8 bytes BUFSEG0 = 0x008 EP0 SA = USBD_BA + 0x0108 EP0 SRAM Buffer: 64 bytes MXPLD0 = 0x40 BUFSEG1 = 0x048 EP1 SA = USBD_BA + 0x0148 EP1 SRAM Buffer: 64 bytes MXPLD1 = 0x40 BUFSEG2 = 0x088...
Page 708: Figure 6.18-5 Data Out Transfer
NUC126 USBD_MXPLDx register needs to be written by firmware to assert the signal “Out_Rdy” again to accept the next transaction. Read Data from Buffer OUT PID Data 0/1 ACK PID OUT PID NAK PID OUT PID Data 0/1 ACK PID Bus Packets USB_IRQ Set by Hardware...
Page 709 NUC126 Disconnect, Power Loss, and Disable Reset and Enable Remote Wake enable by LPM Transaction Remote wake enabled 3ms of inactivity ACK response to LPM by SetFeature(Device, RemoteWake) Resume / Resume / Remote wake Remote wake (same as L2 to L0) Figure 6.18-6 LPM State Transition Diagram Aug.
Page 710: Register Map
NUC126 6.18.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value USBD Base Address: USBD_BA = 0x4006_0000 USBD_INTEN USBD_BA+0x000 R/W USB Device Interrupt Enable Register 0x0000_0000 USBD_INTSTS USBD_BA+0x004 R/W USB Device Interrupt Event Status Register 0x0000_0000 USBD_FADDR USBD_BA+0x008 R/W USB Device Function Address Register...
Page 711 NUC126 USBD_MXPLD4 USBD_BA+0x544 R/W Endpoint 4 Maximal Payload Register 0x0000_0000 USBD_CFG4 USBD_BA+0x548 R/W Endpoint 4 Configuration Register 0x0000_0000 USBD_CFGP4 USBD_BA+0x54C R/W Endpoint 4 Set Stall and Clear In/Out Ready Control Register 0x0000_0000 USBD_BUFSEG5 USBD_BA+0x550 R/W Endpoint 5 Buffer Segmentation Register 0x0000_0000 USBD_MXPLD5 USBD_BA+0x554 R/W Endpoint 5 Maximal Payload Register...
Page 712: 6.18.7 Register Description
NUC126 6.18.7 Register Description USB Interrupt Enable Register (USBD_INTEN) Register Offset Description Reset Value USBD_INTEN USBD_BA+0x000 R/W USB Device Interrupt Enable Register 0x0000_0000 Reserved Reserved INNAKEN Reserved WKEN Reserved SOFIEN WKIDLEIEN VBDETIEN USBIEN BUSIEN Bits Description Reserved [31:16] Reserved. Active NAK Function and Its Status in IN Token 0 = When device responds NAK after receiving IN token, IN NAK status will not be [15] INNAKEN...
Page 713 NUC126 Bus Event Interrupt Enable Bit BUSIEN 0 = BUS Event Interrupt Disabled. 1 = BUS Event Interrupt Enabled. Aug. 08, 2018 Page 713 of 943 Rev 1.03...
Page 714 NUC126 USB Interrupt Event Status Register (USBD_INTSTS) Register Offset Description Reset Value USBD_INTSTS USBD_BA+0x004 R/W USB Device Interrupt Event Status Register 0x0000_0000 SETUP Reserved EPEVT7 EPEVT6 EPEVT5 EPEVT4 EPEVT3 EPEVT2 EPEVT1 EPEVT0 Reserved Reserved SOFIF WKIDLEIF VBDETIF USBIF BUSIF Bits Description Setup Event Status [31]...
Page 715 NUC126 Endpoint 2’s USB Event Status 0 = No event occurred in endpoint 2. [18] EPEVT2 1 = USB event occurred on Endpoint 2, check USBD_EPSTS[16:14] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[18] or USBD_INTSTS[1].
Page 716 NUC126 USB Device Function Address Register (USBD_FADDR) A 7-bit value is used as the address of a device on the USB BUS. Register Offset Description Reset Value USBD_FADDR USBD_BA+0x008 R/W USB Device Function Address Register 0x0000_0000 Reserved Reserved Reserved Reserved FADDR Bits Description...
Page 717 NUC126 USB Endpoint Status Register (USBD_EPSTS) Register Offset Description Reset Value USBD_EPSTS USBD_BA+0x00C R USB Device Endpoint Status Register 0x0000_0000 EPSTS7 EPSTS6 EPSTS5 EPSTS5 EPSTS4 EPSTS3 EPSTS2 EPSTS2 EPSTS1 EPSTS0 Reserved Bits Description Endpoint 7 Status These bits are used to indicate the current status of this endpoint 000 = In ACK.
Page 718 NUC126 001 = In NAK. 010 = Out Packet Data0 ACK. 011 = Setup ACK. 110 = Out Packet Data1 ACK. 111 = Isochronous transfer end. Endpoint 3 Status These bits are used to indicate the current status of this endpoint 000 = In ACK.
Page 719 NUC126 USB Bus Status and Attribution Register (USBD_ATTR) Register Offset Description Reset Value USBD_ATTR USBD_BA+0x010 R/W USB Device Bus Status and Attribution Register 0x0000_0040 Reserved Reserved Reserved L1RESUME L1SUSPEND LPMACK BYTEM Reserved DPPUEN USBEN Reserved RWAKEUP PHYEN TOUT RESUME SUSPEND USBRST Bits Description...
Page 720 NUC126 0 = Release the USB bus from K state. 1 = Force USB bus to K (USB_D+ low, USB_D-: high) state, used for remote wake-up. PHY Transceiver Function Enable Bit PHYEN 0 = PHY transceiver function Disabled. 1 = PHY transceiver function Enabled. Time-out Status (Read Only) TOUT 0 = No time-out.
Page 721 NUC126 USB Device VBUS Detection Register (USBD_VBUSDET) Register Offset R/W Description Reset Value USBD_VBUSDET USBD_BA+0x014 R USB Device VBUS Detection Register 0x0000_0000 Reserved Reserved Reserved Reserved VBUSDET Bits Description [31:1] Reserved Reserved. Device VBUS Detection VBUSDET 0 = Controller is not attached to the USB host. 1 = Controller is attached to the USB host.
Page 722 NUC126 USB SETUP Token Buffer Segmentation Register (USBD_STBUFSEG) Register Offset R/W Description Reset Value USBD_STBUFSEG USBD_BA+0x018 R/W Setup Token Buffer Segmentation Register 0x0000_0000 Reserved Reserved Reserved STBUFSEG STBUFSEG Reserved Bits Description [31:9] Reserved Reserved. SETUP Token Buffer Segmentation It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is [8:3] STBUFSEG...
Page 723 NUC126 USB LPM Attribution Register (USBD_LPMATTR) Register Offset R/W Description Reset Value USBD_LPMATTR USBD_BA+0x088 R USB LPM Attribution Register 0x0000_0000 Reserved Reserved Reserved LPMRWAKUP LPMBESL LPMLINKSTS Bits Description [31:9] Reserved Reserved. LPM Remote Wakeup LPMRWAKUP This bit contains the bRemoteWake value received with last ACK LPM Token LPM Best Effort Service Latency These bits contain the BESL value received with last ACK LPM Token 0000 = 125us.
Page 724 NUC126 USB Frame Number Register (USBD_FN) Register Offset R/W Description Reset Value USBD_FN USBD_BA+0x08C R USB Frame number Register 0x0000_0XXX Reserved Reserved Reserved Bits Description [31:11] Reserved Reserved. Frame Number [10:0] These bits contain the 11-bits frame number in the last received SOF packet. Aug.
Page 725 NUC126 USB Drive SE0 Register (USBD_SE0) Register Offset Description Reset Value USBD_SE0 USBD_BA+0x090 R/W USB Device Drive SE0 Control Register 0x0000_0001 Reserved Reserved Reserved Reserved Bits Description [31:1] Reserved Reserved. Drive Single Ended Zero in USB Bus The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low.
Page 726 NUC126 USB Buffer Segmentation Register (USB_BUFSEGx) Register Offset Description Reset Value USBD_BUFSEG0 USBD_BA+0x500 R/W Endpoint 0 Buffer Segmentation Register 0x0000_0000 USBD_BUFSEG1 USBD_BA+0x510 R/W Endpoint 1 Buffer Segmentation Register 0x0000_0000 USBD_BUFSEG2 USBD_BA+0x520 R/W Endpoint 2 Buffer Segmentation Register 0x0000_0000 USBD_BUFSEG3 USBD_BA+0x530 R/W Endpoint 3 Buffer Segmentation Register 0x0000_0000 USBD_BUFSEG4 USBD_BA+0x540 R/W...
Page 727 NUC126 USB Maximal Payload Register (USB_MXPLDx) Register Offset Description Reset Value USBD_MXPLD0 USBD_BA+0x504 R/W Endpoint 0 Maximal Payload Register 0x0000_0000 USBD_MXPLD1 USBD_BA+0x514 R/W Endpoint 1 Maximal Payload Register 0x0000_0000 USBD_MXPLD2 USBD_BA+0x524 R/W Endpoint 2 Maximal Payload Register 0x0000_0000 USBD_MXPLD3 USBD_BA+0x534 R/W Endpoint 3 Maximal Payload Register 0x0000_0000 USBD_MXPLD4 USBD_BA+0x544 R/W...
Page 728 NUC126 USB Configuration Register (USB_CFGx) Register Offset Description Reset Value USBD_CFG0 USBD_BA+0x508 R/W Endpoint 0 Configuration Register 0x0000_0000 USBD_CFG1 USBD_BA+0x518 R/W Endpoint 1 Configuration Register 0x0000_0000 USBD_CFG2 USBD_BA+0x528 R/W Endpoint 2 Configuration Register 0x0000_0000 USBD_CFG3 USBD_BA+0x538 R/W Endpoint 3 Configuration Register 0x0000_0000 USBD_CFG4 USBD_BA+0x548 R/W...
Page 729 NUC126 This bit is used to set the endpoint as Isochronous endpoint, no handshake. 0 = No Isochronous endpoint. 1 = Isochronous endpoint. Endpoint Number [3:0] EPNUM These bits are used to define the endpoint number of the current endpoint Aug.
Page 730 NUC126 USB Extra Configuration Register (USB_CFGPx) Register Offset Description Reset Value USBD_CFGP0 USBD_BA+0x50C R/W Endpoint 0 Set Stall and Clear In/Out Ready Control Register 0x0000_0000 USBD_CFGP1 USBD_BA+0x51C R/W Endpoint 1 Set Stall and Clear In/Out Ready Control Register 0x0000_0000 USBD_CFGP2 USBD_BA+0x52C R/W Endpoint 2 Set Stall and Clear In/Out Ready Control Register 0x0000_0000...
Page 731: 6.19 Usci - Universal Serial Control Interface Controller
NUC126 6.19 USCI - Universal Serial Control Interface Controller 6.19.1 Overview The Universal Serial Control Interface (USCI) is a flexible interface module covering several serial communication protocols. The user can configure this controller as UART, SPI, or I C functional protocol.
Page 732: Figure 6.19-2 Input Conditioning For Uscix_Dat[1:0] And Uscix_Ctl[1:0]
NUC126 6.19.4.1 I/O Processer Input Signal All input stages offer the similar feature set. They are used for all protocols. Table 6.19-1 lists the relative input signals for each selected protocol. Each input signal is handled by an input processor for signal conditioning, such as signal inverse selection control, or a digital input filter.
Page 733: Figure 6.19-3 Input Conditioning For Uscix_Clk
NUC126 SYNCSEL (USCI_CLKIN[0]) USCIx_CLK Data Shift Unit Digital Filter IN_SYNC Protocol Processor Unit Figure 6.19-3 Input Conditioning for USCIx_CLK All configurations of control, clock and data input structures are in USCI_CTLIN0, USCI_CLKIN and USCI_DATIN0 registers respectively. EDGEDET (USCI_DATIN0[4:3]) is used to select the edge detection condition.
Page 734: Figure 6.19-4 Block Diagram Of Data Buffering
NUC126 6.19.4.2 Data Buffering The data handling of the USCI controller is based on a Data Shift Unit (DSU) and a buffer structure. Both of the data shift and buffer registers are 16-bit wide. The inputs of Data Shift Unit include the shift data, the serial bus clock, and the shift control.
Page 735: Figure 6.19-5 Data Access Structure
NUC126 Data Write Access (USCI_TXDAT) TX_BUF Data Read Access (USCI_RXDAT) RX_BUF0 RX_BUF1 Figure 6.19-5 Data Access Structure Transmit Data Path The transmit data path is based on 16-bit wide transmit shift register (TX_SFTR) and transmit buffer TX_BUF. The data transfer parameters like data word length is controlled commonly for transmission and reception by the line control register USCI_LINECTL.
Page 736: Figure 6.19-7 Receive Data Path
NUC126 protocol control signal if it is valid for transmission. Note: Slave can not define the start itself, but has to react.  The timing of loading data from transmit buffer to data shift unit depends on protocol configurations. UART: A transmission of the data word in transmit buffer can be started if TXEMPTY = 0 in normal operation.
Page 737: Figure 6.19-8 Protocol-Relative Clock Generator
NUC126 6.19.4.4 Protocol Control and Status The protocol-related control and status information are located in the protocol control register USCI_PROTCTL and in the protocol status register USCI_PROTSTS. These registers are shared between the available protocols. As a consequence, the meaning of the bit positions in these registers is different within the protocols.
Page 738: Figure 6.19-9 Basic Clock Divider Counter
NUC126 SAMP_CLK Divide by Divider CLKDIV +1 by 2 Divider REF_CLK PROT_CLK DIV_CLK SCLK by 2 REF_CLK2 SPCLKSEL PTCLKSEL (USCI_BRGEN[3:2]) (USCI_BRGEN[1]) Figure 6.19-9 Basic Clock Divider Counter Timing Measurement Counter The timing measurement counter is used for time interval measurement and is enabled by TMCNTEN (USCI_BRGEN [4]) = 1.
Page 739: Figure 6.19-11 Sample Time Counter
NUC126 counter allows generating time intervals for protocol-specific purposes. The period of a sample frequency f is given by the selected input frequency f and the programmed pre-divider PDS_CNT SAMP_CLK value (PDSCNT (USCI_BRGEN [9:8])). The meaning of the sample time depends on the selected protocol.
Page 740: Figure 6.19-12 Event And Interrupt Structure
NUC126 The general event and interrupt structure is shown in below. Clear Clear Event Event Interrupt Indication Indication Enable Flag Flag Event Interrupt Event Condition is met Figure 6.19-12 Event and Interrupt Structure Each general interrupt enable can set by RXENDIEN, RXSTIEN, TXENDIEN, and TXSTIEN of USCI_INTEN [4:1].
Page 741: Table 6.19-4 Protocol-Specific Events And Interrupt Handling
NUC126 Protocol-specific events in USCI_PROTSTS [13:8], USCI_PROTIEN C mode USCI_PROTSTS [5] [6:0] Table 6.19-4 Protocol-specific Events and Interrupt Handling 6.19.4.8 Wake-up The protocol-related wake-up functional information is located in the Wake-up Control Register (USCI_WKCTL) and in the Wake-up Status Register (USCI_WKSTS). These registers are shared between the available protocols.
Page 742: 6.20 Usci - Uart Mode
NUC126 6.20 USCI – UART Mode 6.20.1 Overview The asynchronous serial channel UART covers the reception and the transmission of asynchronous data frames. It performs a serial-to-parallel conversion on data received from the peripheral, and a parallel-to-serial conversion on data transmitted from the controller. The receiver and transmitter being independent, frames can start at different points in time for transmission and reception.
Page 743: Basic Configuration
NUC126 6.20.4 Basic Configuration 6.20.4.1 Basic Configuration of USCI0 UART  Clock Source Configuration Enable USCI0 peripheral clock in USCI0CKEN (CLK_APBCLK1[8]) –  Reset Configuration Reset USCI0 controller in USCI0RST (SYS_IPRST2[8]) –  Pin Configuration USCI0 pins are configured in SYS_GPA_MFPL, SYS_GPB_MFPH, SYS_GPC_MFPL and SYS_GPE_MFPL registers.
Page 744: Functional Description
NUC126 PD.12 MFP1 USCI1_CTL0 PA.0 MFP4 PA.2 MFP8 PD.7 MFP1 USCI1_CTL1 PA.1, PA.14 MFP4 PD.14 MFP1 USCI1_DAT0 PB.0 MFP6 PD.13 MFP1 USCI1_DAT1 PB.1 MFP8 6.20.4.3 Basic Configuration of USCI2 UART  Clock Source Configuration Enable USCI2 peripheral clock in USCI2CKEN (CLK_APBCLK1[10]) –...
Page 745: Figure 6.20-2 Uart Signal Connection For Full-Duplex Communication
NUC126 a receiver. The receiver input signal (RXD) is handled by the input stage USCIx_DAT0 and the transmit output (TXD) signal is handled by the output stage of USCIx_DAT1. For full-duplex communication, an independent communication line is needed for each transfer direction.
Page 746: Figure 6.20-3 Uart Standard Frame Format
NUC126 USCI_DAT0 Data Output (s) USCI_DAT1 Table 6.20-2 Output Signals for Different Protocols 6.20.5.3 Frame Format A standard UART frame is shown in following figure. It consists of:  An idle time with the signal level 1.  One start of frame bit (SOF) with the signal level 0. ...
Page 747 NUC126 level). The number of stop bits is programmable by bit STOPB (UUART_PROTCTL[0]). A new start bit can be transferred directly after the last stop bit. Transfer Status Indication RXBUSY (UUART_PROTSTS[10]) indicates the receiver status. The receiver status can be monitored by RXBUSY bit. In this case, bit RXBUSY is set during a complete frame reception from the beginning of the start of frame bit to the end of the last stop bit.
Page 748: Figure 6.20-4 Uart Bit Timing (Data Sample Time)
NUC126 Sample Time sample taken Figure 6.20-4 UART Bit Timing (data sample time) 6.20.5.6 Baud Rate Generation The baud rate f in UART mode depends on the number of data sample time per bit time and their UART timing. The baud rate setting should only be changed while the transmitter and the receiver are idle. The bits RCLKSEL, SPCLKSEL, PDSCNT, and DSCNT define the baud rate setting: ...
Page 749: Figure 6.20-5 Uart Auto Baud Rate Control
NUC126 measurement counter value into the BRDETITV (UUART_PROTCTL [24:16]) in the next falling edge. It is suggested to use the f (TMCNTSRC (UUART_BRGENC[5]) =1) as the counter source. DIV_CLK The CLKDIV (UUART_BRGEN[25:16]) will be revised by BRDETITV (UUART_PROTCTL [25:16]) after the auto baud rate function done (the time of 4 falling edge of input signal).
Page 750: Figure 6.20-6 Incoming Data Wake-Up
NUC126 0x55 0x33 and 0xAA will be 1, 1, 0, 0 and 1. The UART controller also can play as an RS-485 addressable slave, the protocol-related error of PARITYERR (UUART_PROTSTS[5]) can be acted as the address bit detection when the PARITYEN (UUART_PROTCTL[1]), EVENPARITY (UUART_PROTCTL[2])
Page 751: Figure 6.20-8 Ncts Wake-Up Case 2
NUC126 Case 2 (nCTS transition from high to low): Power-down mode stable count CPU run USCIx_CTL0 (nCTS) Note1: Stable count means HCLK source recovery stable count. Figure 6.20-8 nCTS Wake-Up Case 2 6.20.5.11 Interrupt Events Protocol Interrupt Events The following protocol-related events are generated in UART mode and can lead to a protocol interrupt.
Page 752 NUC126 This interrupt indicates that the transmitter has completely finished all data in the buffer. Bit TXENDIF (UUART_PROTSTS [2]) becomes set at the end of the last stop bit.  Receiver starts interrupt: Bit RXSTIF (UUART_PROTSTS [3]) is set after the sample point of the start bit. ...
Page 753: 6.20.6 Register Map
NUC126 6.20.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value UUART Base Address: UUARTx_BA = 0x4007_0000 + (0x10_0000 * x) x = 0, 1 UUART2_BA = 0x4007_4000 UUART_CTL R/W USCI Control Register 0x0000_0000 UUARTx_BA+0x00 UUART_INTEN...
Page 754: 6.20.7 Register Description
NUC126 6.20.7 Register Description USCI Control Register (UUART_CTL) Register Offset Description Reset Value UUART_CTL UUARTx_BA+0x00 R/W USCI Control Register 0x0000_0000 Reserved Reserved Reserved Reserved FUNMODE Bits Description [31:3] Reserved Reserved. Function Mode This bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI.
Page 755 NUC126 USCI Interrupt Enable Register (UUART_INTEN) Register Offset Description Reset Value UUART_INTEN UUARTx_BA+0x04 R/W USCI Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved RXENDIEN RXSTIEN TXENDIEN TXSTIEN Reserved Bits Description [31:5] Reserved Reserved. Receive End Interrupt Enable Bit This bit enables the interrupt generation in case of a receive finish event. RXENDIEN 0 = The receive end interrupt Disabled.
Page 756 NUC126 USCI Baud Rate Generator Register (UUART_BRGEN) Register Offset R/W Description Reset Value UUART_BRGEN UUARTx_BA+0x08 R/W USCI Baud Rate Generator Register 0x0000_3C00 Reserved CLKDIV CLKDIV Reserved DSCNT PDSCNT Reserved TMCNTSRC TMCNTEN SPCLKSEL PTCLKSEL RCLKSEL Bits Description [31:26] Reserved Reserved. Clock Divider This bit field defines the ratio between the protocol clock frequency f and the clock PROT_CLK...
Page 757 NUC126 protocol processor. 00 = f SAMP_CLK DIV_CLK. 01 = f SAMP_CLK PROT_CLK. 10 = f SAMP_CLK SCLK. 11 = f SAMP_CLK REF_CLK. Protocol Clock Source Selection This bit selects the source signal of protocol clock (f PROT_CLK PTCLKSEL 0 = Reference clock f REF_CLK.
Page 758 NUC126 USCI Input Data Signal Configuration (UUART_DATIN0) Register Offset R/W Description Reset Value UUART_DATIN0 UUARTx_BA+0x10 R/W USCI Input Data Signal Configuration Register 0 0x0000_0000 Reserved Reserved Reserved Reserved EDGEDET ININV Reserved SYNCSEL Bits Description [31:5] Reserved Reserved. Input Signal Edge Detection Mode This bit field selects which edge actives the trigger event of input data signal.
Page 759 NUC126 USCI Input Control Signal Configuration (UUART_CTLIN0) Register Offset R/W Description Reset Value UUART_CTLIN0 UUARTx_BA+0x20 R/W USCI Input Control Signal Configuration Register 0 0x0000_0000 Reserved Reserved Reserved Reserved ININV Reserved SYNCSEL Bits Description [31:3] Reserved Reserved. Input Signal Inverse Selection This bit defines the inverter enable of the input asynchronous signal.
Page 760 NUC126 USCI Input Clock Signal Configuration (UUART_CLKIN) Register Offset Description Reset Value UUART_CLKIN UUARTx_BA+0x28 R/W USCI Input Clock Signal Configuration Register 0x0000_0000 Reserved Reserved Reserved Reserved SYNCSEL Bits Description [31:1] Reserved Reserved. Input Synchronization Signal Selection This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
Page 761 NUC126 USCI Line Control Register (UUART_LINECTL) Register Offset R/W Description Reset Value UUART_LINECTL UUARTx_BA+0x2C R/W USCI Line Control Register 0x0000_0000 Reserved Reserved Reserved DWIDTH CTLOINV Reserved DATOINV Reserved Bits Description [31:12] Reserved Reserved. Word Length of Transmission This bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer.
Page 762 NUC126 LSB First Transmission Selection 0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first. 1 = The LSB, the bit 0 of data buffer, will be transmitted/received first. Aug. 08, 2018 Page 762 of 943 Rev 1.03...
Page 763 NUC126 USCI Transmit Data Register (UUART_TXDAT) Register Offset Description Reset Value UUART_TXDAT UUARTx_BA+0x30 W USCI Transmit Data Register 0x0000_0000 Reserved Reserved TXDAT TXDAT Bits Description [31:16] Reserved Reserved. Transmit Data [15:0] TXDAT Software can use this bit field to write 16-bit transmit data for transmission. Aug.
Page 764 NUC126 USCI Receive Data Register (UUART_RXDAT) Register Offset R/W Description Reset Value UUART_RXDAT UUARTx_BA+0x34 R USCI Receive Data Register 0x0000_0000 Reserved Reserved RXDAT RXDAT Bits Description [31:16] Reserved Reserved. Received Data This bit field monitors the received data which stored in receive data buffer. [15:0] RXDAT Note: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and...
Page 765 NUC126 USCI Transmitter/Receive Buffer Control Register (UUART_BUFCTL) Register Offset R/W Description Reset Value UUART_BUFCTL UUARTx_BA+0x38 R/W USCI Transmit/Receive Buffer Control Register 0x0000_0000 Reserved Reserved RXRST TXRST RXCLR RXOVIEN Reserved TXCLR Reserved Bits Description [31:18] Reserved Reserved. Receive Reset 0 = No effect. 1 = Reset the receive-related counters, state machine, and the content of receive shift [17] RXRST...
Page 766 NUC126 [6:0] Reserved Reserved. Aug. 08, 2018 Page 766 of 943 Rev 1.03...
Page 767 NUC126 USCI Transmit/Receive Buffer Status Register (UUART_BUFSTS) Register Offset R/W Description Reset Value UUART_BUFSTS UUARTx_BA+0x3C R USCI Transmit/Receive Buffer Status Register 0x0000_0101 Reserved Reserved Reserved TXFULL TXEMPTY Reserved RXOVIF Reserved RXFULL RXEMPTY Bits Description [31:10] Reserved Reserved. Transmit Buffer Full Indicator TXFULL 0 = Transmit buffer is not full.
Page 768 NUC126 USCI Wake-up Control Register (UUART_WKCTL) Register Offset R/W Description Reset Value UUART_WKCTL UUARTx_BA+0x54 R/W USCI Wake-up Control Register 0x0000_0000 Reserved Reserved Reserved Reserved PDBOPT Reserved WKEN Bits Description [31:3] Reserved Reserved. Power Down Blocking Option 0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately.
Page 769 NUC126 USCI Wake-up Status Register (UUART_WKSTS) Register Offset R/W Description Reset Value UUART_WKSTS UUARTx_BA+0x58 R/W USCI Wake-up Status Register 0x0000_0000 Reserved Reserved Reserved Reserved Bits Description [31:1] Reserved Reserved. Wake-up Flag When chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
Page 770 NUC126 USCI Protocol Control Register – UART (UUART_PROTCTL) Register Offset R/W Description Reset Value UUART_PROTCTL UUARTx_BA+0x5C R/W USCI Protocol Control Register 0x0000_0000 PROTEN Reserved BCEN Reserved Reserved STICKEN Reserved BRDETITV BRDETITV Reserved WAKECNT CTSWKEN DATWKEN Reserved Reserved ABREN RTSAUDIREN CTSAUTOEN RTSAUTOEN EVENPARITY PARITYEN STOPB Bits...
Page 771 NUC126 0 = nCTS wake-up mode Disabled. 1 = nCTS wake-up mode Enabled. Data Wake-up Mode Enable Bit DATWKEN 0 = Data wake-up mode Disabled. 1 = Data wake-up mode Enabled. Auto-baud Rate Detect Enable Bit 0 = Auto-baud rate detect function Disabled. 1 = Auto-baud rate detect function Enabled.
Page 772 NUC126 USCI Protocol Interrupt Enable Register – UART (UUART_PROTIEN) Register Offset R/W Description Reset Value UUART_PROTIEN UUARTx_BA+0x60 R/W USCI Protocol Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved RLSIEN ABRIEN Reserved Bits Description [31:3] Reserved Reserved. Receive Line Status Interrupt Enable Bit 0 = Receive line status interrupt Disabled.
Page 773 NUC126 USCI Protocol Status Register – UART (UUART_PROTSTS) Register Offset R/W Description Reset Value UUART_PROTSTS UUARTx_BA+0x64 R/W USCI Protocol Status Register 0x0000_0000 Reserved Reserved CTSLV CTSSYNCLV Reserved ABERRSTS RXBUSY ABRDETIF Reserved BREAK FRMERR PARITYERR RXENDIF RXSTIF TXENDIF TXSTIF Reserved Bits Description [31:18] Reserved...
Page 774 NUC126 data. If the ABRIEN (UUART_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated. This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus. 0 = Auto-baud rate detect function is not done.
Page 775: 6.21 Usci - Spi Mode
NUC126 6.21 USCI - SPI Mode 6.21.1 Overview The SPI protocol of USCI controller applies to synchronous serial data communication and allows full duplex transfer. It supports both master and Slave operation mode with the 4-wire bi-direction interface. SPI mode of USCI controller performs a serial-to-parallel conversion on data received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device.
Page 776: Block Diagram
NUC126   Supports 3-wire, no slave select signal, bi-direction interface  Supports wake-up function by slave select signal in Slave mode  Supports one data channel half-duplex transfer 6.21.3 Block Diagram PCLK Protocol-Relative USCIx_CLK Clock Generator USCIx_CTL0 Peripheral Input USCIx_DAT0/1 Device Data...
Page 777 NUC126 PE.4 MFP4 USCI0_CTL0 PC.3 MFP5 PB.8, PE.2 MFP8 PC.2, PC.7 MFP4 USCI0_CTL1 PB.4 MFP8 PC.0, PC.5 MFP4 USCI0_DAT0 PB.2 MFP8 PC.1, PC.6 MFP4 USCI0_DAT1 PB.3 MFP8 6.21.4.2 Basic Configuration of USCI1 SPI  Clock Source Configuration Enable USCI1 peripheral clock in USCI1CKEN (CLK_APBCLK1[9]). –...
Page 778: Functional Description
NUC126  Reset Configuration Reset USCI2 controller in USCI2RST (SYS_IPRST2[10]). –  Pin Configuration Group Pin Name GPIO PC.11, PD.1 MFP4 USCI2_CLK PF.2 MFP5 PC.12, PD.0, PD.9 MFP4 USCI2_CTL0 PF.1 MFP5 PB.7, PC.9, PD.8 MFP4 USCI2 USCI2_CTL1 PF.0 MFP5 PC.13, PD.2 MFP4 USCI2_DAT0 PD.10...
Page 779: Figure 6.21-4 Wire Full-Duplex Spi Communication Signals (Master Mode)
NUC126 SPI_SS Data Frame (USCIx_CTL0) SPI_CLK (USCIx_CLK) SPI_MOSI TX Data Word 0 TX Data Word N (USCIx_DAT0) SPI_MISO RX Data Word 0 RX Data Word N (USCIx_DAT1) Note: x = 0, 1, 2 Figure 6.21-4 Wire Full-Duplex SPI Communication Signals (Master Mode) SPI_SS Data Frame (USCIx_CTL0)
Page 780: Figure 6.21-6 Spi Communication With Different Spi Clock Configuration (Sclkmode=0X0)
NUC126 In SPI protocol, SCLKMODE (USPI_PROTCTL[7:6]) defines not only the idle state of serial bus clock but also the serial clock edge used for transmit and receive data. Both Master and Slave devices on the same communication bus should have the same SCLKMODE configuration. The four kinds of serial bus clock configuration are shown below.
Page 781: Figure 6.21-7 Spi Communication With Different Spi Clock Configuration (Sclkmode=0X1)
NUC126 SPI_SS Data Frame (USCIx_CTL0) SPI_CLK (USCIx_CLK) SPI_MOSI TX[n] [n-1] TX[0] TX[n] [n-1] TX[0] (USCIx_DAT0) SPI_MISO RX[n] [n-1] RX[0] RX[n] [n-1] RX[0] (USCIx_DAT1) Data N Data (N+1) USPI_PROTCTL[0] = 0; USPI_PROTCTL[7:6] = 0x1; USPI_CTLIN0[2] = 1; USPI_LINECTL[0] = 0; Note: x = 0,1,2 USPI_LINECTL[7] = 1;...
Page 782: Figure 6.21-9 Spi Communication With Different Spi Clock Configuration (Sclkmode=0X3)
NUC126 SPI_SS Data Frame (USCIx_CTL0) SPI_CLK (USCIx_CLK) SPI_MOSI TX[n] [n-1] TX[0] TX[n] [n-1] TX[0] (USCIx_DAT0) SPI_MISO RX[n] [n-1] RX[0] RX[n] [n-1] RX[0] (USCIx_DAT1) Data N Data (N+1) USPI_PROTCTL[0] = 0; USPI_PROTCTL[7:6] = 0x3; USPI_CTLIN0[2] = 1; USPI_LINECTL[0] = 0; Note: x = 0,1,2 USPI_LINECTL[7] = 1;...
Page 783: Figure 6.21-1016-Bit Data Length In One Word Transaction With Msb First Format
NUC126 SPI_SS (USCIx_CTL0) SPI_CLK (USCIx_CLK) SPI_MOSI TX[14] TX[8] TX[7] TX[6] TX[15] TX[0] (USCIx_DAT0) SPI_MISO RX[14] RX[8] RX[7] RX[6] RX[15] RX[0] (USCIx_DAT1) Note: x = 0,1,2 Figure 6.21-1016-bit data Length in One Word Transaction with MSB First Format 6.21.5.6 Word Suspend SUSPITV (USPI_PROTCTL[11:8]) provide a configurable suspend interval, 0.5 ~ 15.5 SPI clock periods, between two successive transaction words in Master mode.
Page 784: Figure 6.21-12 Auto Slave Select (Suspitv ≧ 0X3)
NUC126 In SPI Master mode, if the value of SUSPITV (USPI_PROTCTL[11:8]) is less than 3 and the AUTOSS (USPI_PROTCTL[3]) is set as 1, the slave select signal will be kept at active state between two successive word transactions. In SPI Slave mode, to recognize the inactive state of the slave select signal, the inactive period of the received slave select signal must be larger than 2 peripheral clock cycles between two successive transactions.
Page 785: Figure 6.21-14 One Output Data Channel Half-Duplex (Spi Master Mode)
NUC126 are required to communicate with a SPI Master. When the SLV3WIRE (USPI_PROTCTL[1]) is set to 1, the SPI Slave will be ready to transmit/receive data after the SPI protocol is enabled by setting FUNMODE(USPI_CTL [2:0]) to 0x1. 6.21.5.9 Data Transfer Mode The USCI controller supports full-duplex SPI transfer and one data channel half-duplex SPI transfer.
Page 786: Figure 6.21-15 One Input Data Channel Half-Duplex (Spi Master Mode)
NUC126 USCI SPI Master USCI SPI Master SPI Slave Device Master Receive Data SPI_MOSI SPI Data Out (USCIx_DAT0) Serial Bus Clock SPI_CLK SPI_CLK (USCIx_CLK) Slave Select SPI_SS SPI_SS (USCIx_CTL) Note: x = 0, 1, 2 Figure 6.21-15 One Input Data Channel Half-duplex (SPI Master Mode) The one data channel half-duplex transfer mode can be configured...
Page 787 NUC126  Slave time-out interrupt In SPI Slave mode, there is Slave time-out function for user to know that there is no serial clock input during the period of one word transaction. The Slave time-out function uses the timing measurement counter for the calculation of Slave time-out period which is defined by SLVTOCNT (USPI_PROTCTL[25:16]).
Page 788: Figure 6.21-16 Spi Timing In Master Mode
NUC126 CTLOINV=0 SPI_SS CTLOINV=1 SCLKMODE=0x0 SPI_CLK SCLKMODE=0x2 SPI_MOSI TX[6] TX[5] TX[4] TX[3] TX[2] TX[1] TX[7] TX[0] SPI_MISO RX[6] RX[5] RX[4] RX[3] RX[2] RX[1] RX[7] RX[0] Master Mode: FUNMODE=0x1, SLAVE=0, LSB=0, DWIDTH=0x8 Figure 6.21-16 SPI Timing in Master Mode CTLOINV=0 SPI_SS CTLOINV=1 SCLKMODE=0x1 SPI_CLK...
Page 789: Figure 6.21-18 Spi Timing In Slave Mode
NUC126 CTLOINV=0 SPI_SS CTLOINV=1 SCLKMODE=0x0 SPI_CLK SCLKMODE=0x2 SPI_MISO TX0[6] TX0[0] TX1[7] TX1[6] TX0[7] TX1[0] SPI_MOSI RX0[6] RX0[0] RX1[7] RX1[6] RX0[7] RX1[0] Slave Mode: FUNMODE=0x1, SLAVE=1, SLV3WIRE=0, LSB=0, DWIDTH=0x8 Figure 6.21-18 SPI Timing in Slave Mode CTLOINV=0 SPI_SS CTLOINV=1 SCLKMODE=0x1 SPI_CLK SCLKMODE=0x3 SPI_MISO TX0[1]...
Page 790 NUC126 4. Set USPI_BRGEN register to determine the SPI bus clock frequency. 5. According to the requirements of user’s application, configured the settings as follows.  CTLOINV (USPI_LINECTL[7]): If the slave selection signal is active low, set this bit to 1; otherwise, set it to 0.
Page 791 NUC126 protocol is the transition of input slave select signal. Aug. 08, 2018 Page 791 of 943 Rev 1.03...
Page 792: 6.21.6 Register Map
NUC126 6.21.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value USPI Base Address: USPIx_BA = 0x4007_0000 + (0x10_0000 * x) x = 0, 1 USPI2_BA = 0x4007_4000 USPI_CTL R/W USCI Control Register 0x0000_0000 USPIx_BA+0x00 USPI_INTEN...
Page 793: 6.21.7 Register Description
NUC126 6.21.7 Register Description USCI Control Register (USPI_CTL) Register Offset Description Reset Value USPI_CTL USPIx_BA+0x00 USCI Control Register 0x0000_0000 Reserved Reserved Reserved Reserved FUNMODE Bits Description [31:3] Reserved Reserved. Function Mode This bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI.
Page 794 NUC126 USCI Interrupt Enable Register (USPI_INTEN) Register Offset Description Reset Value USPI_INTEN USPIx_BA+0x04 USCI Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved RXENDIEN RXSTIEN TXENDIEN TXSTIEN Reserved Bits Description [31:5] Reserved Reserved. Receive End Interrupt Enable Bit This bit enables the interrupt generation in case of a receive finish event. RXENDIEN 0 = The receive end interrupt Disabled.
Page 795 NUC126 USCI Baud Rate Generator Register (USPI_BRGEN) Register Offset Description Reset Value USPI_BRGEN USPIx_BA+0x08 USCI Baud Rate Generator Register 0x0000_3C00 Reserved CLKDIV CLKDIV Reserved Reserved TMCNTSRC TMCNTEN SPCLKSEL PTCLKSEL RCLKSEL Bits Description [31:26] Reserved Reserved. Clock Divider This bit field defines the ratio between the protocol clock frequency f and the clock PROT_CLK [25:16]...
Page 796 NUC126 0 = Peripheral device clock f PCLK. 1 = Reserved. Aug. 08, 2018 Page 796 of 943 Rev 1.03...
Page 797 NUC126 USCI Input Data Signal Configuration (USPI_DATIN0) Register Offset Description Reset Value USPI_DATIN0 USPIx_BA+0x10 USCI Input Data Signal Configuration Register 0 0x0000_0000 Reserved Reserved Reserved Reserved ININV Reserved SYNCSEL Bits Description [31:3] Reserved Reserved. Input Signal Inverse Selection This bit defines the inverter enable of the input asynchronous signal. ININV 0 = The un-synchronized input signal will not be inverted.
Page 798 NUC126 USCI Input Control Signal Configuration (USPI_CTLIN0) Register Offset Description Reset Value USPI_CTLIN0 USPIx_BA+0x20 USCI Input Control Signal Configuration Register 0 0x0000_0000 Reserved Reserved Reserved Reserved ININV Reserved SYNCSEL Bits Description [31:3] Reserved Reserved. Input Signal Inverse Selection This bit defines the inverter enable of the input asynchronous signal. ININV 0 = The un-synchronized input signal will not be inverted.
Page 799 NUC126 USCI Input Clock Signal Configuration (USPI_CLKIN) Register Offset Description Reset Value USPI_CLKIN USPIx_BA+0x28 USCI Input Clock Signal Configuration Register 0x0000_0000 Reserved Reserved Reserved Reserved SYNCSEL Bits Description [31:1] Reserved Reserved. Input Synchronization Signal Selection This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
Page 800 NUC126 USCI Line Control Register (USPI_LINECTL) Register Offset Description Reset Value USPI_LINECTL USPIx_BA+0x2C USCI Line Control Register 0x0000_0000 Reserved Reserved Reserved DWIDTH CTLOINV Reserved DATOINV Reserved Bits Description [31:12] Reserved Reserved. Word Length of Transmission This bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer.
Page 801 NUC126 0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first. 1 = The LSB, the bit 0 of data buffer, will be transmitted/received first. Aug. 08, 2018 Page 801 of 943 Rev 1.03...
Page 802 NUC126 USCI Transmit Data Register (USPI_TXDAT) Register Offset Description Reset Value USPI_TXDAT USPIx_BA+0x30 USCI Transmit Data Register 0x0000_0000 Reserved Reserved PORTDIR TXDAT TXDAT Bits Description [31:17] Reserved Reserved. Port Direction Control This bit field is only available while USCI operates in SPI protocol (FUNMODE = 0x1) with half-duplex transfer.
Page 803 NUC126 USCI Receive Data Register (USPI_RXDAT) Register Offset Description Reset Value USPI_RXDAT USPIx_BA+0x34 USCI Receive Data Register 0x0000_0000 Reserved Reserved RXDAT RXDAT Bits Description [31:16] Reserved Reserved. Received Data [15:0] RXDAT This bit field monitors the received data which stored in receive data buffer. Aug.
Page 804 NUC126 USCI Transmit/Receive Buffer Control Register (USPI_BUFCTL) Register Offset Description Reset Value USPI_BUFCTL USPIx_BA+0x38 USCI Transmit/Receive Buffer Control Register 0x0000_0000 Reserved Reserved RXRST TXRST RXCLR RXOVIEN Reserved TXCLR TXUDRIEN Reserved Bits Description [31:18] Reserved Reserved. Receive Reset 0 = No effect. [17] RXRST 1 = Reset the receive-related counters, state machine, and the content of receive shift...
Page 805 NUC126 1 = Transmit under-run interrupt Enabled. [5:0] Reserved Reserved. Aug. 08, 2018 Page 805 of 943 Rev 1.03...
Page 806 NUC126 USCI Transmit/Receive Buffer Status Register (USPI_BUFSTS) Register Offset Description Reset Value USPI_BUFSTS USPIx_BA+0x3C USCI Transmit/Receive Buffer Status Register 0x0000_0101 Reserved Reserved Reserved TXUDRIF Reserved TXFULL TXEMPTY Reserved RXOVIF Reserved RXFULL RXEMPTY Bits Description [31:12] Reserved Reserved. Transmit Buffer Under-run Interrupt Status This bit indicates that a transmit buffer under-run event has been detected.
Page 807 NUC126 0 = Receive buffer is not empty. 1 = Receive buffer is empty. Aug. 08, 2018 Page 807 of 943 Rev 1.03...
Page 808 NUC126 USCI Wake-up Control Register (USPI_WKCTL) Register Offset Description Reset Value USPI_WKCTL USPIx_BA+0x54 USCI Wake-up Control Register 0x0000_0000 Reserved Reserved Reserved Reserved PDBOPT WKADDREN WKEN Bits Description [31:3] Reserved Reserved. Power Down Blocking Option 0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately.
Page 809 NUC126 USCI Wake-up Status Register (USPI_WKSTS) Register Offset Description Reset Value USPI_WKSTS USPIx_BA+0x58 USCI Wake-up Status Register 0x0000_0000 Reserved Reserved Reserved Reserved Bits Description [31:1] Reserved Reserved. Wake-up Flag When chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
Page 810 NUC126 USCI Protocol Control Register – SPI (USPI_PROTCTL) Register Offset Description Reset Value USPI_PROTCTL USPIx_BA+0x5C R/W USCI Protocol Control Register 0x0000_0300 PROTEN Reserved TXUDRPOL Reserved SLVTOCNT SLVTOCNT Reserved TSMSEL SUSPITV SCLKMODE Reserved AUTOSS SLV3WIRE SLAVE Bits Description SPI Protocol Enable Bit [31] PROTEN 0 = SPI Protocol Disabled.
Page 811 NUC126 edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation. (SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle Example: SUSPITV = 0x0 …. 0.5 SPI_CLK clock cycle. SUSPITV = 0x1 ….
Page 812 NUC126 USCI Protocol Interrupt Enable Register – SPI (USPI_PROTIEN) Register Offset Description Reset Value USPI_PROTIEN USPIx_BA+0x60 USCI Protocol Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved SLVBEIEN SLVTOIEN SSACTIEN SSINAIEN Bits Description [31:4] Reserved Reserved. Slave Mode Bit Count Error Interrupt Enable Bit If data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH SLVBEIEN...
Page 813 NUC126 USCI Protocol Status Register – SPI (USPI_PROTSTS) Register Offset Description Reset Value USPI_PROTSTS USPIx_BA+0x64 USCI Protocol Status Register 0x0000_0000 Reserved Reserved SLVUDR BUSY SSLINE Reserved SSACTIF SSINAIF Reserved SLVBEIF SLVTOIF RXENDIF RXSTIF TXENDIF TXSTIF Reserved Bits Description [31:19] Reserved Reserved.
Page 814 NUC126 1 = The slave select signal has changed to active. Note: The internal slave select signal is active high. Slave Select Inactive Interrupt Flag (for Slave Only) This bit indicates that the internal slave select signal has changed to inactive. It is cleared by software writes 1 to this bit SSINAIF 0 = The slave select signal has not changed to inactive.
Page 815: Usci - I C Mode
NUC126 6.22 USCI - I C Mode 6.22.1 Overview On I C bus, data is transferred between a Master and a Slave. Data bits transfer on the SCL and SDA lines are synchronously on a byte-by-byte basis. Each data byte is 8-bit. There is one SCL clock pulse for each data bit with the MSB being transmitted first, and an acknowledge bit follows each transferred byte.
Page 816: 6.22.3 Block Diagram
NUC126 6.22.3 Block Diagram PCLK Baud Rate USCI_CLK Generation Peripheral Input Protocol USCI_DATx Device Data Processor Processor Buffer Data User Shift Control Buffer Unit Interface Unit Output Configuration Wake-up Control Control Register To Interrupt Interrupt Signal Generation Figure 6.22-2 USCI I²C Mode Block Diagram 6.22.4 Basic Configuration 6.22.4.1 Basic Configuration of USCI0-I2C...
Page 817 NUC126 PB.2 MFP8 PC.1, PC.6 MFP4 USCI0_DAT1 PB.3 MFP8 6.22.4.2 Basic Configuration of USCI1-I2C  Clock Source Configuration Enable USCI1-I2C peripheral clock in USCI1CKEN (CLK_APBCLK1[9]). –  Reset Configuration Reset USCI1-I2C controller in USCI1RST (SYS_IPRST2[9]). –  Pin Configuration Group Pin Name GPIO PD.15...
Page 818: Functional Description
NUC126 PB.7, PC.9, PD.8 MFP4 USCI2_CTL1 PF.0 MFP5 PC.13, PD.2 MFP4 USCI2_DAT0 PD.10 MFP5 PC.10, PD.3 MFP4 USCI2_DAT1 PD.11 MFP5 6.22.5 Functional Description 6.22.5.1 START or Repeated START Signal Figure 6.22-2 shows the typical I C protocol. Normally, a standard communication consists of four parts: ...
Page 819: Figure 6.22-4 Start And Stop Conditions
NUC126 Repeated START STOP START STOP START Figure 6.22-4 START and STOP Conditions 6.22.5.3 Slave Address Transfer After a (repeated) start condition, the master sends a slave address to identify the target device of the communication. The start address can comprise one or two address bytes (for 7-bit or for 10-bit addressing schemes).
Page 820: Figure 6.22-5 Bit Transfer On The I 2 C Bus
NUC126 Data line stable; Change of data data valid allowed Figure 6.22-5 Bit Transfer on the I C Bus If the master received data, does Not Acknowledge (NACK) the slave, the slave releases the SDA line for the master to generate a STOP or Repeated START signal. Clock pulse for acknowledgement from Master...
Page 821: Figure 6.22-7 Arbitration Lost
NUC126 and SPCLKSEL = 2’b00 (f ). Under these conditions, the baud rate is given by: SAMP_CLK DIV_CLK In order to generate slower frequencies, additional divide-by-2 stages can be selected by PTCLKSEL = 1 (f ), leading to: PROT_CLK REF_CLK2 If SPCLKSEL = 2’b10 (f ), and RCLKSEL = 0 (f ), PTCLKSEL = 0 (f...
Page 822 NUC126 master has lost the transmit arbitration. This is indicated by interrupt flag ARBLOIF (UI2C_PROTSTS [11]) and can generate a protocol interrupt if enabled by ARBLOIEN (UI2C_PROTIEN [4]). When the transmit arbitration has been lost, the software has to initialize the complete frame again, starting with the first address byte together with the start condition for a new master transmit attempt.
Page 823 NUC126 -Step 1. Set FUNMODE (UI2C_CTL [2:0]) = 000b -Step 2. Set FUNMODE (UI2C_CTL [2:0]) = 100b Pin connections: The pins used for SDA and SCL have to be set to open-drain mode by USCI controller to support the wired-AND structure of the I C bus lines.
Page 824: Figure 6.22-8 Control I C Bus According To Current I C Status
NUC126 Figure 6.22-8 Control I C Bus according to Current I C Status Aug. 08, 2018 Page 824 of 943 Rev 1.03...
Page 825: Figure 6.22-9 Master Transmits Data To Slave With A 7-Bit Address
NUC126 Data Transfer on the I C Bus Figure 6.22-9 shows a master transmits data to slave. A master addresses a slave with a 7-bit address and 1-bit write index to denote that the master wants to transmit data to the slave. The master keeps transmitting data after the slave returns acknowledge to the master.
Page 826: Figure 6.22-12 Master Reads Data From Slave By 10-Bit Address
NUC126 ADDRESS 1st byte ADDRESS 2nd byte ‘0’ : write 11110XX ADDRESS 1st byte DATA DATA data transfer ‘1’ : read (n bytes + acknowlegde) 11110XX Figure 6.22-12 Master Reads Data from Slave by 10-bit address Master Mode In Figure 6.22-13, all possible protocols for I C master are shown.
Page 827: Figure 6.22-14 Master Receiver Mode Control Flow With 7-Bit Address
NUC126 ACKIF = 1 STARIF = 1 ACKIF = 1 TXDAT RXDAT (SLA+R) (Data) (RTRG, STA, STO, AA)=(0, 1, 0, x) (PTRG, STA, STO, AA)=(1, 0, 0, 1) Clear protocol status register Writing 1 to ACKIF ARBLOIF = 1 TXDAT = SLA+R RXDAT (PTRG, STA, STO, AA)=(1, 0, 0, x) Write 1 to STARIF...
Page 828: Figure 6.22-15 Save Mode Control Flow With 7-Bit Address
NUC126 C communication, the SCL clock will be released when writing ‘1’ to PTRG Note: During I (UI2C_PROTCTL [5]) in Slave mode. ACKIF = 1 ACKIF = 1 Switch to not addressed mode Own SLA will be recognized RXDAT RXDAT (Data) (SLA+W) ((PTRG, STA, STO, AA)=(0, 0, 0, 1)
Page 829 NUC126 STARIF (UI2C_PROTSTS [8]) is set. Note: After slave gets interrupt flag of NACKIF (UI2C_PROTSTS [10]) and start/stop symbol including STARIF (UI2C_PROTSTS [8]) and STORIF (UI2C_PROTSTS [9]), slave can switch to not address mode and own SLA will not be recognized. If setting this interrupt flag, slave will not receive any I signal or address from master.
Page 830: Figure 6.22-16 Gc Mode With 7-Bit Address
NUC126 ACKIF = 1 ACKIF = 1 Switch to not addressed mode Address 0x0 will be recognized RXDAT RXDAT (SLA+W=0x00) (Data) (PTRG, STA, STO, AA)=(0, 0, 0, 1) (PTRG, STA, STO, AA)=(1, 0, 0, 1) GCFUNC = 1 Writing 1 to ACKIF Clear protocol status register ACKIF = 1 RXDAT...
Page 831: Table 6.22-1 Relationship Between I 2 C Baud Rate And Pclk
NUC126 When I C enter monitor mode, this device always returns NACK to master after each frame reception even address matching. Moreover, this device will store any receive data including address, command code, and data. Note that monitor mode not support 10-bit mode. Interrupt in Monitor mode All interrupts will occur as normal process when the MONEN (UI2C_PROTCTL [9]) is set.
Page 832: Figure 6.22-17 Setup Time Wrong Adjustment
NUC126 For setup time wrong adjustment example, we assume one SCL cycle contains ten PCLKs and set STCTL [5:0] (UI2C_TMCTL[5:0]) to 3 that stretch three PCLKs for setup time setting. The setup time setting limitation: ST = (UI2C_BRGEN[25:16]+1) - 6. For example, if user decide PCLK = 12MHz limit and baud rate =100k, the UI2C_BRGEN[25:16] must set 59, and the STCTL [5:0] maximum value is Two PCLKs can not sample for SCL...
Page 833: Figure 6.22-19 I 2 C Time-Out Count Block Diagram
NUC126 TOCNT Interrupt signal SAMP_CLK Internal counter TOIF Enable Clear Counter TOIEN Writing TOIF 1 C interrupt signal (ACKIF, NACKIF, ...) Figure 6.22-19 I C Time-out Count Block Diagram Wake-up Function When chip enters Power-down mode and set WKEN (WKCTL[0]) to 1, other I C master can wake-up our chip by addressing our I C device, user must configure the related setting before entering sleep...
Page 834: Figure 6.22-20 Eeprom Random Read
NUC126 7. Set ACKIEN, ERRIEN, ARBLOIEN, NACKIEN, STORIEN, STARIEN, and TOIEN to enable C Interrupt in the “UI2C_PROTIEN” register. 8. Set USCI address registers “USCI_ADDR0 ~ USCI_ADDR1”. Random read operation is one of the methods of access EEPROM. The method allows the master to access any address of EEPROM space.
Page 835: 6.22.6 Register Map
NUC126 6.22.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value UI2C Base Address: UI2Cx_BA = 0x4007_0000 + (0x10_0000 * x) x = 0, 1 UI2C2_BA = 0x4007_4000 UI2C_CTL R/W USCI Control Register 0x0000_0000 UI2Cx_BA+0x00 UI2C_BRGEN...
Page 836: 6.22.7 Register Description
NUC126 6.22.7 Register Description USCI Control Register (UI2C_CTL) Register Offset Description Reset Value UI2C_CTL UI2Cx_BA+0x00 USCI Control Register 0x0000_0000 Reserved Reserved Reserved Reserved FUNMODE Bits Description [31:3] Reserved Reserved. Function Mode This bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI.
Page 837 NUC126 USCI Baud Rate Generator Register (UI2C_BRGEN) Register Offset Description Reset Value UI2C_BRGEN UI2Cx_BA+0x08 USCI Baud Rate Generator Register 0x0000_3C00 Reserved CLKDIV CLKDIV Reserved DSCNT PDSCNT Reserved TMCNTSRC TMCNTEN SPCLKSEL PTCLKSEL RCLKSEL Bits Description [31:26] Reserved Reserved. Clock Divider This bit field defines the ratio between the protocol clock frequency f and the clock PROT_CLK divider frequency f...
Page 838 NUC126 00 = f SAMP_CLK DIV_CLK. 01 = f SAMP_CLK PROT_CLK. 10 = f SAMP_CLK SCLK. 11 = f SAMP_CLK REF_CLK. Protocol Clock Source Selection This bit selects the source signal of protocol clock (f PROT_CLK PTCLKSEL 0 = Reference clock f REF_CLK.
Page 839 NUC126 USCI Line Control Register (UI2C_LINECTL) Register Offset Description Reset Value UI2C_LINECTL UI2Cx_BA+0x2C USCI Line Control Register 0x0000_0000 Reserved Reserved Reserved DWIDTH Reserved Bits Description [31:12] Reserved Reserved. Word Length of Transmission This bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer.
Page 840 NUC126 USCI Transmit Data Register (UI2C_TXDAT) Register Offset Description Reset Value UI2C_TXDAT UI2Cx_BA+0x30 USCI Transmit Data Register 0x0000_0000 Reserved Reserved TXDAT TXDAT Bits Description [31:16] Reserved Reserved. Transmit Data [15:0] TXDAT Software can use this bit field to write 8-bit transmit data for transmission. Aug.
Page 841 NUC126 USCI Receive Data Register (UI2C_RXDAT) Register Offset Description Reset Value UI2C_RXDAT UI2Cx_BA+0x34 USCI Receive Data Register 0x0000_0000 Reserved Reserved RXDAT RXDAT Bits Description [31:16] Reserved Reserved. Received Data [15:0] RXDAT This bit field monitors the received data which stored in receive data buffer. Note1: In I C protocol, only use RXDAT[7:0]..
Page 842 NUC126 USCI Device Address Register (UI2C_DEVADDR) Register Offset R/W Description Reset Value UI2C_DEVADDR0 UI2Cx_BA+0x44 R/W USCI Device Address Register 0 0x0000_0000 UI2C_DEVADDR1 UI2Cx_BA+0x48 R/W USCI Device Address Register 1 0x0000_0000 Reserved Reserved Reserved DEVADDR DEVADDR Bits Description [31:10] Reserved Reserved. Device Address In I C protocol, this bit field contains the programmed slave address.
Page 843 NUC126 USCI Device Address Mask Register (UI2C_ADDRMSK) – for I C Only Register Offset R/W Description Reset Value UI2C_ADDRMSK0 UI2Cx_BA+0x4C R/W USCI Device Address Mask Register 0 0x0000_0000 UI2C_ADDRMSK1 UI2Cx_BA+0x50 R/W USCI Device Address Mask Register 1 0x0000_0000 Reserved Reserved Reserved ADDRMSK ADDRMSK...
Page 844 NUC126 USCI Wake-up Control Register (UI2C_WKCTL) Register Offset Description Reset Value UI2C_WKCTL UI2Cx_BA+0x54 USCI Wake-up Control Register 0x0000_0000 Reserved Reserved Reserved Reserved WKADDREN WKEN Bits Description [31:2] Reserved Reserved. Wake-up Address Match Enable Bit WKADDREN 0 = The chip is woken up according data toggle. 1 = The chip is woken up according address match.
Page 845 NUC126 USCI Wake-up Status Register (UI2C_WKSTS) Register Offset Description Reset Value UI2C_WKSTS UI2Cx_BA+0x58 USCI Wake-up Status Register 0x0000_0000 Reserved Reserved Reserved Reserved Bits Description [31:1] Reserved Reserved. Wake-up Flag When chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
Page 846 NUC126 USCI Protocol Control Register – I C (UI2C_PROTCTL) Register Offset Description Reset Value UI2C_PROTCTL UI2Cx_BA+0x5C USCI Protocol Control Register 0x0000_0000 PROTEN Reserved TOCNT TOCNT Reserved MONEN SCLOUTEN Reserved PTRG ADDR10EN GCFUNC Bits Description C Protocol Enable Bit [31] PROTEN 0 = I C Protocol Disabled.
Page 847 NUC126 C Protocol Trigger When a new state is present in the UI2C_PROTSTS register, if the related interrupt enable bits are set, the I C interrupt is requested. It must write one by software to this bit after the related interrupt flags are set to 1 and the I C protocol function will go ahead until the PTRG STOP is active or the PROTEN is disabled.
Page 848 NUC126 USCI Protocol Interrupt Enable Register – I C (UI2C_PROTIEN) Register Offset Description Reset Value UI2C_PROTIEN UI2Cx_BA+0x60 USCI Protocol Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved ACKIEN ERRIEN ARBLOIEN NACKIEN STORIEN STARIEN TOIEN Bits Description [31:7] Reserved Reserved. Acknowledge Interrupt Enable Bit This bit enables the generation of a protocol interrupt if an acknowledge is detected by a master.
Page 849 NUC126 0 = The start condition interrupt Disabled. 1 = The start condition interrupt Enabled. Time-out Interrupt Enable Bit In I C protocol, this bit enables the interrupt generation in case of a time-out event. TOIEN 0 = The time-out interrupt Disabled. 1 = The time-out interrupt Enabled.
Page 850 NUC126 USCI Protocol Status Register – I C (UI2C_PROTSTS) Register Offset Description Reset Value UI2C_PROTSTS UI2Cx_BA+0x64 USCI Protocol Status Register 0x0000_0000 Reserved Reserved ERRARBLO BUSHANG WRSTSWK WKAKDONE SLAREAD SLASEL ACKIF ERRIF ARBLOIF NACKIF STORIF STARIF Reserved ONBUSY TOIF Reserved Bits Description [31:20] Reserved...
Page 851 NUC126 Acknowledge Received Interrupt Flag This bit indicates that an acknowledge has been received in master mode. A protocol interrupt can be generated if UI2C_PROTCTL.ACKIEN = 1. ACKIF [13] 0 = An acknowledge has not been received. 1 = An acknowledge has been received. It is cleared by software writing 1 into this bit Error Interrupt Flag This bit indicates that a Bus Error occurs when a START or STOP condition is present at...
Page 852 NUC126 0 = A time-out interrupt status has not occurred. 1 = A time-out interrupt status has occurred. Note: This bit is cleared by software writing 1 to it. Reserved Reserved. Aug. 08, 2018 Page 852 of 943 Rev 1.03...
Page 853 NUC126 USCI Slave match Address Register (UI2C_ADMAT) Register Offset Description Reset Value UI2C_ADMAT UI2Cx_BA+0x88 C Slave Match Address Register 0x0000_0000 Reserved Reserved Reserved Reserved ADMAT1 ADMAT0 Bits Description Reserved [31:2] Reserved. USCI Address 1 Match Status ADMAT1 When address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
Page 854 NUC126 USCI Timing Configure Control Register (UI2C_TMCTL) Register Offset Description Reset Value UI2C_TMCTL UI2Cx_BA+0x8C C Timing Configure Control Register 0x0000_0000 Reserved Reserved Reserved HTCTL HTCTL STCTL Bits Description [31:8] Reserved Reserved. Hold Time Configure Control This field is used to generate the delay timing between SCL falling edge SDA edge in [11:6] HTCTL transmission mode.
Page 855: Uart Interface Controller (Uart)
NUC126 6.23 UART Interface Controller (UART) 6.23.1 Overview The NUC126 series provides three channels of Universal Asynchronous Receiver/Transmitters (UART). The UART controller performs Normal Speed UART and supports flow control function. The UART controller performs a serial-to-parallel conversion on data received from the peripheral and a parallel-to-serial conversion on data transmitted from the CPU.
Page 856: Block Diagram
NUC126 6.23.3 Block Diagram The UART clock control and block diagram are shown in Figure 6.23-1 and Figure 6.23-2 respectively. Note: The frequency of UARTx_CLK should not be greater than 30 times HCLK. UARTSEL (CLK_CLKSEL1[25:24]) 22.1184MHz UART0CKEN (CLK_APBCLK0[16] HIRC 32.768kHz UART0_CLK 1/(UARTDIV+1) PLL FOUT...
Page 857 NUC126 Each block is described in detail as follows: TX_FIFO The transmitter is buffered with a 16 bytes FIFO to reduce the number of interrupts presented to the CPU. RX_FIFO The receiver is buffered with a 16 bytes FIFO (plus three error bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]), PEF (UART_FIFOSTS[4])) to reduce the number of interrupts presented to the CPU.
Page 858: Basic Configuration
NUC126 LININT LIN Bus Interrupt. WKINT Wake-up Interrupt. ABRINT Auto-Baud Rate Interrupt. Table 6.23-1 UART Interrupt 6.23.4 Basic Configuration The UART Interface Controller Pin description is shown in Table 6.23-2: Type Description UART_TXD Output UART transmit UART_RXD Input UART receive UART_nCTS Input UART modem clear to send...
Page 859 NUC126  Reset Configuration Reset UART1 controller in UART1RST (SYS_IPRST1[17]).  Pin Configuration Group Pin Name GPIO PE.9 MFP1 UART1_RXD PA.1, PA.9, PE.13 MFP3 PA.12, PB.2 MFP4 PE.8 MFP1 UART1_TXD PA.0, PA.8, PE.12 MFP3 PA.13, PB.3 MFP4 UART1 PA.0 MFP1 UART1_nCTS PA.10, PE.10 MFP3...
Page 860: Functional Description
NUC126 PD.4 MFP4 6.23.5 Functional Description The UART controller supports four function modes including UART, IrDA, LIN and RS-485 mode. User can select a function by setting the UART_FUNCSEL register. The four function modes will be described in following section. 6.23.5.1 UART Controller Baud Rate Generator The UART controller includes a programmable baud rate generator capable of dividing clock input by divisors to produce the serial clock that transmitter and receiver need.
Page 861: Table 6.23-4 Uart Controller Baud Rate Parameter Setting Example Table
NUC126 BRD =254, EDIVM1 =8 BRD =190, EDIVM1 =11 9600 BRD =142 BRD =2302 BRD =142, EDIVM1 =15 BRD =510, EDIVM1 =8 4800 BRD =286 BRD =382, EDIVM1 =11 BRD =4606 BRD =286, EDIVM1 =15 Table 6.23-4 UART Controller Baud Rate Parameter Setting Example Table UART Peripheral Clock = 22.1184 MHz UART_BAUD Value Baud Rate...
Page 862: Table 6.23-6 Baud Rate Compensation Example Table 1
NUC126 Example: (1). UART’s peripheral clock = 32.768K and baud rate is 9600 Baud rate is 9600, UART peripheral clock is 32.768K  3.413 peripheral clock/bit If the baud divider is set 1 (3 peripheral clock/bit), the inaccuracy of each bit is -0.413 peripheral clock and BRCOMPDEC =0, BRCOMP Name...
Page 863: Figure 6.23-3 Auto-Baud Rate Measurement
NUC126 the BRCOMP (UART_BRCOMP[8:0]) can be set as 9’b010000010 = 0x82. 6.23.5.3 UART Controller Auto-Baud Rate Function Mode The Auto-Baud Rate function can measure baud rate of receiving data from UART RX pin automatically. When the Auto-Baud Rate measurement is finished, the measuring baud rate is loaded (UART_BAUD[15:0]).
Page 864: Figure 6.23-4 Transmit Delay Time Operation
NUC126 6.23.5.4 UART Controller Transmit Delay Time Value The UART controller programs DLY (UART_TOUT [15:8]) to control the transfer delay time between the last stop bit and next start bit in transmission. The unit is baud. The operation is shown in Figure 6.23-4.
Page 865: Figure 6.23-6 Uart Ncts Wake-Up Case2
NUC126 Power-down mode CPU run stable count HCLK nCTS CTSWKF CTSACTLV (UART_MODEM[8]) = 1 Note: Stable count means HCLK source recovery stable count. Figure 6.23-6 UART nCTS Wake-up Case2 Incoming Data Wake-up When system is in Power-down mode and the WKDATEN (UART_WKCTL [1]) is set, the toggle of incoming data (UART_RXD) pin can wake-up the system.
Page 866: Figure 6.23-8 Uart Received Data Fifo Reached Threshold Wake-Up
NUC126 stable Power-down mode count HCLK DATA0 DATA1 DATAx Start UART_RXD RX FIFO number reached RFITL RFRTWKF Note: Stable count means HCLK source recovery stable count. Figure 6.23-8 UART Received Data FIFO Reached Threshold Wake-up RS-485 Address Match (AAD Mode) Wake-up The RS-485 address match wake-up function is enabled by setting WKRFRTEN (UART_WKCTL[2]) and WKRS485EN (UART_WKCTL[3]).
Page 867: Figure 6.23-10 Uart Received Data Fifo Threshold Time-Out Wake-Up
NUC126 Power-down mode stable count HCLK Time-out DATA0 DATAx UART_RXD Start RX FIFO number not reached RFITL and Time-out TOUTWKF Note: Stable count means HCLK source recovery stable count. Figure 6.23-10 UART Received Data FIFO Threshold Time-out Wake-up 6.23.5.7 UART Controller Interrupt and Status Each UART controller supports ten types of interrupts including: ...
Page 868 NUC126 Auto-baud Rate Detect Time-out Interrupt Flag (ABRDTOIF) – Table 6.23-8 describes the interrupt sources and flags. The interrupt is generated when the interrupt flag is generated and the interrupt enable bit is set. User must clear the interrupt flag after the interrupt is generated.
Page 869: Table 6.23-8 Uart Controller Interrupt Source And Flag List
NUC126 Write ‘1’ to RFRTWKF WKIF = RFRTWKF WKIF = RS485WKF Write ‘1’ to RS485WKF Write ‘1’ to TOUTWKF WKIF = TOUTWKF Write ‘1’ to ABRDIF ABRIF = ABRDIF Auto-Baud Rate ABRIF ABRINT ABRIEN Interrupt ABRIF = ABRDTOIF Write ‘1’ to ABRDTOIF Table 6.23-8 UART Controller Interrupt Source and Flag List 6.23.5.8 UART Function Mode The UART controller provides UART function (Setting FUNCSEL (UART_FUNCSEL [1:0]) to ’00’...
Page 870: Figure 6.23-11 Auto-Flow Control Block Diagram
NUC126 Parity (UART_LINE[ (UART_LINE[ (UART_LINE[ (UART_LINE[ Description Type No Parity No parity bit output. Parity source from Parity bit is generated and checked by software. UART_DA Odd Parity is calculated by adding all the “1’s” in a Odd Parity data stream and adding a parity bit to the total bits, to make the total count an odd number.
Page 871: Figure 6.23-12 Uart Ncts Auto-Flow Control Enabled
NUC126 Figure 6.23-12 demonstrates the nCTS auto-flow control of UART function mode. User must set ATOCTSEN (UART_INTEN [13]) to enable nCTS auto-flow control function. The CTSACTLV (UART_MODEMSTS [8]) can set nCTS pin input active state. The CTSDETF (UART_MODEMSTS[0]) is set when any state change of nCTS pin input has occurred, and then TX data will be automatically transmitted from TX FIFO.
Page 872: Figure 6.23-14 Uart Nrts Auto-Flow With Software Control
NUC126 directly controlled by software programming of RTS(UART_MODEM[1]) control bit. Setting RTSACTLV(UART_MODEM[9]) can control the nRTS pin output is inverse or non-inverse from RTS(UART_MODEM[1]) control bit. User can read the RTSSTS(UART_MODEM[13]) bit to get real nRTS pin output voltage logic status. nRTS pin output status of UART function mode Set UART_MODEM[1]=0 Set UART_MODEM[1]=1 by software...
Page 873: Figure 6.23-16 Irda Tx/Rx Timing Diagram
NUC126 The IrDA SIR Transmit Encoder modulates Non-Return-to-Zero (NRZ) transmit bit stream output from UART. The IrDA SIR physical layer specifies the use of Return-to-Zero, Inverted (RZI) modulation scheme which represents logic 0 as an infra light pulse. The modulated output pulse stream is transmitted to an external output driver and infrared light emitting diode.
Page 874: Figure 6.23-17 Structure Of Lin Frame
NUC126 Frame slot Frame Inter- Response frame space space Header Response Protected Check Data 1 Data 2 Data N Break Synch Identifier Field field field Figure 6.23-17 Structure of LIN Frame Structure of LIN Byte In LIN mode, each byte field is initiated by a START bit with value 0 (dominant), followed by 8 data bits and no parity bit, LSB is first and ended by 1 stop bit with value 1 (recessive) in accordance with the LIN standard.
Page 875: Table 6.23-11 Lin Header Selection In Master Mode
NUC126 Generated by Hardware Generated by Hardware Generated by Hardware (But Software needs to fill ID to PID (UART_LINCTL[31:24]) first) Table 6.23-11 LIN Header Selection in Master Mode When UART is operated in LIN data transmission, LIN bus transfer state can be monitored by hardware or software.
Page 876: Figure 6.23-19 Break Detection In Lin Mode
NUC126 When software enables the break detection function by setting BRKDETEN (UART_LINCTL[10]), the break detection circuit is activated. The break detection circuit is totally independent from the UART receiver. When the break detection function is enabled, the circuit looks at the input UART_RX pin for a start signal.
Page 877 NUC126 3. Select LIN function mode by setting FUNCSEL (UART_FUNCSEL[1:0]) to ‘01’. 4. Enable LIN slave mode by setting the SLVEN (UART_LINCTL[0]) to 1. LIN header reception According to the LIN protocol, a slave node must wait for a valid header which comes from the master node.
Page 878: Figure 6.23-21 Lin Sync Field Measurement
NUC126 (UART_LINCTL[31:24]) value. The controller will enable the receiver (exit from mute mode) and subsequent data (response data) are received in RX FIFO. Slave Mode Non-automatic Resynchronization (NAR) User can disable the automatic resynchronization function to fix the communication baud rate. When operating in Non-Automatic Resynchronization mode, software needs some initial process, and the initialization process flow of Non-Automatic Resynchronization mode is shown as follows: 1.
Page 879: Figure 6.23-22 Uart_Baud Update Sequence In Ar Mode If Slvduen Is 1
NUC126 Note1: It is recommended to set the SLVDUEN bit before every checksum reception. Note2: When a header error is detected, user must write 1 to SLVSYNCF (UART_LINSTS[3]) to re- search new frame header. When writing 1 to it, hardware will reload the initial baud rate TEMP_REG and re-search new frame header.
Page 880 NUC126 Check1: Based on measurement between the first falling edge and the last falling edge of the sync field.  If the difference is more than 14.84%, the header error flag SLVHEF (UART_LINSTS[1]) will be set.  If the difference is less than 14.06%, the header error flag SLVHEF (UART_LINSTS[1]) will not be set.
Page 881: Figure 6.23-24 Rs-485 Nrts Driving Level In Auto Direction Mode
NUC126 Mode (AUD). Software can choose any operation mode by programming the UART_ALTCTL register, and drive the transfer delay time between the last stop bit leaving the TX FIFO and the de-assertion of by setting DLY (UART_TOUT [15:8]) register. RS-485 Normal Multidrop Operation Mode (NMM) In RS-485 Normal Multidrop Operation Mode (RS485NMM (UART_ALTCTL[8]) = 1), in first, software must decide the data which before the address byte be detected will be stored in RX FIFO or not.
Page 882: Figure 6.23-25 Rs-485 Nrts Driving Level With Software Control
NUC126 Setting RTSACTLV (UART_MODEM[9]) can control the nRTS pin output is inverse or non-inverse from RTS(UART_MODEM[1]) control bit. User can read the RTSSTS (UART_MODEM[13]) bit to get real nRTS pin output voltage logic status. nRTS pin output status of RS-485 function mode Set UART_MODEM[1]=0 by software Set UART_MODEM[1]=1 by software RTS control bit...
Page 883: Figure 6.23-26 Structure Of Rs-485 Frame
NUC126 Figure 6.23-26 Structure of RS-485 Frame 6.23.5.12 PDMA Transfer Function UART controller supports PDMA transfer function. By configuring PDMA parameter and set UART_DAT as the PDMA destination address. When TXPDMAEN (UART_INTEN[14]) is set to 1, the controller will issue request to PDMA controller to start the PDMA transmission process automatically.
Page 884: 6.23.6 Register Map
NUC126 6.23.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value UART Base Address: UARTx_BA = 0x4005_0000 + (0x10_0000 * x) x=0, 1 UART2_BA = 0x4015_4000 UART_DAT UARTx_BA+0x00 UART Receive/Transmit Buffer Register Undefined UART_INTEN UARTx_BA+0x04...
Page 885 NUC126 UART_BRCOM UARTx_BA+0x3C UART Baud Rate Compensation Register 0x0000_0000 UART_WKCTL UARTx_BA+0x40 UART Wake-up Control Register 0x0000_0000 UART_WKSTS UARTx_BA+0x44 UART Wake-up Status Register 0x0000_0000 UART_DWKCO UARTx_BA+0x48 UART Imcoming Data Wake-up Compensation Register 0x0000_0000 Aug. 08, 2018 Page 885 of 943 Rev 1.03...
Page 886: 6.23.7 Register Description
NUC126 6.23.7 Register Description UART Receive/Transmit Buffer Register (UART_DAT) Register Offset Description Reset Value UART_DAT UARTx_BA+0x00 UART Receive/Transmit Buffer Register Undefined Reserved Reserved Reserved PARITY Bits Description [31:9] Reserved Reserved. Parity Bit Receive/Transmit Buffer Write Operation: By writing to this bit, the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.
Page 887 NUC126 UART Interrupt Enable Register (UART_INTEN) Register Offset Description Reset Value UART_INTEN UARTx_BA+0x04 UART Interrupt Enable Register 0x0000_0000 Reserved Reserved TXENDIEN Reserved ABRIEN Reserved RXPDMAEN TXPDMAEN ATOCTSEN ATORTSEN TOCNTEN Reserved LINIEN Reserved WKIEN BUFERRIEN RXTOIEN MODEMIEN RLSIEN THREIEN RDAIEN Bits Description [31:23] Reserved...
Page 888 NUC126 0 = nCTS auto-flow control Disabled. 1 = nCTS auto-flow control Enabled. Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). nRTS Auto-flow Control Enable Bit 0 = nRTS auto-flow control Disabled.
Page 889 NUC126 UART FIFO Control Register (UART_FIFO) Register Offset Description Reset Value UART_FIFO UARTx_BA+0x08 UART FIFO Control Register 0x0000_0101 Reserved Reserved RTSTRGLV Reserved RXOFF RFITL Reserved TXRST RXRST Reserved Bits Description [31:20] Reserved Reserved. nRTS Trigger Level for Auto-flow Control Use 0000 = nRTS Trigger Level is 1 byte.
Page 890 NUC126 state machine are cleared. 0 = No effect. 1 = Reset the TX internal state machine and pointers. Note1: This bit will automatically clear at least 3 UART peripheral clock cycles. Note2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set.
Page 891 NUC126 UART Line Control Register (UART_LINE) Register Offset Description Reset Value UART_LINE UARTx_BA+0x0C UART Line Control Register 0x0000_0000 Reserved Reserved Reserved RXDINV TXDINV Bits Description [31:10] Reserved Reserved. RX Data Inverted 0 = Received data signal inverted Disabled. 1 = Received data signal inverted Enabled. Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited RXDINV for TXRXACT (UART_FIFOSTS[31]) is cleared.
Page 892 NUC126 Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. Stick Parity Enable Bit 0 = Stick parity Disabled. 1 = Stick parity Enabled. Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0.
Page 893 NUC126 UART Modem Control Register (UART_MODEM) Register Offset Description Reset Value UART_MODEM UARTx_BA+0x10 UART Modem Control Register 0x0000_0200 Reserved Reserved Reserved RTSSTS Reserved RTSACTLV Reserved Reserved Reserved Bits Description [31:14] Reserved Reserved. nRTS Pin Status (Read Only) This bit mirror from nRTS pin output of voltage logic status. [13] RTSSTS 0 = nRTS pin output is low level voltage logic state.
Page 894 NUC126 UART Modem Status Register (UART_MODEMSTS) Register Offset Description Reset Value UART_MODEM UARTx_BA+0x14 UART Modem Status Register 0x0000_0110 Reserved Reserved Reserved CTSACTLV Reserved CTSSTS Reserved CTSDETF Bits Description [31:9] Reserved Reserved. nCTS Pin Active Level This bit defines the active level state of nCTS pin input. 0 = nCTS pin input is high level active.
Page 895 NUC126 UART FIFO Status Register (UART_FIFOSTS) Register Offset Description Reset Value UART_FIFOSTS UARTx_BA+0x18 UART FIFO Status Register 0xB040_4000 TXRXACT Reserved RXIDLE TXEMPTYF Reserved TXOVIF TXFULL TXEMPTY TXPTR RXFULL RXEMPTY RXPTR Reserved ADDRDETF ABRDTOIF ABRDIF RXOVIF Bits Description TX and RX Active Status (Read Only) This bit indicates TX and RX are active or inactive.
Page 896 NUC126 0 = TX FIFO is not full. 1 = TX FIFO is full. Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. Transmitter FIFO Empty (Read Only) This bit indicates TX FIFO empty or not.
Page 897 NUC126 Note: This bit can be cleared by writing “1” to it. Parity Error Flag This bit is set to logic 1 whenever the received character does not have a valid “parity bit”. 0 = No parity error is generated. 1 = Parity error is generated.
Page 898 NUC126 UART Interrupt Status Register (UART_INTSTS) Register Offset Description Reset Value UART_INTSTS UARTx_BA+0x1C UART Interrupt Status Register 0x0040_0002 ABRINT TXENDINT HWBUFEINT HWTOINT HWMODINT HWRLSINT Reserved Reserved TXENDIF HWBUFEIF HWTOIF HWMODIF HWRLSIF Reserved LININT WKINT BUFERRINT RXTOINT MODEMINT RLSINT THREINT RDAINT LINIF WKIF BUFERRIF...
Page 899 NUC126 0 = No RLS interrupt is generated in PDMA mode. 1 = RLS interrupt is generated in PDMA mode. [25:23] Reserved Reserved. Transmitter Empty Interrupt Flag (Read Only) This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set).
Page 900 NUC126 This bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 0 = No LIN Bus interrupt is generated. 1 = The LIN Bus interrupt is generated. UART Wake-up Interrupt Indicator (Read Only) This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to WKINT [14] 0 = No UART wake-up interrupt is generated.
Page 901 NUC126 LINIF(UART_INTSTS[7]). UART Wake-up Interrupt Flag (Read Only) This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) CTSWKF(UART_WKSTS[0]) is set to 1. WKIF 0 = No UART wake-up interrupt flag is generated. 1 = UART wake-up interrupt flag is generated. Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag.
Page 902 NUC126 1 = THRE interrupt flag is generated. Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty). Receive Data Available Interrupt Flag (Read Only) When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set.
Page 903 NUC126 UART Time-out Register (UART_TOUT) Register Offset Description Reset Value UART_TOUT UARTx_BA+0x20 UART Time-out Register 0x0000_0000 Reserved Reserved TOIC Bits Description [31:16] Reserved Reserved. TX Delay Time Value [15:8] This field is used to programming the transfer delay time between the last stop bit and next start bit.
Page 904 NUC126 UART Baud Rate Divider Register (UART_BAUD) Register Offset Description Reset Value UART_BAUD UARTx_BA+0x24 UART Baud Rate Divider Register 0x0F00_0000 Reserved BAUDM1 BAUDM0 EDIVM1 Reserved Bits Description [31:30] Reserved Reserved. BAUD Rate Mode Selection Bit 1 This bit is baud rate mode selection bit 1. UART provides three baud rate calculation [29] BAUDM1 modes.
Page 905 NUC126 UART IrDA Control Register (UART_IRDA) Register Offset Description Reset Value UART_IRDA UARTx_BA+0x28 UART IrDA Control Register 0x0000_0040 Reserved Reserved Reserved Reserved RXINV TXINV Reserved TXEN Reserved Bits Description [31:7] Reserved Reserved. IrDA Inverse Receive Input Signal 0 = None inverse receiving input signal. 1 = Inverse receiving input signal.
Page 906 NUC126 UART Alternate Control/Status Register (UART_ALTCTL) Register Offset Description Reset Value UART_ALTCTL UARTx_BA+0x2C UART Alternate Control/Status Register 0x0000_000C ADDRMV Reserved ABRDBITS ABRDEN ABRIF Reserved ADDRDEN Reserved RS485AUD RS485AAD RS485NMM LINTXEN LINRXEN Reserved BRKFL Bits Description Address Match Value [31:24] ADDRMV This field contains the RS-485 address match values.
Page 907 NUC126 Note: This bit is used for RS-485 any operation mode. [14:11] Reserved Reserved. RS-485 Auto Direction Function (AUD) 0 = RS-485 Auto Direction Operation function (AUD) Disabled. [10] RS485AUD 1 = RS-485 Auto Direction Operation function (AUD) Enabled. Note: It can be active with RS-485_AAD or RS-485_NMM operation mode. RS-485 Auto Address Detection Operation Mode (AAD) 0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled.
Page 908 NUC126 UART Function Select Register (UART_FUNCSEL) Register Offset Description Reset Value UART_FUNCS UARTx_BA+0x30 UART Function Select Register 0x0000_0000 Reserved Reserved Reserved Reserved TXRXDIS Reserved FUNCSEL Bits Description [31:4] Reserved Reserved. TX and RX Disable Bit Setting this bit can disable TX and RX. 0 = TX and RX Enabled.
Page 909 NUC126 UART LIN Control Register (UART_LINCTL) Register Offset Description Reset Value UART_LINCTL UARTx_BA+0x34 UART LIN Control Register (Only for UART0 and UART1) 0x000C_0000 HSEL BRKFL Reserved BITERREN LINRXOFF BRKDETEN IDPEN SENDH Reserved MUTE SLVDUEN SLVAREN SLVHDEN SLVEN Bits Description LIN PID Bits This field contains the LIN frame ID value when in LIN function mode, the frame ID parity can be generated by software or hardware depends on IDPEN (UART_LINCTL[9]) = 1.
Page 910 NUC126 Bit Error Detect Enable Bit 0 = Bit error detection function Disabled. [12] BITERREN 1 = Bit error detection function Enabled. Note: In LIN function mode, when occur bit error, the BITEF (UART_LINSTS[9]) flag will be asserted. If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated. LIN Receiver Disable Bit If the receiver is enabled (LINRXOFF (UART_LINCTL[11] ) = 0), all received byte data will be accepted and stored in the RX FIFO, and if the receiver is disabled (LINRXOFF...
Page 911 NUC126 Note3: The control and interactions of this field are explained in 6.23.5.10 (Slave mode with automatic resynchronization). LIN Slave Automatic Resynchronization Mode Enable Bit 0 = LIN automatic resynchronization Disabled. 1 = LIN automatic resynchronization Enabled. Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1). SLVAREN Note2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).
Page 912 NUC126 UART LIN Status Register (UART_LINSTS) Register Offset Description Reset Value UART_LINSTS UARTx_BA+0x38 UART LIN Status Register (Only for UART0 and UART1) 0x0000_0000 Reserved Reserved Reserved BITEF BRKDETF Reserved SLVSYNCF SLVIDPEF SLVHEF SLVHDETF Bits Description [31:10] Reserved Reserved. Bit Error Detect Status Flag At TX transfer state, hardware will monitor the bus state, if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state, BITEF (UART_LINSTS[9]) will be set.
Page 913 NUC126 frame header. LIN Slave ID Parity Error Flag This bit is set by hardware when receipted frame ID parity is not correct. 0 = No active. SLVIDPEF 1 = Receipted frame ID parity is not correct. Note1: This bit can be cleared by writing 1 to it. Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0])= 1) and enable LIN frame ID parity check function IDPEN (UART_LINCTL [9]).
Page 914 NUC126 UART Baud Rate Compensation Register (UART_BRCOMP) Register Offset Description Reset Value UART_BRCOM UARTx_BA+0x3C UART Baud Rate Compensation Register 0x0000_0000 BRCOMPDEC Reserved Reserved Reserved BRCOMP BRCOMP Bits Description Baud Rate Compensation Decrease [31] BRCOMPDEC 0 = Positive (increase one module clock) compensation for each compensated bit. 1 = Negative (decrease one module clock) compensation for each compensated bit.
Page 915 NUC126 UART Wake-up Control Register (UART_WKCTL) Register Offset Description Reset Value UART_WKCTL UARTx_BA+0x40 UART Wake-up Control Register 0x0000_0000 Reserved Reserved Reserved Reserved WKTOUTEN WKRS485EN WKRFRTEN WKDATEN WKCTSEN Bits Description [31:5] Reserved Reserved. Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit 0 = Received Data FIFO reached threshold time-out wake-up system function Disabled.
Page 916 NUC126 UART Wake-up Status Register (UART_WKSTS) Register Offset Description Reset Value UART_WKSTS UARTx_BA+0x44 UART Wake-up Status Register 0x0000_0000 Reserved Reserved Reserved Reserved TOUTWKF RS485WKF RFRTWKF DATWKF CTSWKF Bits Description [31:5] Reserved Reserved. Received Data FIFO Threshold Time-out Wake-up Flag This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up.
Page 917 NUC126 0 = Chip stays in power-down state. 1 = Chip wake-up from power-down state by Incoming Data wake-up. Note1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to ‘1’. Note2: This bit can be cleared by writing ‘1’ to it. nCTS Wake-up Flag This bit is set if chip wake-up from power-down state by nCTS wake-up.
Page 918 NUC126 UART Imcoming Data Wake-up Compensation Register (UART_DWKCOMP) Register Offset Description Reset Value UART_DWKCO UARTx_BA+0x48 UART Imcoming Data Wake-up Compensation Register 0x0000_0000 Reserved Reserved STCOMP STCOMP Bits Description Reserved [31:16] Reserved. Start Bit Compensation Value These bits field indicate how many clock cycle selected by UART_CLK do the UART [15:0] STCOMP controller can get the 1...
Page 919: Watchdog Timer (Wdt)
NUC126 6.24 Watchdog Timer (WDT) 6.24.1 Overview The Watchdog Timer (WDT) is used to perform a system reset when system runs into an unknown state. This prevents system from hanging for an infinite period of time. Besides, the Watchdog Timer supports the function to wake up system from Idle/Power-down mode.
Page 920: Functional Description
NUC126 WDTSEL (CLK_CLKSEL1[1:0]) WDTCKEN (CLK_APBCLK0[0]) 32.768 kHz (LXT) WDT_CLK HCLK/2048 10 kHz (LIRC) Figure 6.24-2 Watchdog Timer Clock Control The WDT controller can also be forced enabled and works in 10 kHz after chip powered on or reset while CWDTEN[2:0] is not configured to 0x111, which CWDTEN[2] is defined in Config0[31] and CWDTEN[1:0] is defined in Config0[4:3].
Page 921: Figure 6.24-3 Watchdog Timer Time-Out Interval And Reset Period Timing
NUC126 IF = 1 RSTF = 1 (if RSTEN = 1) WDT_CLK RSTD RSTF WDT reset (low reset)  : Watchdog Clock Time Period  : Watchdog Time-out Interval Period ( (2 ) * T  : Watchdog Reset Delay Period RSTD - Selectable 3/18/130/1026 * T delay period controlled...
Page 922: 6.24.6 Register Map
NUC126 6.24.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value WDT Base Address: WDT_BA = 0x4000_4000 WDT_CTL WDT_BA+0x00 WDT Control Register 0x0000_0700 WDT_ALTCTL WDT_BA+0x04 WDT Alternative Control Register 0x0000_0000 WDT_RSTCNT WDT_BA+0x08 WDT Reset Counter Register 0x0000_0000...
Page 923: 6.24.7 Register Description
NUC126 6.24.7 Register Description WDT Control Register (WDT_CTL) Register Offset Description Reset Value WDT_CTL WDT_BA+0x00 WDT Control Register 0x0000_0700 ICEDEBUG SYNC Reserved Reserved Reserved TOUTSEL WDTEN INTEN WKEN RSTF RSTEN Reserved Bits Description ICE Debug Mode Acknowledge Disable Bit (Write Protect) 0 = ICE debug mode acknowledgement affects WDT counting.
Page 924 NUC126 0 = Set WDT counter stop, and internal up counter value will be reset also. 1 = Set WDT counter start . Note1: This bit is write protected. Refer to the SYS_REGLCTL register. Note2: Perform enable or disable WDTEN bit needs 2 * WDT_CLK period to become active, user can read SYNC (WDT_CTL[30]) to check enabe/disable command is completed or not.
Page 925 NUC126 WDT Alternative Control Register (WDT_ALTCTL) Register Offset Description Reset Value WDT_ALTCTL WDT_BA+0x04 WDT Alternative Control Register 0x0000_0000 Reserved Reserved Reserved Reserved RSTDSEL Bits Description [31:2] Reserved Reserved. WDT Reset Delay Period Selection (Write Protect) When WDT time-out event happened, user has a time named WDT Reset Delay Period to execute WDT counter reset to prevent WDT time-out reset system occurred.
Page 926 NUC126 WDT Reset Counter Register (WDT_RSTCNT) Register Offset Description Reset Value WDT_RSTCN WDT_BA+0x08 WDT Reset Counter Register 0x0000_0000 RSTCNT RSTCNT RSTCNT RSTCNT Bits Description WDT Reset Counter Register Writing 0x00005AA5 to this field will reset the internal 18-bit WDT up counter value RSTCNT [31:0] to 0.
Page 927: Window Watchdog Timer (Wwdt)
NUC126 6.25 Window Watchdog Timer (WWDT) 6.25.1 Overview The Window Watchdog Timer (WWDT) is used to perform a system reset while WWDT counter is not reload within a specified window period when application program run to uncontrollable status by any unpredictable condition.
Page 928: Basic Configuration
NUC126 6.25.4 Basic Configuration  Clock Source Configuration Select the source of WWDT peripheral clock on WWDTSEL (CLK_CLKSEL2[17:16]). – Enable WWDT peripheral clock in WDTCKEN (CLK_APBCLK0[0]). – The WWDT clock control and block diagram are shown in Figure 6.25-2. WWDTSEL (CLK_CLKSEL2[17:16]) WDTCKEN (CLK_APBCLK0[0]) HCLK/2048 WWDT_CLK...
Page 929: Figure 6.25-3 Wwdt Compare Match Interrupt When Cmpdat Is 0X3E
NUC126 1110 1536 1536 * 64 * T 9.8304 s WWDT 1111 2048 2048 * 64 * T 13.1072 s WWDT Table 6.25-1 WWDT Prescale Value Selection and Time-out Period WWDT Counting When the WWDTEN (WWDT_CTL[0]) is set, WWDT counter will start down counting from 0x3F to 0 and the interval of each count and WWDT compare time-out period is selected by PSCSEL (WWDT_CTL[11:8]).
Page 930: Figure 6.25-4 Wwdt Counter Reload And Reset Behavior
NUC126 CNTDAT = 0 and internal pre-scale counter = 0 System reset immediately CNTDAT = Write RLDCNT 6-bit down counter 0x3F ~ 0x1 CNTDAT > CMPDAT 0x5AA5 will CNTDAT reset system Comparator Write RLDCNT CNTDAT <= CMPDAT 6-bit compare value 0x5AA5 will CMPDAT reload CNTDAT to 0x3F...
Page 931: 6.25.6 Register Map
NUC126 6.25.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value WWDT Base Address: WWDT_BA = 0x4000_4100 WWDT_RLDC WWDT_BA+0x00 WWDT Reload Counter Register 0x0000_0000 WWDT_CTL WWDT_BA+0x04 WWDT Control Register 0x003F_0800 WWDT_STAT WWDT_BA+0x08 WWDT Status Register 0x0000_0000...
Page 932: 6.25.7 Register Description
NUC126 6.25.7 Register Description WWDT Reload Counter Register (WWDT_RLDCNT) Register Offset Description Reset Value WWDT_RLDC WWDT_BA+0x00 WWDT Reload Counter Register 0x0000_0000 RLDCNT RLDCNT RLDCNT RLDCNT Bits Description WWDT Reload Counter Register Writing only 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.
Page 933 NUC126 WWDT Control Register (WWDT_CTL) Register Offset Description Reset Value WWDT_CTL WWDT_BA+0x04 WWDT Control Register 0x003F_0800 Note: This register can be written, only one time, after chip is powered on or reset. ICEDEBUG Reserved Reserved CMPDAT Reserved PSCSEL Reserved INTEN WWDTEN Bits Description...
Page 934 NUC126 1100 = Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK. 1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK. 1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK. 1111 = Pre-scale is 2048;...
Page 935 NUC126 WWDT Status Register (WWDT_STATUS) Register Offset Description Reset Value WWDT_STAT WWDT_BA+0x08 WWDT Status Register 0x0000_0000 Reserved Reserved Reserved Reserved WWDTRF WWDTIF Bits Description [31:2] Reserved Reserved. WWDT Timer-out Reset System Flag If this bit is set to 1, it indicates that system has been reset by WWDT counter time- out reset system event.
Page 936 NUC126 WWDT Counter Value Register (WWDT_CNT) Register Offset Description Reset Value WWDT_CNT WWDT_BA+0x0C R WWDT Counter Value Register 0x0000_003F Reserved Reserved Reserved Reserved CNTDAT Bits Description [31:6] Reserved Reserved. WWDT Counter Value CNTDAT [5:0] CNTDAT will be updated continuously. Aug. 08, 2018 Page 936 of 943 Rev 1.03...
Page 937: Application Circuit
NUC126 APPLICATION CIRCUIT AVCC USB_VBUS USB_D- USB OTG Slot USB_D+ DVCC USB_VDD33_CAP DDIO 0.1uF Power DVCC 0.1uF SPI_SS SPI Device SPI_CLK SPI_MISO MISO MOSI SPI_MOSI ICE_DAT ICE_ CLK Interface DVCC DVCC nRESET NUC126 Series 4.7K 4.7K XT1_IN I2C_SCL C Device I2C_SDA 4~ 24 MHz crystal...
Page 938: Package Dimensions
NUC126 PACKAGE DIMENSIONS LQFP 100L (14x14x1.4 mm footprint 2.0 mm) Aug. 08, 2018 Page 938 of 943 Rev 1.03...
Page 939: Lqfp 64L (7X7X1.4 Mm Footprint 2.0 Mm)
NUC126 LQFP 64L (7x7x1.4 mm footprint 2.0 mm) Aug. 08, 2018 Page 939 of 943 Rev 1.03...
Page 940: Lqfp 48L (7X7X1.4 Mm Footprint 2.0 Mm)
NUC126 LQFP 48L (7x7x1.4 mm Footprint 2.0 mm)  C o n t r o l l i n g d i m e n s i o n : M i l l i m e t e r s Dimension in inch Dimension in mm Symbol...
Page 941: Qfn 48L (7X7X0.8 Mm)
NUC126 QFN 48L (7x7x0.8 mm) Aug. 08, 2018 Page 941 of 943 Rev 1.03...
Page 942: Revision History
NUC126 REVISION HISTORY Date Revision Description 2016.10.28 1.00 Preliminary version 1. Revised part number in section 4.1.2. 2017.07.25 1.01 2. Updated Basic Configuration sections in Chapter 6. 1. Revised HIRC trim description in section 6.2.8 and 6.2.12 2017.12.15 1.02 2. Revised Clock Output description in section 6.3.5 1.
Page 943 NUC126 Important Notice Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”.

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