Nuvoton ARM Cortex NuMicro M451 Series Technical Reference Manual
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Nuvoton ARM Cortex NuMicro M451 Series Technical Reference Manual

32-bit microcontroller
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M451
®
®
ARM
Cortex
-M
32-bit Microcontroller
®
NuMicro
Family
M451 Series
Technical Reference Manual
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
May. 4, 2018
Page 1 of 1006
Rev.2.08

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Summary of Contents for Nuvoton ARM Cortex NuMicro M451 Series

  • Page 1 The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions.

  • Page 2: Table Of Contents

    M451 TABLE OF CONTENTS GENERAL DESCRIPTION ..................19 FEATURES ......................... 21 M451 Features ..............21 ® NuMicro Abbreviations ......................27 PARTS INFORMATION LIST AND PIN CONFIGURATION ........29 M451 Selection Guide ............29 ® NuMicro M451 Naming Rule ..............29 ®...
  • Page 3 M451 M453 CAN Series(CAN+USB) LQFP100 Pin Description ....... 144 4.3.11 GPIO Multi-function Pin Summary ............157 4.3.12 BLOCK DIAGRAM ....................167 M451 Block Diagram ............167 ® NuMicro FUNCTIONAL DESCRIPTION .................. 169 -M4 Core ..............169 ® ® Cortex System Manager ................172 Overview ...................
  • Page 4 M451 Overview ................... 343 6.5.1 Features .................... 343 6.5.2 Block Diagram ..................344 6.5.3 Basic Configuration ................344 6.5.4 Functional Description ................344 6.5.5 Register Map ..................351 6.5.6 Register Description ................352 6.5.7 General Purpose I/O (GPIO) ............. 356 Overview ...................
  • Page 5 M451 Functional Description ................440 6.9.5 Register Map ..................470 6.9.6 Register Description ................476 6.9.7 Watchdog Timer (WDT)..............540 6.10 Overview ..................540 6.10.1 Features ..................540 6.10.2 Block Diagram .................. 540 6.10.3 Clock Control ................... 540 6.10.4 Basic Configuration ................541 6.10.5 Functional Description .................
  • Page 6 M451 Register Description ................619 6.13.7 Smart Card Host Interface (SC) ............646 6.14 Overview ..................646 6.14.1 Features ..................646 6.14.2 Block Diagram .................. 646 6.14.3 Basic Configuration ................648 6.14.4 Functional description ................. 648 6.14.5 Register Map..................657 6.14.6 Register Description ................
  • Page 7 M451 Overview ..................808 6.18.1 Features ..................808 6.18.2 Block Diagram .................. 809 6.18.3 Basic Configuration ................810 6.18.4 Functional Description ................. 810 6.18.5 Register Map..................812 6.18.6 Register Description ................814 6.18.7 USB On-The-Go (OTG) ..............845 6.19 Overview ..................845 6.19.1 Features ..................
  • Page 8 M451 Block Diagram .................. 931 6.22.3 Basic Configuration ................931 6.22.4 Operation Procedure ................932 6.22.5 Register Map..................943 6.22.6 Register Description ................946 6.22.7 Digital to Analog Converter (DAC) ............973 6.23 Overview ..................973 6.23.1 Features ..................973 6.23.2 Block Diagram ..................
  • Page 9 M451 List of Figures ® Figure 4.1-1 NuMicro M451 Selection Code ................29 ® Figure 4.2-1 NuMicro M451 Base Series LQFP 48-pin Diagram ..........34 ® Figure 4.2-2 NuMicro M451 Base Series LQFP 64-pin Diagram ..........35 ® Figure 4.2-3 NuMicro M451 Base Series LQFP 100-pin Diagram ..........
  • Page 10 M451 Figure 6.2-10 SRAM Memory Organization (M45xD/M45xC) ............. 188 Figure 6.3-1 Clock Generator Global View Diagram ..............268 Figure 6.3-2 Clock Generator Block Diagram ................269 Figure 6.3-3 System Clock Block Diagram .................. 270 Figure 6.3-4 HXT Stop Protect Procedure ................... 271 Figure 6.3-5 SysTick Clock Control Block Diagram ..............
  • Page 11 M451 Figure 6.7-2 Descriptor Table Entry Structure ................379 Figure 6.7-3 Basic Mode Finite State Machine ................381 Figure 6.7-4 Descriptor Table Link List Structure ................ 382 Figure 6.7-5 Scatter-Gather Mode Finite State Machine ............. 382 Figure 6.7-6 Example of Single Transfer Type and Burst Transfer Type in Basic Mode .... 384 Figure 6.8-1 Timer Controller Block Diagra .................
  • Page 12 M451 Figure 6.9-30 Brake Block Diagram for PWM_CH0 and PWM_CH1 Pair ........459 Figure 6.9-31 Edge Detector Waveform for PWM_CH0 and PWM_CH1 Pair ......460 Figure 6.9-32 Level Detector Waveform for PWM_CH0 and PWM_CH1 Pair ......460 Figure 6.9-33 Brake Source Block Diagram ................461 Figure 6.9-34 Brake System Fail Block Diagram .................
  • Page 13 M451 Figure 6.13-16 Break Detection in LIN Mode ................607 Figure 6.13-17 LIN Frame ID and Parity Format ................. 608 Figure 6.13-18 LIN Sync Field Measurement ................610 Figure 6.13-19 UART_BAUD Update Sequence in AR mode if SLVDUEN is 1 ......611 Figure 6.13-20 UART_BAUD Update Sequence in AR mode if SLVDUEN is 0 ......
  • Page 14 M451 Figure 6.15-18 Bus Management ALERT function ..............702 Figure 6.15-19 SM Bus Time Out Timing ..................703 Figure 6.15-20 I C Data Shifting Direction ................... 707 Figure 6.15-21 I C Time-out Count Block Diagram ..............711 Figure 6.15-22 EEPROM Random Read ..................717 Figure 6.15-23 Protocol of EEPROM Random Read..............
  • Page 15 M451 Figure 6.16-32 SPI Timing in Slave Mode ................... 762 Figure 6.16-33 SPI Timing in Slave Mode (Alternate Phase of SPIn_CLK) ........ 762 Figure 6.17-1 USB Block Diagram ....................786 Figure 6.17-2 NEVWK Interrupt Operation Flow ................787 Figure 6.17-3 Endpoint SRAM Structure ..................788 Figure 6.17-4 Setup Transaction Followed by Data IN Transaction ..........
  • Page 16 M451 Figure 6.22-15 A/D Controller Interrupts ..................942 Figure 6.23-1 Digital-to-Analog Converter Block Diagram ............973 Figure 6.23-2 Data Holding Register Format ................974 Figure 6.23-3 DAC Conversion Started by Software Write Trigger ..........975 Figure 6.23-4 DAC Conversion Started by Hardware Trigger Event ........... 975 Figure 6.23-5 DAC PDMA Underrun Condition Example ............
  • Page 17 M451 List of Tables Table 1-1 Key Features Support Table ..................19 Table 3-1 List of Abbreviations ....................... 28 Table 4-1 M451 GPIO Multi-function Table ................. 166 Table 6-1 Reset Value of Registers ..................... 175 Table 6-2 Power Mode Difference Table ..................179 Table 6-3 Clocks in Power Modes ....................
  • Page 18 M451 Table 6-34 I C Status Code Description ..................709 Table 6-35 SPI/I S Interface Controller Pin .................. 743 Table 6-36 Initialization of a Transmit Object ................867 Table 6-37 Initialization of a Receive Object ................868 Table 6-38 CAN Bit Time Parameters..................872 Table 6-39 CAN Register Map for Each Bit Function ..............

  • Page 19: General Description

    Cortex -M4F based products, including the M451 Base Series, M452 USB Series, M453 CAN Series, and M451M Series which is pin compatible with M051 LQFP48 and M058S LQFP64. By planning a complete product line, Nuvoton hopes to ® ® fulfill the demand for the ARM...
  • Page 20 M451  Security Alarm System  Power Metering  Portable Data Collector  Portable RFID Reader  System Supervisors  Smart Card Reader  Printer  Bar Code Scanner  Motor Control  Digital Power May. 4, 2018 Page 20 of 1006 Rev.2.08...

  • Page 21: Features

    M451 FEATURES ® NuMicro M451 Features  Core ® ® – Cortex -M4F core running up to 72 MHz – Supports DSP extension with hardware divider – Supports IEEE 754 compliant Floating-point Unit (FPU) – Supports Memory Protection Unit (MPU) –...
  • Page 22 M451 – Four I/O modes – TTL/Schmitt trigger input selectable – I/O pin configured as interrupt source with edge/level trigger setting – Supports high driver and high sink current I/O (up to 20 mA at 5V) – Supports software selectable slew rate control –...
  • Page 23 M451 – Supports mask function and tri-state output for each PWM pin – Supports PWM events interrupt – Supports trigger EADC/DAC start conversion – Supports up to 12 independent input capture channels with rising/falling capture and with counter reload option –...
  • Page 24 M451 – Supports the byte reorder function – Supports Byte or Word Suspend mode – Supports 3-wire, no slave select signal, bi-direction interface – Master mode up to 32 MHz and Slave mode up to 16 MHz (when chip works at V S by SPI controllers –...
  • Page 25 M451 – Supports two dedicated external chip select pins for each memory block – Supports accessible space up to 1 MB for each bank, actually external addressable space is dependent on package pin out – Supports 8-/16-bit data width – Supports byte write in 16-bit data width mode –...
  • Page 26 M451  One built-in temperature sensor with 1℃ resolution  Brown-out detector – With 4 levels: 4.4 V/ 3.7 V/ 2.7 V/ 2.2 V – Supports Brown-out Interrupt and Reset option  Low Voltage Reset – Threshold voltage levels: 2.0 V ...

  • Page 27: Abbreviations

    M451 ABBREVIATIONS Acronym Description ACMP Analog Comparator Controller Analog-to-Digital Converter Advanced Encryption Standard Advanced Peripheral Bus Advanced High-Performance Bus Brown-out Detection Controller Area Network Debug Access Port Data Encryption Standard External Bus Interface EPWM Enhanced Pulse Width Modulation FIFO First In, First Out Flash Memory Controller Floating-point Unit GPIO...

  • Page 28: Table 3-1 List Of Abbreviations

    M451 Samples per Second TDES Triple Data Encryption Standard Timer Controller UART Universal Asynchronous Receiver/Transmitter UCID Unique Customer ID Universal Serial Bus Watchdog Timer WWDT Window Watchdog Timer Table 3-1 List of Abbreviations May. 4, 2018 Page 28 of 1006 Rev.2.08...

  • Page 29: Parts Information List And Pin Configuration

    M451 PARTS INFORMATION LIST AND PIN CONFIGURATION ® NuMicro M451 Selection Guide ® 4.1.1 NuMicro M451 Naming Rule ARM–Based M45 X-X X X X X 32-bit Microcontroller CPU Core Corte ® Temperature E: -40 C ~ +105 Function : Base Series Reserved 1M : Series (M051 Pin Compatible) : USB Series...

  • Page 30: Numicro ® M451 Base Series Selection Guide

    M451 ® 4.1.2 NuMicro M451 Base Series Selection Guide Connectivity LQFP √ √ √ √ M451LG6AE 256 8-ch LQFP √ √ √ √ M451LE6AE 128 8-ch LQFP √ √ √ √ M451RG6AE 256 12-ch LQFP √ √ √ √ M451RE6AE 128 12-ch LQFP √...

  • Page 31: Numicro ® M451M Series (M051 Pin Compatible) Selection Guide

    M451 ® 4.1.3 NuMicro M451M Series (M051 Pin Compatible) Selection Guide Connectivity M451MLG6A LQFP √ √ √ 9-ch M451MLE6A LQFP √ √ √ 9-ch M451MLD3A LQFP √ √ √ 11-ch M451MLC3A LQFP √ √ √ 11-ch M451MSD3A LQFP √ √ √...

  • Page 32: Numicro ® M452 Usb Series Selection Guide

    M451 ® 4.1.4 NuMicro M452 USB Series Selection Guide Connectivity LQFP √ √ √ √ M452LG6AE 256 8-ch LQFP √ √ √ √ M452LE6AE 128 8-ch LQFP √ √ √ √ M452RG6AE 256 12-ch LQFP √ √ √ √ M452RE6AE 128 12-ch LQFP √...

  • Page 33: Numicro ® M453 Can Series (Can+Usb) Selection Guide

    M451 ® 4.1.5 NuMicro M453 CAN Series (CAN+USB) Selection Guide Connectivity LQFP √ √ √ √ M453LG6AE 256 8-ch LQFP √ √ √ √ M453LE6AE 128 8-ch LQFP √ √ √ √ M453RG6AE 256 12-ch LQFP √ √ √ √ M453RE6AE 128 12-ch LQFP...

  • Page 34: Pin Configuration

    M451 Pin Configuration ® 4.2.1 NuMicro M451 Base Series LQFP48 Pin Diagram Corresponding Part Number: M451LG6AE, M451LE6AE, M451LD3AE, M451LC3AE PA.3 PE.0 PA.2 PC.4 PA.1 PC.3 PA.0 PC.2 PC.1 PC.0 LQFP 48-pin LDO_CAP PB.0 PB.1 PF.4/XT1_IN PB.2 PF.3/XT1_OUT PB.3 PD.7 PB.4 PF.2 ®...

  • Page 35: Numicro ® M451 Base Series Lqfp64 Pin Diagram

    M451 ® 4.2.2 NuMicro M451 Base Series LQFP64 Pin Diagram Corresponding Part Number: M451RG6AE, M451RE6AE, M451RD3AE, M451RC3AE PA.3 PE.0 PA.2 PC.4 PA.1 PC.3 PA.0 PC.2 PC.1 PC.0 LDO_CAP LQFP 64-pin PB.0 PB.1 PF.4/XT1_IN PB.2 PF.3/XT1_OUT PB.3 PD.7 PB.4 PD.15 PB.8 PD.14 PB.11 PD.13...

  • Page 36: Numicro ® M451 Base Series Lqfp100 Pin Diagram

    M451 ® 4.2.3 NuMicro M451 Base Series LQFP100 Pin Diagram Corresponding Part Number: M451VG6AE, M451VE6AE PE.7 PC.5 PC.15 PE.0 PE.2 PC.4 PA.3 PC.3 PA.2 PC.2 PA.1 PC.1 PA.0 PC.0 PA.12 PC.14 PA.13 PC.13 PA.14 PC.12 PA.15 PC.11 PC.10 LQFP 100-pin PC.9 LDO_CAP PB.0...

  • Page 37: Numicro ® M451M Series (M051 Pin Compatible) Lqfp48 Pin Diagram

    M451 ® 4.2.4 NuMicro M451M Series (M051 Pin Compatible) LQFP48 Pin Diagram Corresponding Part Number: M451MLG6AE, M451MLE6AE, M451MLD3AE, M451MLC3AE PA.3 PE.0 PA.2 PC.4 PA.1 PC.3 PA.0 PC.2 PC.1 PC.0 LQFP 48-pin PB.0 LDO_CAP PB.1 PB.2 PF.4/XT1_IN PB.3 PF.3/XT1_OUT PB.4 PD.7 PB.8 PD.6 ®...

  • Page 38: Numicro ® M451M Series (M058S Pin Compatible) Lqfp64 Pin Diagram

    M451 ® 4.2.5 NuMicro M451M Series (M058S Pin Compatible) LQFP64 Pin Diagram Corresponding Part Number: M451MSD3AE, M451MSC3AE PA.3 PE.0 PA.2 PC.4 PA.1 PC.3 PA.0 PC.2 PC.1 PC.0 PC.13 PC.12 LQFP 64-pin PB.14 PC.11 PB.13 PC.10 PB.0 LDO_CAP PB.1 PB.2 PB.3 PF.4/XT1_IN PB.4 PF.3/XT1_OUT...

  • Page 39: Numicro ® M452 Usb Series Lqfp48 Pin Diagram

    M451 ® 4.2.6 NuMicro M452 USB Series LQFP48 Pin Diagram Corresponding Part Number: M452LG6AE, M452LE6AE PA.3 PE.0 PA.2 PC.4 PA.1 PC.3 PA.0 PC.2 PC.1 PC.0 LQFP 48-pin LDO_CAP PB.0 PB.1 PF.4/XT1_IN PB.2 PF.3/XT1_OUT PB.3 PD.7 PB.4 PF.2 ® Figure 4.2-6 NuMicro M451 USB Series LQFP 48-pin Diagram (M452LG/M452LE Device Only) May.

  • Page 40: Figure 4.2-7 Numicro M451 Usb Series Lqfp 48-Pin Diagram (M452Ld/M452Lc Device Only)

    M451 Corresponding Part Number: M452LD3AE, M452LC3AE PA.3 PE.0 PA.2 PC.4 PA.1 PC.3 PA.0 PC.2 PC.1 PC.0 LQFP 48-pin LDO_CAP PB.0 PB.1 PF.4/XT1_IN PB.2 PF.3/XT1_OUT PB.3 PD.7 PB.4 PF.2 ® Figure 4.2-7 NuMicro M451 USB Series LQFP 48-pin Diagram (M452LD/M452LC Device Only) May.

  • Page 41: Numicro ® M452 Usb Series Lqfp64 Pin Diagram

    M451 ® 4.2.7 NuMicro M452 USB Series LQFP64 Pin Diagram Corresponding Part Number: M452RG6AE, M452RE6AE PA.3 PC.5 PA.2 PC.4 PA.1 PC.3 PA.0 PC.2 PC.1 PC.0 LDO_CAP LQFP 64-pin PB.0 PB.1 PF.4/XT1_IN PB.2 PF.3/XT1_OUT PB.3 PD.7 PB.4 PD.15 PB.8 PD.14 PB.11 PD.13 PB.12 PD.12...

  • Page 42: Figure 4.2-9 Numicro ® M451 Usb Series Lqfp 64-Pin Diagram (M452Rd Device Only)

    M451 Corresponding Part Number:M452RD3AE PA.3 PC.5 PA.2 PC.4 PA.1 PC.3 PA.0 PC.2 PC.1 PC.0 LDO_CAP LQFP 64-pin PB.0 PB.1 PF.4/XT1_IN PB.2 PF.3/XT1_OUT PB.3 PD.7 PB.4 PD.15 PB.8 PD.14 PB.11 PD.13 PB.12 PD.12 ® Figure 4.2-9 NuMicro M451 USB Series LQFP 64-pin Diagram (M452RD Device Only) May.

  • Page 43: Numicro ® M452 Usb Series Lqfp100 Pin Diagram

    M451 ® 4.2.8 NuMicro M452 USB Series LQFP100 Pin Diagram Corresponding Part Number: M452VG6AE, M452VE6AE USB_ID PC.5 USB_VDD33_CAP PE.0 PE.2 PC.4 PA.3 PC.3 PA.2 PC.2 PA.1 PC.1 PA.0 PC.0 PA.12 PC.14 PA.13 PC.13 PA.14 PC.12 PA.15 PC.11 PC.10 LQFP 100-pin PC.9 LDO_CAP PB.0...

  • Page 44: Numicro ® M453 Can Series (Can+Usb) Lqfp48 Pin Diagram

    M451 ® 4.2.9 NuMicro M453 CAN Series (CAN+USB) LQFP48 Pin Diagram Corresponding Part Number: M453LG6AE, M453LE6AE PA.3 PE.0 PA.2 PC.4 PA.1 PC.3 PA.0 PC.2 PC.1 PC.0 LQFP 48-pin LDO_CAP PB.0 PB.1 PF.4/XT1_IN PB.2 PF.3/XT1_OUT PB.3 PD.7 PB.4 PF.2 ® Figure 4.2-11 NuMicro M451 CAN Series (CAN+USB) LQFP 48-pin Diagram (M453LG/M453LE Device Only) May.

  • Page 45: Figure 4.2-12 Numicro M451 Can Series (Can+Usb) Lqfp 48-Pin Diagram (M453Ld/M453Lc Device Only)

    M451 Corresponding Part Number: M453LD3AE, M453LC3AE PA.3 PE.0 PA.2 PC.4 PA.1 PC.3 PA.0 PC.2 PC.1 PC.0 LQFP 48-pin LDO_CAP PB.0 PB.1 PF.4/XT1_IN PB.2 PF.3/XT1_OUT PB.3 PD.7 PB.4 PF.2 ® Figure 4.2-12 NuMicro M451 CAN Series (CAN+USB) LQFP 48-pin Diagram (M453LD/M453LC Device Only) May.

  • Page 46: Numicro ® M453 Can Series (Can+Usb) Lqfp64 Pin Diagram

    M451 ® 4.2.10 NuMicro M453 CAN Series (CAN+USB) LQFP64 Pin Diagram Corresponding Part Number: M453RG6AE, M453RE6AE PA.3 PC.5 PA.2 PC.4 PA.1 PC.3 PA.0 PC.2 PC.1 PC.0 LDO_CAP LQFP 64-pin PB.0 PB.1 PF.4/XT1_IN PB.2 PF.3/XT1_OUT PB.3 PD.7 PB.4 PD.15 PB.8 PD.14 PB.11 PD.13 PB.12...

  • Page 47: Figure 4.2-14 Numicro M451 Can Series (Can+Usb) Lqfp 64-Pin Diagram (M453Rd Device Only)

    M451 Corresponding Part Number: M453RD3AE PA.3 PC.5 PA.2 PC.4 PA.1 PC.3 PA.0 PC.2 PC.1 PC.0 LDO_CAP LQFP 64-pin PB.0 PB.1 PF.4/XT1_IN PB.2 PF.3/XT1_OUT PB.3 PD.7 PB.4 PD.15 PB.8 PD.14 PB.11 PD.13 PB.12 PD.12 ® Figure 4.2-14 NuMicro M451 CAN Series (CAN+USB) LQFP 64-pin Diagram (M453RD Device Only) May.

  • Page 48: Numicro M453 Can Series (Can+Usb) Lqfp100 Pin Diagram

    M451 ® 4.2.11 NuMicro M453 CAN Series (CAN+USB) LQFP100 Pin Diagram Corresponding Part Number: M453VG6AE, M453VE6AE USB_ID PC.5 USB_VDD33_CAP PE.0 PE.2 PC.4 PA.3 PC.3 PA.2 PC.2 PA.1 PC.1 PA.0 PC.0 PA.12 PC.14 PA.13 PC.13 PA.14 PC.12 PA.15 PC.11 PC.10 LQFP 100-pin PC.9 LDO_CAP PB.0...

  • Page 49: Figure 4.2-16 Numicro M451 Can Series (Can+Usb) Lqfp 100-Pin Diagram (M453Vd Device Only)

    M451 Corresponding Part Number: M453VD3AE PF.7 PC.5 USB_VDD33_CAP PE.0 PC.4 PA.3 PC.3 PA.2 PC.2 PA.1 PC.1 PA.0 PC.0 PA.12 PA.13 PC.13 PA.14 PC.12 PA.15 PC.11 PC.10 LQFP 100-pin LDO_CAP PB.0 PB.1 PF.4/XT1_IN PB.2 PF.3/XT1_OUT PB.3 PD.7 PB.4 PD.15 PB.8 PD.14 PD.13 PD.12 PB.11...

  • Page 50: Pin Description

    M451 Pin Description 4.3.1 M451 Base Series LQFP48 Pin Description MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH) PA.0 MFP0 means SYS_GPA_MFPL[3:0]=0x0. PA.9 MFP5 means SYS_GPA_MFPH[7:4]=0x5. Pin No. Pin Name Type MFP* Description PB.5 MFP0 General purpose digital I/O pin. EADC_CH13 MFP1 EADC analog input channel 13.
  • Page 51 M451 Pin No. Pin Name Type MFP* Description MFP0 Ground pin for analog circuit. PD.1 MFP0 General purpose digital I/O pin. EADC_CH11 MFP1 EADC analog input channel 11. (M45xD/M45xC Only) PWM0_SYNC_IN MFP2 PWM0 counter synchronous trigger input pin. UART0_TXD MFP3 Data transmitter output pin for UART0.
  • Page 52 M451 Pin No. Pin Name Type MFP* Description PWM0_CH5 MFP6 PWM0 output/capture input. EBI_nRD MFP7 EBI read enable output pin. PF.3 MFP0 General purpose digital I/O pin. XT1_OUT MFP1 External 4~20 MHz (high speed) crystal output pin. I2C1_SCL MFP3 I2C1 clock pin. PF.4 MFP0 General purpose digital I/O pin.
  • Page 53 M451 Pin No. Pin Name Type MFP* Description Only) UART2_RXD MFP3 Data receiver input pin for UART2. PWM0_CH3 MFP6 PWM0 output/capture input. EBI_AD11 MFP7 EBI address/data bus bit 11. PC.4 MFP0 General purpose digital I/O pin. SPI2 MISO (Master In, Slave Out) pin. (M45xG/M45xE SPI2_MISO MFP2 Only)
  • Page 54 M451 Pin No. Pin Name Type MFP* Description PF.6 MFP0 General purpose digital I/O pin. ICE_DAT MFP1 Serial wired debugger data pin PE.8 MFP0 General purpose digital I/O pin. UART1_TXD MFP1 Data transmitter output pin for UART1. SPI0_MISO1 MFP2 SPI0 2nd MISO (Master In, Slave Out) pin. I2C1_SCL MFP4 I2C1 clock pin.
  • Page 55 M451 Pin No. Pin Name Type MFP* Description I2C1_SDA MFP11 I2C1 data input/output pin. (M45xD/M45xC Only) PE.12 MFP0 General purpose digital I/O pin. SPI1_SS MFP1 SPI1 slave select pin SPI0_SS MFP2 SPI0 slave select pin. UART1_TXD MFP3 Data transmitter output pin for UART1. I2C0_SCL MFP4 I2C0 clock pin.
  • Page 56 M451 Pin No. Pin Name Type MFP* Description UART1_nCTS MFP1 Clear to Send input pin for UART1. UART1_TXD MFP3 Data transmitter output pin for UART1. SC0_CLK MFP5 SmartCard clock pin. PWM1_CH5 MFP6 PWM1 output/capture input. EBI_AD0 MFP7 EBI address/data bus bit 0. INT0 MFP8 External interrupt0 input pin.
  • Page 57 M451 Pin No. Pin Name Type MFP* Description T2_EXT MFP11 Timer2 external capture input. (M45xD/M45xC Only) PB.3 MFP0 General purpose digital I/O pin. EADC_CH3 MFP1 EADC analog input channel 3. SPI0_MISO0 MFP2 SPI0 1st MISO (Master In, Slave Out) pin. SPI1_MISO MFP3 SPI1 MISO (Master In, Slave Out) pin.

  • Page 58: M451 Base Series Lqfp64 Pin Description

    M451 4.3.2 M451 Base Series LQFP64 Pin Description MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH) PA.0 MFP0 means SYS_GPA_MFPL[3:0]=0x0. PA.9 MFP5 means SYS_GPA_MFPH[7:4]=0x5. Pin No. Pin Name Type MFP* Description PB.15 MFP0 General purpose digital I/O pin. EADC_CH12 MFP1 EADC analog input channel 12.
  • Page 59 M451 Pin No. Pin Name Type MFP* Description INT3 MFP8 External interrupt3 input pin. MFP11 Timer3 event counter input / toggle output. (M45xD/M45xC Only) MFP0 Ground pin for analog circuit. PD.8 MFP0 General purpose digital I/O pin. EADC_CH7 MFP1 EADC analog input channel 7. (M45xD/M45xC Only) EBI_nCS0 MFP7 EBI chip select 0 enable output pin.
  • Page 60 M451 Pin No. Pin Name Type MFP* Description INT5 MFP8 External interrupt5 input pin. PF.1 MFP0 General purpose digital I/O pin. X32_IN MFP1 External 32.768 kHZ (low speed) crystal input pin. PF.2 MFP0 General purpose digital I/O pin. TAMPER MFP1 TAMPER detector loop pin PD.12 MFP0...
  • Page 61 M451 Pin No. Pin Name Type MFP* Description I2C1_SCL MFP3 I2C1 clock pin. PF.4 MFP0 General purpose digital I/O pin. XT1_IN MFP1 External 4~20 MHz (high speed) crystal input pin. I2C1_SDA MFP3 I2C1 data input/output pin. MFP0 Ground pin for digital circuit. MFP0 Power supply for I/O ports and LDO source for internal PLL and digital function.
  • Page 62 M451 Pin No. Pin Name Type MFP* Description EBI_AD11 MFP7 EBI address/data bus bit 11. PC.4 MFP0 General purpose digital I/O pin. SPI2_MISO MFP2 SPI2 MISO (Master In, Slave Out) pin. (M45xG/M45xE Only) I2C1_SCL MFP3 I2C1 clock pin. PWM0_CH4 MFP6 PWM0 output/capture input.
  • Page 63 M451 Pin No. Pin Name Type MFP* Description PA.7 MFP0 General purpose digital I/O pin. SPI1_CLK MFP2 SPI1 serial clock pin T0_EXT MFP3 Timer0 external capture input EBI_AD7 MFP7 EBI address/data bus bit 7. PA.6 MFP0 General purpose digital I/O pin. SPI1_MISO MFP2 SPI1 MISO (Master In, Slave Out) pin.
  • Page 64 M451 Pin No. Pin Name Type MFP* Description SPI0_MISO0 MFP2 SPI0 1st MISO (Master In, Slave Out) pin. UART1_nCTS MFP3 Clear to Send input pin for UART1. I2C0_SMBAL MFP4 I2C0 SMBus SMBALTER# pin SC0_DAT MFP5 SmartCard data pin. Data transmitter output pin for UART3. (M45xD/M45xC UART3_TXD MFP9 Only)
  • Page 65 M451 Pin No. Pin Name Type MFP* Description UART0_nCTS MFP3 Clear to Send input pin for UART0. I2C0_SDA MFP4 I2C0 data input/output pin. SC0_RST MFP5 SmartCard reset pin. PWM1_CH3 MFP6 PWM1 output/capture input. EBI_AD2 MFP7 EBI address/data bus bit 2. PA.1 MFP0 General purpose digital I/O pin.
  • Page 66 M451 Pin No. Pin Name Type MFP* Description EADC_CH1 MFP1 EADC analog input channel 1. SPI0_MISO1 MFP2 SPI0 2nd MISO (Master In, Slave Out) pin. UART2_TXD MFP3 Data transmitter output pin for UART2. MFP4 Timer3 event counter input / toggle output SC0_RST MFP5 SmartCard reset pin.
  • Page 67 M451 Pin No. Pin Name Type MFP* Description UART1_nRTS MFP4 Request to Send output pin for UART1. PWM0_CH2 MFP6 PWM0 output/capture input. PB.11 MFP0 General purpose digital I/O pin. EADC_CH8 MFP1 EADC analog input channel 8. PB.12 MFP0 General purpose digital I/O pin. EADC_CH9 MFP1 EADC analog input channel 9.

  • Page 68: M451 Base Series Lqfp100 Pin Description

    M451 4.3.3 M451 Base Series LQFP100 Pin Description MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH) PA.0 MFP0 means SYS_GPA_MFPL[3:0] = 0x0. PA.9 MFP5 means SYS_GPA_MFPH[7:4] = 0x5. Pin No. Pin Name Type MFP* Description PB.13 MFP0 General purpose digital I/O pin. (M45xG/M45xE Only) EADC_CH10 MFP1 EADC analog input channel 10.
  • Page 69 M451 Pin No. Pin Name Type MFP* Description EADC_CH6 MFP1 EADC analog input channel 6. (M45xD/M45xC Only) SPI1_I2SMCLK MFP2 I2S1 master clock output pin. UART0_RXD MFP3 Data receiver input pin for UART0. ACMP1_N MFP5 Comparator1 negative input pin. INT3 MFP8 External interrupt3 input pin.
  • Page 70 M451 Pin No. Pin Name Type MFP* Description T1_EXT MFP3 Timer1 external capture input ACMP1_P0 MFP5 Comparator1 positive input pin. PWM0_BRAKE1 MFP6 PWM0 break input 1 EBI_MCLK MFP7 EBI external clock output pin INT1 MFP8 External interrupt1 input pin. PD.4 MFP0 General purpose digital I/O pin.
  • Page 71 M451 Pin No. Pin Name Type MFP* Description PD.10 MFP0 General purpose digital I/O pin. MFP4 Timer2 event counter input / toggle output PD.11 MFP0 General purpose digital I/O pin. MFP4 Timer3 event counter input / toggle output PD.12 MFP0 General purpose digital I/O pin.
  • Page 72 M451 Pin No. Pin Name Type MFP* Description PF.4 MFP0 General purpose digital I/O pin. XT1_IN MFP1 External 4~20 MHz (high speed) crystal input pin. I2C1_SDA MFP3 I2C1 data input/output pin. MFP0 Ground pin for digital circuit. Power supply for I/O ports and LDO source for internal MFP0 PLL and digital function.
  • Page 73 M451 Pin No. Pin Name Type MFP* Description PC.1 MFP0 General purpose digital I/O pin. CLKO MFP1 Clock Out STDAC MFP2 DAC external trigger input. UART2_nRTS MFP3 Request to Send output pin for UART2. PWM0_CH1 MFP6 PWM0 output/capture input. EBI_AD9 MFP7 EBI address/data bus bit 9.
  • Page 74 M451 Pin No. Pin Name Type MFP* Description PWM0_CH5 MFP6 PWM0 output/capture input. EBI_AD13 MFP7 EBI address/data bus bit 13. PC.6 MFP0 General purpose digital I/O pin. I2C1_SMBAL MFP3 I2C1 SMBus SMBALTER# pin ACMP1_O MFP5 Comparator1 output . PWM1_CH0 MFP6 PWM1 output/capture input.
  • Page 75 M451 Pin No. Pin Name Type MFP* Description UART3_nCTS MFP3 Clear to Send input pin for UART3. PA.11 MFP0 General purpose digital I/O pin. UART3_nRTS MFP3 Request to Send output pin for UART3. PE.6 MFP0 General purpose digital I/O pin. T3_EXT MFP3 Timer3 external capture input...
  • Page 76 M451 Pin No. Pin Name Type MFP* Description (M45xD/M45xC Only) PE.9 MFP0 General purpose digital I/O pin. UART1_RXD MFP1 Data receiver input pin for UART1. SPI0_MOSI1 MFP2 SPI0 2nd MOSI (Master Out, Slave In) pin. I2C1_SDA MFP4 I2C1 data input/output pin. SC0_RST MFP5 SmartCard reset pin.
  • Page 77 M451 Pin No. Pin Name Type MFP* Description I2C0_SDA MFP4 I2C0 data input/output pin. MFP0 Power supply for PE.8~PE.13. DDIO PE.7 MFP0 General purpose digital I/O pin. PC.15 MFP0 General purpose digital I/O pin. PWM1_CH0 MFP6 PWM1 output/capture input. PE.2 MFP0 General purpose digital I/O pin.
  • Page 78 M451 Pin No. Pin Name Type MFP* Description INT0 MFP8 External interrupt0 input pin. SPI1_I2SMCLK MFP9 I2S1 master clock output pin. (M45xD/M45xC Only) PA.12 MFP0 General purpose digital I/O pin. SPI1_I2SMCLK MFP2 I2S1 master clock output pin. PA.13 MFP0 General purpose digital I/O pin. PA.14 MFP0 General purpose digital I/O pin.
  • Page 79 M451 Pin No. Pin Name Type MFP* Description SPI0_CLK MFP2 SPI0 serial clock pin. SPI1_CLK MFP3 SPI1 serial clock pin UART1_RXD MFP4 Data receiver input pin for UART1. SC0_CD MFP5 SmartCard card detect pin. UART3_RXD MFP9 Data receiver input pin for UART3. (M45xD/M45xC Only) T2_EXT MFP11 Timer2 external capture input.
  • Page 80 M451 Pin No. Pin Name Type MFP* Description EADC_CH9 MFP1 EADC analog input channel 9. May. 4, 2018 Page 80 of 1006 Rev.2.08...

  • Page 81: M451M Series (M051 Pin Compatible) Lqfp48 Pin Description

    M451 4.3.4 M451M Series (M051 Pin Compatible) LQFP48 Pin Description MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH) PA.0 MFP0 means SYS_GPA_MFPL[3:0]=0x0. PA.9 MFP5 means SYS_GPA_MFPH[7:4]=0x5. Pin No. Pin Name Type MFP* Description PB.5 MFP0 General purpose digital I/O pin. EADC_CH13 MFP1 EADC analog input channel 13.
  • Page 82 M451 Pin No. Pin Name Type MFP* Description EADC_CH11 MFP1 EADC analog input channel 11. (M45xD/M45xC Only) PWM0_SYNC_IN MFP2 PWM0 counter synchronous trigger input pin. UART0_TXD MFP3 Data transmitter output pin for UART0. ACMP1_P2 MFP5 Comparator1 positive input pin. MFP6 Timer0event counter input / toggle output EBI_nRD MFP7...
  • Page 83 M451 Pin No. Pin Name Type MFP* Description PD.6 MFP0 General purpose digital I/O pin. CLKO MFP1 Clock Out SPI1_SS MFP2 SPI1 slave select pin UART0_RXD MFP3 Data receiver input pin for UART0. ACMP0_O MFP5 Comparator0 output. PWM0_CH5 MFP6 PWM0 output/capture input. EBI_nWR MFP7 EBI write enable output pin.
  • Page 84 M451 Pin No. Pin Name Type MFP* Description PWM0_CH1 MFP6 PWM0 output/capture input. EBI_AD9 MFP7 EBI address/data bus bit 9. UART3_RXD MFP9 Data receiver input pin for UART3. (M45xD/M45xC Only) PC.2 MFP0 General purpose digital I/O pin. SPI2_SS MFP2 SPI2 slave select pin. (M45xG/M45xE Only) UART2_TXD MFP3 Data transmitter output pin for UART2.
  • Page 85 M451 Pin No. Pin Name Type MFP* Description ACMP1_O MFP5 Comparator1 output . PWM1_CH0 MFP6 PWM1 output/capture input. EBI_AD14 MFP7 EBI address/data bus bit 14. UART0_TXD MFP9 Data transmitter output pin for UART0. (M45xD/M45xC Only) PC.7 MFP0 General purpose digital I/O pin. I2C1_SMBSUS MFP3 I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin)
  • Page 86 M451 Pin No. Pin Name Type MFP* Description SPI1_MOSI MFP2 SPI1 MOSI (Master Out, Slave In) pin. T2_EXT MFP3 Timer2 external capture input EBI_AD5 MFP7 EBI address/data bus bit 5. PA.4 MFP0 General purpose digital I/O pin. SPI1_SS MFP2 SPI1 slave select pin EBI_AD4 MFP7 EBI address/data bus bit 4.
  • Page 87 M451 Pin No. Pin Name Type MFP* Description SC0_CLK MFP5 SmartCard clock pin. PWM1_CH5 MFP6 PWM1 output/capture input. EBI_AD0 MFP7 EBI address/data bus bit 0. INT0 MFP8 External interrupt0 input pin. SPI1_I2SMCLK MFP9 I2S1 master clock output pin. (M45xD/M45xC Only) MFP0 Power supply for I/O ports and LDO source for internal PLL and digital function.
  • Page 88 M451 Pin No. Pin Name Type MFP* Description SPI1_MISO MFP3 SPI1 MISO (Master In, Slave Out) pin. UART1_TXD MFP4 Data transmitter output pin for UART1. UART3_TXD MFP9 Data transmitter output pin for UART3. (M45xD/M45xC Only) T0_EXT MFP11 Timer0 external capture input. (M45xD/M45xC Only) PB.4 MFP0 General purpose digital I/O pin.

  • Page 89: M451M Series (M058S Pin Compatible) Lqfp64 Pin Description

    M451 4.3.5 M451M Series (M058S Pin Compatible) LQFP64 Pin Description MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH) PA.0 MFP0 means SYS_GPA_MFPL[3:0]=0x0. PA.9 MFP5 means SYS_GPA_MFPH[7:4]=0x5. Pin No. Pin Name Type MFP* Description PB.5 MFP0 General purpose digital I/O pin. EADC_CH13 MFP1 EADC analog input channel 13.
  • Page 90 M451 Pin No. Pin Name Type MFP* Description PD.8 MFP0 General purpose digital I/O pin. EADC_CH7 MFP1 EADC analog input channel 7. (M45xD/M45xC Only) EBI_nCS0 MFP7 EBI chip select 0 enable output pin. PD.9 MFP0 General purpose digital I/O pin. EADC_CH10 MFP1 EADC analog input channel 10.
  • Page 91 M451 Pin No. Pin Name Type MFP* Description CLKO MFP1 Clock Out SPI1_MISO MFP2 SPI1 MISO (Master In, Slave Out) pin. I2C0_SCL MFP3 I2C0 clock pin. PWM0_BRAKE1 MFP5 PWM0 break input 1 MFP6 Timer1 event counter input / toggle output PE.3 MFP0 General purpose digital I/O pin.
  • Page 92 M451 Pin No. Pin Name Type MFP* Description PWM1_CH1 MFP6 PWM1 output/capture input. PC.11 MFP0 General purpose digital I/O pin. SPI2_MISO MFP2 SPI2 MISO (Master In, Slave Out) pin. (M45xG/M45xE Only) PWM1_CH2 MFP6 PWM1 output/capture input. PC.12 MFP0 General purpose digital I/O pin. SPI2_CLK MFP2 SPI2 serial clock pin.
  • Page 93 M451 Pin No. Pin Name Type MFP* Description UART2_RXD MFP3 Data receiver input pin for UART2. PWM0_CH3 MFP6 PWM0 output/capture input. EBI_AD11 MFP7 EBI address/data bus bit 11. PC.4 MFP0 General purpose digital I/O pin. SPI2 MISO (Master In, Slave Out) pin. (M45xG/M45xE SPI2_MISO MFP2 Only)
  • Page 94 M451 Pin No. Pin Name Type MFP* Description SC0_PWR MFP5 SmartCard power pin. PWM1_BRAKE0 MFP6 PWM1 break input 0 EBI_nCS0 MFP7 EBI chip select 0 enable output pin. INT0 MFP8 External interrupt0 input pin. PE.5 MFP0 General purpose digital I/O pin. I2C1_SDA MFP3 I2C1 data input/output pin.
  • Page 95 M451 Pin No. Pin Name Type MFP* Description PA.4 MFP0 General purpose digital I/O pin. SPI1_SS MFP2 SPI1 slave select pin EBI_AD4 MFP7 EBI address/data bus bit 4. PE.1 MFP0 General purpose digital I/O pin. T3_EXT MFP3 Timer3 external capture input SC0_CD MFP5 SmartCard card detect pin.
  • Page 96 M451 Pin No. Pin Name Type MFP* Description INT0 MFP8 External interrupt0 input pin. SPI1_I2SMCLK MFP9 I2S1 master clock output pin. (M45xD/M45xC Only) MFP0 Ground pin for digital circuit. MFP0 Power supply for I/O ports and LDO source for internal PLL and digital function.
  • Page 97 M451 Pin No. Pin Name Type MFP* Description T2_EXT MFP11 Timer2 external capture input. (M45xD/M45xC Only) PB.3 MFP0 General purpose digital I/O pin. EADC_CH3 MFP1 EADC analog input channel 3. SPI0_MISO0 MFP2 SPI0 1st MISO (Master In, Slave Out) pin. SPI1_MISO MFP3 SPI1 MISO (Master In, Slave Out) pin.

  • Page 98: M452 Usb Series Lqfp48 Pin Description

    M451 4.3.6 M452 USB Series LQFP48 Pin Description MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH) PA.0 MFP0 means SYS_GPA_MFPL[3:0]=0x0. PA.9 MFP5 means SYS_GPA_MFPH[7:4]=0x5. Pin No. Pin Name Type MFP* Description PB.5 MFP0 General purpose digital I/O pin. EADC_CH13 MFP1 EADC analog input channel 13.
  • Page 99 M451 Pin No. Pin Name Type MFP* Description EADC_CH11 MFP1 EADC analog input channel 11. (M45xD/M45xC Only) PWM0_SYNC_IN MFP2 PWM0 counter synchronous trigger input pin. UART0_TXD MFP3 Data transmitter output pin for UART0. ACMP1_P2 MFP5 Comparator1 positive input pin. MFP6 Timer0event counter input / toggle output EBI_nRD MFP7...
  • Page 100 M451 Pin No. Pin Name Type MFP* Description PF.3 MFP0 General purpose digital I/O pin. XT1_OUT MFP1 External 4~20 MHz (high speed) crystal output pin. I2C1_SCL MFP3 I2C1 clock pin. PF.4 MFP0 General purpose digital I/O pin. XT1_IN MFP1 External 4~20 MHz (high speed) crystal input pin. I2C1_SDA MFP3 I2C1 data input/output pin.
  • Page 101 M451 Pin No. Pin Name Type MFP* Description USB external VBUS regulator status pin. (M45xG/M45xE USB_VBUS_ST MFP4 Only) PWM0_CH3 MFP6 PWM0 output/capture input. EBI_AD11 MFP7 EBI address/data bus bit 11. PC.4 MFP0 General purpose digital I/O pin. SPI2_MISO MFP2 SPI2 MISO (Master In, Slave Out) pin. (M45xG/M45xE Only) I2C1_SCL MFP3...
  • Page 102 M451 Pin No. Pin Name Type MFP* Description UART1_nRTS MFP3 Request to Send output pin for UART1. I2C0_SMBSUS MFP4 I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin) SC0_CLK MFP5 SmartCard clock pin. UART3_RXD MFP9 Data receiver input pin for UART3. (M45xD/M45xC Only) I2C1_SDA MFP11 I2C1 data input/output pin.
  • Page 103 M451 Pin No. Pin Name Type MFP* Description UART0_TXD MFP2 Data transmitter output pin for UART0. UART0_nCTS MFP3 Clear to Send input pin for UART0. I2C0_SDA MFP4 I2C0 data input/output pin. SC0_RST MFP5 SmartCard reset pin. PWM1_CH3 MFP6 PWM1 output/capture input. EBI_AD2 MFP7 EBI address/data bus bit 2.
  • Page 104 M451 Pin No. Pin Name Type MFP* Description EADC_CH1 MFP1 EADC analog input channel 1. SPI0_MISO1 MFP2 SPI0 2nd MISO (Master In, Slave Out) pin. UART2_TXD MFP3 Data transmitter output pin for UART2. MFP4 Timer3 event counter input / toggle output SC0_RST MFP5 SmartCard reset pin.

  • Page 105: M452 Usb Series Lqfp64 Pin Description

    M451 4.3.7 M452 USB Series LQFP64 Pin Description MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH) PA.0 MFP0 means SYS_GPA_MFPL[3:0]=0x0. PA.9 MFP5 means SYS_GPA_MFPH[7:4]=0x5. Pin No. Pin Name Type MFP* Description PB.15 MFP0 General purpose digital I/O pin. EADC_CH12 MFP1 EADC analog input channel 12.
  • Page 106 M451 Pin No. Pin Name Type MFP* Description INT3 MFP8 External interrupt3 input pin. MFP11 Timer3 event counter input / toggle output. (M45xD/M45xC Only) MFP0 Ground pin for analog circuit. PD.8 MFP0 General purpose digital I/O pin. EADC_CH7 MFP1 EADC analog input channel 7. (M45xD/M45xC Only) EBI_nCS0 MFP7 EBI chip select 0 enable output pin.
  • Page 107 M451 Pin No. Pin Name Type MFP* Description INT5 MFP8 External interrupt5 input pin. PF.1 MFP0 General purpose digital I/O pin. X32_IN MFP1 External 32.768 kHZ (low speed) crystal input pin. PF.2 MFP0 General purpose digital I/O pin. TAMPER MFP1 TAMPER detector loop pin PD.12 MFP0...
  • Page 108 M451 Pin No. Pin Name Type MFP* Description I2C1_SCL MFP3 I2C1 clock pin. PF.4 MFP0 General purpose digital I/O pin. XT1_IN MFP1 External 4~20 MHz (high speed) crystal input pin. I2C1_SDA MFP3 I2C1 data input/output pin. MFP0 Ground pin for digital circuit. MFP0 Power supply for I/O ports and LDO source for internal PLL and digital function.
  • Page 109 M451 Pin No. Pin Name Type MFP* Description Only) PWM0_CH3 MFP6 PWM0 output/capture input. EBI_AD11 MFP7 EBI address/data bus bit 11. PC.4 MFP0 General purpose digital I/O pin. SPI2_MISO MFP2 SPI2 MISO (Master In, Slave Out) pin. (M45xG/M45xE Only) I2C1_SCL MFP3 I2C1 clock pin.
  • Page 110 M451 Pin No. Pin Name Type MFP* Description CLKO MFP9 Clock Out (M45xD/M45xC Only) PWM0_BRAKE0 MFP10 PWM0 break input 0 (M45xD/M45xC Only) MFP11 Timer1 event counter input / toggle output (M45xD/M45xC Only) PE.9 MFP0 General purpose digital I/O pin. UART1_RXD MFP1 Data receiver input pin for UART1.
  • Page 111 M451 Pin No. Pin Name Type MFP* Description SPI1_CLK MFP1 SPI1 serial clock pin SPI0_CLK MFP2 SPI0 serial clock pin. UART1_RXD MFP3 Data receiver input pin for UART1. I2C0_SDA MFP4 I2C0 data input/output pin. MFP0 Power supply for PE.8~PE.13. DDIO USB_VBUS MFP0 Power supply from USB* host or HUB.
  • Page 112 M451 Pin No. Pin Name Type MFP* Description EBI_AD1 MFP7 EBI address/data bus bit 1. STADC MFP10 ADC external trigger input. (M45xD/M45xC Only) PA.0 MFP0 General purpose digital I/O pin. UART1_nCTS MFP1 Clear to Send input pin for UART1. UART1_TXD MFP3 Data transmitter output pin for UART1.
  • Page 113 M451 Pin No. Pin Name Type MFP* Description SPI1_CLK MFP3 SPI1 serial clock pin UART1_RXD MFP4 Data receiver input pin for UART1. SC0_CD MFP5 SmartCard card detect pin. UART3_RXD MFP9 Data receiver input pin for UART3. (M45xD/M45xC Only) T2_EXT MFP11 Timer2 external capture input.

  • Page 114: M452 Usb Series Lqfp100 Pin Description

    M451 4.3.8 M452 USB Series LQFP100 Pin Description MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH) PA.0 MFP0 means SYS_GPA_MFPL[3:0] = 0x0. PA.9 MFP5 means SYS_GPA_MFPH[7:4] = 0x5. Pin No. Pin Name Type MFP* Description PB.13 MFP0 General purpose digital I/O pin. (M45xG/M45xE Only) EADC_CH10 MFP1 EADC analog input channel 10.
  • Page 115 M451 Pin No. Pin Name Type MFP* Description Set this pin low reset to initial state. PD.0 MFP0 General purpose digital I/O pin. EADC_CH6 MFP1 EADC analog input channel 6. (M45xD/M45xC Only) SPI1_I2SMCLK MFP2 I2S1 master clock output pin. UART0_RXD MFP3 Data receiver input pin for UART0.
  • Page 116 M451 Pin No. Pin Name Type MFP* Description PD.3 MFP0 General purpose digital I/O pin. MFP1 Timer2 event counter input / toggle output T1_EXT MFP3 Timer1 external capture input ACMP1_P0 MFP5 Comparator1 positive input pin. PWM0_BRAKE1 MFP6 PWM0 break input 1 EBI_MCLK MFP7 EBI external clock output pin...
  • Page 117 M451 Pin No. Pin Name Type MFP* Description PF.2 MFP0 General purpose digital I/O pin. TAMPER MFP1 TAMPER detector loop pin PD.10 MFP0 General purpose digital I/O pin. (M45xG/M45xE Only) MFP4 Timer2 event counter input / toggle output (M45xG/M45xE Only) Not connected (M45xD/M45xC Only) PD.11 MFP0...
  • Page 118 M451 Pin No. Pin Name Type MFP* Description PWM0_CH5 MFP6 PWM0 output/capture input. EBI_nRD MFP7 EBI read enable output pin. PF.3 MFP0 General purpose digital I/O pin. XT1_OUT MFP1 External 4~20 MHz (high speed) crystal output pin. I2C1_SCL MFP3 I2C1 clock pin. PF.4 MFP0 General purpose digital I/O pin.
  • Page 119 M451 Pin No. Pin Name Type MFP* Description UART2_nCTS MFP3 Clear to Send input pin for UART2. PWM0_CH0 MFP6 PWM0 output/capture input. EBI_AD8 MFP7 EBI address/data bus bit 8. INT2 MFP8 External interrupt2 input pin. Data transmitter output pin for UART3. (M45xD/M45xC UART3_TXD MFP9 Only)
  • Page 120 M451 Pin No. Pin Name Type MFP* Description SPI2_CLK MFP2 SPI2 serial clock pin. (M45xG/M45xE Only) I2C1_SDA MFP3 I2C1 data input/output pin. T2_EXT MFP4 Timer2 external capture input SC0_CD MFP5 SmartCard card detect pin. PWM0_CH0 MFP6 PWM0 output/capture input. EBI_nCS1 MFP7 EBI chip select 1 enable output pin.
  • Page 121 M451 Pin No. Pin Name Type MFP* Description PF.5 MFP0 General purpose digital I/O pin. ICE_CLK MFP1 Serial wired debugger clock pin PF.6 MFP0 General purpose digital I/O pin. ICE_DAT MFP1 Serial wired debugger data pin PA.8 MFP0 General purpose digital I/O pin. UART3_TXD MFP3 Data transmitter output pin for UART3.
  • Page 122 M451 Pin No. Pin Name Type MFP* Description SC0_PWR MFP5 SmartCard power pin. CLKO MFP9 Clock Out (M45xD/M45xC Only) PWM0_BRAKE0 MFP10 PWM0 break input 0 (M45xD/M45xC Only) MFP11 Timer1 event counter input / toggle output (M45xD/M45xC Only) PE.9 MFP0 General purpose digital I/O pin. UART1_RXD MFP1 Data receiver input pin for UART1.
  • Page 123 M451 Pin No. Pin Name Type MFP* Description PE.13 MFP0 General purpose digital I/O pin. SPI1_CLK MFP1 SPI1 serial clock pin SPI0_CLK MFP2 SPI0 serial clock pin. UART1_RXD MFP3 Data receiver input pin for UART1. I2C0_SDA MFP4 I2C0 data input/output pin. MFP0 Power supply for PE.8~PE.13.
  • Page 124 M451 Pin No. Pin Name Type MFP* Description UART1_nRTS MFP1 Request to Send output pin for UART1. UART1_RXD MFP3 Data receiver input pin for UART1. SC0_DAT MFP5 SmartCard data pin. PWM1_CH4 MFP6 PWM1 output/capture input. EBI_AD1 MFP7 EBI address/data bus bit 1. STADC MFP10 ADC external trigger input.
  • Page 125 M451 Pin No. Pin Name Type MFP* Description EBI_nWRL MFP7 EBI low byte write enable output pin. INT1 MFP8 External interrupt1 input pin. PB.1 MFP0 General purpose digital I/O pin. EADC_CH1 MFP1 EADC analog input channel 1. SPI0_MISO1 MFP2 SPI0 2nd MISO (Master In, Slave Out) pin. UART2_TXD MFP3 Data transmitter output pin for UART2.
  • Page 126 M451 Pin No. Pin Name Type MFP* Description T1_EXT MFP11 Timer1 external capture input. (M45xD/M45xC Only) PB.8 MFP0 General purpose digital I/O pin. EADC_CH5 MFP1 EADC analog input channel 5. UART1_nRTS MFP4 Request to Send output pin for UART1. PWM0_CH2 MFP6 PWM0 output/capture input.

  • Page 127: M453 Can Series(Can+Usb) Lqfp48 Pin Description

    M451 4.3.9 M453 CAN Series(CAN+USB) LQFP48 Pin Description MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH) PA.0 MFP0 means SYS_GPA_MFPL[3:0]=0x0. PA.9 MFP5 means SYS_GPA_MFPH[7:4]=0x5. Pin No. Pin Name Type MFP* Description PB.5 MFP0 General purpose digital I/O pin. EADC_CH13 MFP1 EADC analog input channel 13.
  • Page 128 M451 Pin No. Pin Name Type MFP* Description EADC_CH11 MFP1 EADC analog input channel 11. (M45xD/M45xC Only) PWM0_SYNC_IN MFP2 PWM0 counter synchronous trigger input pin. UART0_TXD MFP3 Data transmitter output pin for UART0. ACMP1_P2 MFP5 Comparator1 positive input pin. MFP6 Timer0event counter input / toggle output EBI_nRD MFP7...
  • Page 129 M451 Pin No. Pin Name Type MFP* Description PF.3 MFP0 General purpose digital I/O pin. XT1_OUT MFP1 External 4~20 MHz (high speed) crystal output pin. I2C1_SCL MFP3 I2C1 clock pin. PF.4 MFP0 General purpose digital I/O pin. XT1_IN MFP1 External 4~20 MHz (high speed) crystal input pin. I2C1_SDA MFP3 I2C1 data input/output pin.
  • Page 130 M451 Pin No. Pin Name Type MFP* Description Only) UART2_RXD MFP3 Data receiver input pin for UART2. USB_VBUS_ST MFP4 USB external VBUS regulator status pin. (M45xG/M45xE Only) PWM0_CH3 MFP6 PWM0 output/capture input. EBI_AD11 MFP7 EBI address/data bus bit 11. PC.4 MFP0 General purpose digital I/O pin.
  • Page 131 M451 Pin No. Pin Name Type MFP* Description SPI0_MOSI0 MFP2 SPI0 1st MOSI (Master Out, Slave In) pin. UART1_nRTS MFP3 Request to Send output pin for UART1. I2C0_SMBSUS MFP4 I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin) SC0_CLK MFP5 SmartCard clock pin. UART3_RXD MFP9 Data receiver input pin for UART3.
  • Page 132 M451 Pin No. Pin Name Type MFP* Description (M45xG/M45xE Only) UART0_TXD MFP2 Data transmitter output pin for UART0. UART0_nCTS MFP3 Clear to Send input pin for UART0. I2C0_SDA MFP4 I2C0 data input/output pin. SC0_RST MFP5 SmartCard reset pin. PWM1_CH3 MFP6 PWM1 output/capture input.
  • Page 133 M451 Pin No. Pin Name Type MFP* Description EBI_nWRL MFP7 EBI low byte write enable output pin. INT1 MFP8 External interrupt1 input pin. PB.1 MFP0 General purpose digital I/O pin. EADC_CH1 MFP1 EADC analog input channel 1. SPI0_MISO1 MFP2 SPI0 2nd MISO (Master In, Slave Out) pin. UART2_TXD MFP3 Data transmitter output pin for UART2.
  • Page 134 M451 Pin No. Pin Name Type MFP* Description T1_EXT MFP11 Timer1 external capture input. (M45xD/M45xC Only) May. 4, 2018 Page 134 of 1006 Rev.2.08...

  • Page 135: M453 Can Series(Can+Usb) Lqfp64 Pin Description

    M451 4.3.10 M453 CAN Series(CAN+USB) LQFP64 Pin Description MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH) PA.0 MFP0 means SYS_GPA_MFPL[3:0]=0x0. PA.9 MFP5 means SYS_GPA_MFPH[7:4]=0x5. Pin No. Pin Name Type MFP* Description PB.15 MFP0 General purpose digital I/O pin. EADC_CH12 MFP1 EADC analog input channel 12.
  • Page 136 M451 Pin No. Pin Name Type MFP* Description INT3 MFP8 External interrupt3 input pin. MFP11 Timer3 event counter input / toggle output. (M45xD/M45xC Only) MFP0 Ground pin for analog circuit. PD.8 MFP0 General purpose digital I/O pin. EADC_CH7 MFP1 EADC analog input channel 7. (M45xD/M45xC Only) EBI_nCS0 MFP7 EBI chip select 0 enable output pin.
  • Page 137 M451 Pin No. Pin Name Type MFP* Description INT5 MFP8 External interrupt5 input pin. PF.1 MFP0 General purpose digital I/O pin. X32_IN MFP1 External 32.768 kHZ (low speed) crystal input pin. PF.2 MFP0 General purpose digital I/O pin. TAMPER MFP1 TAMPER detector loop pin PD.12 MFP0...
  • Page 138 M451 Pin No. Pin Name Type MFP* Description I2C1_SCL MFP3 I2C1 clock pin. PF.4 MFP0 General purpose digital I/O pin. XT1_IN MFP1 External 4~20 MHz (high speed) crystal input pin. I2C1_SDA MFP3 I2C1 data input/output pin. MFP0 Ground pin for digital circuit. MFP0 Power supply for I/O ports and LDO source for internal PLL and digital function.
  • Page 139 M451 Pin No. Pin Name Type MFP* Description UART2_RXD MFP3 Data receiver input pin for UART2. USB_VBUS_ST MFP4 USB external VBUS regulator status pin. (M45xG/M45xE Only) PWM0_CH3 MFP6 PWM0 output/capture input. EBI_AD11 MFP7 EBI address/data bus bit 11. PC.4 MFP0 General purpose digital I/O pin.
  • Page 140 M451 Pin No. Pin Name Type MFP* Description I2C1_SCL MFP4 I2C1 clock pin. SC0_PWR MFP5 SmartCard power pin. CLKO MFP9 Clock Out (M45xD/M45xC Only) PWM0_BRAKE0 MFP10 PWM0 break input 0 (M45xD/M45xC Only) Timer1 event counter input / toggle output MFP11 (M45xD/M45xC Only) PE.9 MFP0...
  • Page 141 M451 Pin No. Pin Name Type MFP* Description I2C0_SCL MFP4 I2C0 clock pin. PE.13 MFP0 General purpose digital I/O pin. SPI1_CLK MFP1 SPI1 serial clock pin SPI0_CLK MFP2 SPI0 serial clock pin. UART1_RXD MFP3 Data receiver input pin for UART1. I2C0_SDA MFP4 I2C0 data input/output pin.
  • Page 142 M451 Pin No. Pin Name Type MFP* Description CAN0_TXD MFP4 CAN bus transmitter input. SC0_DAT MFP5 SmartCard data pin. PWM1_CH4 MFP6 PWM1 output/capture input. EBI_AD1 MFP7 EBI address/data bus bit 1. STADC MFP10 ADC external trigger input. (M45xD/M45xC Only) PA.0 MFP0 General purpose digital I/O pin.
  • Page 143 M451 Pin No. Pin Name Type MFP* Description EBI_nWRH MFP7 EBI high byte write enable output pin PB.2 MFP0 General purpose digital I/O pin. EADC_CH2 MFP1 EADC analog input channel 2. SPI0_CLK MFP2 SPI0 serial clock pin. SPI1_CLK MFP3 SPI1 serial clock pin UART1_RXD MFP4 Data receiver input pin for UART1.

  • Page 144: M453 Can Series(Can+Usb) Lqfp100 Pin Description

    M451 4.3.11 M453 CAN Series(CAN+USB) LQFP100 Pin Description MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH) PA.0 MFP0 means SYS_GPA_MFPL[3:0] = 0x0. PA.9 MFP5 means SYS_GPA_MFPH[7:4] = 0x5. Pin No. Pin Name Type MFP* Description PB.13 MFP0 General purpose digital I/O pin. (M45xG/M45xE Only) EADC_CH10 MFP1 EADC analog input channel 10.
  • Page 145 M451 Pin No. Pin Name Type MFP* Description Set this pin low reset to initial state. PD.0 MFP0 General purpose digital I/O pin. EADC_CH6 MFP1 EADC analog input channel 6. (M45xD/M45xC Only) SPI1_I2SMCLK MFP2 I2S1 master clock output pin. UART0_RXD MFP3 Data receiver input pin for UART0.
  • Page 146 M451 Pin No. Pin Name Type MFP* Description PD.3 MFP0 General purpose digital I/O pin. MFP1 Timer2 event counter input / toggle output T1_EXT MFP3 Timer1 external capture input ACMP1_P0 MFP5 Comparator1 positive input pin. PWM0_BRAKE1 MFP6 PWM0 break input 1 EBI_MCLK MFP7 EBI external clock output pin...
  • Page 147 M451 Pin No. Pin Name Type MFP* Description PF.2 MFP0 General purpose digital I/O pin. TAMPER MFP1 TAMPER detector loop pin PD.10 MFP0 General purpose digital I/O pin. (M45xG/M45xE Only) MFP4 Timer2 event counter input / toggle output (M45xG/M45xE Only) Not connected (M45xD/M45xC Only) PD.11 MFP0...
  • Page 148 M451 Pin No. Pin Name Type MFP* Description PWM0_CH5 MFP6 PWM0 output/capture input. EBI_nRD MFP7 EBI read enable output pin. PF.3 MFP0 General purpose digital I/O pin. XT1_OUT MFP1 External 4~20 MHz (high speed) crystal output pin. I2C1_SCL MFP3 I2C1 clock pin. PF.4 MFP0 General purpose digital I/O pin.
  • Page 149 M451 Pin No. Pin Name Type MFP* Description UART2_nCTS MFP3 Clear to Send input pin for UART2. CAN0_TXD MFP4 CAN bus transmitter input. PWM0_CH0 MFP6 PWM0 output/capture input. EBI_AD8 MFP7 EBI address/data bus bit 8. INT2 MFP8 External interrupt2 input pin. UART3_TXD MFP9 Data transmitter output pin for UART3.
  • Page 150 M451 Pin No. Pin Name Type MFP* Description EBI_AD12 MFP7 EBI address/data bus bit 12. PE.0 MFP0 General purpose digital I/O pin. SPI2_CLK MFP2 SPI2 serial clock pin. (M45xG/M45xE Only) I2C1_SDA MFP3 I2C1 data input/output pin. T2_EXT MFP4 Timer2 external capture input SC0_CD MFP5 SmartCard card detect pin.
  • Page 151 M451 Pin No. Pin Name Type MFP* Description EBI_ALE MFP7 EBI address latch enable output pin. INT1 MFP8 External interrupt1 input pin. PF.5 MFP0 General purpose digital I/O pin. ICE_CLK MFP1 Serial wired debugger clock pin PF.6 MFP0 General purpose digital I/O pin. ICE_DAT MFP1 Serial wired debugger data pin...
  • Page 152 M451 Pin No. Pin Name Type MFP* Description SPI0_MISO1 MFP2 SPI0 2nd MISO (Master In, Slave Out) pin. I2C1_SCL MFP4 I2C1 clock pin. SC0_PWR MFP5 SmartCard power pin. CLKO MFP9 Clock Out (M45xD/M45xC Only) PWM0_BRAKE0 MFP10 PWM0 break input 0 (M45xD/M45xC Only) MFP11 Timer1 event counter input / toggle output (M45xD/M45xC Only)
  • Page 153 M451 Pin No. Pin Name Type MFP* Description UART1_TXD MFP3 Data transmitter output pin for UART1. I2C0_SCL MFP4 I2C0 clock pin. PE.13 MFP0 General purpose digital I/O pin. SPI1_CLK MFP1 SPI1 serial clock pin SPI0_CLK MFP2 SPI0 serial clock pin. UART1_RXD MFP3 Data receiver input pin for UART1.
  • Page 154 M451 Pin No. Pin Name Type MFP* Description EBI_AD2 MFP7 EBI address/data bus bit 2. PA.1 MFP0 General purpose digital I/O pin. UART1_nRTS MFP1 Request to Send output pin for UART1. UART1_RXD MFP3 Data receiver input pin for UART1. CAN0_TXD MFP4 CAN bus transmitter input.
  • Page 155 M451 Pin No. Pin Name Type MFP* Description PB.0 MFP0 General purpose digital I/O pin. EADC_CH0 MFP1 EADC analog input. SPI0_MOSI1 MFP2 SPI0 2nd MOSI (Master Out, Slave In) pin. UART2_RXD MFP3 Data receiver input pin for UART2. MFP4 Timer2 event counter input / toggle output MFP5 DAC analog output EBI_nWRL...
  • Page 156 M451 Pin No. Pin Name Type MFP* Description SPI1_SS MFP3 SPI1 slave select pin UART1_nCTS MFP4 Clear to Send input pin for UART1. ACMP0_N MFP5 Comparator0 negative input pin. EBI_AD7 MFP7 EBI address/data bus bit 7. Data transmitter output pin for UART2. (M45xD/M45xC UART2_TXD MFP9 Only)

  • Page 157: Gpio Multi-Function Pin Summary

    M451 4.3.12 GPIO Multi-function Pin Summary MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH) PA.0 MFP0 means SYS_GPA_MFPL[3:0]=0x0. PA.9 MFP5 means SYS_GPA_MFPH[7:4]=0x5. Group Pin Name GPIO MFP* Type Description ACMP0_N PB.4 MFP5 Comparator0 negative input pin. ACMP0_O PD.6 MFP5 Comparator0 output.
  • Page 158 M451 Group Pin Name GPIO MFP* Type Description EADC_CH13 PB.5 MFP1 ADC13 analog input. EADC_CH14 PB.6 MFP1 ADC14 analog input. EADC_CH15 PB.7 MFP1 ADC15 analog input. STADC PD.2 MFP1 ADC external trigger input. ADC external trigger input. (M45xD/M45xC STADC PB.7 MFP10 Only) STADC...
  • Page 159 M451 Group Pin Name GPIO MFP* Type Description EBI_AD11 PC.3 MFP7 EBI address/data bus bit 11. EBI_AD12 PC.4 MFP7 EBI address/data bus bit 12. EBI_AD13 PC.5 MFP7 EBI address/data bus bit 13. EBI_AD14 PC.6 MFP7 EBI address/data bus bit 14. EBI_AD15 PC.7 MFP7...
  • Page 160 M451 Group Pin Name GPIO MFP* Type Description I2C1_SCL PC.4 MFP3 I2C1 clock pin. I2C1_SCL PE.4 MFP3 I2C1 clock pin. I2C1_SCL PE.8 MFP4 I2C1 clock pin. I2C1_SCL PE.10 MFP11 I2C1 clock pin. (M45xD/M45xC Only) I2C1_SDA PF.4 MFP3 I2C1 data input/output pin. I2C1_SDA PE.0 MFP3...
  • Page 161 M451 Group Pin Name GPIO MFP* Type Description PWM0_BRAKE0 PE.8 MFP10 PWM0 break input 0 (M45xD/M45xC Only) PWM0_BRAKE1 PD.3 MFP6 PWM0 break input 1 PWM0_BRAKE1 PD.5 MFP5 PWM0 break input 1 PWM0_CH0 PC.0 MFP6 PWM0 output/capture input. PWM0_CH0 PE.0 MFP6 PWM0 output/capture input.
  • Page 162 M451 Group Pin Name GPIO MFP* Type Description PWM1_CH3 PA.2 MFP6 PWM1 output/capture input. PWM1_CH4 PC.13 MFP6 PWM1 output/capture input. PWM1_CH4 PA.1 MFP6 PWM1 output/capture input. PWM1_CH5 PC.14 MFP6 PWM1 output/capture input. PWM1_CH5 PA.0 MFP6 PWM1 output/capture input. SC0_CD PE.0 MFP5 SmartCard card detect pin.
  • Page 163 M451 Group Pin Name GPIO MFP* Type Description SPI1_CLK PD.4 MFP2 SPI1 serial clock pin SPI1_CLK PA.7 MFP2 SPI1 serial clock pin SPI1_CLK PE.13 MFP1 SPI1 serial clock pin SPI1_CLK PB.2 MFP3 SPI1 serial clock pin SPI1_MISO PB.6 MFP3 SPI1 MISO (Master In, Slave Out) pin. SPI1_MISO PD.5 MFP2...
  • Page 164 M451 Group Pin Name GPIO MFP* Type Description PD.1 MFP6 Timer0event counter input / toggle output PD.4 MFP6 Timer0event counter input / toggle output T0_EXT PD.2 MFP3 Timer0 external capture input TMR0 T0_EXT PA.7 MFP3 Timer0 external capture input Timer0 external capture input (M45xD/M45xC T0_EXT PB.3 MFP11...
  • Page 165 M451 Group Pin Name GPIO MFP* Type Description Data transmitter output pin for UART0. UART0_TXD PC.6 MFP9 (M45xD/M45xC Only) UART0_nCTS PA.2 MFP3 Clear to Send input pin for UART0. UART0_nRTS PA.3 MFP3 Request to Send output pin for UART0. UART1_RXD PE.9 MFP1 Data receiver input pin for UART1.

  • Page 166: Table 4-1 M451 Gpio Multi-Function Table

    M451 Group Pin Name GPIO MFP* Type Description (M45xD/M45xC Only) UART3_TXD PD.12 MFP3 Data transmitter output pin for UART3. UART3_TXD PA.8 MFP3 Data transmitter output pin for UART3. UART3_TXD PB.3 MFP9 Data transmitter output pin for UART3. (M45xD/M45xC Only) Data transmitter output pin for UART3. UART3_TXD PE.10 MFP9...

  • Page 167: Block Diagram

    M451 BLOCK DIAGRAM ® NuMicro M451 Block Diagram ® Figure 5.1-1 NuMicro M45xG/M45xE Block Diagram May. 4, 2018 Page 167 of 1006 Rev.2.08...

  • Page 168: Figure 5.1-2 Numicro M45Xd/M45Xc Block Diagram

    M451 ® Figure 5.1-2 NuMicro M45xD/M45xC Block Diagram May. 4, 2018 Page 168 of 1006 Rev.2.08...

  • Page 169: Functional Description

    M451 FUNCTIONAL DESCRIPTION ® ® Cortex -M4 Core ® The Cortex -M4 processor, a configurable, multistage, 32-bit RISC processor, has three AMBA AHB-Lite interfaces for best parallel performance and includes an NVIC component. The processor with optional hardware debug functionality can execute Thumb code and is compatible with other Cortex-M profile processors.
  • Page 170 M451  Hardware integer divide instructions, SDIV and UDIV  Handler and Thread modes  Thumb and Debug states  Support for interruptible-continued instructions LDM, STM, PUSH, and POP for low interrupt latency  Automatic processor state saving and restoration for low latency Interrupt Service Routine (ISR) entry and exit ...
  • Page 171 M451 asserted.  Serial Wire Debug Port(SW-DP) or Serial Wire JTAG Debug Port (SWJ-DP) debug access  Optional Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches  Optional Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system profiling ...

  • Page 172: System Manager

    M451 System Manager 6.2.1 Overview The system manager provides the functions of system control, power modes, wake-up sources, reset sources, system memory map, product ID and multi-function pin control. The following sections describe the functions for  System Reset  Power Modes and Wake-up Sources ...

  • Page 173: Figure 6.2-1 System Reset Sources

    M451 Glitch Filter nRESET 36 us ~50k ohm POROFF(SYS_PORCTL[15:0]) Power-on Reset LVREN(SYS_BODCTL[7]) Reset Pulse Width Low Voltage 3.2ms Reset BODRSTEN(SYS_BODCTL[3]) Brown-out Reset WDT/WWDT System Reset Reset Pulse Width Reset Controller Reset 64 WDT clocks CPU Lockup Reset Pulse Width Reset 2 system clocks CHIP Reset CHIPRST(SYS_IPRST0[0])
  • Page 174 M451 ® There are a total of 9 reset sources in the NuMicro family. In general, CPU reset is used to reset Cortex-M4 only; the other reset sources will reset Cortex-M4 and all peripherals. However, there are small differences between each reset source and they are listed in Table 6-1. Reset Sources NRESET Lockup...

  • Page 175: Table 6-1 Reset Value Of Registers

    M451 WDT_ALTCTL 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 WWDT_RLDCNT 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 WWDT_CTL 0x3F0800 0x3F0800 0x3F0800 0x3F0800 0x3F0800 - 0x3F0800 WWDT_STATUS 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 WWDT_CNT 0x3F 0x3F 0x3F 0x3F 0x3F 0x3F Reload Reload Reload Reload Reload Reload...

  • Page 176: Figure 6.2-2 Nreset Reset Waveform

    M451 nRESET 0.7 V 36 us 0.2 V 36 us nRESET Reset Figure 6.2-2 nRESET Reset Waveform 6.2.2.2 Power-on Reset (POR) The Power-on reset (POR) is used to generate a stable system reset signal and forces the system to be reset when power-on to avoid unexpected behavior of MCU. When applying the power to MCU, the POR module will detect the rising voltage and generate reset signal to system until the voltage is ready for MCU operation.

  • Page 177: Figure 6.2-4 Low Voltage Reset (Lvr) Waveform

    M451 ( < LVRDGSEL) ( =LVRDGSEL) ( =LVRDGSEL) Low Voltage Reset 200 us Delay for LVR stable LVREN Figure 6.2-4 Low Voltage Reset (LVR) Waveform 6.2.2.4 Brown-out Detector Reset (BOD Reset) If the Brown-out Detector (BOD) function is enabled by setting the Brown-out Detector Enable Bit BODEN (SYS_BODCTL[0]), Brown-Out Detector function will detect AV during system operation.

  • Page 178: Figure 6.2-5 Brown-Out Detector (Bod) Waveform

    M451 BODH Hysteresis BODL (< BODDGSEL) (= BODDGSEL) BODOUT (= BODDGSEL) BODRSTEN Brown-out Reset Figure 6.2-5 Brown-out Detector (BOD) Waveform 6.2.2.5 Watchdog Timer Reset (WDT) In most industrial applications, system reliability is very important. To automatically recover the MCU from failure status is one way to improve system reliability. The watchdog timer(WDT) is widely used to check if the system works fine.

  • Page 179: Power Modes And Wake-Up Sources

    M451 reloaded from CONFIG setting and keep its original software setting for booting from APROM or LDROM. User can set the SYSRESETREQ(AIRCR[2]) to 1 to assert the MCU Reset. 6.2.3 Power Modes and Wake-up Sources There are several wake-up sources in Idle mode and Power-down mode. Table 6-2 lists the available clocks for each power mode.
  • Page 180 M451 1. LXT (32768 Hz XTL) ON or OFF depends on SW setting in run mode. 2. LIRC (10 kHz OSC) ON or OFF depends on S/W setting in run mode. 3. If TIMER clock source is selected as LIRC/LXT and LIRC/LXT is on. 4.

  • Page 181: System Power Distribution

    M451 Table 6-3 Clocks in Power Modes Wake-up sources in Power-down mode: RTC, WDT, I²C, Timer, UART, BOD, GPIO, USBH, USBD, OTG, CAN and ACMP After chip enters power down, the following wake-up sources can wake chip up to normal mode. Table 6-4 lists the condition about how to enter Power-down mode again for each peripheral.

  • Page 182: Figure 6.2-7 Numicro M451 Power Distribution Diagram

    M451  RTC power from V provides the power for PF.0~PF.2, RTC and 80 bytes backup registers.  A dedicated power from V supplies the power for PE.8~PE.13. DDIO The outputs of internal voltage regulators, LDO_CAP and USB_VDD33_CAP, require an external capacitor which should be located close to the corresponding pin.

  • Page 183: System Memory Map

    M451 6.2.5 System Memory Map ® The NuMicro M451 series provides 4G-byte addressing space. The memory locations assigned to each on-chip controllers are shown in theTable 6-5. The detailed register definition, memory space, ® and programming will be described in the following sections for each on-chip peripheral. The NuMicro M451 series only supports little-endian data format.
  • Page 184 M451 0x4004_1000 – 0x4004_1FFF RTC_BA Real Time Clock (RTC) Control Register 0x4004_3000 – 0x4004_3FFF EADC_BA Enhanced Analog-Digital-Converter (EADC) Control Registers 0x4004_4000 – 0x4004_4FFF Reserved Reserved 0x4004_5000 – 0x4004_5FFF ACMP01_BA Analog Comparator 0/ 1 Control Registers 0x4004_6000 – 0x4004_6FFF Reserved Reserved 0x4004_7000 –...

  • Page 185: Table 6-5 Address Space Assignments For On-Chip Controllers

    M451 0x4009_5000 – 0x4009_5FFF Reserved Reserved 0x400A_0000 – 0x400A_0FFF CAN0_BA CAN0 Bus Control Registers 0x400A_1000 – 0x400A_1FFF Reserved Reserved 0x400B_0000 – 0x400B_0FFF Reserved Reserved 0x400B_1000 – 0x400B_1FFF Reserved Reserved 0x400B_0000 – 0x400B_0FFF Reserved Reserved 0x400B_1000 – 0x400B_1FFF Reserved Reserved 0x400C_0000 – 0x400C_0FFF USBD_BA USB Device Control Register 0x400E_0000 –...

  • Page 186: Sram Memory Organization

    M451 6.2.6 SRAM Memory Organization The M45xG/M45xE supports embedded SRAM with total 32 KB size and the SRAM organization is separated to two banks: SRAM bank0 and SRAM bank1. Each of these two banks has 16 KB address space and can be accessed simultaneously. The SRAM bank0 supports parity error check to make sure chip operating more stable.

  • Page 187: Figure 6.2-9 Sram Memory Organization (M45Xg/M45Xe)

    M451 Figure 6.2-9 shows the SRAM organization of M45xG/M45xE. There are two SRAM banks in M45xG/M45xE and each bank is addressed to 16 KB. The bank0 address space is from 0x2000_0000 to 0x2000_3FFF. The bank1 address space is from 0x2000_4000 to 0x2000_7FFF. The address between 0x2000_8000 to 0x3FFF_FFFF is illegal memory space and chip will enter hardfault if CPU accesses these illegal memory addresses.

  • Page 188: Figure 6.2-10 Sram Memory Organization (M45Xd/M45Xc)

    M451 Figure 6.2-10 shows the SRAM organization of M45xD/M45xC. There are two SRAM banks in M45xD/M45xC and each bank is addressed to 8 KB. The bank0 address space is from 0x2000_0000 to 0x2000_1FFF. The bank1 address space is from 0x2000_2000 to 0x2000_3FFF. The address between 0x2000_4000 to 0x3FFF_FFFF is illegal memory space and chip will enter hardfault if CPU accesses these illegal memory addresses.
  • Page 189 M451 recode the address with parity error. Chip will enter interrupt when SRAM parity error occurred if PERRIEN (SYS_SRAM_INTCTL[0]) is set to 1. When SRAM parity error occurred, chip will stop detecting SRAM parity error until user writes 1 to clear the PERRIF(SYS_SRAM_STATUS[0]) bit. May.

  • Page 190: Register Map

    M451 6.2.7 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value SYS Base Address: SYS_BA = 0x4000_0000 0xXXXX_XXXX SYS_PDID SYS_BA+0x00 R Part Device Identification Number Register SYS_RSTSTS SYS_BA+0x04 R/W System Reset Status Register 0x0000_0043 SYS_IPRST0 SYS_BA+0x08 R/W Peripheral Reset Control Register 0...
  • Page 191 M451 SYS_SRAM_BIST SYS_BA+0xD4 R System SRAM BIST Test Status Register 0x00xx_00xx SYS_IRCTCTL SYS_BA+0xF0 R/W HIRC Trim Control Register 0x0000_0000 SYS_IRCTIEN SYS_BA+0xF4 R/W HIRC Trim Interrupt Enable Register 0x0000_0000 SYS_IRCTISTS SYS_BA+0xF8 R/W HIRC Trim Interrupt Status Register 0x0000_0000 SYS_REGLCTL SYS_BA+0x100 R/W Register Lock Control Register 0x0000_0000 SYS_AHBMCTL SYS_BA+0x400 R/W AHB Bus Matrix Priority Control Register...

  • Page 192: Register Description

    M451 6.2.8 Register Description Part Device Identification Number Register (SYS_PDID) Register Offset Description Reset Value 0xXXXX_XXXX SYS_PDID SYS_BA+0x00 Part Device Identification Number Register [1] Every part number has a unique default reset value. PDID PDID PDID PDID Bits Description Part Device Identification Number (Read Only) [31:0] PDID This register reflects device part number code.
  • Page 193 M451 System Reset Status Register (SYS_RSTSTS) This register provides specific information for software to identify this chip’s reset source from last operation. Register Offset Description Reset Value SYS_RSTSTS SYS_BA+0x04 System Reset Status Register 0x0000_0043 Reserved Reserved Reserved CPULKRF CPURF Reserved SYSRF BODRF LVRF...
  • Page 194 M451 Bits Description BOD Reset Flag The BOD reset flag is set by the “Reset Signal” from the Brown-Out Detector to indicate the previous reset source. BODRF 0 = No reset from BOD. 1 = The BOD had issued the reset signal to reset the system. Note: Write 1 to clear this bit to 0.
  • Page 195 M451 Peripheral Reset Control Register 0 (SYS_IPRST0) Register Offset Description Reset Value Peripheral Reset Control Register 0 SYS_IPRST0 SYS_BA+0x08 0x0000_0000 Reserved Reserved Reserved CRCRST Reserved USBHRST EBIRST PDMARST CPURST CHIPRST Bits Description [31:8] Reserved Reserved. CRC Calculation Controller Reset (Write Protect) Set this bit to 1 will generate a reset signal to the CRC calculation controller.
  • Page 196 M451 this bit will automatically return to 0 after the 2 clock cycles. 0 = Processor core normal operation. 1 = Processor core one-shot reset. Note: This bit is write protected. Refer to the SYS_REGLCTL register. Chip One-shot Reset (Write Protect) Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.
  • Page 197 M451 Peripheral Reset Control Register 1 (SYS_IPRST1) Setting these bits 1 will generate asynchronous reset signals to the corresponding module controller. Users need to set these bits to 0 to release corresponding module controller from reset state. Register Offset Description Reset Value SYS_IPRST1 SYS_BA+0x0C...
  • Page 198 M451 1 = UART1 controller reset. UART0 Controller Reset [16] UART0RST 0 = UART0 controller normal operation. 1 = UART0 controller reset. Reserved [15] Reserved. SPI2 Controller Reset (M45xG/M45xE Only) [14] SPI2RST 0 = SPI2 controller normal operation. 1 = SPI2 controller reset. SPI1 Controller Reset SPI1RST 0 = SPI1 controller normal operation.
  • Page 199 M451 Peripheral Reset Control Register 2 (SYS_IPRST2) Setting these bits to 1 will generate asynchronous reset signals to the corresponding module controller. Users need to set these bits to 0 to release corresponding module controller from reset state. Register Offset Description Reset Value SYS_IPRST2...
  • Page 200 M451 Brown-out Detector Control Register (SYS_BODCTL) Partial of the SYS_BODCTL control registers values are initiated by the flash configuration and partial bits are write-protected bit. Register Offset Description Reset Value SYS_BODCTL SYS_BA+0x18 Brown-Out Detector Control Register 0x0000_038X Reserved Reserved Reserved LVRDGSEL Reserved BODDGSEL...
  • Page 201 M451 Bits Description Low Voltage Reset Enable Bit (Write Protect) The LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default. 0 = Low Voltage Reset function Disabled. LVREN 1 = Low Voltage Reset function Enabled.
  • Page 202 M451 Bits Description Brown-out Detector Enable Bit (Write Protect) The default value is set by flash controller user configuration register CBODEN (CONFIG0 [23]). 0 = Brown-out Detector function Disabled. BODEN 1 = Brown-out Detector function Enabled. Note1: This bit is write protected. Refer to the SYS_REGLCTL register. Note2: LIRC must be enabled before enable BOD.
  • Page 203 M451 Internal Voltage Source Control Register (SYS_IVSCTL) Register Offset Description Reset Value SYS_IVSCTL SYS_BA+0x1C Internal Voltage Source Control Register 0x0000_0000 Reserved Reserved Reserved Reserved VBATUGEN VTEMPEN Bits Description [31:2] Reserved Reserved. VBAT Unity Gain Buffer Enable Bit This bit is used to enable/disable VBAT unity gain buffer function. 0 = VBAT unity gain buffer function Disabled (default).
  • Page 204 M451 Power-on Reset Controller Register (SYS_PORCTL) Register Offset Description Reset Value SYS_PORCTL SYS_BA+0x24 Power-On-Reset Controller Register 0x0000_XXXX Reserved Reserved POROFF POROFF Bits Description [31:16] Reserved Reserved. Power-on Reset Enable Bit (Write Protect) When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again.
  • Page 205 M451 VREF Control Register (SYS_VREFCTL) Register Offset Description Reset Value SYS_VREFCTL SYS_BA+0x28 VREF Control Register 0x0000_0000 Reserved Reserved Reserved Reserved VREFCTL Bits Description [31:5] Reserved Reserved. Control Bits (Write Protect) 00000 = V is from external pin. 00011 = V is internal 2.56V.
  • Page 206 M451 USB PHY Control Register (SYS_USBPHY) Register Offset Description Reset Value SYS_USBPHY SYS_BA+0x2C USB PHY Control Register (M45xG/M45xE Only) 0x0000_0003 Reserved Reserved Reserved LDO33EN Reserved USBROLE Bits Description [31:9] Reserved Reserved. USB LDO33 Enable Bit (Write Protect) (M45xG/M45xE Only) 0 = USB LDO33 Disabled. LDO33EN 1 = USB LDO33 Enabled.
  • Page 207 M451 GPIOA Low Byte Multiple Function Control Register (SYS_GPA_MFPL) Please refer to 4.3.12 GPIO Multi-function Pin Summary. Register Offset R/W Description Reset Value SYS_GPA_MFPL SYS_BA+0x30 R/W GPIOA Low Byte Multiple Function Control Register 0x0000_0000 PA7MFP PA6MFP PA5MFP PA4MFP PA3MFP PA2MFP PA1MFP PA0MFP Bits...
  • Page 208 M451 GPIOA High Byte Multiple Function Control Register (SYS_GPA_MFPH) Please refer to 4.3.12 GPIO Multi-function Pin Summary. Register Offset R/W Description Reset Value SYS_GPA_MFPH SYS_BA+0x34 R/W GPIOA High Byte Multiple Function Control Register 0x0000_0000 PA15MFP PA14MFP PA13MFP PA12MFP PA11MFP PA10MFP PA9MFP PA8MFP Bits...
  • Page 209 M451 GPIOB Low Byte Multiple Function Control Register (SYS_GPB_MFPL) Please refer to 4.3.12 GPIO Multi-function Pin Summary. Register Offset Description Reset Value SYS_GPB_MFPL SYS_BA+0x38 R/W GPIOB Low Byte Multiple Function Control Register 0x0000_0000 PB7MFP PB6MFP PB5MFP PB4MFP PB3MFP PB2MFP PB1MFP PB0MFP Bits Description...
  • Page 210 M451 GPIOB High Byte Multiple Function Control Register (SYS_GPB_MFPH) Please refer to 4.3.12 GPIO Multi-function Pin Summary. Register Offset R/W Description Reset Value SYS_GPB_MFPH SYS_BA+0x3C R/W GPIOB High Byte Multiple Function Control Register 0x0000_0000 PB15MFP PB14MFP PB13MFP PB12MFP PB11MFP PB10MFP PB9MFP PB8MFP Bits...
  • Page 211 M451 GPIOC Low Byte Multiple Function Control Register (SYS_GPC_MFPL) Please refer to 4.3.12 GPIO Multi-function Pin Summary. Register Offset Description Reset Value SYS_GPC_MFPL SYS_BA+0x40 R/W GPIOC Low Byte Multiple Function Control Register 0x0000_0000 PC7MFP PC6MFP PC5MFP PC4MFP PC3MFP PC2MFP PC1MFP PC0MFP Bits Description...
  • Page 212 M451 GPIOC High Byte Multiple Function Control Register (SYS_GPC_MFPH) Please refer to 4.3.12 GPIO Multi-function Pin Summary. Register Offset Description Reset Value SYS_GPC_MFPH SYS_BA+0x44 R/W GPIOC High Byte Multiple Function Control Register 0x0000_0000 PC15MFP PC14MFP PC13MFP PC12MFP PC11MFP PC10MFP PC9MFP PC8MFP Bits Description...
  • Page 213 M451 GPIOD Low Byte Multiple Function Control Register (SYS_GPD_MFPL) Please refer to 4.3.12 GPIO Multi-function Pin Summary. Register Offset Description Reset Value SYS_GPD_MFPL SYS_BA+0x48 GPIOD Low Byte Multiple Function Control Register 0x0000_0000 PD7MFP PD6MFP PD5MFP PD4MFP PD3MFP PD2MFP PD1MFP PD0MFP Bits Description [31:28]...
  • Page 214 M451 GPIOD High Byte Multiple Function Control Register (SYS_GPD_MFPH) Please refer to 4.3.12 GPIO Multi-function Pin Summary Register Offset R/W Description Reset Value SYS_GPD_MFPH SYS_BA+0x4C R/W GPIOD High Byte Multiple Function Control Register 0x0000_0000 PD15MFP PD14MFP PD13MFP PD12MFP PD11MFP PD10MFP PD9MFP PD8MFP Bits...
  • Page 215 M451 GPIOE Low Byte Multiple Function Control Register (SYS_GPE_MFPL) Please refer to 4.3.12 GPIO Multi-function Pin Summary. Register Offset Description Reset Value SYS_GPE_MFPL SYS_BA+0x50 GPIOE Low Byte Multiple Function Control Register 0x0000_0000 PE7MFP PE6MFP PE5MFP PE4MFP PE3MFP PE2MFP PE1MFP PE0MFP Bits Description [31:28]...
  • Page 216 M451 GPIOE High Byte Multiple Function Control Register (SYS_GPE_MFPH) Please refer to 4.3.12 GPIO Multi-function Pin Summary. Register Offset R/W Description Reset Value SYS_GPE_MFPH SYS_BA+0x54 R/W GPIOE High Byte Multiple Function Control Register 0x0000_0000 Reserved PE14_MFP PE13MFP PE12MFP PE11MFP PE10MFP PE9MFP PE8MFP Bits...
  • Page 217 M451 GPIOF Low Byte Multiple Function Control Register (SYS_GPF_MFPL) Please refer to 4.3.12 GPIO Multi-function Pin Summary. Register Offset Description Reset Value SYS_GPF_MFPL SYS_BA+0x58 GPIOF Low Byte Multiple Function Control Register 0x0000_0000 PF7MFP PF6MFP PF5MFP PF4MFP PF3MFP PF2MFP PF1MFP PF0MFP Bits Description [31:28]...
  • Page 218 M451 System SRAM Parity Error Interrupt Enable Control Register (SYS_SRAM_INTCTL) Register Offset Description Reset Value SYS_SRAM_INTCTL SYS_BA+0xC0 System SRAM Interrupt Enable Control Register 0x0000_0000 Reserved Reserved Reserved Reserved PERRIEN Bits Description [31:1] Reserved Reserved. SRAM Parity Check Error Interrupt Enable Bit PERRIEN 0 = SRAM parity check error interrupt Disabled.
  • Page 219 M451 System SRAM Parity Check Status Register (SYS_SRAM_STATUS) Register Offset Description Reset Value SYS_SRAM_STATUS SYS_BA+0xC4 System SRAM Parity Error Status Register 0x0000_0000 Reserved Reserved Reserved Reserved PERRIF Bits Description [31:1] Reserved Reserved. SRAM Parity Check Error Flag PERRIF 0 = No System SRAM parity error. 1 = System SRAM parity error occur.
  • Page 220 M451 System SRAM Parity Error Address Register (SYS_SRAM_ERRADDR) Register Offset Description Reset Value SYS_SRAM_ERRADDR SYS_BA+0xC8 R System SRAM Parity Check Error Address Register 0x0000_0000 ERRADDR ERRADDR ERRADDR ERRADDR Bits Description System SRAM Parity Error Address [31:0] ERRADDR This register shows system SRAM parity error byte address. May.
  • Page 221 M451 System SRAM BIST Test Control Register (SYS_SRAM_BISTCTL) Register Offset Description Reset Value SYS_SRAM_BIS SYS_BA+0xD0 System SRAM BIST Test Control Register 0x0000_0000 TCTL Reserved Reserved Reserved Reserved USBBIST CANBIST CRBIST SRBIST1 SRBIST0 Bits Description [31:5] Reserved Reserved. USB BIST Enable Bit (Write Protect) This bit enables BIST test for USB RAM USBBIST 0 = system USB BIST Disabled.
  • Page 222 M451 System SRAM BIST Test Status Register (SYS_SRAM_BISTSTS) Register Offset Description Reset Value SYS_SRAM_BIS SYS_BA+0xD4 System SRAM BIST Test Status Register 0x00xx_00xx TSTS Reserved Reserved USBBEND CANBEND CRBEND SRBEND1 SRBEND0 Reserved Reserved USBBEF CANBEF CRBISTEF SRBISTEF1 SRBISTEF0 Bits Description [31:21] Reserved Reserved.
  • Page 223 M451 1 = System CACHE RAM BIST test fail. System SRAM BIST Fail Flag SRBISTEF1 0 = 2nd system SRAM BIST test pass. 1 = 2nd system SRAM BIST test fail. System SRAM BIST Fail Flag SRBISTEF0 0 = 1 system SRAM BIST test pass.
  • Page 224 M451 HIRC Trim Control Register (SYS_IRCTCTL) Register Offset Description Reset Value SYS_IRCTCTL SYS_BA+0xF0 HIRC Trim Control Register 0x0000_0000 Reserved Reserved Reserved CESTOPEN RETRYCNT LOOPSEL Reserved FREQSEL Bits Description [31:9] Reserved Reserved. Clock Error Stop Enable Bit CESTOPEN 0 = The trim operation is keep going if clock is inaccuracy. 1 = The trim operation is stopped if clock is inaccuracy.
  • Page 225 M451 00 = Disable HIRC auto trim function. 01 = Enable HIRC auto trim function and trim HIRC to 22.1184 MHz. Others = Reserved. Note: HIRC auto trim cannot work normally at power down mode. These bits must be cleared before entering power down mode. May.
  • Page 226 M451 HIRC Trim Interrupt Enable Register (SYS_IRCTIEN) Register Offset Description Reset Value SYS_IRCTIEN SYS_BA+0xF4 HIRC Trim Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved CLKEIEN TFAILIEN Reserved Bits Description [31:3] Reserved Reserved. Clock Error Interrupt Enable Bit This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.
  • Page 227 M451 HIRC Trim Interrupt Status Register (SYS_IRCTISTS) Register Offset Description Reset Value SYS_IRCTISTS SYS_BA+0xF8 HIRC Trim Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved Reserved CLKERRIF TFAILIF FREQLOCK Bits Description [31:3] Reserved Reserved. Clock Error Interrupt Status When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 22.1184 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy Once this bit is set to 1, the auto trim operation stopped and...
  • Page 228 M451 Register Lock Control Register (SYS_REGLCTL) Some of the system control registers need to be protected to avoid inadvertent write and disturb the chip operation. These system control registers are protected after the power-on reset till user to disable register protection. For user to program these protected registers, a register protection disable sequence needs to be followed by a special programming.
  • Page 229 M451 interrupt clear) SYS_SRAM_BISTCTL: address 0x4000_00D0 CLK_APBCLK0 [0]: address 0x4000_0208 (bit[0] is watchdog clock enable) CLK_CLKSEL0: address 0x4000_0210 (for HCLK and CPU STCLK clock source select) CLK_CLKSEL1 [1:0]: address 0x4000_0214 (for watchdog clock source select) CLK_CLKSEL1 [31:30]: address 0x4000_0214 (for window watchdog clock source select) CLK_CLKDSTS: address 0x4000_0274 NMIEN: address 0x4000_0300 FMC_ISPCTL: address 0x4000_C000 (Flash ISP Control register)
  • Page 230 M451 AHB Bus Matrix Priority Control Register (SYS_AHBMCTL) Register Offset Description Reset Value SYS_AHBMCTL SYS_BA+0x400 AHB Bus Matrix Priority Control Register 0x0000_0001 Reserved Reserved Reserved Reserved INTACTEN Bits Description [31:1] Reserved Reserved. Highest AHB Bus Priority of Cortex M4 Core Enable Bit (Write Protect) ®...

  • Page 231: System Timer (Systick)

    M451 6.2.9 System Timer (SysTick) ® The Cortex -M4 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter. When system timer is enabled, it will count down from the value in the SysTick Current Value Register (SYST_VAL) to zero, and reload (wrap) to the value in the SysTick Reload Value Register (SYST_LOAD) on the next clock cycle, and then decrement on subsequent clocks.
  • Page 232 M451 6.2.9.2 System Timer Control Register Description SysTick Control and Status Register (SYST_CTRL) Register Offset Description Reset Value SYST_CTRL SCS_BA+0x10 SysTick Control and Status Register 0x0000_0000 Reserved Reserved COUNTFLAG Reserved Reserved CLKSRC TICKINT ENABLE Bits Description [31:17] Reserved Reserved. System Tick Counter Flag Returns 1 if timer counted to 0 since last time this register was read.
  • Page 233 M451 SysTick Reload Value Register (SYST_LOAD) Register Offset Description Reset Value SYST_LOAD SCS_BA+0x14 SysTick Reload Value Register 0xXXXX_XXXX Reserved RELOAD RELOAD RELOAD Bits Description [31:24] Reserved Reserved. System Tick Reload Value RELOAD [23:0] Value to load into the Current Value register when the counter reaches 0. May.
  • Page 234 M451 SysTick Current Value Register (SYST_VAL) Register Offset Description Reset Value SYST_VAL SCS_BA+0x18 SysTick Current Value Register 0xXXXX_XXXX Reserved CURRENT CURRENT CURRENT Bits Description [31:24] Reserved Reserved. System Tick Current Value Current counter value. This is the value of the counter at the time it is sampled. The [23:0] CURRENT counter does not provide read-modify-write protection.

  • Page 235: Nested Vectored Interrupt Controller (Nvic)

    M451 6.2.10 Nested Vectored Interrupt Controller (NVIC) The NVIC and the processor core interface are closely coupled to enable low latency interrupt processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge of the stacked, or nested, interrupts to enable tail-chaining of interrupts. You can only fully access the NVIC from privileged mode, but you can cause interrupts to enter a pending state in user mode if you enable the Configuration and Control Register.

  • Page 236: Table 6-6 Exception Model

    M451 Bus Fault 0x00000014 Configurable Usage Fault 0x00000018 Configurable Reserved 7 ~ 10 Reserved SVCall 0x0000002C Configurable Debug Monitor 0x00000030 Configurable Reserved Reserved PendSV 0x00000038 Configurable SysTick 0x0000003C Configurable 0x00000000 + Interrupt (IRQ0 ~ IRQ) 16 ~ 79 Configurable (Vector Number)*4 Table 6-6 Exception Model Interrupt Number Vector...
  • Page 237 M451 GPE_INT External interrupt from PE[14:0] pin GPF_INT External interrupt from PF[7:0] pin SPI0_INT SPI0 interrupt SPI1_INT SPI1 interrupt BRAKE0_INT PWM0 brake interrupt PWM0_P0_INT PWM0 pair 0 interrupt PWM0_P1_INT PWM0 pair 1 interrupt PWM0_P2_INT PWM0 pair 2 interrupt BRAKE1_INT PWM1 brake interrupt PWM1_P0_INT PWM1 pair 0 interrupt PWM1_P1_INT...

  • Page 238: Table 6-7 Interrupt Number Table

    M451 USBOTG_INT USB OTG interrupt (M45xG/M45xE Only) CAN0_INT CAN0 interrupt Reserved Reserved SC0_INT Smart card host 0 interrupt Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Table 6-7 Interrupt Number Table 6.2.10.2 Operation Description NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set- Enable or Interrupt Clear-Enable register bit-field.
  • Page 239 M451 6.2.10.3 NVIC Control Registers R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value NVIC Base Address: NVIC_BA = 0xE000_E100 NVIC_ISER1 NVIC_BA+0x000 IRQ0 ~ IRQ63 Set-Enable Control Register 0x0000_0000 NVIC_ISER2 NVIC_BA+0x004 IRQ0 ~ IRQ63 Set-Enable Control Register 0x0000_0000 NVIC_ICER1 NVIC_BA+0x080...
  • Page 240 M451 IRQ0 ~ IRQ63 Set-Enable Control Register (NVIC_ISER1) Register Offset Description Reset Value NVIC_ISER1 NVIC_BA+0x000 IRQ0 ~ IRQ63 Set-Enable Control Register 0x0000_0000 SETENA SETENA SETENA SETENA Bits Description Interrupt Set Enable Bit The NVIC_ISER0-NVIC_ISER3 registers enable interrupts, and show which interrupts are enabled Write Operation: 0 = No effect.
  • Page 241 M451 IRQ0 ~ IRQ63 Set-Enable Control Register (NVIC_ISER2) Register Offset Description Reset Value NVIC_ISER2 NVIC_BA+0x004 IRQ0 ~ IRQ63 Set-Enable Control Register 0x0000_0000 SETENA SETENA SETENA SETENA Bits Description Interrupt Set Enable Bit The NVIC_ISER0-NVIC_ISER3 registers enable interrupts, and show which interrupts are enabled Write Operation: 0 = No effect.
  • Page 242 M451 IRQ0 ~ IRQ63 Clear-Enable Control Register (NVIC_ICER1) Register Offset Description Reset Value NVIC_ICER1 NVIC_BA+0x080 IRQ0 ~ IRQ63 Clear-Enable Control Register 0x0000_0000 CALENA CALENA CALENA CALENA Bits Description Interrupt Clear Enable Bit The NVIC_ICER0-NVIC_ICER3 registers disable interrupts, and show which interrupts are enabled.
  • Page 243 M451 IRQ0 ~ IRQ63 Clear-Enable Control Register (NVIC_ICER2) Register Offset Description Reset Value NVIC_ICER2 NVIC_BA+0x084 IRQ0 ~ IRQ63 Clear-Enable Control Register 0x0000_0000 CALENA CALENA CALENA CALENA Bits Description Interrupt Clear Enable Bit The NVIC_ICER0-NVIC_ICER3 registers disable interrupts, and show which interrupts are enabled.
  • Page 244 M451 IRQ0 ~ IRQ63 Set-Pending Control Register (NVIC_ISPR1) Register Offset Description Reset Value NVIC_ISPR1 NVIC_BA+0x100 IRQ0 ~ IRQ63 Set-Pending Control Register 0x0000_0000 SETPEND SETPEND SETPEND SETPEND Bits Description Interrupt Set-pending The NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state, and show which interrupts are pending Write Operation: 0 = No effect.
  • Page 245 M451 IRQ0 ~ IRQ63 Set-Pending Control Register (NVIC_ISPR2) Register Offset Description Reset Value NVIC_ISPR2 NVIC_BA+0x104 IRQ0 ~ IRQ63 Set-Pending Control Register 0x0000_0000 SETPEND SETPEND SETPEND SETPEND Bits Description Interrupt Set-pending The NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state, and show which interrupts are pending Write Operation: 0 = No effect.
  • Page 246 M451 IRQ0 ~ IRQ63 Clear-Pending Control Register (NVIC_ICPR1) Register Offset Description Reset Value NVIC_ICPR1 NVIC_BA+0x180 IRQ0 ~ IRQ63 Clear-Pending Control Register 0x0000_0000 CALPEND CALPEND CALPEND CALPEND Bits Description Interrupt Clear-pending The NVIC_ICPR0-NVIC_ICPR2 registers remove the pending state from interrupts, and show which interrupts are pending Write Operation: 0 = No effect.
  • Page 247 M451 IRQ0 ~ IRQ63 Clear-Pending Control Register (NVIC_ICPR2) Register Offset Description Reset Value NVIC_ICPR2 NVIC_BA+0x184 IRQ0 ~ IRQ63 Clear-Pending Control Register 0x0000_0000 CALPEND CALPEND CALPEND CALPEND Bits Description Interrupt Clear-pending The NVIC_ICPR0-NVIC_ICPR2 registers remove the pending state from interrupts, and show which interrupts are pending Write Operation: 0 = No effect.
  • Page 248 M451 IRQ0 ~ IRQ63 Active Bit Register (NVIC_IABR1) Register Offset Description Reset Value NVIC_IABR1 NVIC_BA+0x200 IRQ0 ~ IRQ63 Active Bit Register 0x0000_0000 ACTIVE ACTIVE ACTIVE ACTIVE Bits Description Interrupt Active Flags The NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active. [31:0] ACTIVE 0 = interrupt not active.
  • Page 249 M451 IRQ0 ~ IRQ63 Active Bit Register (NVIC_IABR2) Register Offset Description Reset Value NVIC_IABR2 NVIC_BA+0x204 IRQ0 ~ IRQ63 Active Bit Register 0x0000_0000 ACTIVE ACTIVE ACTIVE ACTIVE Bits Description Interrupt Active Flags The NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active. [31:0] ACTIVE 0 = interrupt not active.
  • Page 250 M451 IRQ0 ~ IRQ63 Interrupt Priority Register (NVIC_IPR1) Register Offset Description Reset Value NVIC_IPR1 NVIC_BA+0x300 R/W IRQ0 ~ IRQ63 Priority Control Register 0x0000_0000 PRI_4n_3 Reserved PRI_4n_2 Reserved PRI_4n_1 Reserved PRI_4n_0 Reserved Bits Description Priority of IRQ_4n+3 [31:28] PRI_4n_3 “0” denotes the highest priority and “15” denotes the lowest priority [27:24] Reserved Reserved.
  • Page 251 M451 IRQ0 ~ IRQ63 Interrupt Priority Register (NVIC_IPR2) Register Offset Description Reset Value NVIC_IPR2 NVIC_BA+0x33C R/W IRQ0 ~ IRQ63 Priority Control Register 0x0000_0000 PRI_4n_3 Reserved PRI_4n_2 Reserved PRI_4n_1 Reserved PRI_4n_0 Reserved Bits Description Priority of IRQ_4n+3 [31:28] PRI_4n_3 “0” denotes the highest priority and “15” denotes the lowest priority [27:24] Reserved Reserved.
  • Page 252 M451 Software Trigger Interrupt Register (STIR) Register Offset Description Reset Value STIR NVIC_BA+0xE00 Software Trigger Interrupt Registers 0x0000_0000 Reserved Reserved Reserved INTID INTID Bits Description [31:9] Reserved Reserved. Interrupt ID Write to the STIR To Generate An Interrupt from Software When the USERSETMPEND bit in the SCR is set to 1, unprivileged software can access [8:0] INTID...
  • Page 253 M451 6.2.10.4 NMI Control Registers R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value NMI Base Address: NMI_BA = 0x4000_0300 NMIEN NMI_BA+0x00 NMI Source Interrupt Enable Register 0x0000_0000 NMISTS NMI_BA+0x04 NMI source interrupt Status Register 0x0000_0000 May.
  • Page 254 M451 NMI Source Interrupt Enable Register (NMIEN) Register Offset Description Reset Value NMIEN NMI_BA+0x00 NMI Source Interrupt Enable Register 0x0000_0000 Reserved Reserved UART1_INT UART0_INT EINT5 EINT4 EINT3 EINT2 EINT1 EINT0 TAMPER_INT RTC_INT Reserved CLKFAIL SRAM_PERR PWRWU_INT IRC_INT BODOUT Bits Description [31:16] Reserved Reserved.
  • Page 255 M451 0 = External interrupt from PB.0, PD.3 or PE.5 pin NMI source Disabled. 1 = External interrupt from PB.0, PD.3 or PE.5 pin NMI source Enabled. Note: This bit is write protected. Refer to the SYS_REGLCTL register. External Interrupt From PA.0, PD.2 or PE.4 Pin NMI Source Enable (Write Protect) 0 = External interrupt from PA.0, PD.2 or PE.4 pin NMI source Disabled.
  • Page 256 M451 NMI Source Interrupt Status Register (NMISTS) Register Offset Description Reset Value NMISTS NMI_BA+0x04 NMI source interrupt Status Register 0x0000_0000 Reserved Reserved UART1_INT UART0_INT EINT5 EINT4 EINT3 EINT2 EINT1 EINT0 TAMPER_INT RTC_INT Reserved CLKFAIL SRAM_PERR PWRWU_INT IRC_INT BODOUT Bits Description [31:16] Reserved Reserved.
  • Page 257 M451 TAMPER_INT Interrupt Flag (Read Only) TAMPER_INT 0 = Backup register tamper detected interrupt is deasserted. 1 = Backup register tamper detected interrupt is asserted. RTC Interrupt Flag (Read Only) RTC_INT 0 = RTC interrupt is deasserted. 1 = RTC interrupt is asserted. Reserved Reserved.

  • Page 258: System Control Register

    M451 6.2.11 System Control Register ® The Cortex -M4 status and operation mode control are managed by System Control Registers. ® ® Including CPUID, Cortex -M4 interrupt priority and Cortex -M0 power management can be controlled through these system control registers. ®...
  • Page 259 M451 Interrupt Control State Register (ICSR) Register Offset Description Reset Value ICSR SCS_BA+0xD04 Interrupt Control and State Register 0x0000_0000 NMIPENDSET Reserved PENDSVSET PENDSVRTC_CAL PENDSTSET PENDSTRTC_CAL Reserved ISRPREEMPT ISRPENDING Reserved VECTPENDING VECTPENDING Reserved Reserved VECTACTIVE Bits Description NMI Set-pending Bit Write Operation: 0 = No effect.
  • Page 260 M451 SysTick Exception Set-pending Bit Write Operation: 0 = No effect. [26] PENDSTSET 1 = Changes SysTick exception state to pending. Read Operation: 0 = SysTick exception is not pending. 1 = SysTick exception is pending. SysTick Exception Clear-pending Bit Write Operation: PENDSTRTC_CA 0 = No effect.
  • Page 261 M451 Application Interrupt and Reset Control Register (AIRCR) Register Offset Description Reset Value AIRCR SCS_BA+0xD0C Application Interrupt and Reset Control Register 0xFA05_0000 VECTORKEY VECTORKEY ENDIANNESS Reserved PRIGROUP Reserved SYSRESETREQ VECTCLRACTIVE VECTRESET Bits Description Register Access Key When writing this register, this field should be 0x05FA, otherwise the write action will be [31:16] VECTORKEY unpredictable.

  • Page 262: Table 6-8 Priority Grouping

    M451 Group Number Of Group PRIGROUP Binary Point Subpriority Bits Subpriorities Priorities Priority Bits 0b000 bxxxxxxx.y [7:1] 0b001 bxxxxxx.yy [7:2] [1:0] 0b010 bxxxxx.yyy [7:3] [2:0] 0b011 bxxxx.yyyy [7:4] [3;0] 0b100 bxxx.yyyyy [7:5] [4:0] 0b101 bxx.yyyyyy [7:6] [5:0] 0b110 bx.yyyyyyy [6:0] 0b111 b.yyyyyyyy None...
  • Page 263 M451 System Control Register (SCR) Register Offset Description Reset Value SCS_BA+0xD10 System Control Register 0x0000_0000 Reserved Reserved Reserved Reserved SEVONPEND Reserved SLEEPDEEP SLEEPONEXIT Reserved Bits Description Reserved [31:5] Reserved. Send Event on Pending 0 = Only enabled interrupts or events can wake up the processor, while disabled interrupts are excluded.
  • Page 264 M451 System Handler Priority Register 1 (SHPR1) Register Offset Description Reset Value SHPR1 SCS_BA+0xD18 R/W System Handler Priority Register 1 0x0000_0000 Reserved PRI_6 PRI_5 PRI_4 Bits Description [31:24] Reserved Reserved. [23:16] PRI_6 Priority of system handler 6, UsageFault [15:8] PRI_5 Priority of system handler 5, BusFault [7:0] PRI_4...
  • Page 265 M451 System Handler Priority Register 2 (SHPR2) Register Offset Description Reset Value SHPR2 SCS_BA+0xD1C System Handler Priority Register 2 0x0000_0000 PRI_11 Reserved Reserved Reserved Reserved Bits Description Priority of System Handler 11 – SVCall [31:30] PRI_11 “0” denotes the highest priority and “3” denotes the lowest priority. [29:0] Reserved Reserved.
  • Page 266 M451 System Handler Priority Register 3 (SHPR3) Register Offset Description Reset Value SHPR3 SCS_BA+0xD20 System Handler Priority Register 3 0x0000_0000 PRI_15 Reserved PRI_14 Reserved Reserved Reserved Bits Description Priority of System Handler 15 – SysTick [31:30] PRI_15 “0” denotes the highest priority and “3” denotes the lowest priority. [29:24] Reserved Reserved.

  • Page 267: Clock Controller

    M451 Clock Controller 6.3.1 Overview The clock controller generates clocks for the whole chip, including system clocks and all peripheral clocks. The clock controller also implements the power control function with the individually clock ON/OFF control, clock source selection and a clock divider. The chip will not enter Power-down mode until CPU sets the Power-down enable bit PDEN(CLK_PWRCTL[7]) and ®...

  • Page 268: Figure 6.3-1 Clock Generator Global View Diagram

    M451 CPUCLK 22.1184 22.1184 MHz 4~24 10 kHz 1/(HCLKDIV+1) HCLK PDMA PLLFOUT I2C0 32.768 kHz 32.768 PCLK0 PCLK0 CAN0 4~24 MHz PCLK1 PCLK1 I2C1 10 kHz CLK_CLKSEL0[2:0] ACMP01 22.1184 MHz 22.1184 MHz 10 kHz PLL FOUT 4~24 MHz TMR 0 T0~T1 TMR 1 CLK_PLLCTL[19]...

  • Page 269: Clock Generator

    M451 6.3.2 Clock Generator The clock generator consists of 5 clock sources, which are listed below:  32.768 kHz external low speed crystal oscillator (LXT)  4~20 MHz external high speed crystal oscillator (HXT)  Programmable PLL output clock frequency (PLLFOUT), PLL source can be selected from external 4~20 MHz external high speed crystal (HXT) or 22.1184 MHz internal high speed oscillator (HIRC) ...

  • Page 270: System Clock And Systick Clock

    M451 6.3.3 System Clock and SysTick Clock The system clock has 5 clock sources, which were generated from clock generator block. The clock source switch depends on the register HCLKSEL (CLK_CLKSEL0[2:0]). The block diagram is shown in the Figure 6.3-3. HCLKSEL (CLK_CLKSEL0[2:0]) HIRC...

  • Page 271: Peripherals Clock

    M451 Set HXTFDEN To enable HXT clock detector HXTFIF = 1? System clock source = System clock keep “HXT” or “PLL with original clock HXT” ? Switch system clock to HIRC Figure 6.3-4 HXT Stop Protect Procedure ® The clock source of SysTick in Cortex -M4 core can use CPU clock or external clock (SYST_CTRL[2]).

  • Page 272: Power-Down Mode Clock

    M451 6.3.5 Power-down Mode Clock When entering Power-down mode, system clocks, some clock sources and some peripheral clocks are disabled. Some clock sources and peripherals clock are still active in Power-down mode. For theses clocks, which still keep active, are listed below: ...

  • Page 273: Figure 6.3-7 Clock Output Block Diagram

    M451 CLKOEN (CLK_CLKOCTL[4]) Enable FREQSEL divide-by-2 counter 16 chained (CLK_CLKOCTL[3:0]) divide-by-2 counter CLKO_CLK DIV1EN …... (CLK_CLKOCTL[5]) CLK1HZEN 0000 (CLK_CLKOCTL[6]) 0001 16 to 1 1110 CLKO 1111 RTCSEL(CLK_CLKSEL3[8]) LIRC 1 Hz clock from RTC /32768 Figure 6.3-7 Clock Output Block Diagram May.

  • Page 274: Register Map

    M451 6.3.7 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value CLK Base Address: CLK_BA = 0x4000_0200 CLK_PWRCTL CLK_BA+0x00 System Power-down Control Register 0x0000_001X CLK_AHBCLK CLK_BA+0x04 AHB Devices Clock Enable Control Register 0x0000_8004 CLK_APBCLK0 CLK_BA+0x08 APB Devices Clock Enable Control Register 0...

  • Page 275: Register Description

    M451 6.3.8 Register Description System Power-down Control Register (CLK_PWRCTL) Register Offset Description Reset Value CLK_PWRCT CLK_BA+0x00 System Power-down Control Register 0x0000_001X Reserved Reserved Reserved HXTGAIN Reserved PDWTCPU PDEN PDWKIF PDWKIEN PDWKDLY LIRCEN HIRCEN LXTEN HXTEN Bits Description [31:12] Reserved Reserved. HXT Gain Control Bit (Write Protect) This is a protected register.
  • Page 276 M451 source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC. 0 = Chip operating normally or chip in idle mode because of WFI command. 1 = Chip enters Power-down mode instant or wait CPU sleep command WFI. Note: This bit is write protected.

  • Page 277: Table 6-9 Power-Down Mode Control Table

    M451 [7]) [8]) Normal operation All clocks are controlled by control register. Idle mode Only CPU clock is disabled. (CPU enter Sleep mode) Power-down mode Most clocks are disabled except LIRC/LXT, and only (CPU enters Deep RTC/WDT/Timer peripheral Sleep mode) clocks still enable if their clock sources are selected as LIRC/LXT.
  • Page 278 M451 AHB Devices Clock Enable Control Register (CLK_AHBCLK) The bits in this register are used to enable/disable clock for system clock, AHB bus devices clock. Register Offset Description Reset Value CLK_AHBCL CLK_BA+0x04 AHB Devices Clock Enable Control Register 0x0000_8004 Reserved Reserved FMCIDLE Reserved...
  • Page 279 M451 APB Devices Clock Enable Control Register (CLK_APBCLK0) The bits in this register are used to enable/disable clock for peripheral controller clocks. Register Offset Description Reset Value CLK_APBCL CLK_BA+0x08 APB Devices Clock Enable Control Register 0 0x0000_0001 Reserved EADCCKEN USBDCKEN OTGCKEN Reserved CAN0CKEN...
  • Page 280 M451 1 = UART1 clock Enabled. UART0 Clock Enable Bit [16] UART0CKEN 0 = UART0 clock Disabled. 1 = UART0 clock Enabled. Reserved [15] Reserved. SPI2 Clock Enable Bit (M45xG/M45xE Only) [14] SPI2CKEN 0 = SPI2 clock Disabled. 1 = SPI2 clock Enabled. SPI1 Clock Enable Bit SPI1CKEN 0 = SPI1 clock Disabled.
  • Page 281 M451 1 = RTC APB clock Enabled. Watchdog Timer Clock Enable Bit (Write Protect) 0 = Watchdog timer clock Disabled. WDTCKEN 1 = Watchdog timer clock Enabled. Note: This bit is write protected. Refer to the SYS_REGLCTL register. May. 4, 2018 Page 281 of 1006 Rev.2.08...
  • Page 282 M451 APB Devices Clock Enable Control Register 1 (CLK_APBCLK1) The bits in this register are used to enable/disable clock for peripheral controller clocks. Register Offset Description Reset Value CLK_APBCL CLK_BA+0x0C APB Devices Clock Enable Control Register 1 0x0000_0000 Reserved Reserved PWM1CKEN PWM0CKEN Reserved...
  • Page 283 M451 Clock Source Select Control Register 0 (CLK_CLKSEL0) Register Offset Description Reset Value CLK_CLKSEL CLK_BA+0x10 Clock Source Select Control Register 0 0x0000_003X Reserved Reserved Reserved PCLK1SEL PCLK0SEL STCLKSEL HCLKSEL Bits Description [31:8] Reserved Reserved. PCLK1 Clock Source Selection (Write Protect) 0 = APB1 bus clock source from HCLK.
  • Page 284 M451 011 = Clock source from LIRC. 111= Clock source from HIRC. Other = Reserved. Note: This bit is write protected. Refer to the SYS_REGLCTL register. May. 4, 2018 Page 284 of 1006 Rev.2.08...
  • Page 285 M451 Clock Source Select Control Register 1 (CLK_CLKSEL1) Before clock switching, the related clock sources (pre-selected and newly-selected) must be turned Register Offset Description Reset Value CLK_CLKSEL CLK_BA+0x14 Clock Source Select Control Register 1 0xB377_770F WWDTSEL CLKOSEL Reserved UARTSEL Reserved TMR3SEL Reserved TMR2SEL...
  • Page 286 M451 [19] Reserved Reserved. TIMER2 Clock Source Selection 000 = Clock source from 4~20 MHz external high speed crystal oscillator (HXT). 001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 010 = Clock source from PCLK1. [18:16] TMR2SEL 011 = Clock source from external clock T2 pin.
  • Page 287 M451 Clock Source Select Control Register 2 (CLK_CLKSEL2) Before clock switching, the related clock sources (pre-select and new-select) must be turned on. Register Offset Description Reset Value CLK_CLKSEL CLK_BA+0x18 Clock Source Select Control Register 2 0x0000_00AB Reserved Reserved Reserved SPI2SEL SPI1SEL SPI0SEL PWM1SEL...
  • Page 288 M451 Clock Source Select Control Register 3 (CLK_CLKSEL3) Before clock switching, the related clock sources (pre-select and new-select) must be turned on. Register Offset Description Reset Value CLK_CLKSEL CLK_BA+0x1C Clock Source Select Control Register 3 0x0000_0003 Reserved Reserved Reserved RTCSEL Reserved SC0SEL Bits...
  • Page 289 M451 Clock Divider Number Register 0 (CLK_CLKDIV0) Register Offset Description Reset Value CLK_CLKDIV0 CLK_BA+0x20 Clock Divider Number Register 0 0x0000_0000 Reserved EADCDIV Reserved UARTDIV USBDIV HCLKDIV Bits Description [31:24] Reserved Reserved. EADC Clock Divide Number From EADC Clock Source EADCDIV [23:16] EADC clock frequency = (EADC clock source frequency) / (EADCDIV + 1).
  • Page 290 M451 Clock Divider Number Register 1 (CLK_CLKDIV1) Register Offset Description Reset Value CLK_CLKDIV CLK_BA+0x24 Clock Divider Number Register 1 0x0000_0000 Reserved Reserved Reserved SC0DIV Bits Description [31:8] Reserved Reserved. SC0 Clock Divide Number From SC0 Clock Source SC0DIV [7:0] SC0 clock frequency = (SC0 clock source frequency ) / (SC0DIV + 1). May.
  • Page 291 M451 PLL Control Register (CLK_PLLCTL) The PLL reference clock input is from the 4~20 MHz external high speed crystal oscillator (HXT) clock input or from the 22.1184 MHz internal high speed RC oscillator (HIRC). This register is used to control the PLL output frequency and PLL operation mode. Programming these bits needs to write “59h”, “16h”, “88h”...
  • Page 292 M451 too. 0 = PLL is in normal mode. 1 = PLL is in Power-down mode (default). Note: This bit is write protected. Refer to the SYS_REGLCTL register. PLL Output Divider Control (Write Protect) [15:14] OUTDIV Refer to the formulas below the table. Note: This bit is write protected.
  • Page 293 M451 Clock Status Monitor Register (CLK_STATUS) The bits in this register are used to monitor if the chip clock source is stable or not, and whether the clock switch is failed. Register Offset Description Reset Value CLK_STATUS CLK_BA+0x50 R Clock Status Monitor Register 0x0000_00XX Reserved Reserved...
  • Page 294 M451 Clock Output Control Register (CLK_CLKOCTL) Register Offset Description Reset Value CLK_CLKOC CLK_BA+0x60 Clock Output Control Register 0x0000_0000 Reserved Reserved Reserved Reserved CLK1HZEN DIV1EN CLKOEN FREQSEL Bits Description [31:7] Reserved Reserved. Clock Output 1Hz Enable Bit CLK1HZEN 0 = 1 Hz clock output for 32.768 kHz frequency compensation Disabled. 1 = 1 Hz clock output for 32.768 kHz frequency compensation Enabled.
  • Page 295 M451 Clock Fail Detector Control Register (CLK_CLKDCTL) Register Offset Description Reset Value CLK_CLKDCT CLK_BA+0x70 Clock Fail Detector Control Register 0x0000_0000 Reserved Reserved HXTFQIEN HXTFQDEN Reserved LXTFIEN LXTFDEN Reserved Reserved HXTFIEN HXTFDEN Reserved Bits Description [31:18] Reserved Reserved. HXT Clock Frequency Monitor Interrupt Enable Bit 0 = 4~20 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail [17] HXTFQIEN...
  • Page 296 M451 Clock Fail Detector Status Register (CLK_CLKDSTS) Register Offset Description Reset Value CLK_CLKDST CLK_BA+0x74 Clock Fail Detector Status Register 0x0000_0000 Reserved Reserved Reserved HXTFQIF Reserved LXTFIF HXTFIF Bits Description [31:9] Reserved Reserved. HXT Clock Frequency Monitor Interrupt Flag 0 = 4~20 MHz external high speed crystal oscillator (HXT) clock is normal. HXTFQIF 1 = 4~20 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal.
  • Page 297 M451 Clock Frequency Detector Upper Boundary Register (CLK_CDUPB) Register Offset Description Reset Value CLK_CDUPB CLK_BA+0x78 Clock Frequency Detector Upper Boundary Register 0x0000_0000 Reserved Reserved Reserved UPERBD UPERBD Bits Description [31:10] Reserved Reserved. HXT Clock Frequency Detector Upper Boundary The bits define the high value of frequency monitor window. [9:0] UPERBD When HXT frequency monitor value higher than this register, the HXT frequency detect fail...
  • Page 298 M451 Clock Frequency Detector Lower Boundary Register (CLK_CDLOWB) Register Offset Description Reset Value CLK_CDLOWB CLK_BA+0x7c Clock Frequency Detector Lower Boundary Register 0x0000_0000 Reserved Reserved Reserved LOWERBD LOWERBD Bits Description [31:10] Reserved Reserved. HXT Clock Frequency Detector Lower Boundary The bits define the low value of frequency monitor window. [9:0] LOWERBD When HXT frequency monitor value lower than this register, the HXT frequency detect fail...

  • Page 299: Flash Memeory Controller (Fmc)

    M451 Flash Memeory Controller (FMC) 6.4.1 Overview ® The NuMicro M451 series is equipped with 40/72/128/256 KB on-chip embedded flash for application and configurable Data Flash to store some application dependent data. A User Configuration block provides for system initiation. A 4 KB loader ROM (LDROM) is used for In- System-Programming (ISP) function.

  • Page 300: Block Diagram

    M451 6.4.3 Block Diagram The flash memory controller (FMC) consists of AHB slave interface, cache memory controller, flash control registers, flash initialization controller, flash operation control and embedded flash memory. The block diagram of flash memory controller is shown as follows. Cortex-M4 S-BUS Cortex-M4 I-BUS / D-BUS Flash Memory Controller...
  • Page 301 M451 May. 4, 2018 Page 301 of 1006 Rev.2.08...
  • Page 302 M451 AHB Slave Interface ® There are two AHB slave interfaces in flash memory controller, one is from both Cortex -M4 I- ® Bus and D-Bus for the instruction and data fetch; the other is from Cortex -M4 S-Bus for flash control registers access including ISP registers.

  • Page 303: Functional Description

    M451 6.4.4 Functional Description FMC functions include the memory organization, boot selection, IAP, ISP, the embedded flash programming, and checksum calculation. The flash memory map and system memory map are also introduced in the memory organization. 6.4.4.1 Memory Organization The FMC memory consists of the embedded flash memory. The embedded flash memory is programmable, and includes APROM, LDROM, Data Flash and the User Configuration block.
  • Page 304 M451 User Configuration Block User Configuration block is internal programmable configuration area for boot options, such as flash security lock, boot select, brown-out voltage level, and Data Flash base address. It works like a fuse for power on setting. It is loaded from flash memory to its corresponding control registers during chip power on.
  • Page 305 M451 CONFIG0 (Address = 0x0030_0000) CWDTEN[2] CWDTPDEN Reserved CFGXT1 CFOSC Reserved CBODEN CBOV CBORST Reserved Reserved CIOINI Reserved Reserved CWDTEN[1:0] Reserved LOCK DFEN Bits Descriptions Watchdog Timer Hardware Enable Bit When watchdog timer hardware enable function is enabled, the watchdog enable bit WDTEN (WDT_CTL[7]) and watchdog reset enable bit RSTEN (WDT_CTL[1]) is set to 1 automatically after power on.
  • Page 306 M451 Brown-Out Voltage Selection 00 = Brown-out voltage is 2.2V. [22:21] CBOV 01 = Brown-out voltage is 2.7V. 10 = Brown-out voltage is 3.7V. 11 = Brown-out voltage is 4.5V. Brown-Out Reset Enable Bit [20] CBORST 0 = Brown-out reset Enabled after powered on. 1 = Brown-out reset Disabled after powered on.
  • Page 307 M451 CONFIG1 (Address = 0x0030_0004) Reserved Reserved DFBA DFBA DFBA Bits Descriptions [31:20] Reserved Reserved. Data Flash Base Address This register works only when DFEN (CONFIG0[0])set to 0. If DFEN (CONFIG0[0]) is set [19:0] DFBA to 0, the Data Flash base address is defined by user. Since on-chip flash erase unit is 2 KB, it is mandatory to keep bit 10-0 as 0.

  • Page 308: Figure 6.4-3 Flash Memory Map

    M451 Flash Memory Map ® In the NuMicro M451 series, the flash memory map is different from system memory map. The system memory map is used by CPU fetch code or data from FMC memory. The flash memory map is used for ISP function to read, program or erase FMC memory. Figure 6.4-3 shows the flash memory map.

  • Page 309: Figure 6.4-4 System Memory Map With Iap Mode

    M451 System Memory Map with IAP mode The system memory map is used by CPU to fetch code or data from FMC memory. The Data Flash is shared with APROM and the Data Flash base address is defined by CONFIG1. The content of CONFIG1 is loaded into DFBA (Data Flash Base Address Register) at the flash ®...

  • Page 310: Figure 6.4-5 Ldrom With Iap Mode

    M451 ApplicationROM (APROM) 0x0000_0200 0x0010_01FF 0x0000_01FF System Memory Vector LDROM (512B) 0x0010_0000 0x0000_0000 Figure 6.4-5 LDROM with IAP Mode In APROM with IAP mode, the APROM (0x0000_0000~0x0000_01FF) is mapping to the system ® memory vector for Cortex -M4 instruction or data access. ApplicationROM (APROM) 0x0000_0200...

  • Page 311: Figure 6.4-7 System Memory Map Without Iap Mode

    M451 System Memory Map without IAP mode There are two kinds of system memory map without IAP mode when chip booting: (1) LDROM without IAP and (2) APROM without IAP. In LDROM without IAP mode, LDROM base is mapping to 0x0000_0000. CPU program cannot run to access APROM. In APROM without IAP mode, APROM base is mapping to 0x0000_0000.

  • Page 312: Figure 6.4-8 Boot Source Selection

    M451 6.4.4.2 Boot Selection ® The NuMicro M451 provides four booting sources for user to select, including LDROM with IAP, LDROM without IAP, APROM with IAP and APROM without IAP. The booting source and system memory map are setting by CBS (CONFIG0[7:6]). LDROM with IAP LDROM with IAP Boot Source...
  • Page 313 M451  Supports flash data read function  Supports company ID read function  Supports device ID read function  Supports unique ID read function  Supports memory checksum calculation function  Supports system memory vector remap function ISP CMDs FMC_ISPDAT ISP CMD FMC_ISPCMD FMC_ISPADDR...

  • Page 314: Table 6-10 Isp Command List

    M451 It must be 2 KB page alignment It must be 2 KB alignment FMC_MPDAT0~FMC_MPDAT3 : FMC_ISPDAT: Unique ID Word 0 0x0000_0000 FMC_MPDAT0~FMC_MPDAT3 : FMC_ISPDAT: Unique ID Word 1 Read Unique ID 0x04 0x0000_0004 FMC_MPDAT0~FMC_MPDAT3 : FMC_ISPDAT: Unique ID Word 2 0x0000_0008 FMC_MPDAT0~FMC_MPDAT3 : Valid address in APROM or LDROM...

  • Page 315: Figure 6.4-9 Isp Procedure Example

    M451 Start Enable ISPEN Write FMC_ISPADDR End of Flash Write FMC_ISPCMD Operation (Write FMC_ISPDAT ) (Read FMC_ISPDAT) Set ISPGO = 1 & Check ISPFF = 1? Add ISB instruction End of ISP Operation Check ISPGO = 0 Stop Figure 6.4-9 ISP Procedure Example Finally, set the ISPGO (FMC_ISPTRG[0]) register to perform the relative ISP function.
  • Page 316 M451    FMC_ISPCTL ISP Control Register    FMC_ISPADDR ISP Address Register  FMC_ISPDAT ISP Data Register FMC_ISPCMD ISP CMD Register 0x21 0x61 0x27    FMC_ISPTRG ISP Trigger Register   FMC_ISPSTS ISP Status Register ...

  • Page 317: Figure 6.4-10 Isp 32-Bit Programming Procedure

    M451 Start Enable ISPEN Write FMC_ISPADDR Write FMC_ISPCMD End of Flash Operation Write FMC_ISPDAT Set ISPGO = 1 Check ISPFF = 1? Add ISB instruction End of ISP Operation Check ISPGO = 0 Stop Figure 6.4-10 ISP 32-bit Programming Procedure Start Enable ISPEN Write FMC_ISPADDR...

  • Page 318: Figure 6.4-12 Multi-Word Programming Time

    M451 Multi-word Programming ® The NuMicro M451 supports multi-word programming function to speed up flash updated procedure. The maximum programming length is up to 256 bytes, and the minimum programming length is 8 bytes (2 words). The multi-word programming is the fastest programming function if the programming words more than 8 bytes, because only one set of flash setup time and hold time needed for one time operation.

  • Page 319: Figure 6.4-13 Firmware In Sram For Multi-Word Programming

    M451 Cortex-M4 CPU Embedded SRAM Flash Memory Controller AHB Slave Interface Flash Control Registers Flash Operation Control Embedded Flash Memory (APROM) (LDROM) (Data Flash) Figure 6.4-13 Firmware in SRAM for Multi-word Programming The multi-word programming flow is shown below. The starting ISP address (FMC_ISPADDR) has to be 8-byte align, FMC_ISPADDR[2:0] should be 0.

  • Page 320: Figure 6.4-14 Multi-Word Programming Flow

    M451 Start Enable ISPEN Write FMC_ISPADDR Write FMC_MPDAT0 Write FMC_MPDAT1 Write FMC_MPDAT2 Write FMC_MPDAT3 Set ISPGO = 1 Programming Finish? Read FMC_MPSTS Read FMC_MPSTS Read FMC_MPADDR Check MPBUSY==0? (D1,D0)=00? MPBUSY == 0? Write FMC_MPDAT0 Write FMC_MPDAT1 End of ISP Operation? Read FMC_MPSTS Multi-Word Programming...

  • Page 321: Figure 6.4-15 Fast Flash Programming Verification Flow

    M451 6.4.4.6 Fast Flash Programming Verification In traditional flash programming operation, the controller receives the programming trigger event then control the timing to perform the programming embedded flash memory. as show in Figure 6.4-17. ® The NuMicro M451 supports the fast flash programming verification function, which provides hardware verification for flash programming to save time of the CPU read back and comparison.

  • Page 322: Figure 6.4-16 Verification Flow

    M451 Traditional (2) Flash PROGRAM (3) Flash READ back to check Programming and (1) Flash ERASE (All data) (All data) Verification Flow M451 (2) Flash PROGRAM (3) Read PGFF Flag to check Fast Programming (1) Flash ERASE (All data) (FMC_ISPSTS) Verification Flow Figure 6.4-16 Verification Flow The fast flash programming verification function is released for 32-bit programming and 64-bit...
  • Page 323 M451 Three steps complete this checksum calculation. Step 1: perform ISP “Run Memory Checksum” operation Step 2: perform ISP “Read Memory Checksum” operation Step 3: read FMC_ISPDAT to get checksum. In step 1, user has to set the memory starting address (FMC_ISPADDR) and size (FMC_ISPDAT) to calculate.

  • Page 324: Figure 6.4-18 Checksum Calculation Flow

    M451 Figure 6.4-18 Checksum Calculation Flow May. 4, 2018 Page 324 of 1006 Rev.2.08...

  • Page 325: Register Map

    M451 6.4.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value FMC Base Address FMC_BA = 0x4000_C000 FMC_ISPCTL FMC_BA+0x00 ISP Control Register 0x0000_0000 FMC_ISPADDR FMC_BA+0x04 ISP Address Register 0x0000_0000 FMC_ISPDAT FMC_BA+0x08 ISP Data Register 0x0000_0000 FMC_ISPCMD...

  • Page 326: Register Description

    M451 6.4.6 Register Description ISP Control Register (FMC_ISPCTL) Register Offset Description Reset Value FMC_ISPCTL FMC_BA+0x00 ISP Control Register 0x0000_0000 Reserved Reserved Reserved Reserved ISPFF LDUEN CFGUEN APUEN Reserved ISPEN Bits Description [31:7] Reserved Reserved. ISP Fail Flag (Write Protect) This bit is set by hardware when a triggered ISP meets any of the following conditions: This bit needs to be cleared by writing 1 to it.
  • Page 327 M451 Reserved Reserved. Boot Select (Write Protect) Set/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened 0 = Booting from APROM.
  • Page 328 M451 ISP Address (FMC_ISPADDR) Register Offset Description Reset Value FMC_ISPADDR FMC_BA+0x04 ISP Address Register 0x0000_0000 ISPADDR ISPADDR ISPADDR ISPADDR Bits Description ISP Address ® The NuMicro M451 series is equipped with embedded flash. ISPADDR[1:0] must be kept [31:0] ISPADDR 00 for ISP 32-bit operation. ISPADDR[2:0] must be kept 000 for ISP 64-bit operation. For Checksum Calculation command, this field is the flash starting address for checksum calculation, 2 KB alignment is necessary for checksum calculation.
  • Page 329 M451 ISP Data Register (FMC_ISPDAT) Register Offset Description Reset Value FMC_ISPDAT FMC_BA+0x08 ISP Data Register 0x0000_0000 ISPDAT ISPDAT ISPDAT ISPDAT Bits Description ISP Data Write data to this register before ISP program operation. Read data from this register after ISP read operation. [31:0] ISPDAT For Run Checksum Calculation command, ISPDAT is the memory size (byte) and 2 KB...
  • Page 330 M451 ISP CMD (FMC_ISPCMD) Register Offset Description Reset Value FMC_ISPCMD FMC_BA+0x0C ISP CMD Register 0x0000_0000 Reserved Reserved Reserved Reserved Bits Description [31:7] Reserved Reserved. ISP CMD ISP command table is shown below: 0x00= FLASH 32-bit Read. 0x40= FLASH 64-bit Read. 0x04= Read Unique ID.
  • Page 331 M451 ISP Trigger Control Register (FMC_ISPTRG) Register Offset Description Reset Value FMC_ISPTRG FMC_BA+0x10 ISP Trigger Control Register 0x0000_0000 Reserved Reserved Reserved Reserved ISPGO Bits Description [31:1] Reserved Reserved. ISP Start Trigger (Write Protect) Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
  • Page 332 M451 Data Flash Base Address Register (FMC_DFBA) Register Offset Description Reset Value FMC_DFBA FMC_BA+0x14 Data Flash Base Address 0xXXXX_XXXX DFBA DFBA DFBA DFBA Bits Description Data Flash Base Address This register indicates Data Flash start address. It is a read only register. [31:0] DFBA The Data Flash is shared with APROM.
  • Page 333 M451 Flash Access Time Control Register (FMC_FTCTL) Register Offset Description Reset Value FMC_FTCTL FMC_BA+0x18 Flash Access Time Control Register 0x0000_0000 Reserved Reserved Reserved Reserved Reserved Bits Description [31:7] Reserved Reserved. Frequency Optimization Mode (Write Protect) ® The NuMicro M451 series support adjustable flash access timing to optimize the flash access cycles in different working frequency.
  • Page 334 M451 ISP Status Register (FMC_ISPSTS) Register Offset Description Reset Value FMC_ISPSTS FMC_BA+0x40 ISP Status Register 0x0000_0000 Reserved VECMAP VECMAP Reserved Reserved ISPFF PGFF Reserved ISPBUSY Bits Description [31:24] Reserved Reserved. Vector Page Mapping Address (Read Only) [23:9] VECMAP All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[14:0], 9’h000} ~ {VECMAP[14:0], 9’h1FF} [8:7] Reserved...
  • Page 335 M451 Boot Selection of CONFIG (Read Only) This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened. 00 = LDROM with IAP mode. [2:1] 01 = LDROM without IAP mode. 10 = APROM with IAP mode.
  • Page 336 M451 ISP Data 0 Register (FMC_MPDAT0) Register Offset Description Reset Value FMC_MPDAT0 FMC_BA+0x80 ISP Data0 Register 0x0000_0000 ISPDAT0 ISPDAT0 ISPDAT0 ISPDAT0 Bits Description ISP Data 0 ISPDAT0 [31:0] This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data.
  • Page 337 M451 ISP Data 1 Register (FMC_MPDAT1) Register Offset Description Reset Value FMC_MPDAT1 FMC_BA+0x84 ISP Data1 Register 0x0000_0000 ISPDAT1 ISPDAT1 ISPDAT1 ISPDAT1 Bits Description ISP Data 1 [31:0] ISPDAT1 This register is the second 32-bit data for 64-bit/multi-word programming. May. 4, 2018 Page 337 of 1006 Rev.2.08...
  • Page 338 M451 ISP Data 2 Register (FMC_MPDAT2) Register Offset Description Reset Value FMC_MPDAT2 FMC_BA+0x88 ISP Data2 Register 0x0000_0000 ISPDAT2 ISPDAT2 ISPDAT2 ISPDAT2 Bits Description ISP Data 2 [31:0] ISPDAT2 This register is the third 32-bit data for multi-word programming. May. 4, 2018 Page 338 of 1006 Rev.2.08...
  • Page 339 M451 ISP Data 3 Register (FMC_MPDAT3) Register Offset Description Reset Value FMC_MPDAT3 FMC_BA+0x8C ISP Data3 Register 0x0000_0000 ISPDAT3 ISPDAT3 ISPDAT3 ISPDAT3 Bits Description ISP Data 3 [31:0] ISPDAT3 This register is the fourth 32-bit data for multi-word programming. May. 4, 2018 Page 339 of 1006 Rev.2.08...
  • Page 340 M451 ISP Multi-Program Status Register (FMC_MPSTS) Register Offset Description Reset Value FMC_MPSTS FMC_BA+0xC0 ISP Multi-Program Status Register 0x0000_0000 Reserved Reserved Reserved Reserved ISPFF PPGO MPBUSY Bits Description [31:8] Reserved Reserved. ISP DATA 3 Flag (Read Only) This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete.
  • Page 341 M451 ISP Fail Flag (Read Only) This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions: (1) APROM writes to itself if APUEN is set to 0.
  • Page 342 M451 ISP Multi-Word Program Address Register (FMC_MPADDR) Register Offset Description Reset Value FMC_MPADDR FMC_BA+0xC4 ISP Multi-Program Address Register 0x0000_0000 MPADDR MPADDR MPADDR MPADDR Bits Description ISP Multi-word Program Address MPADDR [31:0] MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1. MPADDR will keep the final ISP address when ISP multi-word program is complete.

  • Page 343: External Bus Interface (Ebi)

    M451 External Bus Interface (EBI) 6.5.1 Overview ® The NuMicro M451 is equipped with an external bus interface (EBI) for external device used. To ® save the connections between external device and the NuMicro M451, EBI operating at address bus and data bus multiplex mode. The EBI supports two chip selects that can connect two external devices with different timing setting requirement.

  • Page 344: Block Diagram

    M451 6.5.3 Block Diagram HCLK EBI_MCLK MCLK MCLKDIV Divider Idle Cycle Timing Controller RAHDOFF EBI_ADR[19:16] WAHDOFF TACC EBI State EBI_AD[15:0] TAHD Machine EBI Signal TALE Timing EBI_nCS Controller Register Controller EBI_nRD Output DW16 Controller EBI_nWR EBI_ALE EBI request WBUFEN Address Hit Request Controller Figure 6.5-1 EBI Block Diagram...

  • Page 345: Figure 6.5-2 Connection Of 16-Bit Ebi Data Width With 16-Bit Device

    M451 mapped external device (for Bank0/EBI_nCS0) to 0x6000_0000 ~ 0x6003_FFFF, 0x6004_0000 ~ 0x6007_FFFF, 0x6008_0000 ~ 0x600B_FFFF and 0x600C_0000 ~ 0x600F_FFFF simultaneously. 6.5.5.2 EBI Data Width Connection - Address Bus and Data Bus Multiplex Mode The EBI supports device whose address bus and data bus are multiplexed. For the external device with separated address and data bus, the connection to device needs additional latch device to latch the address.

  • Page 346: Figure 6.5-3 Connection Of 8-Bit Ebi Data Width With 8-Bit Device

    M451 1M x 8-bit External Bus Interface SRAM EBI_ADR[19:16] Addr[19:16] EBI_AD[15:8] Addr[15:8] Address latch device EBI_AD[7:0] Addr[7:0] EBI_ALE EBI_nCS EBI_nRD EBI_nWR EBI_AD[7:0] EBI_AD[7:0] Data[7:0] Figure 6.5-3 Connection of 8-bit EBI Data Width with 8-bit Device When system access data width is larger than EBI data width, EBI controller will finish a system access command by operating EBI access more than once.
  • Page 347 M451 6.5.5.3 EBI Operating Control MCLK Control In the chip, all EBI signals will be synchronized by EBI_MCLK when EBI is operating. When chip connects to the external device with slower operating frequency, the EBI_MCLK can divide most to HCLK/32 by setting MCLKDIV (EBI_CTLx[10:8]). Therefore, chip can suitable for a wide frequency range of EBI device.

  • Page 348: Figure 6.5-4 Timing Control Waveform For 16-Bit Data Width

    M451 tASU tALE tLHD tA2D tACC tAHD EBI_MCLK EBI_nCS EBI_ALE EBI_nRD Address RData EBI_AD[15:0] output[15:0] input EBI_ADR[18:16] Address output[18:16] EBI_nWR Address EBI_AD[15:0] WData output[15:0] output[15:0] EBI_ADR[18:16] Address output[18:16] Note: The EBI_MCLK is HCLK/2, MCLKDIV (EBI_CTLx[10:8]) = 1 Figure 6.5-4 Timing Control Waveform for 16-bit Data Width Figure 6.5-4 shows an example of setting 16-bit data width.

  • Page 349: Figure 6.5-5 Timing Control Waveform For 8-Bit Data Width

    M451 tASU tALE tLHD tA2D tACC tAHD EBI_MCLK EBI_nCS EBI_ALE EBI_nRD RData EBI_AD[7:0] Address output[7:0] input EBI_AD[15:8] Address output[15:8] EBI_ADR[19:16] Address output[19:16] EBI_nWR EBI_AD[7:0] Address output[7:0] WData output[7:0] EBI_AD[15:8] Address output[15:8] EBI_ADR[19:16] Address output[19:16] Note: The EBI_MCLK is HCLK/2, MCLKDIV (EBI_CTLx[10:8]) = 1 Figure 6.5-5 Timing Control Waveform for 8-bit Data Width Figure 6.5-5 figure above shows an example of setting 8-bit data width.

  • Page 350: Figure 6.5-6 Timing Control Waveform For Insert Idle Cycle

    M451 Insert Idle Cycle When EBI accessing continuously, there may occur bus conflict if the device access time is much slow with system operating. EBI controller supply additional idle cycle to solve this problem. During idle cycle, all control signals of EBI are inactive. Figure 6.5-6 shows idle cycle. tASU tALE tLHD tA2D...

  • Page 351: Register Map

    M451 6.5.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value EBI Base Address: EBI_BA = 0x4001_0000 EBI_CTL0 EBI_BA+0x00 External Bus Interface Bank0 Control Register 0x0000_0000 EBI_TCTL0 EBI_BA+0x04 External Bus Interface Bank0 Timing Control Register 0x0000_0000 EBI_CTL1 EBI_BA+0x10...

  • Page 352: Register Description

    M451 6.5.7 Register Description External Bus Interface Control Register (EBI_CTLx) Register Offset Description Reset Value EBI_CTL0 EBI_BA+0x00 External Bus Interface Bank0 Control Register 0x0000_0000 EBI_CTL1 EBI_BA+0x10 External Bus Interface Bank1 Control Register 0x0000_0000 Reversed WBUFEN Reversed TALE Reversed MCLKDIV Reversed CSPOLINV DW16 Bits...
  • Page 353 M451 This bit defines the active level of EBI chip select pin (EBI_nCS). 0 = Chip select pin (EBI_nCS) is active low. 1 = Chip select pin (EBI_nCS) is active high. EBI Data Width 16-bit Select This bit defines if the EBI data width is 8-bit or 16-bit. DW16 0 = EBI data width is 8-bit.
  • Page 354 M451 External Bus Interface Timing Control Register (EBI_TCTLx) Register Offset Description Reset Value EBI_TCTL0 EBI_BA+0x04 External Bus Interface Bank0 Timing Control Register 0x0000_0000 EBI_TCTL1 EBI_BA+0x14 External Bus Interface Bank1 Timing Control Register 0x0000_0000 Reserved WAHDOFF RAHDOFF Reserved Reversed TAHD TACC Reserved Bits Description...
  • Page 355 M451 [2:0] Reserved Reserved. May. 4, 2018 Page 355 of 1006 Rev.2.08...

  • Page 356: General Purpose I/O (Gpio)

    M451 General Purpose I/O (GPIO) 6.6.1 Overview ® The NuMicro M451 series has up to 87(for M45xG/M45xE)/76(for M45xD/M45xC) General Purpose I/O pins to be shared with other function pins depending on the chip configuration. These 87(for M45xG/M45xE)/76(for M45xD/M45xC) pins are arranged in 6 ports named as PA, PB, PC, PD, PE and PF.

  • Page 357: Block Diagram

    M451 6.6.3 Block Diagram Control Registers PA[15:0] PF[7:0] Control Register Control Register PA[15:0] PB[15:0] PB[15:0] Control Register PC[15:0] PC[15:0] Control Register PD[15:0] PE[14:0] PD[15:0] Control Register PF[7:0] PE[14:0] Control Register Interrupt, Wake-up Event De-bounce Control Register Detector GPIO_INT Figure 6.6-1 GPIO Controller Block Diagram Note: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC.

  • Page 358: Functional Description

    M451 6.6.5 Functional Description 6.6.5.1 Input Mode Set MODEn (Px_MODE[2n+1:2n]) to 00 as the Px.n pin is in Input mode and the I/O pin is in tri- state (high impedance) without output drive capability. The PIN (Px_PIN[n]) value reflects the status of the corresponding port pins.

  • Page 359: Figure 6.6-4 Quasi-Bidirectional I/O Mode

    M451 6.6.5.4 Quasi-bidirectional Mode Set MODEn (Px_MODE[2n+1:2n]) to 11 as the Px.n pin is in Quasi-bidirectional mode and the I/O pin supports digital output and input function at the same time but the source current is only up to hundreds uA. Before the digital input function is performed the corresponding DOUT (Px_DOUT[n]) bit must be set to 1.

  • Page 360: Register Map

    M451 6.6.6 Register Map R: read only, W: write only, R/W: both read and write. Register Offset Description Reset Value GPIO Base Address: GPIO_BA = 0x4000_4000 PA_MODE GPIO_BA+0x000 PA I/O Mode Control 0xXXXX_XXXX PA_DINOFF GPIO_BA+0x004 PA Digital Input Path Disable Control 0x0000_0000 PA_DOUT GPIO_BA+0x008...
  • Page 361 M451 PC_DBEN GPIO_BA+0x094 PC De-Bounce Enable Control Register 0x0000_0000 PC_INTTYPE GPIO_BA+0x098 PC Interrupt Trigger Type Control 0x0000_0000 PC_INTEN GPIO_BA+0x09C PC Interrupt Enable Control Register 0x0000_0000 PC_INTSRC GPIO_BA+0x0A0 PC Interrupt Source Flag 0x0000_XXXX PC_SMTEN GPIO_BA+0x0A4 PC Input Schmitt Trigger Enable Register 0x0000_0000 PC_SLEWCTL GPIO_BA+0x0A8 PC High Slew Rate Control Register...
  • Page 362 M451 PF_DOUT GPIO_BA+0x148 PF Data Output Value 0x0000_00FF PF_DATMSK GPIO_BA+0x14C PF Data Output Write Mask 0x0000_0000 PF_PIN GPIO_BA+0x150 PF Pin Value 0x0000_00XX PF_DBEN GPIO_BA+0x154 PF De-Bounce Enable Control Register 0x0000_0000 PF_INTTYPE GPIO_BA+0x158 PF Interrupt Trigger Type Control 0x0000_0000 PF_INTEN GPIO_BA+0x15C PF Interrupt Enable Control Register 0x0000_0000 PF_INTSRC...

  • Page 363: Register Description

    M451 6.6.7 Register Description Port A-F I/O Mode Control (Px_MODE) Register Offset Description Reset Value PA_MODE GPIO_BA+0x000 PA I/O Mode Control 0xXXXX_XXXX PB_MODE GPIO_BA+0x040 PB I/O Mode Control 0xXXXX_XXXX PC_MODE GPIO_BA+0x080 PC I/O Mode Control 0xXXXX_XXXX PD_MODE GPIO_BA+0x0C0 PD I/O Mode Control 0xXXXX_XXXX PE_MODE GPIO_BA+0x100...
  • Page 364 M451 Port A-F Digital Input Path Disable Control (Px_DINOFF) Register Offset Description Reset Value PA_DINOFF GPIO_BA+0x004 PA Digital Input Path Disable Control 0x0000_0000 PB_DINOFF GPIO_BA+0x044 PB Digital Input Path Disable Control 0x0000_0000 PC_DINOFF GPIO_BA+0x084 PC Digital Input Path Disable Control 0x0000_0000 PD_DINOFF GPIO_BA+0x0C4...
  • Page 365 M451 Port A-F Data Output Value (Px_DOUT) Register Offset Description Reset Value PA_DOUT GPIO_BA+0x008 PA Data Output Value 0x0000_FFFF PB_DOUT GPIO_BA+0x048 PB Data Output Value 0x0000_FFFF PC_DOUT GPIO_BA+0x088 PC Data Output Value 0x0000_FFFF PD_DOUT GPIO_BA+0x0C8 PD Data Output Value 0x0000_FFFF PE_DOUT GPIO_BA+0x108 PE Data Output Value...
  • Page 366 M451 Port A-F Data Output Write Mask (Px_DATMSK) Register Offset Description Reset Value PA_DATMSK GPIO_BA+0x00C PA Data Output Write Mask 0x0000_0000 PB_DATMSK GPIO_BA+0x04C PB Data Output Write Mask 0x0000_0000 PC_DATMSK GPIO_BA+0x08C PC Data Output Write Mask 0x0000_0000 PD_DATMSK GPIO_BA+0x0CC PD Data Output Write Mask 0x0000_0000 PE_DATMSK GPIO_BA+0x10C...
  • Page 367 M451 Port A-F Pin Value (Px_PIN) Register Offset Description Reset Value PA_PIN GPIO_BA+0x010 PA Pin Value 0x0000_XXXX PB_PIN GPIO_BA+0x050 PB Pin Value 0x0000_XXXX PC_PIN GPIO_BA+0x090 PC Pin Value 0x0000_XXXX PD_PIN GPIO_BA+0x0D0 PD Pin Value 0x0000_XXXX PE_PIN GPIO_BA+0x110 PE Pin Value 0x0000_XXXX PF_PIN GPIO_BA+0x150...
  • Page 368 M451 Port A-F De-Bounce Enable Control Register (Px_DBEN) Register Offset Description Reset Value PA_DBEN GPIO_BA+0x014 PA De-Bounce Enable Control Register 0x0000_0000 PB_DBEN GPIO_BA+0x054 PB De-Bounce Enable Control Register 0x0000_0000 PC_DBEN GPIO_BA+0x094 PC De-Bounce Enable Control Register 0x0000_0000 PD_DBEN GPIO_BA+0x0D4 PD De-Bounce Enable Control Register 0x0000_0000 PE_DBEN GPIO_BA+0x114...
  • Page 369 M451 Port A-F Interrupt Type Control (Px_INTTYPE) Register Offset Description Reset Value PA_INTTYPE GPIO_BA+0x018 PA Interrupt Trigger Type Control 0x0000_0000 PB_INTTYPE GPIO_BA+0x058 PB Interrupt Trigger Type Control 0x0000_0000 PC_INTTYPE GPIO_BA+0x098 PC Interrupt Trigger Type Control 0x0000_0000 PD_INTTYPE GPIO_BA+0x0D8 PD Interrupt Trigger Type Control 0x0000_0000 PE_INTTYPE GPIO_BA+0x118...
  • Page 370 M451 Port A-F Interrupt Enable Control Register (Px_INTEN) Register Offset Description Reset Value PA_INTEN GPIO_BA+0x01C PA Interrupt Enable Control Register 0x0000_0000 PB_INTEN GPIO_BA+0x05C PB Interrupt Enable Control Register 0x0000_0000 PC_INTEN GPIO_BA+0x09C PC Interrupt Enable Control Register 0x0000_0000 PD_INTEN GPIO_BA+0x0DC PD Interrupt Enable Control Register 0x0000_0000 PE_INTEN GPIO_BA+0x11C...
  • Page 371 M451 If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 0 = Px.n level low or high to low interrupt Disabled. 1 = Px.n level low or high to low interrupt Enabled.
  • Page 372 M451 Port A-F Interrupt Source Flag (Px_INTSRC) Register Offset Description Reset Value PA_INTSRC GPIO_BA+0x020 PA Interrupt Source Flag 0x0000_XXXX PB_INTSRC GPIO_BA+0x060 PB Interrupt Source Flag 0x0000_XXXX PC_INTSRC GPIO_BA+0x0A0 PC Interrupt Source Flag 0x0000_XXXX PD_INTSRC GPIO_BA+0x0E0 PD Interrupt Source Flag 0x0000_XXXX PE_INTSRC GPIO_BA+0x120 PE Interrupt Source Flag...
  • Page 373 M451 Port A-F Input Schmitt Trigger Enable Register (Px_SMTEN) Register Offset Description Reset Value PA_SMTEN GPIO_BA+0x024 PA Input Schmitt Trigger Enable Register 0x0000_0000 PB_SMTEN GPIO_BA+0x064 PB Input Schmitt Trigger Enable Register 0x0000_0000 PC_SMTEN GPIO_BA+0x0A4 PC Input Schmitt Trigger Enable Register 0x0000_0000 PD_SMTEN GPIO_BA+0x0E4...
  • Page 374 M451 Port A-F High Slew Rate Control Register (Px_SLEWCTL) Register Offset Description Reset Value PA_SLEWCTL GPIO_BA+0x028 PA High Slew Rate Control Register 0x0000_0000 PB_SLEWCTL GPIO_BA+0x068 PB High Slew Rate Control Register 0x0000_0000 PC_SLEWCTL GPIO_BA+0x0A8 PC High Slew Rate Control Register 0x0000_0000 PD_SLEWCTL GPIO_BA+0x0E8 PD High Slew Rate Control Register...
  • Page 375 M451 Port E High Drive Strength Control Register (PE_DRVCTL) Register Offset Description Reset Value PE_DRVCTL GPIO_BA+0x12C PE High Drive Strength Control Register 0x0000_0000 Reserved Reserved Reserved HDRVEN[13:8] Reserved Bits Description [31:14] Reserved Reserved. Port E Pin[N] Driving Strength Control 0 = Px.n output with basic driving strength. HDRVEN[13:8] 1 = Px.n output with high driving strength.
  • Page 376 M451 Interrupt De-bounce Control Register (GPIO_DBCTL) Register Offset Description Reset Value GPIO_DBCTL GPIO_BA+0x440 Interrupt De-bounce Control Register 0x0000_0020 Reserved Reserved Reserved Reserved ICLKON DBCLKSRC DBCLKSEL Bits Description [31:6] Reserved Reserved. Interrupt Clock on Mode 0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1.
  • Page 377 M451 GPIO Px.n Pin Data Input/Outut Register (Pxn_PDIO) Register Offset Description Reset Value PAn_PDIO GPIO_BA+0x800+(0x04 * n) GPIO PA.n Pin Data Input/Output Register 0x0000_000X n=0,1..15 PBn_PDIO GPIO_BA+0x840+(0x04 * n) GPIO PB.n Pin Data Input/Output Register 0x0000_000X n=0,1..15 PCn_PDIO GPIO_BA+0x880+(0x04 * n) GPIO PC.n Pin Data Input/Output Register 0x0000_000X n=0,1..15...

  • Page 378: Pdma Controller (Pdma)

    M451 PDMA Controller (PDMA) 6.7.1 Overview The peripheral direct memory access (PDMA) controller is used to provide high-speed data transfer. The PDMA controller can transfer data from one address to another without CPU intervention. This has the benefit of reducing the workload of CPU and keeps CPU resources free for other applications.

  • Page 379: Basic Configuration

    M451 6.7.4 Basic Configuration The peripheral direct memory access (PDMA) controller peripheral clock is enabled in PDMACKEN (CLK_AHBCLK[1]). 6.7.5 Functional Description The PDMA controller transfers data from one address to another without CPU intervention. For M45xG/M45xE, the PDMA controller supports 12 independent channels, for M45xD/M45xC, the PDMA controller supports 8 independent channels and serves only one channel at one time, as the result, PDMA controller supports two level channel priorities: fixed and round-robin priority, PDMA controller serves channel in order from highest to lowest priority channel.

  • Page 380: Table 6-11 Channel Priority Table (M45Xg/M45Xe Only)

    M451 PDMA_PRISET Channel Number Priority Setting Arbitration Priority In Descending Order Channel11, Fixed Priority Highest Channel10, Fixed Priority Channel0, Fixed Priority Channel11, Round-Robin Priority Channel10, Round-Robin Priority Channel0, Round-Robin Priority Lowest Table 6-11 Channel Priority Table (M45xG/M45xE Only) PDMA_PRISET Channel Number Priority Setting Arbitration Priority In Descending Order Channel7, Fixed Priority...

  • Page 381: Figure 6.7-3 Basic Mode Finite State Machine

    M451 PDMA controller will not perform any transfer and then clear this operation request. Finishing this task will also generate an interrupt to CPU if corresponding PDMA interrupt bit is enabled. Transfer State OPMODE (PDMA_DSCTn_CTL[1:0]) = 0x1 Next Request Transfer done Idle State OPMODE (PDMA_DSCTn_CTL[1:0]) = 0x0 Figure 6.7-3 Basic Mode Finite State Machine...

  • Page 382: Figure 6.7-4 Descriptor Table Link List Structure

    M451 PDMA_SCATBA DSCTn DSCT_NEXT MSB 16 bits LSB 16 bits DSCTn-1 DSCT_DA without [1:0] DSCT_SA DSCT_CTL Current DSCT Entry DSCT_NEXT DSCT1 DSCT_DA DSCT0 DSCT_SA Load the information to the channel n descriptor table DSCT_CTL Next DSCT Entry SRAM Note: for M45xG/M45xE n denotes 11, for M45xC/M45xD...
  • Page 383 M451 6.7.5.3 Transfer Type The PDMA controller supports two transfer types: single transfer type and burst transfer type, configure by setting TXTYPE (PDMA_DSCTn_CTL[2]). When PDMA controller operated in single transfer type, each transfer data needs one request signal for one transfer, after transferred data, TXCNT (PDMA_DSCTn_CTL[29:16]) will decrease 1.

  • Page 384: Figure 6.7-6 Example Of Single Transfer Type And Burst Transfer Type In Basic Mode

    M451 Execution Channel 1 Channel 0 Channel 1 Channel 0 Channel 1 transfer 1 transfer CH1 Request data data CH0 Request 128 transfer data 128 transfer data TXCNT (PDMA_DSCTn_CTL[29:16]) BURSIZE Non-useful (PDMA_DSCTn_CTL[6:4]) TXTYPE Single Transfer Burst Transfer (PDMA_DSCTn_CTL[2]) Figure 6.7-6 Example of Single Transfer Type and Burst Transfer Type in Basic Mode 6.7.5.4 Channel Time-out (M45xD/M45xC Only) When the PDMA transfer channel is enabled, corresponding channel time-out TOUTENn...

  • Page 385: Register Map

    M451 6.7.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value PDMA Base Address: PDMA_BA = 0x4000_8000 DSCT_CTL_BA = 0x4000_8000 DSCT_SA_BA = 0x4000_8004 DSCT_DA_BA = 0x4000_8008 DSCT_NEXT_BA = 0x4000_800c CURSCAT_BA = 0x4000_80C0 PDMA_DSCTn_CTL Descriptor Table Control Register of PDMA Channel n DSCT_CTL_BA +...
  • Page 386 M451 PDMA Time-out Counter Ch3 and Ch2 Register PDMA_TOC2_3 PDMA_BA + 0x444 0xFFFF_FFFF (M45xD/M45xC Only) PDMA Time-out Counter Ch5 and Ch4 Register PDMA_TOC4_5 PDMA_BA + 0x448 0xFFFF_FFFF (M45xD/M45xC Only) PDMA Time-out Counter Ch7 and Ch6 Register PDMA_TOC6_7 PDMA_BA + 0x44C R/W 0xFFFF_FFFF (M45xD/M45xC Only) PDMA_REQSEL0_3...

  • Page 387: Register Description

    M451 6.7.7 Register Description Descriptor Table Control Register (PDMA_DSCTn_CTL) Register Offset R/W Description Reset Value PDMA_DSCTn_CTL Descriptor Table Control Register of PDMA Channel n DSCT_CTL_BA + 0xXXXX_XXXX (0x10*n) n = 0~11 (M45xD/M45xC Only Support Channel 0~7) Reserved TXCNT TXCNT Reserved TXWIDTH DAINC SAINC...
  • Page 388 M451 Bits Description bit is enabled when PDMA controller finishes transfer task, it will not generates interrupt. 0 = Table interrupt Enabled. 1 = Table interrupt Disabled. Note: If this bit set to ‘1’, the TEMPTYF will not be set. Burst Size This field is used for peripheral to determine the burst size or used for determine the re- arbitration size.
  • Page 389 M451 Start Source Address Register (PDMA_DSCTn_SA) Register Offset R/W Description Reset Value PDMA_DSCTn_SA Source Address Register of PDMA Channel n DSCT_SA_BA + 0xXXXX_XXXX (0x10*n) n = 0~11 (M45xD/M45xC Only Support Channel 0~7) Bits Description PDMA Transfer Source Address Register [31:0] This field indicates a 32-bit source address of PDMA controller.
  • Page 390 M451 Destination Address Register (PDMA_DSCTn_DA) Register Offset R/W Description Reset Value PDMA_DSCTn_DA Destination Address Register of PDMA Channel n DSCT_DA_BA + 0xXXXX_XXXX (0x10*n) n = 0~11 (M45xD/M45xC Only Support Channel 0~7) Bits Description PDMA Transfer Destination Address Register [31:0] This field indicates a 32-bit destination address of PDMA controller. May.
  • Page 391 M451 First Scatter-Gather Descriptor Table Offset Address (PDMA_DSCTn_NEXT) Register Offset R/W Description Reset Value First Scatter-Gather Descriptor Table Offset Address PDMA_DSCTn_NEXT DSCT_NEXT_BA + of PDMA Channel n 0xXXXX_XXXX (0x10*n) n = 0~11 (M45xD/M45xC Only Support Channel 0~7) Reserved Reserved NEXT NEXT Reserved Bits...
  • Page 392 M451 Current Scatter-Gather Descriptor Table Address (PDMA_CURSCAT) Register Offset R/W Description Reset Value Current Scatter-Gather Descriptor Table Address of PDMA_CURSCATn PDMA Channel n CURSCAT_BA + (0x04*n) R 0xXXXX_XXXX n = 0~11 (M45xD/M45xC Only Support Channel 0~7) CURADDR CURADDR CURADDR CURADDR Bits Description PDMA Current Description Address Register (Read Only)
  • Page 393 M451 Channel Control Register (PDMA_CHCTL) Register Offset R/W Description Reset Value PDMA_CHCTL PDMA_BA + 0x400 R/W PDMA Channel Control Register 0x0000_0000 Reserved Reserved Reserved CHEN11 CHEN10 CHEN9 CHEN8 CHEN7 CHEN6 CHEN5 CHEN4 CHEN3 CHEN2 CHEN1 CHEN0 Bits Description [31:12] Reserved Reserved.
  • Page 394 M451 PDMA Transfer Stop Control Register (PDMA_STOP) Register Offset R/W Description Reset Value PDMA_STOP PDMA_BA + 0x404 PDMA Transfer Stop Control Register 0x0000_0000 Reserved Reserved Reserved STOP11 STOP10 STOP9 STOP8 STOP7 STOP6 STOP5 STOP4 STOP3 STOP2 STOP1 STOP0 Bits Description [31:12] Reserved Reserved.
  • Page 395 M451 PDMA Software Request Register (PDMA_SWREQ) Register Offset R/W Description Reset Value PDMA_SWREQ PDMA_BA + 0x408 PDMA Software Request Register 0x0000_0000 Reserved Reserved Reserved SWREQ11 SWREQ10 SWREQ9 SWREQ8 SWREQ7 SWREQ6 SWREQ5 SWREQ4 SWREQ3 SWREQ2 SWREQ1 SWREQ0 Bits Description [31:12] Reserved Reserved.
  • Page 396 M451 PDMA Channel Request Status Register (PDMA_TRGSTS) Register Offset R/W Description Reset Value PDMA_TRGSTS PDMA_BA + 0x40C PDMA Channel Request Status Register 0x0000_0000 Reserved Reserved Reserved REQSTS11 REQSTS10 REQSTS9 REQSTS8 REQSTS7 REQSTS6 REQSTS5 REQSTS4 REQSTS3 REQSTS2 REQSTS1 REQSTS0 Bits Description [31:12] Reserved Reserved.
  • Page 397 M451 PDMA Fixed Priority Setting Register (PDMA_PRISET) Register Offset R/W Description Reset Value PDMA_PRISET PDMA_BA + 0x410 R/W PDMA Fixed Priority Setting Register 0x0000_0000 Reserved Reserved Reserved FPRISET11 FPRISET10 FPRISET9 FPRISET8 FPRISET7 FPRISET6 FPRISET5 FPRISET4 FPRISET3 FPRISET2 FPRISET1 FPRISET0 Bits Description [31:12] Reserved...
  • Page 398 M451 PDMA Fix Priority Clear Register (PDMA_PRICLR) Register Offset R/W Description Reset Value PDMA_PRICLR PDMA_BA + 0x414 PDMA Fixed Priority Clear Register 0x0000_0000 Reserved Reserved Reserved FPRICLR11 FPRICLR10 FPRICLR9 FPRICLR8 FPRICLR7 FPRICLR6 FPRICLR5 FPRICLR4 FPRICLR3 FPRICLR2 FPRICLR1 FPRICLR0 Bits Description [31:12] Reserved Reserved.
  • Page 399 M451 PDMA Interrupt Enable Register (PDMA_INTEN) Register Offset R/W Description Reset Value PDMA_INTEN PDMA_BA + 0x418 R/W PDMA Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved INTEN11 INTEN10 INTEN9 INTEN8 INTEN7 INTEN6 INTEN5 INTEN4 INTEN3 INTEN2 INTEN1 INTEN0 Bits Description [31:12] Reserved Reserved.
  • Page 400 M451 PDMA Interrupt Status Register (PDMA_INTSTS) Register Offset R/W Description Reset Value PDMA_INTSTS PDMA_BA + 0x41C R/W PDMA Interrupt Status Register 0x0000_0000 Reserved Reserved REQTOF7 REQTOF6 REQTOF5 REQTOF4 REQTOF3 REQTOF2 REQTOF1 REQTOF0 Reserved TEIF TDIF ABTIF Bits Description [31:16] Reserved Reserved.
  • Page 401 M451 PDMA Channel Read/Write Target Abort Flag Register (PDMA_ABTSTS) Register Offset R/W Description Reset Value PDMA Channel Read/Write Target Abort Flag PDMA_ABTSTS PDMA_BA + 0x420 0x0000_0000 Register Reserved Reserved Reserved ABTIF11 ABTIF10 ABTIF9 ABTIF8 ABTIF7 ABTIF6 ABTIF5 ABTIF4 ABTIF3 ABTIF2 ABTIF1 ABTIF0 Bits...
  • Page 402 M451 PDMA Channel Transfer Done Flag Register (PDMA_TDSTS) Register Offset R/W Description Reset Value PDMA_TDSTS PDMA_BA + 0x424 R/W PDMA Channel Transfer Done Flag Register 0x0000_0000 Reserved Reserved Reserved TDIF11 TDIF10 TDIF9 TDIF8 TDIF7 TDIF6 TDIF5 TDIF4 TDIF3 TDIF2 TDIF1 TDIF0 Bits Description...
  • Page 403 M451 PDMA Scatter-Gather Table Empty Status Register (PDMA_SCATSTS) Register Offset R/W Description Reset Value PDMA_SCATSTS PDMA_BA + 0x428 R/W PDMA Scatter-Gather Table Empty Status Register 0x0000_0000 Reserved Reserved Reserved TEMPTYF11 TEMPTYF10 TEMPTYF9 TEMPTYF8 TEMPTYF7 TEMPTYF6 TEMPTYF5 TEMPTYF4 TEMPTYF3 TEMPTYF2 TEMPTYF1 TEMPTYF0 Bits Description...
  • Page 404 M451 PDMA Transfer Active Flag Register (PDMA_TACTSTS) Register Offset R/W Description Reset Value PDMA_TACTSTS PDMA_BA + 0x42C PDMA Transfer Active Flag Register 0x0000_0000 Reserved Reserved Reserved TXACTF11 TXACTF10 TXACTF9 TXACTF8 TXACTF7 TXACTF6 TXACTF5 TXACTF4 TXACTF3 TXACTF2 TXACTF1 TXACTF0 Bits Description [31:12] Reserved Reserved.
  • Page 405 M451 PDMA Time-out Enable Register (PDMA_TOUTEN) (M45xD/M45xC Only) Register Offset R/W Description Reset Value PDMA Time-out Enable Register (M45xD/M45xC PDMA_TOUTEN PDMA_BA + 0x434 0x0000_0000 Only) Reserved Reserved Reserved TOUTEN7 TOUTEN6 TOUTEN5 TOUTEN4 TOUTEN3 TOUTEN2 TOUTEN1 TOUTEN0 Bits Description [31:8] Reserved Reserved.
  • Page 406 M451 PDMA Time-out Interrupt Enable Register (PDMA_TOUTIEN) (M45xD/M45xC Only) Register Offset R/W Description Reset Value PDMA Time-out Interrupt Enable Register PDMA_TOUTIEN PDMA_BA + 0x438 0x0000_0000 (M45xD/M45xC Only) Reserved Reserved Reserved TOUTIEN7 TOUTIEN6 TOUTIEN5 TOUTIEN4 TOUTIEN3 TOUTIEN2 TOUTIEN1 TOUTIEN0 Bits Description [31:8] Reserved Reserved.
  • Page 407 M451 PDMA Scatter-Gather Descriptor Table Base Address Register (PDMA_SCATBA) Register Offset R/W Description Reset Value PDMA Scatter-Gather Descriptor Table Base Address PDMA_SCATBA PDMA_BA + 0x43C 0x2000_0000 Register SCATBA SCATBA Reserved Reserved Bits Description PDMA Scatter-gather Descriptor Table Address Register In Scatter-Gather mode, this is the base address for calculating the next link - list address.
  • Page 408 M451 PDMA Time-out Counter Ch1 and Ch0 Register (PDMA_TOC0_1) (M45xD/M45xC Only) Register Offset R/W Description Reset Value PDMA Time-out Counter Ch1 and Ch0 Register PDMA_TOC0_1 PDMA_BA + 0x440 0xFFFF_FFFF (M45xD/M45xC Only) TOC1 TOC1 TOC0 TOC0 Bits Description Time-out Counter for Channel 1 [31:16] TOC1 This controls the period of time-out function for channel 1.
  • Page 409 M451 PDMA Time-out Counter Ch3 and Ch2 Register (PDMA_TOC2_3) (M45xD/M45xC Only) Register Offset R/W Description Reset Value PDMA Time-out Counter Ch3 and Ch2 Register PDMA_TOC2_3 PDMA_BA + 0x444 0xFFFF_FFFF (M45xD/M45xC Only) TOC3 TOC3 TOC2 TOC2 Bits Description Time-out Period Counter for Channel 3 [31:16] TOC3 This controls the period of time-out function for channel 3.
  • Page 410 M451 PDMA Time-out Counter Ch5 and Ch4 Register (PDMA_TOC4_5) (M45xD/M45xC Only) Register Offset R/W Description Reset Value PDMA Time-out Counter Ch5 and Ch4 Register PDMA_TOC4_5 PDMA_BA + 0x448 0xFFFF_FFFF (M45xD/M45xC Only) TOC5 TOC5 TOC4 TOC4 Bits Description Time-out Period Counter for Channel 5 [31:16] TOC5 This controls the period of time-out function for channel 5.
  • Page 411 M451 PDMA Time-out Counter Ch7 and Ch6 Register (PDMA_TOC6_7) (M45xD/M45xC Only) Register Offset R/W Description Reset Value PDMA Time-out Counter Ch7 and Ch6 Register PDMA_TOC6_7 PDMA_BA + 0x44C 0xFFFF_FFFF (M45xD/M45xC Only) TOC7 TOC7 TOC6 TOC6 Bits Description Time-out Period Counter for Channel 7 [31:16] TOC7 This controls the period of time-out function for channel 7.
  • Page 412 M451 PDMA Request Source Select Register 0 (PDMA_REQSEL0_3) Register Offset R/W Description Reset Value PDMA_REQSEL0_ PDMA_BA + 0x480 R/W PDMA Request Source Select Register 0 0x1F1F_1F1F Reserved REQSRC3 Reserved REQSRC2 Reserved REQSRC1 Reserved REQSRC0 Bits Description [31:29] Reserved Reserved. Channel 3 Request Source Selection This filed defines which peripheral is connected to PDMA channel 3.
  • Page 413 M451 Bits Description 7 = Channel connects to UART3_TX. 8 = Channel connects to DAC_TX. 9 = Channel connects to ADC_RX. 11 = Channel connects to PWM0_P1_RX. 12 = Channel connects to PWM0_P2_RX. 13 = Channel connects to PWM0_P3_RX. 14 = Channel connects to PWM1_P1_RX. 15 = Channel connects to PWM1_P2_RX.
  • Page 414 M451 PDMA Request Source Select Register 1 (PDMA_REQSEL4_7) Register Offset R/W Description Reset Value PDMA_REQSEL4_ PDMA_BA + 0x484 R/W PDMA Request Source Select Register 1 0x1F1F_1F1F Reserved REQSRC7 Reserved REQSRC6 Reserved REQSRC5 Reserved REQSRC4 Bits Description [31:29] Reserved Reserved. Channel 7 Request Source Selection This filed defines which peripheral is connected to PDMA channel 7.
  • Page 415 M451 PDMA Request Source Select Register 2 (PDMA_REQSEL8_11) (M45xG/M45xE Only) Register Offset R/W Description Reset Value PDMA_REQSEL8_ PDMA_BA + 0x488 R/W PDMA Request Source Select Register 2 0x1F1F_1F1F Reserved REQSRC11 Reserved REQSRC10 Reserved REQSRC9 Reserved REQSRC8 Bits Description [31:29] Reserved Reserved.

  • Page 416: Timer Controller (Tmr)

    M451 Timer Controller (TMR) 6.8.1 Overview The Timer controller includes four 32-bit timers, Timer0 ~ Timer3, allowing user to easily implement a timer control for applications. The timer can perform functions, such as frequency measurement, delay timing, clock generation, and event counting by external input pins, and interval measurement by external capture pins.

  • Page 417: Block Diagram

    M451 6.8.3 Block Diagram The Timer Controller block diagram and clock control are shown as follows. WKEN 24-bit CMPDAT (TIMERx_CTL[23]) (TIMERx_CMP[23:0]) Timer RSTCNT(TIMERx_CTL[26]) TWKF Wakeup Reset counter (TIMERx_INTSTS[1]) CNTEN(TIMERx_CTL[30]) (TIMERx_INTSTS[0]) TMRx_CLK 8 - bit 24 - bit up counter Prescale T0 ~ T3 EXTCNTEN (TIMERx_CTL[24]) Reset counter...

  • Page 418: Basic Configuration

    M451 TMR0SEL(CLK_CLKSEL1[10:8]) TMR1SEL(CLK_CLKSEL1[14:12]) TMR0CKEN(CLK_APBCLK0[2]) 22.1184 MHz (HIRC) TMR1CKEN(CLK_APBCLK0[3]) 10 kHz (LIRC) TMR0_CLK T0~T1 TMR1_CLK PCLK0 32.768 KHz (LXT) 4~24 MHz (HXT) TMR2SEL(CLK_CLKSEL1[18:16]) TMR3SEL(CLK_CLKSEL1[22:20]) TMR2CKEN(CLK_APBCLK0[4]) 22.1184 MHz (HIRC) TMR3CKEN(CLK_APBCLK0[5]) 10 kHz (LIRC) TMR2_CLK T2~T3 TMR3_CLK PCLK1 32.768 KHz (LXT) Legend: 4~24 MHz (HXT) HXT = High Speed External clock signal LXT = Low Speed External clock signal HIRC = High Speed Internal clock signal...
  • Page 419 M451 (TIMERx_CTL[30]) set, timer counter starts counting. Once (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value, (TIMERx_INTSTS[0]) will be set to 1, CNT value and CNTEN bit is cleared automatically by timer controller then timer counting operation stops. In the meantime, if the INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal is generated and sent to NVIC to inform CPU also.

  • Page 420: Figure 6.8-3 Continuous Counting Mode

    M451 TIF = 1 and TIF = 1 and TIF = 1 and Interrupt Interrupt Interrupt Generation Generation Generation Clear TIF as 0 Clear TIF as 0 Clear TIF as 0 CMPDAT = 80 and Set and Set and Set CMPDAT = 200 CMPDAT = 500 CMPDAT = 80...
  • Page 421 M451 TIMERx_CTL Tx_EXT (CAPEDGE=0x02) Clear by software CAPIF TIMERx_CAP Figure 5.20-4 External Capture Mode 6.8.5.9 External Reset Counter Mode Timer controller also provides reset counter function to reset CNT (TIMERx_CNT[23:0]) value while edge transition detected on Tx_EXT (x= 0~3). In this mode, most the settings are the same as event capture mode except CAPFUNCS (TIMERx_EXTCTL[4]) should be as 1 for select Tx_EXT transition is using to trigger reset counter value.
  • Page 422 M451 6.8.5.10 Timer Trigger Function Timer controller provides timer time-out interrupt or capture interrupt to trigger PWM, DAC and EADC. If TRGSSEL (TIMERx_CTL[18]) is 0, time-out interrupt signal is used to trigger PWM, EADC and DAC. If TRGSSEL (TIMERx_CTL[18]) is 1, capture interrupt signal is used to trigger PWM, EADC and DAC.

  • Page 423: Register Map

    M451 6.8.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value TMR Base Address: TMR_BA01 = 0x4005_0000 TMR_BA23 = 0x4005_1000 TIMER0_CTL TMR_BA01+0x00 Timer0 Control and Status Register 0x0000_0005 TIMER0_CMP TMR_BA01+0x04 Timer0 Compare Register 0x0000_0000 TIMER0_INTS TMR_BA01+0x08...
  • Page 424 M451 TIMER3_INTS TMR_BA23+0x28 Timer3 Interrupt Status Register 0x0000_0000 TIMER3_CNT TMR_BA23+0x2C R Timer3 Data Register 0x0000_0000 TIMER3_CAP TMR_BA23+0x30 Timer3 Capture Data Register 0x0000_0000 TIMER3_EXT TMR_BA23+0x34 Timer3 External Control Register 0x0000_0000 TIMER3_EINT TMR_BA23+0x38 Timer3 External Interrupt Status Register 0x0000_0000 May. 4, 2018 Page 424 of 1006 Rev.2.08...

  • Page 425: Register Description

    M451 6.8.7 Register Description Timer Control Register (TIMERx_CTL) Register Offset Description Reset Value TIMER0_CTL TMR_BA01+0x00 Timer0 Control and Status Register 0x0000_0005 TIMER1_CTL TMR_BA01+0x20 Timer1 Control and Status Register 0x0000_0005 TIMER2_CTL TMR_BA23+0x00 Timer2 Control and Status Register 0x0000_0005 TIMER3_CTL TMR_BA23+0x20 Timer3 Control and Status Register 0x0000_0005 ICEDEBUG CNTEN...
  • Page 426 M451 Timer Counting Mode Select 00 = The Timer controller is operated in One-shot mode. [28:27] OPMODE 01 = The Timer controller is operated in Periodic mode. 10 = The Timer controller is operated in Toggle-output mode. 11 = The Timer controller is operated in Continuous Counting mode. Timer Counter Reset Bit Setting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.
  • Page 427 M451 0 = Timer interrupt trigger PWM Disabled. 1 = Timer interrupt trigger PWM Enabled. Note: If TRGSSEL (TIMERx_CTL[18]) = 0, time-out interrupt signal will trigger PWM. If TRGSSEL (TIMERx_CTL[18]) = 1, capture interrupt signal will trigger PWM. Trigger Source Select Bit This bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal.
  • Page 428 M451 Timer Compare Register (TIMERx_CMP) Register Offset Description Reset Value TIMER0_CMP TMR_BA01+0x04 Timer0 Compare Register 0x0000_0000 TIMER1_CMP TMR_BA01+0x24 Timer1 Compare Register 0x0000_0000 TIMER2_CMP TMR_BA23+0x04 Timer2 Compare Register 0x0000_0000 TIMER3_CMP TMR_BA23+0x24 Timer3 Compare Register 0x0000_0000 Reserved CMPDAT CMPDAT CMPDAT Bits Description [31:24] Reserved Reserved.
  • Page 429 M451 Timer Interrupt Status Register (TIMERx_INTSTS) Register Offset Description Reset Value TIMER0_INTS TMR_BA01+0x08 Timer0 Interrupt Status Register 0x0000_0000 TIMER1_INTS TMR_BA01+0x28 Timer1 Interrupt Status Register 0x0000_0000 TIMER2_INTS TMR_BA23+0x08 Timer2 Interrupt Status Register 0x0000_0000 TIMER3_INTS TMR_BA23+0x28 Timer3 Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved Reserved...
  • Page 430 M451 Timer Data Register (TIMERx_CNT) Register Offset Description Reset Value TIMER0_CNT TMR_BA01+0x0C R Timer0 Data Register 0x0000_0000 TIMER1_CNT TMR_BA01+0x2C R Timer1 Data Register 0x0000_0000 TIMER2_CNT TMR_BA23+0x0C R Timer2 Data Register 0x0000_0000 TIMER3_CNT TMR_BA23+0x2C R Timer3 Data Register 0x0000_0000 Reserved Bits Description [31:24] Reserved...
  • Page 431 M451 Timer Capture Data Register (TIMERx_CAP) Register Offset Description Reset Value TIMER0_CAP TMR_BA01+0x10 Timer0 Capture Data Register 0x0000_0000 TIMER1_CAP TMR_BA01+0x30 Timer1 Capture Data Register 0x0000_0000 TIMER2_CAP TMR_BA23+0x10 Timer2 Capture Data Register 0x0000_0000 TIMER3_CAP TMR_BA23+0x30 Timer3 Capture Data Register 0x0000_0000 Reserved CAPDAT CAPDAT CAPDAT...
  • Page 432 M451 Timer External Control Register (TIMERx_EXTCTL) Register Offset Description Reset Value TIMER0_EXT TMR_BA01+0x14 Timer0 External Control Register 0x0000_0000 TIMER1_EXT TMR_BA01+0x34 Timer1 External Control Register 0x0000_0000 TIMER2_EXT TMR_BA23+0x14 Timer2 External Control Register 0x0000_0000 TIMER3_EXT TMR_BA23+0x34 Timer3 External Control Register 0x0000_0000 Reserved Reserved Reserved CNTDBEN...
  • Page 433 M451 1 = External Reset Mode Enabled. Note1: When CAPFUNCS is 0, transition on Tx_EXT (x= 0~3) pin is using to save the 24- bit timer counter value. Note2: When CAPFUNCS is 1, transition on Tx_EXT (x= 0~3) pin is using to reset the 24- bit timer counter value.
  • Page 434 M451 Timer External Interrupt Status Register (TIMERx_EINTSTS) Register Offset Description Reset Value TIMER0_EINT TMR_BA01+0x18 Timer0 External Interrupt Status Register 0x0000_0000 TIMER1_EINT TMR_BA01+0x38 Timer1 External Interrupt Status Register 0x0000_0000 TIMER2_EINT TMR_BA23+0x18 Timer2 External Interrupt Status Register 0x0000_0000 TIMER3_EINT TMR_BA23+0x38 Timer3 External Interrupt Status Register 0x0000_0000 Reserved Reserved...

  • Page 435: Pwm Generator And Capture Timer (Pwm)

    M451 PWM Generator and Capture Timer (PWM) 6.9.1 Overview The M451 provides two PWM generators － PWM0 and PWM1 as Figure 6.9-1. Each PWM supports 6 channels of PWM output or input capture. There is a 12-bit prescaler to support flexible clock to the 16-bit PWM counter with 16-bit comparator.
  • Page 436 M451 – Level detect brake source to auto recover function after brake condition removed  Supports interrupt on the following events: – PWM counter match zero, period value or compared value – Brake condition happened  Supports trigger EADC/DAC on the following events: –...

  • Page 437: Block Diagram

    M451 6.9.3 Block Diagram PWM0_SYNC_OUT PWM0_SYNC_IN PWM0_BRAKE0 SYNC_IN NVIC_MUX PWM0_CH0 PWM0_BRAKE1 PWM0 CLOCK PWM0_CH5 CONTROLLER TIMER0 PDMA TIMER1 SYNC_OUT TIMER2 TIMER3 ACMP Clock Fail Brown-Out Detect SYNC_IN SYNC_IN SRAM Parity Error EADC PWM1_CH0 CPU Lockup Brake Source PWM1_BRAKE0 PWM1 PWM1_CH5 PWM1_BRAKE1 Note: Only capture mode output to PDMA...

  • Page 438: Figure 6.9-3 Pwm Clock Source Control

    M451 PWM System Clock/HCLK HCLKSEL HCLKDIV PWMnSEL (CLK_CLKSEL2[N]), Frequency Ratio (CLK_CLKSEL0[2:0]) (CLK_CLKDIV0[3:0]) N Denotes 0 Or 1 Don’t care Don’t care Table 6-13 PWM System Clock Source Control Registers Setting Table ECLKSRC0 (PWM_CLKSRC[2:0]) PWM0 system clock TIMER0 PWM0_CLK0 TIMER1 TIMER2 TIMER3 ECLKSRC0 (PWM_CLKSRC[2:0]) PWM1 system clock...

  • Page 439: Figure 6.9-4 Pwm Independent Mode Architecture Diagram

    M451 PWM0_BRAKE0 Interrupt Interrupt events IRQ_MUX Generator Trigger events Trigger EADC/DAC Generator PWM0_BRAKE1 PWM0_CLK0 Prescaler0 Counter0 PWM0_CH0 Pulse Output 12bits 16bits Generator0 Control0 Comparator0 PWM0_BRAKE0 16bits PWM0_BRAKE1 Counter1 PWM0_CH1 Pulse Output 16bits Generator1 Control1 Comparator1 PWM0_BRAKE0 16bits PWM0_BRAKE1 PWM0_CLK2 Prescaler2 Counter2 PWM0_CH2 Pulse...

  • Page 440: Basic Configuration

    M451 PWM0_BRAKE0 Interrupt Events Interrupt IRQ_MUX Generator PWM0_BRAKE1 Trigger Events Trigger EADC/DAC Generator Free Trigger Comparator0 PWM0_SYNC_IN PWM0_CH0 Comparator0 PWM0_CLK0 Prescaler0 Pulse Output Counter0 12bits Generator0 Control0 PWM0_CH1 Comparator1 PWM0_BRAKE0 Free Trigger PWM0_BRAKE1 Comparator2 PWM0_CH2 Comparator2 PWM0_CLK2 Prescaler2 Pulse Output Counter2 12bits Generator2...

  • Page 441: Figure 6.9-6 Pwm_Ch0 Prescaler Waveform

    M451 PWM_CLK CLKPSC (PWM_CLKPSC0[11:0]) CNTEN0 (PWM_CNTEN[0]) Prescaler 3 2 1 0 4 3 2 1 0 4 3 2 1 0 5 4 3 2 1 (PWM_CNT0[15:0]) Figure 6.9-6 PWM_CH0 prescaler waveform 6.9.5.2 PWM Counter PWM supports 3 counter types operation: Up Counter, Down Counter and Up-Down Counter types.

  • Page 442: Figure 6.9-8 Pwm Down Counter Type

    M451 PERIOD = 5 PERIOD = 8 PERIOD = 8 PWM Counter (CNT) PWM Period PWM Period PWM Period zero point event period point event Figure 6.9-8 PWM Down Counter Type 6.9.5.5 Up-Down Counter Type In the up-down counter operation, the 16 bits PWM counter is an up-down counter and starts counting-up from zero to PERIOD and then starts counting down to zero to complete a PWM period.

  • Page 443: Figure 6.9-10 Pwm Cmpdat Events In Up-Down Counter Type

    M451 CMPDAT = 4 CMPDAT = 5 CMPDAT= 0 PWM Counter (CNT) PWM Direction (DIRF) PWM Period PWM Period Up-count compared point event (CMPU) Down-count compared point event (CMPD) Figure 6.9-10 PWM CMPDAT Events in Up-Down Counter Type FTCMPDAT is a free trigger comparator register. Each complementary paired channel only supports one FTCMPDAT.

  • Page 444: Figure 6.9-11 Pwm Double Buffering Illustration

    M451 Load from PERIOD to PBUF, from FTCMPDAT to FTCMPBUF Initialize Load from CMPDAT start S/W Write CMPDAT S/W Write PERIOD to CMPBUF PERIOD PBUF CMPDAT CMPBUF FTCMPDAT FTCMPBUF S/W Write FTCMPDAT CMPU CMPD FTCMPU FTCMPD Figure 6.9-11 PWM Double Buffering Illustration 6.9.5.8 Period Loading Mode Period Loading mode is the default loading mode.

  • Page 445: Figure 6.9-12 Period Loading In Up-Count Mode

    M451 point 1 point 2 point 3 point 4 point 5 point 6 PERIOD PERIOD DATA0 PERIOD DATA1 PERIOD DATA2 PBUF PERIOD DATA0 PERIOD DATA1 PERIOD DATA2 CMPDAT CMPDAT DATA1 CMPDAT DATA1 CMPBUF PERIOD DATA1 PERIOD DATA0 PERIOD DATA2 CMPDAT DATA1 CMPDAT DATA0 CMPU Note:...

  • Page 446: Figure 6.9-13 Immediately Loading In Up-Count Mode

    M451 point 1 point 2 point 3 PERIOD PERIOD DATA0 PERIOD DATA1 PERIOD DATA2 PBUF PERIOD DATA0 PERIOD DATA1 PERIOD DATA2 CMPDAT CMPDAT DATA1 CMPBUF CMPDAT DATA1 CNT wraparound 0xFFFF PERIOD DATA1 PERIOD DATA0 CMPDAT DATA1 PERIOD DATA2 CMPDAT DATA0 CMPU Note: Write...

  • Page 447: Figure 6.9-14 Window Loading In Up-Count Mode

    M451 point 3 point 7 point 1 point 2 point 4 point 5 point 6 point 8 point 9 PERIOD PERIOD DATA0 PERIOD DATA 3 PERIOD DATA2 PERIOD DATA1 PBUF PERIOD DATA0 PERIOD DATA1 PERIOD DATA2 PERIOD DATA3 CMPDAT CMPDAT DATA1 CMPBUF CMPDAT DATA0 CMPDAT DATA1...

  • Page 448: Figure 6.9-15 Center Loading In Up-Down-Count Mode

    M451 point 1 point 2 point 3 point 4 point 5 point 6 point 7 point 8 PERIOD PERIOD DATA0 PERIOD DATA1 PERIOD DATA2 PBUF PERIOD DATA0 PERIOD DATA1 PERIOD DATA2 CMPDAT CMPDAT DATA1 CMPDAT DATA2 CMPBUF CMPDAT DATA0 CMPDAT DATA1 CMPDAT DATA2 PERIOD DATA1 PERIOD DATA0...

  • Page 449: Figure 6.9-16 Pwm One-Shot Mode Output Waveform

    M451 point 1 point 2 point 3 point 4 point 5 point 6 PERIOD DATA1 Continuous one- One-shot shot PERIOD DATA0 CMPDAT DATA3 CMPDAT DATA0 PWM OUT Note: Write Load Figure 6.9-16 PWM One-shot Mode Output Waveform In Auto-reload mode, CMPDAT and PERIOD should be written first and then the CNTENn channel n corresponding bit is set to 1 to enable PWM prescaler and start to run counter.

  • Page 450: Figure 6.9-17 Pwm Pulse Generation

    M451 Center Center CMPDATm CMPDATm CMPDATn CMPDATn Zero Zero PWM OUT PWM OUT PWM period PWM period Note: 1. Zero = L Note: 1. Zero = H 2. CMPUn = X 2. CMPUn = T 3. CMPUm = H 3. CMPUm = H 4.

  • Page 451: Figure 6.9-19 Pwm Independent Mode Waveform

    M451 1 (Highest) CNT = zero CNT = CMPDm CNT = CMPDn 4 (Lowest) CNT = period (PERIOD) Table 6-15 PWM Pulse Generation Event Priority for Down-Counter Priority Up Event Down Event 1 (Highest) CNT = CMPUm CNT = CMPDm CNT= CMPUn CNT = CMPDn CNT = zero...

  • Page 452: Figure 6.9-20 Pwm Complementary Mode Waveform

    M451 6.9.5.16 Complementary mode Complementary mode is enabled when the pair channel corresponding OUTMODEn (PWM_CTL1[26:24]) bit set to 1. In this mode there are 3 PWM generators utilized for complementary mode, with total of 3 PWM output paired pins in this module. In Complimentary modes, the internal odd PWM signal must always be the complement of the corresponding even PWM signal.

  • Page 453: Figure 6.9-21 Pwm Group Function Waveform

    M451 Setting: GROUPEN (PWM_CTL0[24]) = 0x1 Setting: OUTMODE0 (PWM_CTL1[24]) = 0x1 PWM_CH0 PWM_CH1 Setting: OUTMODE2 (PWM_CTL1[25]) = 0x1 PWM_CH2 PWM_CH3 Setting: OUTMODE4 (PWM_CTL1[26]) = 0x1 PWM_CH4 PWM_CH5 Figure 6.9-21 PWM Group Function Waveform 6.9.5.19 Synchronous function Synchronous function can only be enabled when complementary mode is enabled. Figure 6.9-23 is counter synchronous function block diagram.

  • Page 454: Figure 6.9-23 Pwm Counter Synchronous Function Block Diagram

    M451 The SYNC_OUT of the first PWM0 pair counter outputs not only to the next PWM0 pair counter SYNC_IN, but also outputs to PWM0_SYNC_OUT pin for different chip counters synchronization and the last pair of PWM0 will generate SYNC_OUT signal to the first pair counter of PWM1. By default setting, SYNC_IN “OR”...

  • Page 455: Figure 6.9-24 Pwm Synchronous Function With Sinsrc=0

    M451 CH0_PERIOD = 900 CH0_PERIOD = 600 PHSDIR0 = 1 (PWM_SYNC[24]) PHS = 0 (PWM_PHS0) PWM SYNC input PWM_CH0 PWM period PWM period PWM period CH2_PERIOD = 900 CH2_CMPDAT = 600 PHSDIR2 = 0 (PWM_SYNC[25]) PHS = 600 (PWM_PHS2) PWM_CH2 PWM period PWM period PWM period...

  • Page 456: Figure 6.9-26 Pwm_Ch0 And Pwm_Ch1 Output Control In Complementary Mode

    M451 Complementary Dead Time Insertion PWM_CH0 Independent Mode PWM_ Dead Time Four Steps WGCTL0 Insert0 12-bits PWM_CH1 Dead Time Independent Mode Insert0 12-bits Four Steps DTEN (PWM_DTCTL0[16]) DTCNT (PWM_DTCTL0[11:0]) Figure 6.9-26 PWM_CH0 and PWM_CH1 Output Control in Complementary Mode 6.9.5.21 Dead-Time Insertion In the complementary application, the complement channels may drive the external devices like power switches.

  • Page 457: Figure 6.9-27 Dead-Time Insertion

    M451 PWM_CH0 without Dead-Time PWM_CH1 without Dead-Time PWM_CH0 with Dead-Time PWM_CH1 with Dead-Time Dead-Time Interval Effect of Dead-Time for complementary pairs Figure 6.9-27 Dead-Time Insertion 6.9.5.22 PWM Mask Output Function Each of the PWM channel output value can be manually overridden with the settings in the PWM Mask Enable Control Register (PWM_MSKEN) and the PWM Masked Data Register (PWM_MSK) With these settings, the PWM channel outputs can be assigned to specified logic states independent of the duty cycle comparison units.

  • Page 458: Figure 6.9-29 Brake Noise Filter Block Diagram

    M451 recognize the effective edge of the brake signal. Configuring the BRKxNFEN (PWM_BNF[8, 0]) will enable the noise filter function. By default, it is disabled. In M45xD/M45xC, external brake input pin can be selected by setting BK0SRC (PWM_BNF[16]) and BK1SRC (PWM_BNF[24]) as Figure 6.9-33.

  • Page 459: Figure 6.9-30 Brake Block Diagram For Pwm_Ch0 And Pwm_Ch1 Pair

    M451 BRKEIF0 or BRKEIF1 (PWM_INTSTS1[1:0]) Edge Detect Edge Detect Brake Interrupt Brake Source BRKEIEN0_1 (PWM_INTEN1[0]) BRK_INT BRKLIF0 or BRKLIF1 (PWM_INTSTS1[9:8]) Level Detect Brake Interrupt BRKLIEN0_1 (PWM_INTEN1[8]) BRKLSTS0 (PWM_INTSTS1[24]) BRKAEVEN BRKESTS0 (PWM_BRKCTL0[17:16]) (PWM_INTSTS1[16]) PWM_OUT0 Level Detect Low level Brake Source detection PWM_OUT1 BRKAODD BRKESTS1(PWM_INTSTS1[17])

  • Page 460: Figure 6.9-31 Edge Detector Waveform For Pwm_Ch0 And Pwm_Ch1 Pair

    M451 Setting: BRKAEVEN = 3 (High) BRKAODD = 2 (Low) Edge Detect Brake Source BRKEIF0 s/w clear BRKEIF1 s/w clear BRKESTS0 BRKESTS1 PWM_CH0 PWM_CH1 PWM_CH0 signals resume at next start PWM_CH1 signals resume at next start of PWM period after BRKEIF0 clear of PWM period after BRKEIF1 clear Note: Output Brake State...

  • Page 461: Figure 6.9-33 Brake Source Block Diagram

    M451 6.9-33. Among the above described brake sources, the brake source coming from system fail can still be specified to several different system fail conditions. These conditions include clock fail, Brown-out detect, SRAM parity check error and Cortex -M4 lockup. Figure 6.9-34 shows that by setting corresponding enable bits, the enabled system fail condition can be one of the sources to issue the Brake system fail to the PWM brake.

  • Page 462: Figure 6.9-35 Initial State And Polarity Control With Rising Edge Dead-Time Insertion

    M451 high. This implies the PWM OFF state is low and ON state is high. This definition is variable through setting the PWM Negative Polarity Control Register (PWM_POLCTL), for each individual PWM channel. Figure 6.9-35 shows the initial state before PWM starting with different polarity settings.

  • Page 463: Figure 6.9-36 Pwm_Ch0 And Pwm_Ch1 Pair Accumulate Interrupt Waveform

    M451 IFSEL4_5 (PWM_IFA[22:20])), user can select one of the 8 interrupt sources to accumulate, and compare with 4 bits IFCNTn_m (IFCNT0_1 (PWM_IFA[3:0]), IFCNT2_3 (PWM_IFA[11:8]) and IFCNT4_5 (PWM_IFA[19:16])), when interrupt accumulator equals IFCNTn_m then set IFAIFn_m (IFAIF0_1 (PWM_INTSTS0[7]), IFAIF2_3 (PWM_INTSTS0[15]) and IFAIF4_5 (PWM_INTSTS0[23])) as PWM_INT signal when enable IFAIENn_m (IFAIEN0_1 (PWM_INTEN0[7]), IFAIEN2_3 (PWM_INTEN0[15]) and IFAEN4_5 (PWM_INTEN0[23])).

  • Page 464: Figure 6.9-37 Pwm_Ch0 And Pwm_Ch1 Pair Interrupt Architecture Diagram

    M451 ZIF0 (PWM_INTSTS0[0]) ZIEN0 (PWM_INTEN0[0]) PIF0 (PWM_INTSTS0[8]) PIEN0 (PWM_INTEN0[8]) CMPUIF0 (PWM_INTSTS0[16]) CMPUIEN0 (PWM_INTEN0[16]) CMPDIF0 (PWM_INTSTS0[24]) CMPDIEN0 (PWM_INTEN0[24]) ZIF1 (PWM_INTSTS0[1]) ZIEN1 (PWM_INTEN0[1]) PIF1 (PWM_INTSTS0[9]) PIEN1 (PWM_INTEN0[9]) CMPUIF1 (PWM_INTSTS0[17]) CMPUIEN1 (PWM_INTEN0[17]) IFAEN0_1 (PWM_IFA[7]) CMPDIF1 (PWM_INTSTS0[25]) CMPDIEN1 (PWM_INTEN0[25]) PWM_INT IFSEL0_1 (PWM_IFA[6:4]) PWM_CH0 zero point IFAIEN0_1 (PWM_INTEN0[7]) PWM_CH0 period point...

  • Page 465: Figure 6.9-38 Pwm_Ch0 And Pwm_Ch1 Pair Trigger Eadc Block Diagram

    M451 6.9.5.26 PWM Trigger EADC/DAC Generator PWM can be one of the EADC conversion trigger source. Each PWM pair channels share the same trigger source. Setting TRGSELn is to select the trigger sources, where TRGSELn is TRGSEL0, TRGSEL1, …, and TRGSEL5, which are located in PWM_EADCTS0[3:0], PWM_EADCTS0[11:8], PWM_EADCTS0[19:16], PWM_EADCTS0[27:24], PWM_EADCTS1[3:0] and PWM_EADTS1[11:8], respectively.

  • Page 466: Figure 6.9-39 Pwm Trigger Eadc In Up-Down Counter Type Timing Waveform

    M451 PWM_PERIODn PWM_CMPDATn PWM_FTCMPDATn PWM_CNTn zero point trigger period point trigger CMPU point trigger CMPD point trigger FTCMPU point trigger FTCMPD point trigger Figure 6.9-39 PWM Trigger EADC in Up-Down Counter Type Timing Waveform PWM can also be used to trigger DAC conversion. Each PWM pair channel (CH0 and CH1, CH2 and CH3, CH4 and CH5) generates a trigger signal.

  • Page 467: Figure 6.9-41 Pwm_Ch0 Capture Block Diagram

    M451 counter to the register RCAPDATn (PWM_RCAPDATn[15:0]) or the register FCAPDATn (PWM_FCAPDATn[15:0]) if the input channel has a rising transition or a falling transition, respectively. The capture function will also generate an interrupt CAP_INT (using PWM_INT vector) if the rising or falling latch occurs and the corresponding channel n’s rising or falling interrupt enable bits are set, where the CAPRIENn (PWM_CAPIEN[5:0]) is for the rising edge and the CAPFIENn (PWM_CAPIEN[13:8]) is for the falling edge.

  • Page 468: Figure 6.9-42 Capture Operation Waveform

    M451 When the rising edge at channel n is detected, the corresponding bit CRLIFn (PWM_CAPIF[5:0]) is set by hardware. Similarly, a falling edge detection at chnnel n causes the corresponding bit CFLIFn (PWM_CAPIF[13:8]) set by hardware. CRLIFn and CFLIFn can be cleared by software by writing ‘1’.

  • Page 469: Figure 6.9-43 Capture Pdma Operation Waveform Of Channel 0

    M451 6.9.5.28 Capture PDMA Function The PWM module supports the PDMA transfer function when operating in the capture mode. When the corresponding PDMA enable bit CHENn_m (CHEN0_1 at PWM_PDMACTL[0], CHEN2_3 at PWM_PDMACTL[8] and CHEN4_5 at PWM_PDMACTL[16], where n and m denote complement pair channels) is set, the capture module will issue a request to PDMA controller when the preceding capture event has happened.

  • Page 470: Register Map

    M451 6.9.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value PWM Base Address: PWM0_BA = 0x4005_8000 PWM1_BA = 0x4005_9000 PWM_CTL0 PWMx_BA+0x00 R/W PWM Control Register 0 0x0000_0000 x=0, 1 PWM_CTL1 PWMx_BA+0x04 R/W PWM Control Register 1...
  • Page 471 M451 x=0, 1 PWM_CMPDAT0 PWMx_BA+0x50 R/W PWM Comparator Register 0 0x0000_0000 x=0, 1 PWM_CMPDAT1 PWMx_BA+0x54 R/W PWM Comparator Register 1 0x0000_0000 x=0, 1 PWM_CMPDAT2 PWMx_BA+0x58 R/W PWM Comparator Register 2 0x0000_0000 x=0, 1 PWM_CMPDAT3 PWMx_BA+0x5C R/W PWM Comparator Register 3 0x0000_0000 x=0, 1 PWM_CMPDAT4...
  • Page 472 M451 PWM_WGCTL1 PWMx_BA+0xB4 R/W PWM Generation Register 1 0x0000_0000 x=0, 1 PWM_MSKEN PWMx_BA+0xB8 R/W PWM Mask Enable Register 0x0000_0000 x=0, 1 PWM_MSK PWMx_BA+0xBC R/W PWM Mask Data Register 0x0000_0000 x=0, 1 PWM_BNF PWMx_BA+0xC0 R/W PWM Brake Noise Filter Register 0x0000_0000 x=0, 1 PWM_FAILBRK PWMx_BA+0xC4...
  • Page 473 M451 PWM_FTCMPDA T0_1 PWMx_BA+0x100 R/W PWM Free Trigger Compare Register 0 0x0000_0000 x=0, 1 PWM_FTCMPDA T2_3 PWMx_BA+0x104 R/W PWM Free Trigger Compare Register 2 0x0000_0000 x=0, 1 PWM_FTCMPDA T4_5 PWMx_BA+0x108 R/W PWM Free Trigger Compare Register 4 0x0000_0000 x=0, 1 PWM_SSCTL PWMx_BA+0x110 R/W PWM Synchronous Start Control Register 0x0000_0000...
  • Page 474 M451 PWM_RCAPDAT PWMx_BA+0x22C R PWM Rising Capture Data Register 4 0x0000_0000 x=0, 1 PWM_FCAPDAT PWMx_BA+0x230 R PWM Falling Capture Data Register 4 0x0000_0000 x=0, 1 PWM_RCAPDAT PWMx_BA+0x234 R PWM Rising Capture Data Register 5 0x0000_0000 x=0, 1 PWM_FCAPDAT PWMx_BA+0x238 R PWM Falling Capture Data Register 5 0x0000_0000 x=0, 1...
  • Page 475 M451 x=0, 1 PWM_CMPBUF3 PWMx_BA+0x328 R PWM CMPDAT3 Buffer 0x0000_0000 x=0, 1 PWM_CMPBUF4 PWMx_BA+0x32C R PWM CMPDAT4 Buffer 0x0000_0000 x=0, 1 PWM_CMPBUF5 PWMx_BA+0x330 R PWM CMPDAT5 Buffer 0x0000_0000 x=0, 1 PWM_FTCBUF0 PWMx_BA+0x340 R PWM FTCMPDAT0_1 Buffer 0x0000_0000 x=0, 1 PWM_FTCBUF2 PWMx_BA+0x344 R PWM FTCMPDAT2_3 Buffer 0x0000_0000...

  • Page 476: Register Description

    M451 6.9.7 Register Description PWM Control Register 0 (PWM_CTL0) Register Offset Description Reset Value PWM_CTL0 PWMx_BA+0x00 PWM Control Register 0 0x0000_0000 DBGTRIOFF DBGHALT Reserved GROUPEN Reserved IMMLDEN5 IMMLDEN4 IMMLDEN3 IMMLDEN2 IMMLDEN1 IMMLDEN0 Reserved WINLDEN5 WINLDEN4 WINLDEN3 WINLDEN2 WINLDEN1 WINLDEN0 Reserved CTRLD5 CTRLD4 CTRLD3...
  • Page 477 M451 [15:14] Reserved Reserved. Window Load Enable Bit Each bit n controls the corresponding PWM channel n. 0 = PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. [13:8] WINLDENn 1 = PERIOD will load to PBUF at the end point of each period.
  • Page 478 M451 PWM Control Register 1 (PWM_CTL1) Register Offset Description Reset Value PWM_CTL1 PWMx_BA+0x04 PWM Control Register 1 0x0000_0000 Reserved OUTMODE4 OUTMODE2 OUTMODE0 Reserved CNTMODE5 CNTMODE4 CNTMODE3 CNTMODE2 CNTMODE1 CNTMODE0 Reserved CNTTYPE5 CNTTYPE4 CNTTYPE3 CNTTYPE2 CNTTYPE1 CNTTYPE0 Bits Description [31:27] Reserved Reserved.
  • Page 479 M451 PWM Synchronization Register (PWM_SYNC) Register Offset Description Reset Value PWM_SYNC PWMx_BA+0x08 PWM Synchronization Register 0x0000_0000 Reserved PHSDIR4 PHSDIR2 PHSDIR0 SINPINV SFLTCNT SFLTCSEL SNFLTEN Reserved SINSRC4 SINSRC2 SINSRC0 Reserved PHSEN4 PHSEN2 PHSEN0 Bits Description [31:27] Reserved Reserved. PWM Phase Direction Control Each bit n controls corresponding PWM channel n.
  • Page 480 M451 01 = Counter equal to 0. 10 = Counter equal to PWM_CMPDATm, m denotes 1, 3, 5. 11 = SYNC_OUT will not be generated. [7:3] Reserved Reserved. SYNC Phase Enable Bit Each bit n controls corresponding PWM channel n. [2:0] PHSENn 0 = PWM counter load PHS value Disabled.
  • Page 481 M451 PWM Software Control Synchronization Register (PWM_SWSYNC) Register Offset Description Reset Value PWM_SWSYN PWMx_BA+0x0C PWM Software Control Synchronization Register 0x0000_0000 Reserved Reserved Reserved Reserved SWSYNC4 SWSYNC2 SWSYNC0 Bits Description [31:3] Reserved Reserved. Software SYNC Function Each bit n controls corresponding PWM channel n. [2:0] SWSYNCn When SINSRCn (PWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from...
  • Page 482 M451 PWM Clock Source Register (PWM_CLKSRC) Register Offset Description Reset Value PWM_CLKSR PWMx_BA+0x10 PWM Clock Source Register 0x0000_0000 Reserved Reserved ECLKSRC4 Reserved ECLKSRC2 Reserved ECLKSRC0 Bits Description [31:19] Reserved Reserved. PWM_CH45 External Clock Source Select 000 = PWMx_CLK, x denotes 0 or 1. 001 = TIMER0 overflow.
  • Page 483 M451 PWM Clock Pre-Scale Register 0_1, 2_3, 4_5 (PWM_CLKPSC0_1, 2_3, 4_5) Register Offset Description Reset Value PWM_CLKPS PWMx_BA+0x14 PWM Clock Pre-scale Register 0 0x0000_0000 C0_1 PWM_CLKPS PWMx_BA+0x18 PWM Clock Pre-scale Register 2 0x0000_0000 C2_3 PWM_CLKPS PWMx_BA+0x1C PWM Clock Pre-scale Register 4 0x0000_0000 C4_5 Reserved...
  • Page 484 M451 PWM Counter Enable Register (PWM_CNTEN) Register Offset Description Reset Value PWM_CNTEN PWMx_BA+0x20 PWM Counter Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved CNTEN5 CNTEN4 CNTEN3 CNTEN2 CNTEN1 CNTEN0 Bits Description [31:6] Reserved Reserved. PWM Counter Enable Bits Each bit n controls the corresponding PWM channel n. [5:0] CNTENn 0 = PWM Counter and clock prescaler Stop Running.
  • Page 485 M451 PWM Clear Counter Register (PWM_CNTCLR) Register Offset Description Reset Value PWM_CNTCL PWMx_BA+0x24 PWM Clear Counter Register 0x0000_0000 Reserved Reserved Reserved Reserved CNTCLR5 CNTCLR4 CNTCLR3 CNTCLR2 CNTCLR1 CNTCLR0 Bits Description [31:6] Reserved Reserved. Clear PWM Counter Control Bit It is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n.
  • Page 486 M451 PWM Load Register (PWM_LOAD) Register Offset Description Reset Value PWM_LOAD PWMx_BA+0x28 PWM Load Register 0x0000_0000 Reserved Reserved Reserved Reserved LOAD5 LOAD4 LOAD3 LOAD2 LOAD1 LOAD0 Bits Description [31:6] Reserved Reserved. Re-load PWM Comparator Register (CMPDAT) Control Bit This bit is software write, hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n.
  • Page 487 M451 PWM Period Register 0~5 (PWM_PERIOD0~5) Register Offset Description Reset Value PWM_PERIO PWMx_BA+0x30 PWM Period Register 0 0x0000_0000 PWM_PERIO PWMx_BA+0x34 PWM Period Register 1 0x0000_0000 PWM_PERIO PWMx_BA+0x38 PWM Period Register 2 0x0000_0000 PWM_PERIO PWMx_BA+0x3C PWM Period Register 3 0x0000_0000 PWM_PERIO PWMx_BA+0x40 PWM Period Register 4 0x0000_0000...
  • Page 488 M451 PWM Comparator Register 0~5 (PWM_CMPDAT0~5) Register Offset Description Reset Value PWM_CMPDA PWMx_BA+0x50 PWM Comparator Register 0 0x0000_0000 PWM_CMPDA PWMx_BA+0x54 PWM Comparator Register 1 0x0000_0000 PWM_CMPDA PWMx_BA+0x58 PWM Comparator Register 2 0x0000_0000 PWM_CMPDA PWMx_BA+0x5C PWM Comparator Register 3 0x0000_0000 PWM_CMPDA PWMx_BA+0x60 PWM Comparator Register 4 0x0000_0000...
  • Page 489 M451 PWM Dead-Time Control Register 0_1, 2_3, 4_5 (PWM_DTCTL0_1, 2_3, 4_5) Register Offset Description Reset Value PWM_DTCTL PWMx_BA+0x70 PWM Dead-Time Control Register 0 0x0000_0000 PWM_DTCTL PWMx_BA+0x74 PWM Dead-Time Control Register 2 0x0000_0000 PWM_DTCTL PWMx_BA+0x78 PWM Dead-Time Control Register 4 0x0000_0000 Reserved DTCKSEL Reserved...
  • Page 490 M451 PWM Counter Phase Register 0_1, 2_3, 4_5 (PWM_PHS0_1, 2_3, 4_5) Register Offset Description Reset Value PWM_PHS0_1 PWMx_BA+0x80 PWM Counter Phase Register 0 0x0000_0000 PWM_PHS2_3 PWMx_BA+0x84 PWM Counter Phase Register 2 0x0000_0000 PWM_PHS4_5 PWMx_BA+0x88 PWM Counter Phase Register 4 0x0000_0000 Reserved Reserved Bits...
  • Page 491 M451 PWM Counter Register 0~5 (PWM_CNT0~5) Register Offset Description Reset Value PWM_CNT0 PWMx_BA+0x90 PWM Counter Register 0 0x0000_0000 PWM_CNT1 PWMx_BA+0x94 PWM Counter Register 1 0x0000_0000 PWM_CNT2 PWMx_BA+0x98 PWM Counter Register 2 0x0000_0000 PWM_CNT3 PWMx_BA+0x9C PWM Counter Register 3 0x0000_0000 PWM_CNT4 PWMx_BA+0xA0 PWM Counter Register 4 0x0000_0000...
  • Page 492 M451 PWM Generation Register 0 (PWM_WGCTL0) Register Offset Description Reset Value PWM_WGCTL PWMx_BA+0xB0 PWM Generation Register 0 0x0000_0000 Reserved PRDPCTL5 PRDPCTL4 PRDPCTL3 PRDPCTL2 PRDPCTL1 PRDPCTL0 Reserved ZPCTL5 ZPCTL4 ZPCTL3 ZPCTL2 ZPCTL1 ZPCTL0 Bits Description [31:28] Reserved Reserved. PWM Period (Center) Point Control Each bit n controls the corresponding PWM channel n.
  • Page 493 M451 PWM Generation Register 1 (PWM_WGCTL1) Register Offset Description Reset Value PWM_WGCTL PWMx_BA+0xB4 PWM Generation Register 1 0x0000_0000 Reserved CMPDCTL5 CMPDCTL4 CMPDCTL3 CMPDCTL2 CMPDCTL1 CMPDCTL0 Reserved CMPUCTL5 CMPUCTL4 CMPUCTL3 CMPUCTL2 CMPUCTL1 CMPUCTL0 Bits Description [31:28] Reserved Reserved. PWM Compare Down Point Control Each bit n controls the corresponding PWM channel n.
  • Page 494 M451 PWM Mask Enable Register (PWM_MSKEN) Register Offset Description Reset Value PWM_MSKEN PWMx_BA+0xB8 PWM Mask Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved MSKEN5 MSKEN4 MSKEN3 MSKEN2 MSKEN1 MSKEN0 Bits Description [31:6] Reserved Reserved. PWM Mask Enable Bits Each bit n controls the corresponding PWM channel n. The PWM output signal will be masked when this bit is enabled.
  • Page 495 M451 PWM Mask DATA Register (PWM_MSK) Register Offset Description Reset Value PWM_MSK PWMx_BA+0xBC PWM Mask Data Register 0x0000_0000 Reserved Reserved Reserved Reserved MSKDAT5 MSKDAT4 MSKDAT3 MSKDAT2 MSKDAT1 MSKDAT0 Bits Description [31:6] Reserved Reserved. PWM Mask Data Bit This data bit control the state of PWMn output pin, if corresponding mask function is enabled.
  • Page 496 M451 PWM Brake Noise Filter Register (PWM_BNF) Register Offset Description Reset Value PWM_BNF PWMx_BA+0xC0 PWM Brake Noise Filter Register 0x0000_0000 Reserved BK1SRC Reserved BK0SRC BRK1PINV BRK1FCNT BRK1NFSEL BRK1NFEN BRK0PINV BRK0FCNT BRK0NFSEL BRK0NFEN Bits Description [31:25] Reserved Reserved. Brake 1 Pin Source Select (M45xD/M45xC Only) For PWM0 setting: 0 = Brake 1 pin source come from PWM0_BRAKE1.
  • Page 497 M451 100 = Filter clock = HCLK/16. 101 = Filter clock = HCLK/32. 110 = Filter clock = HCLK/64. 111 = Filter clock = HCLK/128. PWM Brake 1 Noise Filter Enable Bit BRK1NFEN 0 = Noise filter of PWM Brake 1 Disabled. 1 = Noise filter of PWM Brake 1 Enabled.
  • Page 498 M451 PWM System Fail Brake Control Register (PWM_FAILBRK) Register Offset Description Reset Value PWM_FAILBR PWMx_BA+0xC4 PWM System Fail Brake Control Register 0x0000_0000 Reserved Reserved Reserved Reserved CORBRKEN RAMBRKEN BODBRKEN CSSBRKEN Bits Description [31:4] Reserved Reserved. Core Lockup Detection Trigger PWM Brake Function 0 Enable Bit CORBRKEN 0 = Brake Function triggered by Core lockup detection Disabled.
  • Page 499 M451 PWM Brake Edge Detect Control Register 0_1, 2_3, 4_5 (PWM_BRKCTL0_1, 2_3, 4_5) Register Offset R/W Description Reset Value PWM_BRKCTL0_ PWMx_BA+0xC8 R/W PWM Brake Edge Detect Control Register 0 0x0000_0000 PWM_BRKCTL2_ PWMx_BA+0xCC R/W PWM Brake Edge Detect Control Register 2 0x0000_0000 PWM_BRKCTL4_ PWMx_BA+0xD0...
  • Page 500 M451 BKP0 Pin As Level-detect Brake Source Enable Bit (Write Protect) 0 = PWMx_BRAKE0 pin as level-detect brake source Disabled. [12] BRKP0LEN 1 = PWMx_BRAKE0 pin as level-detect brake source Enabled. Note: This register is write protected. Refer to SYS_REGLCTL register. [11:10] Reserved Reserved.
  • Page 501 M451 PWM Pin Polar Inverse Control (PWM_POLCTL) Register Offset Description Reset Value PWM_POLCT PWMx_BA+0xD4 PWM Pin Polar Inverse Register 0x0000_0000 Reserved Reserved Reserved Reserved PINV5 PINV4 PINV3 PINV2 PINV1 PINV0 Bits Description [31:6] Reserved Reserved. PWM PIN Polar Inverse Control Bits The register controls polarity state of PWM output.
  • Page 502 M451 PWM Output Enable Register (PWM_POEN) Register Offset Description Reset Value PWM_POEN PWMx_BA+0xD8 PWM Output Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved POEN5 POEN4 POEN3 POEN2 POEN1 POEN0 Bits Description [31:6] Reserved Reserved. PWM Pin Output Enable Bits Each bit n controls the corresponding PWM channel n. [5:0] POENn 0 = PWM pin at tri-state.
  • Page 503 M451 PWM Software Brake Control Register (PWM_SWBRK) Register Offset Description Reset Value PWM_SWBR PWMx_BA+0xDC PWM Software Brake Control Register 0x0000_0000 Reserved Reserved Reserved BRKLTRG4 BRKLTRG2 BRKLTRG0 Reserved BRKETRG4 BRKETRG2 BRKETRG0 Bits Description [31:11] Reserved Reserved. PWM Level Brake Software Trigger (Write Only) (Write Protect) Each bit n controls the corresponding PWM pair n.
  • Page 504 M451 PWM Interrupt Enable Register 0 (PWM_INTEN0) Register Offset Description Reset Value PWM_INTEN0 PWMx_BA+0xE0 PWM Interrupt Enable Register 0 0x0000_0000 Reserved CMPDIEN5 CMPDIEN4 CMPDIEN3 CMPDIEN2 CMPDIEN1 CMPDIEN0 IFAIEN4_5 Reserved CMPUIEN5 CMPUIEN4 CMPUIEN3 CMPUIEN2 CMPUIEN1 CMPUIEN0 IFAIEN2_3 Reserved PIEN5 PIEN4 PIEN3 PIEN2 PIEN1 PIEN0...
  • Page 505 M451 PWM_CH0/1 Interrupt Flag Accumulator Interrupt Enable Bit IFAIEN0_1 0 = Interrupt Flag accumulator interrupt Disabled. 1 = Interrupt Flag accumulator interrupt Enabled. Reserved Reserved. PWM Zero Point Interrupt Enable Bits Each bit n controls the corresponding PWM channel n. [5:0] ZIENn 0 = Zero point interrupt Disabled.
  • Page 506 M451 PWM Interrupt Enable Register 1 (PWM_INTEN1) Register Offset Description Reset Value PWM_INTEN1 PWMx_BA+0xE4 PWM Interrupt Enable Register 1 0x0000_0000 Reserved Reserved Reserved BRKLIEN4_5 BRKLIEN2_3 BRKLIEN0_1 Reserved BRKEIEN4_5 BRKEIEN2_3 BRKEIEN0_1 Bits Description [31:11] Reserved Reserved. PWM Level-detect Brake Interrupt Enable Bit for Channel4/5 (Write Protect) 0 = Level-detect Brake interrupt for channel4/5 Disabled.
  • Page 507 M451 PWM Interrupt Flag Register 0 (PWM_INTSTS0) Register Offset Description Reset Value PWM_INTSTS PWMx_BA+0xE8 PWM Interrupt Flag Register 0 0x0000_0000 Reserved CMPDIF5 CMPDIF4 CMPDIF3 CMPDIF2 CMPDIF1 CMPDIF0 IFAIF4_5 Reserved CMPUIF5 CMPUIF4 CMPUIF3 CMPUIF2 CMPUIF1 CMPUIF0 IFAIF2_3 Reserved PIF5 PIF4 PIF3 PIF2 PIF1 PIF0...
  • Page 508 M451 Flag is set by hardware when condition match IFSEL0_1 in PWM_IFA register, software can clear this bit by writing 1 to it. Reserved Reserved. PWM Zero Point Interrupt Flag Each bit n controls the corresponding PWM channel n. [5:0] ZIFn This bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero.
  • Page 509 M451 PWM Interrupt Flag Register 1 (PWM_INTSTS1) Register Offset Description Reset Value PWM_INTSTS PWMx_BA+0xEC PWM Interrupt Flag Register 1 0x0000_0000 Reserved BRKLSTS5 BRKLSTS4 BRKLSTS3 BRKLSTS2 BRKLSTS1 BRKLSTS0 Reserved BRKESTS5 BRKESTS4 BRKESTS3 BRKESTS2 BRKESTS1 BRKESTS0 Reserved BRKLIF5 BRKLIF4 BRKLIF3 BRKLIF2 BRKLIF1 BRKLIF0 Reserved BRKEIF5...
  • Page 510 M451 0 = PWM channel1 level-detect brake state is released. 1 = When PWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel1 at brake state. Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
  • Page 511 M451 PWM Channel3 Level-detect Brake Interrupt Flag (Write Protect) 0 = PWM channel3 level-detect brake event do not happened. [11] BRKLIF3 1 = When PWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear. Note: This register is write protected.
  • Page 512 M451 1 = When PWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. Note: This register is write protected. Refer to SYS_REGLCTL register. May. 4, 2018 Page 512 of 1006 Rev.2.08...
  • Page 513 M451 PWM Interrupt Flag Accumulator Register (PWM_IFA) Register Offset Description Reset Value PWM_IFA PWMx_BA+0xF0 PWM Interrupt Flag Accumulator Register 0x0000_0000 Reserved IFAEN4_5 IFSEL4_5 IFCNT4_5 IFAEN2_3 IFSEL2_3 IFCNT2_3 IFAEN0_1 IFSEL0_1 IFCNT0_1 Bits Description [31:24] Reserved Reserved. PWM_CH4 and PWM_CH5 Interrupt Flag Accumulator Enable Bit [23] IFAEN4_5 0 = PWM_CH4 and PWM_CH5 interrupt flag accumulator Disabled.
  • Page 514 M451 110 = CNT equal to CMPU in channel 3. 111 = CNT equal to CMPD in channel 3. PWM_CH2 and PWM_CH3 Interrupt Flag Counter The register sets the count number which defines how many times of PWM_CH2 and IFCNT2_3 [11:8] PWM_CH3 period occurs to set bit IFAIF2_3 to request the PWM period interrupt.
  • Page 515 M451 PWM Trigger DAC Enable Register (PWM_DACTRGEN) Register Offset Description Reset Value PWM_DACTR PWMx_BA+0xF4 PWM Trigger DAC Enable Register 0x0000_0000 Reserved CDTRGEN5 CDTRGEN4 CDTRGEN3 CDTRGEN2 CDTRGEN1 CDTRGEN0 Reserved CUTRGEN5 CUTRGEN4 CUTRGEN3 CUTRGEN2 CUTRGEN1 CUTRGEN0 Reserved PTE5 PTE4 PTE3 PTE2 PTE1 PTE0 Reserved ZTE5...
  • Page 516 M451 1 = PWM period point trigger DAC function Enabled. PWM can trigger EADC/DAC/DMA to start action when PWM counter down count to zero if this bit is set to1. Each bit n controls the corresponding PWM channel n. May. 4, 2018 Page 516 of 1006 Rev.2.08...
  • Page 517 M451 PWM Trigger EADC Source Select Register 0 (PWM_EADCTS0) Register Offset Description Reset Value PWM_EADCT PWMx_BA+0xF8 PWM Trigger EADC Source Select Register 0 0x0000_0000 TRGEN3 Reserved TRGSEL3 TRGEN2 Reserved TRGSEL2 TRGEN1 Reserved TRGSEL1 TRGEN0 Reserved TRGSEL0 Bits Description PWM_CH3 Trigger EADC Enable Bit TRGEN3 0 = PWM_CH3 Trigger EADC Disabled.
  • Page 518 M451 0000 = PWM_CH2 zero point. 0001 = PWM_CH2 period point. 0010 = PWM_CH2 zero or period point. 0011 = PWM_CH2 up-count CMPDAT point. 0100 = PWM_CH2 down-count CMPDAT point. 0101 = PWM_CH3 zero point. 0110 = PWM_CH3 period point. 0111 = PWM_CH3 zero or period point.
  • Page 519 M451 0101 = PWM_CH1 zero point. 0110 = PWM_CH1 period point. 0111 = PWM_CH1 zero or period point. 1000 = PWM_CH1 up-count CMPDAT point. 1001 = PWM_CH1 down-count CMPDAT point. 1010 = PWM_CH0 up-count free CMPDAT point. 1011 = PWM_CH0 down-count free CMPDAT point. 1100 = PWM_CH2 up-count free CMPDAT point.
  • Page 520 M451 PWM Trigger EADC Source Select Register 1 (PWM_EADCTS1) Register Offset Description Reset Value PWM_EADCT PWMx_BA+0xFC PWM Trigger EADC Source Select Register 1 0x0000_0000 Reserved Reserved TRGEN5 Reserved TRGSEL5 TRGEN4 Reserved TRGSEL4 Bits Description [31:16] Reserved Reserved. PWM_CH5 Trigger EADC Enable Bit [15] TRGEN5 0 = PWM_CH5 Trigger EADC Disabled.
  • Page 521 M451 PWM_CH4 Trigger EADC Source Select 0000 = PWM_CH4 zero point. 0001 = PWM_CH4 period point. 0010 = PWM_CH4 zero or period point. 0011 = PWM_CH4 up-count CMPDAT point. 0100 = PWM_CH4 down-count CMPDAT point. 0101 = PWM_CH5 zero point. 0110 = PWM_CH5 period point.
  • Page 522 M451 PWM Free Trigger Compare Register 0_1, 2_3, 4_5 (PWM_FTCMPDAT0_1, 2_3, 4_5) Register Offset Description Reset Value PWM_FTCMP PWMx_BA+0x100 R/W PWM Free Trigger Compare Register 0 0x0000_0000 DAT0_1 PWM_FTCMP PWMx_BA+0x104 R/W PWM Free Trigger Compare Register 2 0x0000_0000 DAT2_3 PWM_FTCMP PWMx_BA+0x108 R/W PWM Free Trigger Compare Register 4 0x0000_0000...
  • Page 523 M451 PWM Synchronous Start Control Register (PWM_SSCTL) Register Offset Description Reset Value PWMx_BA+0x11 PWM_SSCTL PWM Synchronous Start Control Register 0x0000_0000 Reserved Reserved Reserved Reserved SSEN5 SSEN4 SSEN3 SSEN2 SSEN1 SSEN0 Bits Description [31:6] Reserved Reserved. PWM Synchronous Start Function Enable Bits When synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
  • Page 524 M451 PWM Synchronous Start Trigger Register (PWM_SSTRG) Register Offset Description Reset Value PWMx_BA+0x11 PWM_SSTRG PWM Synchronous Start Trigger Register 0x0000_0000 Reserved Reserved Reserved Reserved CNTSEN Bits Description [31:1] Reserved Reserved. PWM Counter Synchronous Start Enable Bit (Write Only) PMW counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx and PWM1_CHx) start counting at the same time.
  • Page 525 M451 PWM Status Register (PWM_STATUS) Register Offset Description Reset Value PWM_STATU PWMx_BA+0x120 R/W PWM Status Register 0x0000_0000 Reserved DACTRGF Reserved ADCTRGF5 ADCTRGF4 ADCTRGF3 ADCTRGF2 ADCTRGF1 ADCTRGF0 Reserved SYNCINF4 SYNCINF2 SYNCINF0 Reserved CNTMAXF5 CNTMAXF4 CNTMAXF3 CNTMAXF2 CNTMAXF1 CNTMAXF0 Bits Description [31:25] Reserved Reserved.
  • Page 526 M451 PWM Capture Input Enable Register (PWM_CAPINEN) Register Offset Description Reset Value PWM_CAPIN PWMx_BA+0x200 R/W PWM Capture Input Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved CAPINEN5 CAPINEN4 CAPINEN3 CAPINEN2 CAPINEN1 CAPINEN0 Bits Description [31:6] Reserved Reserved. Capture Input Enable Bits Each bit n controls the corresponding PWM channel n.
  • Page 527 M451 PWM Capture Control Register (PWM_CAPCTL) Register Offset Description Reset Value PWM_CAPCT PWMx_BA+0x204 R/W PWM Capture Control Register 0x0000_0000 Reserved FCRLDEN5 FCRLDEN4 FCRLDEN3 FCRLDEN2 FCRLDEN1 FCRLDEN0 Reserved RCRLDEN5 RCRLDEN4 RCRLDEN3 RCRLDEN2 RCRLDEN1 RCRLDEN0 Reserved CAPINV5 CAPINV4 CAPINV3 CAPINV2 CAPINV1 CAPINV0 Reserved CAPEN5 CAPEN4...
  • Page 528 M451 PWM Capture Status Register (PWM_CAPSTS) Register Offset Description Reset Value PWM_CAPST PWMx_BA+0x208 R PWM Capture Status Register 0x0000_0000 Reserved Reserved Reserved CFLIFOV5 CFLIFOV4 CFLIFOV3 CFLIFOV2 CFLIFOV1 CFLIFOV0 Reserved CRLIFOV5 CRLIFOV4 CRLIFOV3 CRLIFOV2 CRLIFOV1 CRLIFOV0 Bits Description [31:14] Reserved Reserved. Capture Falling Latch Interrupt Flag Overrun Status (Read Only) This flag indicates if falling latch happened when the corresponding CFLIF is 1.
  • Page 529 M451 PWM Rising Capture Data Register 0~5 (PWM_RCAPDAT 0~5) Register Offset Description Reset Value PWM_RCAPD PWMx_BA+0x20C R PWM Rising Capture Data Register 0 0x0000_0000 PWM_RCAPD PWMx_BA+0x214 R PWM Rising Capture Data Register 1 0x0000_0000 PWM_RCAPD PWMx_BA+0x21C R PWM Rising Capture Data Register 2 0x0000_0000 PWM_RCAPD PWMx_BA+0x224 R...
  • Page 530 M451 PWM Falling Capture Data Register 0~5 (PWM_FCAPDAT 0~5) Register Offset Description Reset Value PWM_FCAPD PWMx_BA+0x210 R PWM Falling Capture Data Register 0 0x0000_0000 PWM_FCAPD PWMx_BA+0x218 R PWM Falling Capture Data Register 1 0x0000_0000 PWM_FCAPD PWMx_BA+0x220 R PWM Falling Capture Data Register 2 0x0000_0000 PWM_FCAPD PWMx_BA+0x228 R...
  • Page 531 M451 PWM PDMA Control Register (PWM_PDMACTL) Register Offset Description Reset Value PWM_PDMAC PWMx_BA+0x23C R/W PWM PDMA Control Register 0x0000_0000 Reserved Reserved CHSEL4_5 CAPORD4_5 CAPMOD4_5 CHEN4_5 Reserved CHSEL2_3 CAPORD2_3 CAPMOD2_3 CHEN2_3 Reserved CHSEL0_1 CAPORD0_1 CAPMOD0_1 CHEN0_1 Bits Description [31:21] Reserved Reserved. Select Channel 4/5 to Do PDMA Transfer [20] CHSEL4_5...
  • Page 532 M451 0 = PWM_FCAPDAT2/3 is the first captured data to memory. 1 = PWM_RCAPDAT2/3 is the first captured data to memory. [10:9] CAPMOD2_3 Select PWM_RCAPDAT2/3 or PWM_FCAODAT2/3 to Do PDMA Transfer 00 = Reserved. 01 = PWM_RCAPDAT2/3. 10 = PWM_FCAPDAT2/3. 11 = Both PWM_RCAPDAT2/3 and PWM_FCAPDAT2/3.
  • Page 533 M451 PWM Capture Channel 0_1, 2_3, 4_5 PDMA Register (PWM_PDMACAP 0_1, 2_3, 4_5) Register Offset Description Reset Value PWM_PDMAC PWMx_BA+0x240 R PWM Capture Channel 01 PDMA Register 0x0000_0000 AP0_1 PWM_PDMAC PWMx_BA+0x244 R PWM Capture Channel 23 PDMA Register 0x0000_0000 AP2_3 PWM_PDMAC PWMx_BA+0x248 R PWM Capture Channel 45 PDMA Register...
  • Page 534 M451 PWM Capture Interrupt Enable Register (PWM_CAPIEN) Register Offset Description Reset Value PWM_CAPIE PWMx_BA+0x250 R/W PWM Capture Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved CAPFIEN5 CAPFIEN4 CAPFIEN3 CAPFIEN2 CAPFIEN1 CAPFIEN0 Reserved CAPRIEN5 CAPRIEN4 CAPRIEN3 CAPRIEN2 CAPRIEN1 CAPRIEN0 Bits Description [31:14] Reserved Reserved.
  • Page 535 M451 PWM Capture Interrupt Flag Register (PWM_CAPIF) Register Offset Description Reset Value PWM_CAPIF PWMx_BA+0x254 R/W PWM Capture Interrupt Flag Register 0x0000_0000 Reserved Reserved Reserved CFLIF5 CFLIF4 CFLIF3 CFLIF2 CFLIF1 CFLIF0 Reserved CRLIF5 CRLIF4 CRLIF3 CRLIF2 CRLIF1 CRLIF0 Bits Description [31:14] Reserved Reserved.
  • Page 536 M451 PWM Period Register Buffer 0~5 (PWM_PBUF0~5) Register Offset Description Reset Value PWM_PBUF0 PWMx_BA+0x304 R PWM PERIOD0 Buffer 0x0000_0000 PWM_PBUF1 PWMx_BA+0x308 R PWM PERIOD1 Buffer 0x0000_0000 PWM_PBUF2 PWMx_BA+0x30C R PWM PERIOD2 Buffer 0x0000_0000 PWM_PBUF3 PWMx_BA+0x310 R PWM PERIOD3 Buffer 0x0000_0000 PWM_PBUF4 PWMx_BA+0x314 R PWM PERIOD4 Buffer 0x0000_0000...
  • Page 537 M451 PWM Comparator Register Buffer 0~5 (PWM_CMPBUF0~5) Register Offset Description Reset Value PWM_CMPBU PWMx_BA+0x31C R PWM CMPDAT0 Buffer 0x0000_0000 PWM_CMPBU PWMx_BA+0x320 R PWM CMPDAT1 Buffer 0x0000_0000 PWM_CMPBU PWMx_BA+0x324 R PWM CMPDAT2 Buffer 0x0000_0000 PWM_CMPBU PWMx_BA+0x328 R PWM CMPDAT3 Buffer 0x0000_0000 PWM_CMPBU PWMx_BA+0x32C R PWM CMPDAT4 Buffer...
  • Page 538 M451 PWM_FTCMPDAT Buffer (PWM_FTCBUF0_1,2_3,4_5) Register Offset Description Reset Value PWM_FTCBU PWMx_BA+0x340 R PWM FTCMPDAT0_1 Buffer 0x0000_0000 F0_1 PWM_FTCBU PWMx_BA+0x344 R PWM FTCMPDAT2_3 Buffer 0x0000_0000 F2_3 PWM_FTCBU PWMx_BA+0x348 R PWM FTCMPDAT4_5 Buffer 0x0000_0000 F4_5 Reserved Reserved FTCMPBUF FTCMPBUF Bits Description [31:16] Reserved Reserved.
  • Page 539 M451 PWM FTCMPDAT Indicator Register (PWM_FTCI) Register Offset Description Reset Value PWM_FTCI PWMx_BA+0x34C R/W PWM FTCMPDAT Indicator Register 0x0000_0000 Reserved Reserved Reserved FTCMD4 FTCMD2 FTCMD0 Reserved FTCMU4 FTCMU2 FTCMU0 Bits Description [31:11] Reserved Reserved. PWM FTCMPDAT Down Indicator [10:8] FTCMDn Indicator will be set to high when FTCMPDATn equal to PERIODn and DIRF=0, software can write 1 to clear this bit.

  • Page 540: Watchdog Timer (Wdt)

    M451 6.10 Watchdog Timer (WDT) 6.10.1 Overview The purpose of Watchdog Timer (WDT) is to perform a system reset when system runs into an unknown state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog Timer supports the function to wake-up system from Idle/Power-down mode. 6.10.2 Features ...

  • Page 541: Basic Configuration

    M451 WDTSEL (CLK_CLKSEL1[1:0]) WDTCKEN (CLK_APBCLK0[0]) 10 kHz (LIRC) WDT _CLK HCLK/2048 32.768 kHz (LXT) Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable. Figure 6.10-2 Watchdog Timer Clock Control 6.10.5 Basic Configuration The WDT peripheral clock is enabled in WDTCKEN (CLK_APBCLK0[0]) and clock source can be selected in WDTSEL (CLK_CLKSEL1[1:0]).

  • Page 542: Figure 6.10-3 Watchdog Timer Time-Out Interval And Reset Period Timing

    M451 (3/18/130/1026) * T (3/18/130/1026) * T (3/18/130/1026) * T (3/18/130/1026) * T (3/18/130/1026) * T Table 6-17 Watchdog Timer Time-out Interval Period Selection RSTF = 1 IF = 1 (if RSTEN = 1) WDT_CLK RSTD RSTF WDT reset (low reset) ·...

  • Page 543: Register Map

    M451 6.10.7 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value WDT Base Address: WDT_BA = 0x4004_0000 WDT_CTL WDT_BA+0x00 WDT Control Register 0x0000_0700 WDT_ALTCTL WDT_BA+0x04 WDT Alternative Control Register 0x0000_0000 May. 4, 2018 Page 543 of 1006 Rev.2.08...

  • Page 544: Register Description

    M451 6.10.8 Register Description WDT Control Register (WDT_CTL) Register Offset Description Reset Value WDT_CTL WDT_BA+0x00 WDT Control Register 0x0000_0700 ICEDEBUG Reserved Reserved Reserved TOUTSEL WDTEN INTEN WKEN RSTF RSTEN RSTCNT Bits Description ICE Debug Mode Acknowledge Disable Control (Write Protect) 0 = ICE debug mode acknowledgement affects WDT counting.
  • Page 545 M451 CPU. 0 = WDT time-out interrupt Disabled. 1 = WDT time-out interrupt Enabled. Note: This bit is write protected. Refer to the SYS_REGLCTL register. WDT Time-out Wake-up Flag (Write Protect) This bit indicates the interrupt wake-up flag status of WDT 0 = WDT does not cause chip wake-up.
  • Page 546 M451 WDT Alternative Control Register (WDT_ALTCTL) Register Offset Description Reset Value WDT_ALTCTL WDT_BA+0x04 WDT Alternative Control Register 0x0000_0000 Reserved Reserved Reserved Reserved RSTDSEL Bits Description [31:2] Reserved Reserved. WDT Reset Delay Selection (Write Protect) When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by setting RSTCNT (WDT_CTL[0]) to prevent WDT time-out reset happened.

  • Page 547: Window Watchdog Timer (Wwdt)

    M451 6.11 Window Watchdog Timer (WWDT) 6.11.1 Overview The Window Watchdog Timer (WWDT) is used to perform a system reset within a specified window period to prevent software run to uncontrollable status by any unpredictable condition. 6.11.2 Features  6-bit down counter value (CNTDAT) and 6-bit compare value (CMPDAT) to make the WWDT time-out window period flexible ...

  • Page 548: Clock Control

    M451 6.11.4 Clock Control The WWDT clock control are shown as Figure 6.11-2. WWDTSEL (CLK_CLKSEL1[31:30]) WDTCKEN (CLK_APBCLK0[0]) 10 kHz (LIRC) WWDT_CLK HCLK/2048 Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable. Figure 6.11-2 WWDT Clock Control 6.11.5 Basic Configuration The WWDT peripheral clock is enabled in WDTCKEN (CLK_APBCLK0[0]) and clock source can...

  • Page 549: Figure 6.11-3 Wwdt Reset And Reload Behavior

    M451 1110 1536 1536 * 64 * T 9.8304 s WWDT 1111 2048 2048 * 64 * T 13.1072 s WWDT Table 6-18 WWDT Prescaler Value Selection 6.11.6.1 WWDT Counting When the WWDTEN (WWDT_CTL[0]) is set, WWDT down counter will start counting from 0x3F to 0.

  • Page 550: Table 6-19 Cmpdat Setting Limitation

    M451 PSCSEL Prescale Value Valid CMPDAT Value 0000 0x3 ~ 0x3F 0001 0x2 ~ 0x3F Others Others 0x0 ~ 0x3F Table 6-19 CMPDAT Setting Limitation May. 4, 2018 Page 550 of 1006 Rev.2.08...

  • Page 551: Register Map

    M451 6.11.7 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value WWDT Base Address: WWDT_BA = 0x4004_0100 WWDT_RLDC WWDT_BA+0x00 WWDT Reload Counter Register 0x0000_0000 WWDT_CTL WWDT_BA+0x04 WWDT Control Register 0x003F_0800 WWDT_STAT WWDT_BA+0x08 WWDT Status Register 0x0000_0000...

  • Page 552: Register Description

    M451 6.11.8 Register Description WWDT Reload Counter Register (WWDT_RLDCNT) Register Offset Description Reset Value WWDT_RLDC WWDT_BA+0x00 WWDT Reload Counter Register 0x0000_0000 RLDCNT RLDCNT RLDCNT RLDCNT Bits Description WWDT Reload Counter Register Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F. Note: User can only write WWDT_RLDCNT register to reload WWDT counter value [31:0] RLDCNT...
  • Page 553 M451 WWDT Control Register (WWDT_CTL) Register Offset Description Reset Value WWDT_CTL WWDT_BA+0x04 WWDT Control Register 0x003F_0800 Note: This register can be write only one time after chip is powered on or reset. ICEDEBUG Reserved Reserved CMPDAT Reserved PSCSEL Reserved INTEN WWDTEN Bits Description...
  • Page 554 M451 1100 = Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK. 1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK. 1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK. 1111 = Pre-scale is 2048;...
  • Page 555 M451 WWDT Status Register (WWDT_STATUS) Register Offset Description Reset Value WWDT_STAT WWDT_BA+0x08 WWDT Status Register 0x0000_0000 Reserved Reserved Reserved Reserved WWDTRF WWDTIF Bits Description [31:2] Reserved Reserved. WWDT Timer-out Reset Flag This bit indicates the system has been reset by WWDT time-out reset or not. WWDTRF 0 = WWDT time-out reset did not occur.
  • Page 556 M451 WWDT Counter Value Register (WWDT_CNT) Register Offset Description Reset Value WWDT_CNT WWDT_BA+0x0C R WWDT Counter Value Register 0x0000_003F Reserved Reserved Reserved Reserved CNTDAT Bits Description [31:6] Reserved Reserved. WWDT Counter Value [5:0] CNTDAT CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value. May.

  • Page 557: Real Time Clock (Rtc)

    M451 6.12 Real Time Clock (RTC) 6.12.1 Overview The Real Time Clock (RTC) controller provides the real time and calendar message. The RTC offers programmable time tick and alarm match interrupts. The data format of time and calendar messages are expressed in BCD format. A digital frequency compensation feature is available to compensate external crystal oscillator frequency accuracy.

  • Page 558: Block Diagram

    M451 6.12.3 Block Diagram The RTC block diagram is shown below. Time Alarm Calendar Alarm Time Alarm Calendar Mask Register Mask Register Register Alarm Register (RTC_TAMSK) (RTC_CAMSK) (RTC_TALM) (RTC_CALM) ALMIEN (RTC_INTEN[0]) Calendar Time Loading Loading Alarm Interrupt Compare Register Register Operation (RTC_TIME) (RTC_CAL)

  • Page 559: Table 6-20 Rtc Control Registers Access Attribute

    M451 check rationality between RTC_WEEKDAY and RTC_CAL either. 6.12.5.3 RTC Read/Write Enable The RWEN bits (RTC_RWEN[15:0]) is served as read/write access of RTC registers to unlock register read/write protection function. If RTC_RWEN[15:0] is written to 0xa965, user can read register access enable flag RWENF (RTC_RWEN[16]) to check the RTC registers are read/write accessible or locked.
  • Page 560 M451 32776 1111 32768 0111 32775 1110 32767 0110 32774 1101 32766 0101 32773 1100 32765 0100 32772 1011 32764 0011 32771 1010 32763 0010 32770 1001 32762 0001 32769 1000 32761 0000 Following are the compensation examples for the real RTC source clock is higher or lower than 32768 Hz.
  • Page 561 M451 0x01 0x13 0x01 (AM01) 0x21 (PM01) 0x02 0x14 0x02 (AM02) 0x22 (PM02) 0x03 0x15 0x03 (AM03) 0x23 (PM03) 0x04 0x16 0x04 (AM04) 0x24 (PM04) 0x05 0x17 0x05 (AM05) 0x25 (PM05) 0x06 0x18 0x06 (AM06) 0x26 (PM06) 0x07 0x19 0x07 (AM07) 0x27 (PM07) 0x08 0x20...
  • Page 562 M451 RTC_CALM 00/00/00 (year/month/day) RTC_TALM 00:00:00 (hour : minute : second) RTC_CLKFMT 1 (24-hour mode) RTC_WEEKDAY 6 (Saturday) RTC_INTEN RTC_INTSTS RTC_LEAPYEAR RTC_TICK In RTC_CAL and RTC_CALM, only 2 BCD digits are used to express “year”. The 2 BCD digits of xy means 20xy, rather than 19xy or 21xy. Example of 12-Hour Time Setting If current RTC time is PM12:59:30 in 12-Hour Time Scale mode, the RTC_TIME setting as: RTC_TIME[21:16]: 0x32 (0x12+0x20)
  • Page 563 M451 RTC_SPR5 Battery Power Domain RTC_SPR6 Battery Power Domain RTC_SPR7 Battery Power Domain RTC_SPR8 Battery Power Domain RTC_SPR9 Battery Power Domain RTC_SPR10 Battery Power Domain RTC_SPR11 Battery Power Domain RTC_SPR12 Battery Power Domain RTC_SPR13 Battery Power Domain RTC_SPR14 Battery Power Domain RTC_SPR15 Battery Power Domain RTC_SPR16...

  • Page 564: Figure 6.12-2 Backup I/O Control Diagram

    M451 Falling edge High Level Low level 6.12.5.12 Backup Domain GPIO Function When PF.0/X32O and PF.1/X32I pins are not used as low speed 32K oscillator function, they can be used as GPIO pin function. The CTLSEL (RTC_LXTOCTL[3]) is used to select the PF.0/X32O pin is controlled by RTC or GPIO module.

  • Page 565: Register Map

    M451 6.12.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value RTC Base Address: RTC_BA = 0x4004_1000 RTC_INIT RTC_BA+0x00 RTC Initiation Register 0x0000_0000 RTC_RWEN RTC_BA+0x04 RTC Access Enable Register 0x0000_0000 RTC_FREQAD RTC_BA+0x08 RTC Frequency Compensation Register 0x0000_0700...
  • Page 566 M451 RTC_SPR10 RTC_BA+0x68 RTC Spare Register 10 0x0000_0000 RTC_SPR11 RTC_BA+0x6C RTC Spare Register 11 0x0000_0000 RTC_SPR12 RTC_BA+0x70 RTC Spare Register 12 0x0000_0000 RTC_SPR13 RTC_BA+0x74 RTC Spare Register 13 0x0000_0000 RTC_SPR14 RTC_BA+0x78 RTC Spare Register 14 0x0000_0000 RTC_SPR15 RTC_BA+0x7C RTC Spare Register 15 0x0000_0000 RTC_SPR16 RTC_BA+0x80...

  • Page 567: Register Description

    M451 6.12.7 Register Description RTC Initiation Register (RTC_INIT) Register Offset Description Reset Value RTC_INIT RTC_BA+0x00 RTC Initiation Register 0x0000_0000 INIT INIT INIT INIT INIT[0]/ACTIVE Bits Description RTC Initiation When RTC block is powered on, RTC is at reset state. User has to write a number (0x [31:1] INIT[31:1] a5eb1357) to INIT to make RTC leaving reset state.
  • Page 568 M451 RTC Access Enable Register (RTC_RWEN) Register Offset Description Reset Value RTC_RWEN RTC_BA+0x04 RTC Access Enable Register 0x0000_0000 Reserved Reserved RWENF RWEN RWEN Bits Description [31:17] Reserved Reserved. RTC Register Access Enable Flag (Read Only) 0 = RTC register read/write Disabled. [16] RWENF 1 = RTC register read/write Enabled.
  • Page 569 M451 RTC Frequency Compensation Register (RTC_FREQADJ) Register Offset Description Reset Value RTC_FREQA RTC_BA+0x08 RTC Frequency Compensation Register 0x0000_0700 Reserved Reserved Reserved INTEGER Reserved FRACTION Bits Description [31:12] Reserved Reserved. [11:8] INTEGER Integer Part Fraction Part [5:0] FRACTION Formula = (fraction part of detected value) x 60. Note: Digit in RTC_FREQADJ must be expressed as hexadecimal number.
  • Page 570 M451 RTC Time Loading Register (RTC_TIME) Register Offset Description Reset Value RTC_TIME RTC_BA+0x0C RTC Time Loading Register 0x0000_0000 Reserved Reserved TENHR Reserved TENMIN Reserved TENSEC Bits Description [31:22] Reserved Reserved. 10-hour Time Digit (0~2) [21:20] TENHR When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication.
  • Page 571 M451 RTC Calendar Loading Register (RTC_CAL) Register Offset Description Reset Value RTC_CAL RTC_BA+0x10 RTC Calendar Loading Register 0x0005_0101 Reserved TENYEAR YEAR Reserved TENMON Reserved TENDAY Bits Description [31:24] Reserved Reserved. [23:20] TENYEAR 10-Year Calendar Digit (0~9) [19:16] YEAR 1-Year Calendar Digit (0~9) [15:13] Reserved Reserved.
  • Page 572 M451 RTC Time Scale Selection Register (RTC_CLKFMT) Register Offset Description Reset Value RTC_CLKFMT RTC_BA+0x14 RTC Time Scale Selection Register 0x0000_0001 Reserved Reserved Reserved Reserved 24HEN Bits Description [31:1] Reserved Reserved. 24-hour / 12-hour Time Scale Selection Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale 24HEN 0 = 12-hour time scale with AM and PM indication selected.
  • Page 573 M451 RTC Day of the Week Register (RTC_WEEKDAY) Register Offset Description Reset Value RTC_WEEKD RTC_BA+0x18 RTC Day of the Week Register 0x0000_0006 Reserved Reserved Reserved Reserved WEEKDAY Bits Description [31:3] Reserved Reserved. Day of the Week Register 000 = Sunday. 001 = Monday.
  • Page 574 M451 RTC Time Alarm Register (RTC_TALM) Register Offset Description Reset Value RTC_TALM RTC_BA+0x1C RTC Time Alarm Register 0x0000_0000 Reserved Reserved TENHR Reserved TENMIN Reserved TENSEC Bits Description [31:22] Reserved Reserved. 10-hour Time Digit of Alarm Setting (0~2) [21:20] TENHR When RTC runs as 12-hour time scale mode, the high bit of TENHR (RTC_TIME[21]) means AM/PM indication.
  • Page 575 M451 RTC Calendar Alarm Register (RTC_CALM) Register Offset Description Reset Value RTC_CALM RTC_BA+0x20 RTC Calendar Alarm Register 0x0000_0000 Reserved TENYEAR YEAR Reserved TENMON Reserved TENDAY Bits Description [31:24] Reserved Reserved. [23:20] TENYEAR 10-Year Calendar Digit of Alarm Setting (0~9) [19:16] YEAR 1-Year Calendar Digit of Alarm Setting (0~9) [15:13]...
  • Page 576 M451 RTC Leap Year Indication Register (RTC_LEAPYEAR) Register Offset Description Reset Value RTC_LEAPYE RTC_BA+0x24 RTC Leap Year Indicator Register 0x0000_0000 Reserved Reserved Reserved Reserved LEAPYEAR Bits Description [31:1] Reserved Reserved. Leap Year Indication Register (Read Only) LEAPYEAR 0 = This year is not a leap year. 1 = This year is leap year.
  • Page 577 M451 RTC Interrupt Enable Register (RTC_INTEN) Register Offset Description Reset Value RTC_INTEN RTC_BA+0x28 RTC Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved SNPDIEN TICKIEN ALMIEN Bits Description [31:3] Reserved Reserved. Snoop Detection Interrupt Enable Bit SNPDIEN 0 = Snoop detected interrupt Disabled. 1 = Snoop detected interrupt Enabled.
  • Page 578 M451 RTC Interrupt Indication Register (RTC_INTSTS) Register Offset Description Reset Value RTC_INTSTS RTC_BA+0x2C RTC Interrupt Indicator Register 0x0000_0000 Reserved Reserved Reserved Reserved SNPDIF TICKIF ALMIF Bits Description [31:3] Reserved Reserved. Snoop Detect Interrupt Flag When tamper pin transition event is detected, this bit is set to 1 and an interrupt is generated if Snoop Detection Interrupt enabled SNPDIEN (RTC_INTEN[2]) is set to1.
  • Page 579 M451 RTC Time Tick Register (RTC_TICK) Register Offset Description Reset Value RTC_TICK RTC_BA+0x30 RTC Time Tick Register 0x0000_0000 Reserved Reserved Reserved Reserved TICK Bits Description [31:3] Reserved Reserved. Time Tick Register These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. 000 = Time tick is 1 second.
  • Page 580 M451 RTC Time Alarm MASK Register (RTC_TAMSK) Register Offset Description Reset Value RTC_TAMSK RTC_BA+0x34 RTC Time Alarm Mask Register 0x0000_0000 Reserved Reserved Reserved Reserved MTENHR MTENMIN MMIN MTENSEC MSEC Bits Description [31:6] Reserved Reserved. MTENHR Mask 10-Hour Time Digit of Alarm Setting (0~2) Mask 1-Hour Time Digit of Alarm Setting (0~9) MTENMIN Mask 10-Min Time Digit of Alarm Setting (0~5)
  • Page 581 M451 RTC Calendar Alarm MASK Register (RTC_CAMSK) Register Offset Description Reset Value RTC_CAMSK RTC_BA+0x38 RTC Calendar Alarm Mask Register 0x0000_0000 Reserved Reserved Reserved Reserved MTENYEAR MYEAR MTENMON MMON MTENDAY MDAY Bits Description Reserved Reserved. MTENYEAR Mask 10-Year Calendar Digit of Alarm Setting (0~9) MYEAR Mask 1-Year Calendar Digit of Alarm Setting (0~9) MTENMON...
  • Page 582 M451 RTC Spare Functional Control Register (RTC_SPRCTL) Register Offset Description Reset Value RTC_SPRCTL RTC_BA+0x3C RTC Spare Functional Control Register 0x0000_0080 Reserved Reserved Reserved SPRRWRDY Reserved SPRCSTS Reserved SNPTYPE1 SPRRWEN SNPTYPE0 SNPDEN Bits Description [31:8] Reserved Reserved. SPR Register Ready This bit indicates if the registers RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19 are ready to be accessed.
  • Page 583 M451 This bit controls TAMPER detect event is high level/rising edge or low level/falling edge. 0 = Low level/Falling edge detection. 1 = High level/Rising edge detection.. Snoop Detection Enable Bit SNPDEN 0 = TAMPER pin detection is Disabled. 1 = TAMPER pin detection is Enabled. May.
  • Page 584 M451 RTC Spare Register (RTC_SPRx) Register Offset Description Reset Value RTC_SPR0 RTC_BA+0x40 RTC Spare Register 0 0x0000_0000 RTC_SPR1 RTC_BA+0x44 RTC Spare Register 1 0x0000_0000 RTC_SPR2 RTC_BA+0x48 RTC Spare Register 2 0x0000_0000 RTC_SPR3 RTC_BA+0x4C RTC Spare Register 3 0x0000_0000 RTC_SPR4 RTC_BA+0x50 RTC Spare Register 4 0x0000_0000 RTC_SPR5...
  • Page 585 M451 Bits Description Spare Register This field is used to store back-up information defined by user. This field will be cleared by hardware automatically once a snooper pin event is detected. SPARE [31:0] Before storing back-up information in to RTC_SPRx register, user should write 0xA965 to RTC_RWEN[15:0] to make sure register read/write enable bit REWNF (RTC_RWEN[16]) is enabled.
  • Page 586 M451 RTC 32K Oscillator Control Register (RTC_LXTCTL) Register Offset Description Reset Value RTC_LXTCTL RTC_BA+0x100 RTC 32.768 kHz Oscillator Control Register 0x0000_000E Reserved Reserved Reserved Reserved GAIN LXTEN Bits Description [31:4] Reserved Reserved. Oscillator Gain Option User can select oscillator gain according to crystal external loading and operating temperature range.
  • Page 587 M451 X32KO Control Register (RTC_LXTOCTL) Register Offset Description Reset Value RTC_LXTOCT RTC_BA+0x104 X32KO Pin Control Register 0x0000_0000 Reserved Reserved Reserved Reserved CTLSEL DOUT OPMODE Bits Description [31:4] Reserved Reserved. IO Pin State Backup Selection When low speed 32 kHz oscillator is disabled, X32KO (PF.0) pin can be used as GPIO function.
  • Page 588 M451 X32KI Control Register (RTC_LXTICTL) Register Offset Description Reset Value RTC_LXTICTL RTC_BA+0x108 X32KI Pin Control Register 0x0000_0000 Reserved Reserved Reserved Reserved CTLSEL DOUT OPMODE Bits Description [31:4] Reserved Reserved. IO Pin State Backup Selection When low speed 32 kHz oscillator is disabled, X32KI (PF.1) pin can be used as GPIO function.
  • Page 589 M451 TAMPER Control Register (RTC_TAMPCTL) Register Offset Description Reset Value RTC_TAMPC RTC_BA+0x10C TAMPER Pin Control Register 0x0000_0000 Reserved Reserved Reserved Reserved CTLSEL DOUT OPMODE Bits Description [31:4] Reserved Reserved. IO Pin State Backup Selection When tamper function is disabled, TAMPER pin can be used as GPIO function. User can program CTLSEL bit to decide PF.2 I/O function is controlled by system power domain GPIO module or V power domain RTC_TAMPCTL control register.

  • Page 590: Uart Interface Controller (Uart)

    M451 6.13 UART Interface Controller (UART) 6.13.1 Overview ® NuMicro M451 series provides four channels Universal Asynchronous Receiver/Transmitters (UART). UART Controller performs Normal Speed UART and supports flow control function. The UART Controller performs a serial-to-parallel conversion on data received from the peripheral and a parallel-to-serial conversion on data transmitted from the CPU. Each UART Controller channel supports ten types of interrupts.

  • Page 591: Block Diagram

    M451 √ √ Auto Flow Control (CTS/RTS) √ √ IrDA √ √ √ RS-485 Function Mode √ √ Auto-Flow Control √ √ nCTS Wake-up √ √ RX Data Wake-up √ √ Auto-Baud Rate Measurement STOP Bit Length 1, 1.5, 2 bit 1, 1.5, 2 bit 1, 2 bit √...

  • Page 592: Figure 6.13-1 Uart Clock Control Diagram

    M451 UARTSEL(CLK_CLKSEL1[25:24]) UART0CKEN(CLK_APBCLK0[16]) 22.1184 MHz HIRC 32.768 kHz UART0_ CLK UARTDIV+1 PLL FOUT UARTDIV(CLK_CLKDIV0[11:8]) 4~24 MHz UART1_ CLK UART1CKEN(CLK_APBCLK0[17]) UART2CKEN(CLK_APBCLK0[18]) UART2_ CLK UART3CKEN(CLK_APBCLK0[19]) UART3_ CLK Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable. Figure 6.13-1 UART Clock Control Diagram APB_BUS UART Interrupt...

  • Page 593: Figure 6.13-2 Uart Block Diagram

    M451 Figure 6.13-2 UART Block Diagram Each block is described in detail as follows: TX_FIFO The transmitter is buffered with a 16 bytes FIFO to reduce the number of interrupts presented to the CPU. RX_FIFO The receiver is buffered with a 16 bytes FIFO (plus three error bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]), PEF (UART_FIFOSTS[4])) to reduce the number of interrupts presented to the CPU.

  • Page 594: Basic Configuration

    M451 6.13.4 Basic Configuration The UART Controller function pins are configured in SYS_GPA_MFPL, SYS_GPA_MFPH, SYS_GPB_MFPL, SYS_GPB_MFPH, SYS_GPC_MFPL, SYS_GPD_MFPL, SYS_GPD_MFPH and SYS_GPE_MFPH Multiple Function Registers. The UART Controller clock are enabled in UAR0TCKEN (CLK_APBCLK0[16]) for UART0, UART1CKEN(CLK_APBCLK0[17]) for UART1, UART2CKEN(CLK_APBCLK0[18] for UART2 and UART3CKEN(CLK_APBCLK0[19] for UART3.

  • Page 595: Table 6-24 Uart Controller Baud Rate Parameter Setting Example Table

    M451 UART Peripheral Clock = 22.1184 MHz Baud Rate Mode 0 Mode 1 Mode 2 921600 Not support BRD=0, EDIVM1=11 BRD=22 BRD=1, EDIVM1 =15 460800 BRD=1 BRD=46 BRD=2, EDIVM1 =11 BRD =4, EDIVM1 =15 230400 BRD =4 BRD =94 BRD =6, EDIVM1 =11 BRD =10, EDIVM1 =15 115200 BRD =10...

  • Page 596: Figure 6.13-3 Auto-Baud Rate Measurement

    M451 0x2F00_0046 0x2800_00FE 9600 0x0000_008E 0x2B00_00BE 0x3000_08FE 0x2F00_008E 0x2800_01FE 4800 0x0000_011E 0x2B00_017E 0x3000_11FE 0x2F00_011E Table 6-25 UART Controller Baud Rate Register Setting Example Table 6.13.5.2 UART Controller Auto-Baud Rate Function Mode Auto-Baud Rate function can measure baud rate of receiving data from UART RX pin automatically. When the Auto-Baud Rate measurement is finished, the measuring baud rate is loaded to BRD (UART_BAUD[15:0]).

  • Page 597: Figure 6.13-4 Transmit Delay Time Operation

    M451 Programming Sequence Example: Program ABRDBITS (UART_ALTCTL[20:19]) to determines UART RX data 1 rising ABRDBITS edge time from Start by 2 bit time. Set ABRIEN (UART_INTEN[18]) to enable auto-baud rate function interrupt. Set ABRDEN (UART_ALTCTL[18]) to enable auto-baud rate function. ABRDIF (UART_FIFOSTS[1]) is set, the auto-baud rate measurement is finished.

  • Page 598: Figure 6.13-5 Uart Ncts Wake-Up Case1

    M451 nCTS Wake-Up Case 1 (nCTS transition from low to high) sleep mode stable count CPU run nCTS CTSWKIF CTSACTLV (UART_MODEMSTS[8]) = 0 Figure 6.13-5 UART nCTS Wake-UP Case1 nCTS Wake-Up Case 2 (nCTS transition from high to low) sleep mode CPU run stable count nCTS...
  • Page 599 M451 The Table 6-26 describe the interrupt sources and flags. The interrupt is generated when the interrupt flag is generated and the interrupt enable bit is set. User must clear the interrupt flag after the interrupt is generated. Interrupt Enable Interrupt Source Interrupt Indicator Interrupt Flag...

  • Page 600: Table 6-26 Uart Controller Interrupt Source And Flag List

    M451 Table 6-26 UART Controller Interrupt Source and Flag List 6.13.5.7 UART Function Mode The UART Controller provides UART function (Setting FUNCSEL (UART_FUNCSEL [1:0]) to ’00’ to enable UART function mode). The UART baud rate is up to 1 Mbps. The UART provides full-duplex and asynchronous communications.

  • Page 601: Figure 6.13-8 Auto-Flow Control Block Diagram

    M451 UART Auto-Flow Control Function The UART supports auto-flow control function that uses two signals, nCTS (clear-to-send) and nRTS (request-to-send), to control the flow of data transfer between the UART and external devices (e.g. Modem). When auto-flow is enabled, the UART is not allowed to receive data until the UART asserts nRTS to external device.

  • Page 602: Figure 6.13-9 Uart Ncts Auto-Flow Control Enabled

    M451 nCTS pin input status of UART function mode CTSACTLV=0 CTSSTS UART_MODEMSTS[4] Active nCTS pin input CTSACTLV=1 (default) MODEM _ INT interrupt MODEM _ INT interrupt CTSDETF Clear by softwave Clear by softwave TX pin output Start Stop Idle Idle TX output delay Figure 6.13-9 UART nCTS Auto-Flow Control Enabled...

  • Page 603: Figure 6.13-11 Uart Nrts Auto-Flow With Software Control

    M451 flow is directly controlled by software programming of RTS(UART_MODEM[1]) control bit. Setting RTSACTLV(UART_MODEM[9]) can control the nRTS pin output is inverse or non-inverse from RTS(UART_MODEM[1]) control bit. User can read the RTSSTS(UART_MODEM[13]) bit to get real nRTS pin output voltage logic status. nRTS pin output status of UART function mode Set UART_MODEM[1]=0 Set UART_MODEM[1]=1 by software...

  • Page 604: Figure 6.13-13 Irda Tx/Rx Timing Diagram

    M451 IrDA SIR Transmit Encoder The IrDA SIR Transmit Encoder modulates Non-Return-to-Zero (NRZ) transmit bit stream output from UART. The IrDA SIR physical layer specifies the use of Return-to-Zero, Inverted (RZI) modulation scheme which represents logic 0 as an infra light pulse. The modulated output pulse stream is transmitted to an external output driver and infrared light emitting diode.

  • Page 605: Figure 6.13-14 Structure Of Lin Frame

    M451 (provided by the master task) consists of a break field and a sync field followed by a frame identifier (frame ID). The frame identifier uniquely defines the purpose of the frame. The slave task is appointed for providing the response associated with the frame ID. The response consists of a data field and a checksum field.

  • Page 606: Table 6-29 Lin Header Selection In Master Mode

    M451 Generated by Hardware Handled by Software Handled by Software Generated by Hardware Generated by Hardware Handled by Software Generated by Hardware (But Software needs to fill ID to PID Generated by Hardware Generated by Hardware (UART_LINCTL[31:24]) first Table 6-29 LIN Header Selection in Master Mode When UART is operated in LIN data transmission, LIN bus transfer state can be monitored by hardware or software.

  • Page 607: Figure 6.13-16 Break Detection In Lin Mode

    M451 7. Request header frame ID transmission by writing the protected identifier value to UART_DAT register. 8. Wait until the RDAIF (UART_INTSTS[0]) is set to “1” by hardware and then read back the UART_DAT register. LIN break and delimiter detection When software enables the break detection function by setting BRKDETEN (UART_LINCTL[10]), the break detection circuit is activated.

  • Page 608: Figure 6.13-17 Lin Frame Id And Parity Format

    M451 Figure 6.13-17 LIN Frame ID and Parity Format LIN Slave Mode The UART0/UART1 controller supports LIN Slave mode. To enable and initialize the LIN Slave mode, the following steps are necessary: 1. Set the UART_BAUD register to select the desired baud rate 2.
  • Page 609 M451  The header error flag asserts.  Writing 1 to the SLVSYNCF (UART_LINSTS[3]) to re-search a new frame header. Mute mode and LIN exit from mute mode condition In Mute mode, a LIN slave node will not receive any data until specified condition occurred. It allows header detection only and prevents the reception of any other characters.

  • Page 610: Figure 6.13-18 Lin Sync Field Measurement

    M451 measurement is stored in an internal 13-bit register and the UART_BAUD register value will be automatically updated at the end of the fifth falling edge. If the measure timer (13-bit) overflows before five falling edges, then the header error flag SLVHEF (UART_LINSTS [1]) will be set. Break field LIN Bus start...

  • Page 611: Figure 6.13-19 Uart_Baud Update Sequence In Ar Mode If Slvduen Is 1

    M451 Figure 6.13-19 UART_BAUD Update Sequence in AR mode if SLVDUEN is 1 Frame slot Inter- frame Protected space Response Synch Break Identifier field Field field Check Data 1 Data 2 Data N Measurement If LINS_DUM_EN value is 0, time H/W will not restore initial baud rate UA_BAUD UART_BAUD...
  • Page 612 M451 the SLVDUEN (UART_LINCTL[3]) bit before every checksum reception) LIN header error detection In LIN Slave function mode, when user enables the header detection function by setting the SLVHDEN (UART_LINCTL[1]), hardware will handle the header detect flow. If the header has an error, the LIN header error flag SLVHEF (UART_LINSTS[1]) will be set and an interrupt is generated if the LINIEN (UART_INTEN[8]) bit is set.
  • Page 613 M451 RS-485 Normal Multidrop Operation Mode (NMM) In RS-485 Normal Multidrop Operation Mode (RS485NMM (UART_ALTCTL[8]) = 1), in first, software must decide the data which before the address byte be detected will be stored in RX FIFO or not. If software wants to ignore any data before address byte detected, the flow is set RXOFF (UART_FIFO [8]) then enable RS485NMM (UART_ALTCTL [8]) and the receiver will ignore any data until an address byte is detected (bit 9 = 1) and the address byte data will be stored in the RX FIFO.
  • Page 614 M451 RS-485 Auto Address Detection Operation Mode (AAD) In RS-485 Auto Address Detection Operation Mode (RS485AAD (UART_ALTCTL[9]) = 1), the receiver will ignore any data until an address byte is detected (bit 9 = 1) and the address byte data matches the ADDRMV (UART_ALTCTL[31:24]) value. The address byte data will be stored in the RX FIFO.

  • Page 615: Figure 6.13-21 Rs-485 Nrts Driving Level In Auto Direction Mode

    M451 RS-485 Auto Direction Function (AUD) Another option function of RS-485 controllers is RS-485 auto direction control function (RS485AUD (UART_ALTCTL[10) = 1). The RS-485 transceiver control is implemented by using the nRTS control signal from an asynchronous serial port. The nRTS line is connected to the RS- 485 transceiver enable pin such that setting the nRTS line to high (logic 1) enables the RS-485 transceiver.

  • Page 616: Figure 6.13-23 Structure Of Rs-485 Frame

    M451 Programming Sequence Example: Program FUNCSEL in UART_FUNCSEL to select RS-485 function. Program the RXOFF (UART_FIFO[8]) to determine enable or disable the receiver RS- 485 receiver Program the RS485NMM (UART_ALTCTL[8]) or RS485AAD (UART_ALTCTL[9]) mode. If the RS485AAD (UART_ALTCTL[9]) mode is selected, the ADDRMV (UART_ALTCTL[31:24]) is programmed for auto address match value.

  • Page 617: Register Map

    M451 6.13.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value UART Base Address: UART0_BA = 0x4007_0000 UART1_BA = 0x4007_1000 UART2_BA = 0x4007_2000 UART3_BA = 0x4007_3000 UART_DAT UARTx_BA+0x00 UART Receive/Transmit Buffer Register Undefined x=0,1,2,3 UART_INTEN...
  • Page 618 M451 UART_LINSTS UARTx_BA+0x38 UART LIN Status Register 0x0000_0000 x=0,1 May. 4, 2018 Page 618 of 1006 Rev.2.08...

  • Page 619: Register Description

    M451 6.13.7 Register Description UART Receive/Transmit Buffer Register (UART_DAT) Register Offset Description Reset Value UART_DAT UARTx_BA+0x00 UART Receive/Transmit Buffer Register Undefined x=0,1,2,3 Reserved Reserved Reserved Bits Description [31:8] Reserved Reserved. Receiving/Transmit Buffer Write Operation: By writing one byte to this register, the data byte will be stored in transmitter FIFO. The [7:0] UART Controller will send out the data stored in transmitter FIFO top location through the UART_TXD.
  • Page 620 M451 UART Interrupt Enable Register (UART_INTEN) Register Offset Description Reset Value UART_INTEN UARTx_BA+0x04 UART Interrupt Enable Register 0x0000_0000 x=0,1,2,3 Reserved Reserved ABRIEN Reserved RXPDMAEN TXPDMAEN ATOCTSEN ATORTSEN TOCNTEN WKDATIEN WKCTSIEN LINIEN Reserved BUFERRIEN RXTOIEN MODEMIEN RLSIEN THREIEN RDAIEN Bits Description [31:19] Reserved Reserved.
  • Page 621 M451 Incoming Data Wake-up Interrupt Enable Bit 0 = Incoming data wake-up system function Disabled. 1 = Incoming data wake-up system function Enabled, when the system is in Power-down [10] WKDATIEN mode, incoming data will wake-up system from Power-down mode.. Note: Hardware will clear this bit when the incoming data wake-up operation finishes and “system clock”...
  • Page 622 M451 UART FIFO Control Register (UART_FIFO) Register Offset Description Reset Value UART_FIFO UARTx_BA+0x08 UART FIFO Control Register 0x0000_0101 x=0,1,2,3 Reserved Reserved RTSTRGLV Reserved RXOFF RFITL Reserved TXRST RXRST Reserved Bits Description [31:20] Reserved Reserved. nRTS Trigger Level for Auto-flow Control Use 0000 = nRTS Trigger Level is 1 byte.
  • Page 623 M451 state machine are cleared. 0 = No effect. 1 = Reset the TX internal state machine and pointers. Note: This bit will automatically clear at least 3 UART peripheral clock cycles. RX Field Software Reset When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.
  • Page 624 M451 UART Line Control Register (UART_LINE) Register Offset Description Reset Value UART_LINE UARTx_BA+0x0C UART Line Control Register 0x0000_0000 x=0,1,2,3 Reserved Reserved Reserved Reserved Bits Description [31:7] Reserved Reserved. Break Control Bit 0 = Break Control Disabled. 1 = Break Control Enabled. Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0).
  • Page 625 M451 00 = 5 bits. 01 = 6 bits. 10 = 7 bits. 11 = 8 bits. May. 4, 2018 Page 625 of 1006 Rev.2.08...
  • Page 626 M451 UART MODEM Control Register (UART_MODEM) Register Offset Description Reset Value UART_MODEM UARTx_BA+0x10 UART Modem Control Register 0x0000_0200 x=0,1,2,3 Reserved Reserved Reserved RTSSTS Reserved RTSACTLV Reserved Reserved Reserved Bits Description [31:14] Reserved Reserved. nRTS Pin Status (Read Only) This bit mirror from nRTS pin output of voltage logic status. [13] RTSSTS 0 = nRTS pin output is low level voltage logic state.
  • Page 627 M451 UART Modem Status Register (UART_MODEMSTS) Register Offset Description Reset Value UART_MODEM UARTx_BA+0x14 UART Modem Status Register 0x0000_0110 x=0,1,2,3 Reserved Reserved Reserved CTSACTLV Reserved CTSSTS Reserved CTSDETF Bits Description Reserved [31:9] Reserved. nCTS Pin Active Level This bit defines the active level state of nCTS pin input. CTSACTLV 0 = nCTS pin input is high level active.
  • Page 628 M451 UART FIFO Status Register (UART_FIFOSTS) Register Offset Description Reset Value UART_FIFOSTS UARTx_BA+0x18 UART FIFO Status Register 0x1040_4000 x=0,1,2,3 Reserved TXEMPTYF Reserved TXOVIF TXFULL TXEMPTY TXPTR RXFULL RXEMPTY RXPTR Reserved ADDRDETF ABRDTOIF ABRDIF RXOVIF Bits Description [31:29] Reserved Reserved. Transmitter Empty Flag (Read Only) This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.
  • Page 629 M451 TX FIFO Pointer (Read Only) This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one. TXPTR [21:16] The Maximum value shown in TXPTR is 15.
  • Page 630 M451 Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode . Note2: This bit is read only, but can be cleared by writing ‘1’ to it. Auto-baud Rate Time-out Interrupt (Read Only) 0 = Auto-baud rate counter is underflow.
  • Page 631 M451 UART Interrupt Status Control Register (UART_INTSTS) Register Offset Description Reset Value UART_INTSTS UARTx_BA+0x1C UART Interrupt Status Register 0x0000_0002 x=0,1,2,3 Reserved HWBUFEINT HWTOINT HWMODINT HWRLSINT Reserved Reserved HWBUFEIF HWTOIF HWMODIF HWRLSIF DATWKIF CTSWKIF LININT Reserved BUFERRINT RXTOINT MODEMINT RLSINT THREINT RDAINT LINIF WKIF...
  • Page 632 M451 1 = Buffer error interrupt flag is generated. Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared. in DMA Mode, Time-out Interrupt Flag (Read Only) This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]).
  • Page 633 M451 Buffer Error Interrupt Indicator (Read Only) This bit is set if BFERRIEN(UART_INTEN[5] and BERRIF(UART_INTSTS[5]) are both set to 1. [13] BUFERRINT 0 = No buffer error interrupt is generated. 1 = Buffer error interrupt is generated. Time-out Interrupt Indicator (Read Only) This bit is set if TOUTIEN(UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
  • Page 634 M451 Buffer Error Interrupt Flag (Read Only) This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BERRIF (UART_INTSTS[5])is set, the transfer is not correct. If BFERRIEN (UART_INTEN [8]) is enabled, the buffer error interrupt will be generated.
  • Page 635 M451 UART Time-out Register (UART_TOUT) Register Offset Description Reset Value UART_TOUT UARTx_BA+0x20 UART Time-out Register 0x0000_0000 x=0,1,2,3 Reserved Reserved TOIC Bits Description [31:16] Reserved Reserved. TX Delay Time Value [15:8] This field is used to programming the transfer delay time between the last stop bit and next start bit.
  • Page 636 M451 UART Baud Rate Divider Register (UART_BAUD) Register Offset Description Reset Value UART_BAUD UARTx_BA+0x24 UART Baud Rate Divisor Register 0x0F00_0000 x=0,1,2,3 Reserved BAUDM1 BAUDM0 EDIVM1 Reserved Bits Description [31:30] Reserved Reserved. BAUD Rate Mode Selection Bit 1 This bit is baud rate mode selection bit 1. UART provides three baud rate calculation [29] BAUDM1 modes.
  • Page 637 M451 UART_IrDA Control Register (UART_IRDA) Register Offset Description Reset Value UART_IRDA UARTx_BA+0x28 UART IrDA Control Register 0x0000_0040 x=0,1,2,3 Reserved Reserved Reserved Reserved RXINV TXINV Reserved TXEN Reserved Bits Description [31:7] Reserved Reserved. IrDA Inverse Receive Input Signal RXINV 0 = None inverse receiving input signal. 1 = Inverse receiving input signal.
  • Page 638 M451 UART Alternate Control/Status Register (UART_ALTCTL) Register Offset Description Reset Value UART_ALTCTL UARTx_BA+0x2C UART Alternate Control/Status Register 0x0000_000C x=0,1,2,3 ADDRMV Reserved ABRDBITS ABRDEN ABRIF Reserved ADDRDEN Reserved RS485AUD RS485AAD RS485NMM LINTXEN LINRXEN Reserved BRKFL Bits Description Address Match Value [31:24] ADDRMV This field contains the RS-485 address match values.
  • Page 639 M451 [14:11] Reserved Reserved. RS-485 Auto Direction Function (AUD) 0 = RS-485 Auto Direction Operation function (AUD) Disabled. [10] RS485AUD 1 = RS-485 Auto Direction Operation function (AUD) Enabled. Note: It can be active with RS-485_AAD or RS-485_NMM operation mode. RS-485 Auto Address Detection Operation Mode (AAD) 0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled.
  • Page 640 M451 UART Function Select Register (UART_FUNCSEL) Register Offset Description Reset Value UART_FUNCS UARTx_BA+0x30 UART Function Select Register 0x0000_0000 x=0,1,2,3 Reserved Reserved Reserved Reserved FUNCSEL Bits Description Reserved [31:2] Reserved. Function Select 00 = UART function. [1:0] FUNCSEL 01 = LIN function (Only Available in UART0/UART1 Channel). 10 = IrDA function.
  • Page 641 M451 UART LIN Control Register (UART_LINCTL) (Only Available in UART0/UART1 Channel) Register Offset Description Reset Value UART_LINCTL UARTx_BA+0x34 UART LIN Control Register 0x000C_0000 x=0,1 HSEL BRKFL Reserved BITERREN RXOFF BRKDETEN IDPEN SENDH Reserved MUTE SLVDUEN SLVAREN SLVHDEN SLVEN Bits Description LIN PID Bits This field contains the LIN frame ID value when in LIN function mode, the frame ID parity can be generated by software or hardware depends on IDPEN (UART_LINCTL[9]) = 1.
  • Page 642 M451 Bit Error Detect Enable Bit 0 = Bit error detection function Disabled. [12] BITERREN 1 = Bit error detection Enabled. Note: In LIN function mode, when occur bit error, the BITEF (UART_LINSTS[9]) flag will be asserted. If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated. LIN Receiver Disable Bit If the receiver is enabled (RXOFF (UART_LINCTL[11] ) = 0), all received byte data will be accepted and stored in the RX-FIFO, and if the receiver is disabled (RXOFF...
  • Page 643 M451 Note3: The control and interactions of this field are explained in 6.13.5.9 (Slave mode with automatic resynchronization). LIN Slave Automatic Resynchronization Mode Enable Bit 0 = LIN automatic resynchronization Disabled. 1 = LIN automatic resynchronization Enabled. Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1). SLVAREN Note2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).
  • Page 644 M451 UART LIN Status Register (UART_LINSTS) (Not Available in UART2/UART3 Channel) Register Offset Description Reset Value UART_LINSTS UARTx_BA+0x38 UART LIN Status Register 0x0000_0000 x=0,1 Reserved Reserved Reserved BITEF BRKDETF Reserved SLVSYNCF SLVIDPEF SLVHEF SLVHDETF Bits Description [31:10] Reserved Reserved. Bit Error Detect Status Flag (Read Only) At TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BITEF (UART_LINSTS[9]) will be set.
  • Page 645 M451 This bit is set by hardware when receipted frame ID parity is not correct. 0 = No active. 1 = Receipted frame ID parity is not correct. Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0])= 1) and enable LIN frame ID parity check function IDPEN (UART_LINCTL [9]).

  • Page 646: Smart Card Host Interface (Sc)

    M451 6.14 Smart Card Host Interface (SC) 6.14.1 Overview The Smart Card Interface controller (SC controller) is based on ISO/INTENC 7816-3 standard and fully compliant with PC/SC Specifications. It also provides status of card insertion/removal. 6.14.2 Features  ISO-7816-3 T = 0, T = 1 compliant. ...

  • Page 647: Figure 6.14-1 Sc Clock Control Diagram (4-Bit Pre-Scale Counter In Clock Controller)

    M451 Clock Controller SC Controller CLKKEEP HIRC PCLK0 1/(SC0DIV+1) SC_ CLK Engine Clock SC0CKEN SCOSEL SCOSEL SC0DIV SC0CKEN CLKKEEP SC0_PINCSR[6] CLK_CLKSEL3[1:0] CLK_CLKDIV1[7:0] CLK_APBCLK[1] Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable. Figure 6.14-1 SC Clock Control Diagram (4-bit Pre-scale Counter in Clock Controller) RX_FIFO TX/RX Control Unit...

  • Page 648: Basic Configuration

    M451 6.14.4 Basic Configuration The SC function pins are configured in SYS_GPA_MFPL, SYS_GPB_MFPL, SYS_GPE_MFPL and GPE_MPFH Multiple Function Pin Registers (refer Register Map). SC Host Controller Pin description is shown as follows: Type Description SC_DATA Bi-direction SC Host Controller DATA SC_CD Input SC Host Controller Card Detect...

  • Page 649: Figure 6.14-4 Sc Activation Sequence

    M451 programming method is shown in Activation description. The activation sequence timing can be controlled by setting SC_TMRx (x = 0, 1 ,2). This programming procedure provides user has a flexible timing setting for activation sequence. Hardware Timing Control: Set ACTEN (SC_ALTCTL[3]) to ‘1’ and the interface will perform the activation sequence by hardware.

  • Page 650: Figure 6.14-5 Sc Warm Reset Sequence

    M451 Hardware Timing Control: Set WARSTEN (SC_ALTCTL[4]) to ‘1’ and the interface will perform the warm reset sequence by hardware. The SC_RST to SC_DATA reception mode (T4) and SC_DATA reception mode to SC_RST assert (T5) can be selected by programming INITSEL (SC_ALTCTL[9:8]).

  • Page 651: Figure 6.14-6 Sc Deactivation Sequence

    M451 DACTEN (SC_ALTCTL[2]) to ‘1’ and the interface will perform the deactivation sequence by hardware. The Deactivation Trigger to SC_RST low (T7), SMC_RST low to SC_CLK (T8) and stop SC_CLK to stop SC_PWR (T9) time can be selected by programming INITSEL (SC_ALTCTL[9:8]).

  • Page 652: Figure 6.14-7 Basic Operation Flow

    M451 Start Init system clock Configure SC function pin Card inertion? Insert smart card Activation sequence Receive ATR? Check parameter ok? Warm reset In specific mode? Negotiabled transmission protocol Application Deactivation sequence Card removal Figure 6.14-7 Basic Operation Flow 6.14.5.2 Initial Character TS According to 7816-3, the initial character TS has two possible patterns shown in Figure 6.14-8.

  • Page 653: Figure 6.14-8 Initial Character Ts

    M451 Direct Convention Start Start Character T0 t = 12 ~ 9600 ETU Start Start Character T0 Inverse Convention t = 12 ~ 9600 ETU Direct Convention 0_ 1101_ 1100_ 1 (0x3B) 0_ 1100_ 0000_ 1 (0x3F) Inverse Convention Figure 6.14-8 Initial Character TS 6.14.5.3 Error Signal and Character Repetition According to ISO7816-3 T=0 mode description, as shown in Figure 6.14-9, if the receiver receives...
  • Page 654 M451 start counting. The SC_TMRCTL0, SC_TMRCTL1 and SC_TMRCTL2 timer operation mode are listed in Table 6-32 Timer2/Timer1/Timer0 Operation Mode. Note: Only SC_TMRCTL0 supports mode 0011. OPMODE(SCT MRCTLx[27:2 Operation Description 4]) (X=0 ~2) The down counter started when TMRx_SEN (SC_ALTCTL[7:5]) enabled and ended when counter time-out. The time-out value will be CNT (SC_TMRCTL0[23:0], SC_TMRCTL1[7:0], SC_TMRCTL2[7:0])+1 0000 Start...

  • Page 655: Figure 6.14-10 Transmit Direction Block Guard Time Operation

    M451 new value of CNT (SC_TMRCTL0[23:0], SC_TMRCTL1[7:0], SC_TMRCTL2[7:0]) and re-counting. The time-out value will be CNT (SC_TMRCTL0[23:0], SC_TMRCTL1[7:0], SC_TMRCTL2[7:0])+1. Same as 0010, but when the down counter equals to 0, it will set TMRx_IS(SC_INTSTS[5:3]) and counter will re-load the CNT (SC_TMRCTL0[23:0], SC_TMRCTL1[7:0], SC_TMRCTL2[7:0]) value. When the next START bit is detected, counter will re-count until software clears TMRx_SEN (SC_ALTCTL[7:5]).

  • Page 656: Figure 6.14-11 Receive Direction Block Guard Time Operation

    M451 In receive direction, the smart card host controller sends data to smart card, first. If the smart card sends data to smart card host controller at the time which is less than BGT (SC_CTL[12:8]),the block guard time interrupt BGTIF (SC_INTSTS[6]) generated when...

  • Page 657: Register Map

    M451 6.14.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value SC Base Address: SC_BA = 0x4009_0000 SC_DAT SC_BA+0x00 SC Receiving/Transmit Holding Buffer Register. 0xXXXX_XXXX SC_CTL SC_BA+0x04 SC Control Register. 0x0000_0000 SC_ALTCTL SC_BA+0x08 SC Alternate Control Register.

  • Page 658: Register Description

    M451 6.14.7 Register Description SC Receiving Buffer Register (SC_DAT) Register Offset R/W Description Reset Value SC_BA+0x00 R/W SC Receiving/Transmit Holding Buffer Register. SC_DAT 0xXXXX_XXXX Reserved Reserved Reserved Bits Description [31:8] Reserved Reserved. Receiving/ Transmit Holding Buffer Write Operation: By writing data to DAT, the SC will send out an 8-bit data. [7:0] Note: If SCEN(SC_CTL[0]) is not enabled, DAT cannot be programmed.
  • Page 659 M451 SC Control Register (SC_CTL) Register Offset Description Reset Value SC_CTL SC_BA+0x04 SC Control Register. 0x0000_0000 DBGOFF SYNC Reserved CDLV CDDBSEL TXRTYEN TXRTY RXRTYEN RXRTY TMRSEL RXTRGLV CONSEL AUTOCEN TXOFF RXOFF SCEN Bits Description ICE Debug Mode Acknowledge Enable Bit DBGOFF [31] 0 = When DBGACK is high, the internal counter will be hold.
  • Page 660 M451 1 = TX error retry function Enabled. TX Error Retry Count Number This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred. [22:20] TXRTY Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number. Note2: This field cannot be changed when TXRTYEN enabled.
  • Page 661 M451 01 = Reserved. 10 = Reserved. 11 = Inverse convention. Note: If AUTOCEN(SC_CTL[3]) enabled, this fields are ignored. Auto Convention Enable Bit 0 = Auto-convention Disabled. 1 = Auto-convention Enabled. When hardware receives TS in answer to reset state and the TS is direct convention, CONSEL(SC_CTL[5:4]) will be set to 00 automatically, otherwise if the TS is inverse convention, and CONSEL (SC_CTL[5:4]) will be set to 11.
  • Page 662 M451 SC Alternate Control Register (SC_ALTCTL) Register Offset Description Reset Value SC_ALTCTL SC_BA+0x08 SC Alternate Control Register. 0x0000_0000 Reserved Reserved ACTSTS2 ACTSTS1 ACTSTS0 RXBGTEN ADACEN Reserved INITSEL CNTEN2 CNTEN1 CNTEN0 WARSTEN ACTEN DACTEN RXRST TXRST Bits Description [31:16] Reserved Reserved. Internal Timer2 Active State (Read Only) This bit indicates the timer counter status of timer2.
  • Page 663 M451 Activation: refer to SC Activation Sequence in Figure 6.14-4 Warm-reset: refer to Warm-Reset Sequence in Figure 6.14-5 Deactivation: refer to Deactivation Sequence in Figure 6.14-6 Internal Timer2 Start Enable Bit This bit enables Timer 2 to start counting. Software can fill 0 to stop it and set 1 to reload and count.
  • Page 664 M451 This bit enables SC controller to initiate the card by activation sequence 0 = No effect. 1 = Activation sequence generator Enabled. Note1: When the activation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1. Note2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don’t fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.
  • Page 665 M451 SC Extend Guard Time Register (SC_EGT) Register Offset Description Reset Value SC_EGT SC_BA+0x0C SC Extend Guard Time Register. 0x0000_0000 Reserved Reserved Reserved Bits Description [31:8] Reserved Reserved. Extended Guard Time [7:0] This field indicates the extended guard timer value. Note: The counter is ETU base and the real extended guard time is EGT.
  • Page 666 M451 SC Receiver buffer Time-out Register (SC_RXTOUT) Register Offset Description Reset Value SC_RXTOUT SC_BA+0x10 SC Receive buffer Time-out Register. 0x0000_0000 Reserved Reserved Reserved RFTM RFTM Bits Description [31:9] Reserved Reserved. SC Receiver FIFO Time-out (ETU Base) The time-out counter resets and starts counting whenever the RX buffer received a new data word.
  • Page 667 M451 SC Clock Divider Control Register (SC_ETUCTL) Register Offset Description Reset Value SC_ETUCTL SC_BA+0x14 SC ETU Control Register. 0x0000_0173 Reserved Reserved CMPEN Reserved ETURDIV ETURDIV Bits Description [31:16] Reserved Reserved. Compensation Mode Enable Bit This bit enables clock compensation function. When this bit enabled, hardware will alternate between n clock cycles and n-1 clock cycles, where n is the value to be written [15] CMPEN...
  • Page 668 M451 SC Interrupt Control Register (SC_INTEN) Register Offset Description Reset Value SC_INTEN SC_BA+0x18 SC Interrupt Enable Control Register. 0x0000_0000 Reserved Reserved Reserved ACERRIEN RXTOIF INITIEN CDIEN BGTIEN TMR2IEN TMR1IEN TMR0IEN TERRIEN TBEIEN RDAIEN Bits Description [31:11] Reserved Reserved. Auto Convention Error Interrupt Enable Bit This field is used for auto-convention error interrupt enable.
  • Page 669 M451 1 = Timer2 interrupt Enabled. Timer1 Interrupt Enable Bit This field is used to enable the TMR1 interrupt. TMR1IEN 0 = Timer1 interrupt Disabled. 1 = Timer1 interrupt Enabled. Timer0 Interrupt Enable Bit This field is used to enable TMR0 interrupt enable. TMR0IEN 0 = Timer0 interrupt Disabled.
  • Page 670 M451 SC Interrupt Status Register (SC_INTSTS) Register Offset Description Reset Value SC_INTSTS SC_BA+0x1C SC Interrupt Status Register. 0x0000_0002 Reserved Reserved Reserved ACERRIF RBTOIF INITIF CDIF BGTIF TMR2IF TMR1IF TMR0IF TERRIF TBEIF RDAIF Bits Description [31:11] Reserved Reserved. Auto Convention Error Interrupt Status Flag (Read Only) This field indicates auto convention sequence error.
  • Page 671 M451 Timer1 Interrupt Status Flag (Read Only) TMR1IF This field is used for TMR1 interrupt status flag. Note: This bit is read only, but it can be cleared by writing 1 to it. Timer0 Interrupt Status Flag (Read Only) TMR0IF This field is used for TMR0 interrupt status flag.
  • Page 672 M451 SC Transfer Status Register (SC_STATUS) Register Offset Description Reset Value SC_STATUS SC_BA+0x20 SC Status Register. 0x0000_0202 TXACT TXOVERR TXRERR Reserved TXPOINT RXACT RXOVERR RXRERR Reserved RXPOINT Reserved CDPINSTS CINSERT CREMOVE TXFULL TXEMPTY TXOV Reserved Reserved RXFULL RXEMPTY RXOV Bits Description Transmit in Active Status Flag (Read Only) 0 = This bit is cleared automatically when TX transfer is finished or the last byte...
  • Page 673 M451 Note2 This bit is a flag and cannot generate any interrupt to CPU. Note3: If CPU enables receiver retry function by setting RXRTYEN (SC_CTL[19]) , the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])). [20:18] Reserved Reserved. Receiver Buffer Pointer Status Flag (Read Only) This field indicates the RX buffer pointer status flag.
  • Page 674 M451 Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag. Receiver Parity Error Status Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid “parity bit”.
  • Page 675 M451 SC PIN Control State Register (SC_PINCTL) Register Offset Description Reset Value SC_PINCTL SC_BA+0x24 SC Pin Control State Register. 0x0000_00x0 Reserved SYNC Reserved Reserved RSTSTS PWRSTS DATSTS Reserved SCDOSTS PWRINV Reserved SCDOUT Reserved Reserved CLKKEEP Reserved SCRST PWREN Bits Description Reserved [31] Reserved.
  • Page 676 M451 SC Data Pin Output Status This bit is the pin status of SCDATOUT 0 = SCDATOUT pin to low. SCDOSTS [12] 1 = SCDATOUT pin to high. Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically.
  • Page 677 M451 Read this field to get SC_PWR pin status. 0 = SC_PWR pin status is low. 1 = SC_PWR pin status is high. Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. So don’t fill this field when operating in these modes. May.
  • Page 678 M451 SC Timer Control Register 0 (SC_TMRCTL0) Register Offset Description Reset Value SC_TMRCTL0 SC_BA+0x28 SC Internal Timer Control Register 0. 0x0000_0000 Reserved OPMODE Bits Description [31:28] Reserved Reserved. Timer 0 Operation Mode Selection [27:24] OPMODE This field indicates the internal 24-bit timer operation selection. Refer to 6.14.5.4 for programming Timer0 Timer 0 Counter Value (ETU Base) [23:0]...
  • Page 679 M451 SC Timer Control Register 1 (SC_TMRCTL1) Register Offset Description Reset Value SC_TMRCTL1 SC_BA+0x2C SC Internal Timer Control Register 1. 0x0000_0000 Reserved OPMODE Reserved Reserved Bits Description [31:28] Reserved Reserved. Timer 1 Operation Mode Selection [27:24] OPMODE This field indicates the internal 8-bit timer operation selection. Refer to 6.14.5.4 for programming Timer1 Reserved [23:8]...
  • Page 680 M451 SC Timer Control Register 2 (SC_TMRCTL2) Register Offset Description Reset Value SC_TMRCTL2 SC_BA+0x30 SC Internal Timer Control Register 2. 0x0000_0000 Reserved OPMODE Reserved Reserved Bits Description [31:28] Reserved Reserved. Timer 2 Operation Mode Selection [27:24] OPMODE This field indicates the internal 8-bit timer operation selection Refer to 6.14.5.4 for programming Timer2 Reserved [23:8]...
  • Page 681 M451 SC UART Mode Control Register (SC_UARTCTL) Register Offset Description Reset Value SC_UARTCTL SC_BA + 0x34 SC UART Mode Control Register. 0x0000_0000 Reserved Reserved Reserved PBOFF Reserved UARTEN Bits Description [31:8] Reserved Reserved. Odd Parity Enable Bit 0 = Even number of logic 1’s are transmitted or check the data word and parity bits in receiving mode.
  • Page 682 M451 SC Timer Current Data Register A (SC_TMRDAT0) Register Offset Description Reset Value SC_TMRDAT0 SC_BA+0x38 SC Timer Current Data Register A. 0x0000_07FF Reserved CNT0 CNT0 CNT0 Bits Description [31:24] Reserved Reserved. Timer0 Current Data Value (Read Only) CNT0 [23:0] This field indicates the current count values of timer0. May.
  • Page 683 M451 SC Timer Current Data Register B (SC_TMRDAT1_2) Register Offset Description Reset Value SC_TMRDAT1_2 SC_BA+0x3C SC Timer Current Data Register B. 0x0000_7F7F Reserved Reserved CNT2 CNT1 Bits Description [31:16] Reserved Reserved. Timer2 Current Data Value (Read Only) CNT2 [15:8] This field indicates the current count values of timer2. Timer1 Current Data Value (Read Only) [7:0] CNT1...

  • Page 684: I 2 C Serial Interface Controller (I 2 C)

    M451 6.15 C Serial Interface Controller (I 6.15.1 Overview C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. The I C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously.

  • Page 685: Block Diagram

    M451  I2C1 pins are configured on SYS_GPC_MFPL or SYS_GPE_MFPL or SYS_GPE_MFPH or SYS_GPF_MFPL registers.  Enable I2C1 clock (I2C1CKEN) on CLK_APBCLK0[9] register.  Reset I2C1 controller (I2C1RST) on SYS_IPRST1[9] register. 6.15.4 Block Diagram The block diagram of I C controller is shown as Figure 6.15-1. APB Interface Wakeup Control Control Register...

  • Page 686: Figure 6.15-3 I 2 C Protocol

    M451 specification. The I C port handles byte transfers autonomously. To enable this port, the bit I2CEN in I2C_CTL should be set to '1'. The I C hardware interfaces to the I C bus via two pins: SDA and SCL. When I/O pins are used as I C ports, user must set the pins function to I C in advance.
  • Page 687 M451 START or Repeated START signal When the bus is free/idle, which means no master device is engaging the bus (both SCL and SDA lines are high), a master can initiate a transfer by sending a START signal. A START signal, usually referred to as the “S”...

  • Page 688: Figure 6.15-4 Start And Stop Conditions

    M451 STOP signal The master can terminate the communication by generating a STOP signal. A STOP signal, usually referred to as the “P” bit, is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH. The Figure 6.15-4 shows the waveform of START, Repeat START and STOP.
  • Page 689 M451 Slave Address Transfer The first byte of data transferred by the master immediately after the START signal is the Slave address (SLA). This is a 7-bit calling address followed by a Read/Write (R/W) bit. The R/W bit signals of the slave indicate the data transfer direction. No two slaves in the system can have the same address.

  • Page 690: Figure 6.15-5 Bit Transfer On The I 2 C Bus

    M451 Data Transfer When a slave receives a correct address with an R/W bit, the data will follow R/W bit specified to transfer. Each transferred byte is followed by an acknowledge bit on the 9th SCL clock cycle. If the slave signals a Not Acknowledge (NACK), the master can generate a STOP signal to abort the data transfer or generate a Repeated START signal and start a new transfer cycle.

  • Page 691: Figure 6.15-7 Master Transmits Data To Slave

    M451 Data transfer on I C bus The Figure 6.15-7 shows a master transmits data to slave. A master addresses a slave with a 7- bit address and 1-bit write index to denote that the master wants to transmit data to the slave. The master keeps transmitting data after the slave returns acknowledge to the master.

  • Page 692: Figure 6.15-9 Control I

    M451 Updated Status Last Status STATUS=0x18 STATUS=0x08 I2C_DAT (SLA+W) Register Control I2C_DAT=SLA+W Master to Slave (STA,STO,SI,AA)=(0,0,1,x) Slave to Master Figure 6.15-9 Control I C Bus according to the current I C Status May. 4, 2018 Page 692 of 1006 Rev.2.08...

  • Page 693: Figure 6.15-10 Master Transmitter Mode Control Flow

    M451 Master Mode InFigure 6.15-10 and Figure 6.15-11, all possible protocols for I C master are shown. User needs to follow proper path of the flow to implement required I C protocol. In other words, user can send a START signal to bus and I C will be in Master Transmitter (MT) mode (Figure 6.15-10) or Master receiver (MR) mode (Figure 6.15-11) after START signal has been sent successfully and new status code would be 0x08.

  • Page 694: Figure 6.15-11 Master Receiver Mode Control Flow

    M451 STATUS=0x08 STATUS=0x40 STATUS=0x50 I2C_DAT I2C_DAT (SLA+R) (Data) (STA,STO,SI,AA)=(1,0,1,x) I2C_DAT=SLA+R (STA,STO,SI,AA)=(0,0,1,1) (STA,STO,SI,AA)=(0,0,1,x) (Arbitration Lost) ACK STATUS=0x38 I2C_DAT (Data) (STA,STO,SI,AA)=(0,0,1,0) STATUS=0x58 I2C_DAT (Data) (STA,STO,SI,AA)=(0,0,1,0) STATUS=0x48 STATUS=0x08 (STA,STO,SI,AA)=(1,1,1,x) (Arbitration Lost) STATUS=0x38 STATUS=0xF8 I2C_DAT ACK/ (SLA+R) I2C_DAT=SLA+R (STA,STO,SI,AA)=(0,0,1,X) (STA,STO,SI,AA)=(0,1,1,x) (Arbitration Lost) ACK STATUS= 0x68, 0x78, 0xB0 STATUS=0x10 I2C_DAT (SLA+R)

  • Page 695: Figure 6.15-12 Save Mode Control Flow

    M451 Slave Mode When reset default, I C is not addressed and will not recognize the address on I C bus. User can set slave address by I2C_ADDRn (n=0~3) and set (STA, STO, SI, AA) = (0, 0, 1, 1) to let I recognize the address sent by master.
  • Page 696 M451 code will be 0xA0. User could follow the action for status code 0x88 as shown in the above figure when getting 0xA0 status. If I C is still transmitting data in addressed Slave mode but got a STOP or Repeat START, the status code will be 0xA0.

  • Page 697: Figure 6.15-13 Gc Mode

    M451 General Call (GC) Mode If the GC bit (I2C_ADDRn [0]) is set, the I C port hardware will respond to General Call address (00H). User can clear GC bit to disable general call function. When the GC bit is set and the I C in Slave mode, it can receive the general call address by 0x00 after master send general call address to I...

  • Page 698: Figure 6.15-14 Arbitration Lost

    M451 Multi-Master In some applications, there are two or more masters on the same I C bus to access slaves, and the masters may transmit data simultaneously. The I C supports multi-master by including collision detection and arbitration to prevent data corruption. If for some reason two masters initiate command at the same time, the arbitration procedure determines which master wins and can continue with the command.

  • Page 699: Table 6-33 Reserved Smbus Address

    M451 Bus Management (SMBus/PMBus Compatiable) This section is relevant only when Bus Management feature is supported. Introduction The Bus Management is an I C interface through which various devices can communicate with each other and with the rest of the system. It is based on I C principles of operation.

  • Page 700: Figure 6.15-15 Bus Management Packet Protocol Diagram Element Key

    M451 of the eleven protocols to communicate. The protocols are Quick CMD, Send Byte, Receive Byte, Write Byte, Write Word, Read Byte, Read Word, Process Call, Block Read, Block Write and Block Write-Block Read Process Call. These protocols should be implemented by the user software.

  • Page 701: Figure 6.15-167-Bit Addressable Device To Host Communication

    M451 with the alerting device’s address. This peripheral supports the Host Notify protocol by setting the BUSEN (I2C_BUSCTL[7]), BMHEN (I2C_BUSCTL[3]) and ALERTEN (I2C_BUSCTL[4]). In this case the host will acknowledge the Bus Management Host address (0b0001000). This protocol is used when the device acts as a master and the host as a slave.

  • Page 702: Figure 6.15-18 Bus Management Alert Function

    M451 ALERT_N I2C Controller Host Slave ARA Command Figure 6.15-18 Bus Management ALERT function Packet error checking A packet error checking mechanism has been introduced in the SMBus specification to improve reliability and communication robustness. Packet Error Checking is implemented by appending a Packet Error Code (PEC) at the end of each message transfer.

  • Page 703: Figure 6.15-19 Sm Bus Time Out Timing

    M451 Start Stop LOW:SEXT LOW:MEXT LOW:MEXT LOW:MEXT SMBCLK SMBDAT Figure 6.15-19 SM Bus Time Out Timing Bus management time-out: The SCLK low time-out condition when bus no IDLE = (BUSTO(I2C_BUSTOUT[7:0]) +1) x 16x1024 (14-bit) x T (if TOCDIV4 = 0). Time-out PCLK = (BUSTO(I2C_BUSTOUT[7:0])+1) x 16x1024 (14-bit) x 4 x T...
  • Page 704 M451 I2C_WKSTS(wake up status register), I2C_BUSCTL (bus management register), I2C_BUSTCTL (bus management timer control register), I2C_BUSSTS (bus management status register), I2C_PKTSIZE (TX/RX byte number), I2C_PKTCRC (PEC value register), I2C_BUSTOUT (bus management timer register), and I2C_CLKTOUT (bus management clock low timer register). May.
  • Page 705 M451 Address Registers (ADDR) The I C port is equipped with four slave address registers, I2C_ADDRn (n=0~3). The contents of the register are irrelevant when I C is in Master mode. In Slave mode, the bit field ADDR(I2C_ADDRn[7:1]) must be loaded with the chip’s own slave address. The I C hardware will react if the contents of I2C_ADDRn are matched with the received slave address.
  • Page 706 M451 Slave Address Mask Registers (ADDRMSK) The I C bus controller supports multiple address recognition with four address mask registers I2C_ADDRMSKn (n=0~3). When the bit in the address mask register is set to 1, it means the received corresponding address bit is "Don’t care". If the bit is set to 0, it means the received corresponding register bit should be exactly the same as address register.

  • Page 707: Figure 6.15-20 I 2 C Data Shifting Direction

    M451 Data Register (I2C_DAT) This register contains a byte of serial data to be transmitted or a byte which just has been received. The CPU can be read from or written to the 8-bit (I2C_DAT [7:0]) directly while it is not in the process of shifting a byte.
  • Page 708 M451 Control Register (I2C_CTL) The CPU can be read from and written to I2C_CTL [7:0] directly. When the I C port is enabled by setting I2CEN (I2C_CTL [6]) to high, the internal states will be controlled by I2C_CTL and I logic hardware.

  • Page 709: Table 6-34 I 2 C Status Code Description

    M451 Status Register (I2C_STATUS) I2C_STATUS [7:0] is an 8-bit read-only register. The bit field I2C_STATUS [7:0] contains the status code and there are 26 possible status codes. All states are listed in Table 6-34. When I2C_STATUS [7:0] is F8H, no serial interrupt is requested. All other I2C_STATUS [7:0] values correspond to the defined I C states.
  • Page 710 M451 Clock Baud Rate Bits (I2C_CLKDIV) The data baud rate of I C is determines by CLK(I2C_CLKDIV [7:0] )register when I C is in Master Mode, and it is not necessary in a Slave mode. In the Slave mode, I C will automatically synchronize it with any clock frequency from master I C device.

  • Page 711: Figure 6.15-21 I 2 C Time-Out Count Block Diagram

    M451 Time-out Control Register (I2C_TOCTL) There is a 14-bit time-out counter which can be used to deal with the I C bus hang-up. If the time- out counter is enabled, the counter starts up counting until it overflows (TOIF=1) and generates C interrupt to CPU or stops counting by clearing TOCEN to 0.
  • Page 712 M451 Wake-up Control Register (I2C_WKCTL) When chip enters Power-down mode, other I C master can wake up our chip by addressing our C device, user must configure the related setting before entering Sleep mode. When the chip is woken-up by address match with one of the four address register, the following data will be abandoned at this time.
  • Page 713 M451 Wake-up Status Register (I2C_WKSTS) When system is woken up by other I C master device, WKIF is set to indicate this event. User needs write “1” to clear this bit. May. 4, 2018 Page 713 of 1006 Rev.2.08...
  • Page 714 M451 Bus Management Control Register (I2C_BUSCTL) The SM bus management control events are defined in this register. It includes the Acknowledge Control by Manual (ACKMEN (I2C_BUSCTL[0])), Packet Error Checking Enable (PECEN (I2C_BUSCTL[1])), device (BMDEN(I2C_BUSCTL[2])) or host (BMHEN (I2C_BUSCTL[3])) enable in this peripheral device. Both the alert and the suspend function can be set in ALERTEN (I2C_BUSCTL[4]), SCTLOSTS (I2C_BUSCTL[5])) and SCTLOEN (I2C_BUSCTL[6]).
  • Page 715 M451 C Byte Number Register (I2C_PKTSIZE) When the PECEN bit (I2C_BUSCTL[1]) is set. The I C controller will calculate the PEC value of the data on the bus. The I2C_PKTSIZE is used to define the data number in the bus. When the counter reach the value of I2C_PKTSIZE, the final PEC value will be transmitted or received automatically when the PECTXEN bit (I2C_BUSCTL[8]) is set.
  • Page 716 M451 C PEC VALUR Register (I2C_PKTCRC) The register indicates the calculated PEC value of data on the I C bus. The detail of information is defined the PEC section of SM Bus. May. 4, 2018 Page 716 of 1006 Rev.2.08...

  • Page 717: Figure 6.15-22 Eeprom Random Read

    M451 C Bus Management Timer and I C CLock Low Timer Register (I2C_BUSTOUT/ I2C_CLKTOUT) Both of the definition of these registers are described in the time-out section of SM Bus. 6.15.5.4 Example for Random Read on EEPROM The following steps are used to configure the I C0 related registers when using I C to read data from EEPROM.

  • Page 718: Figure 6.15-23 Protocol Of Eeprom Random Read

    M451 STATUS=0x08 STATUS=0x18 I2C_DAT I2C_DAT (SLA+W) ROM Address High Byte I2C_DAT=ROM Address High Byte I2C_DAT=SLA+W STATUS=0xf8 (STA,STO,SI,AA)=(0,0,1,x) STATUS=0x20 (STA,STO,SI,AA)=(0,0,1,x) (STA,STO,SI,AA)=(1,0,1,x) (STA,STO,SI,AA)=(0,1,1,x) STATUS=0x28 STATUS=0x28 I2C_DAT ROM Address Low Byte I2C_DAT=ROM Address Low Byte (STA,STO,SI,AA)=(0,0,1,x) STATUS=0x30 STATUS=0xf8 (STA,STO,SI,AA)=(0,1,1,x) STATUS=0x58 STATUS=0xf8 STATUS=0x10 STATUS=0x40 Read I2C_DAT to Get Data I2C_DAT I2C_DAT...

  • Page 719: Register Map

    M451 6.15.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value C Base Address: I2Cn_BA = 0x4008_0000 + (0x1000 *n) n= 0,1 I2C_CTL I2Cn_BA+0x00 R/W I C Control Register 0x0000_0000 I2C_ADDR0 I2Cn_BA+0x04 R/W I...

  • Page 720: Register Description

    M451 6.15.7 Register Description C Control Register (I2C_CTL) Register Offset Description Reset Value I2C_CTL I2Cn_BA+0x00 C Control Register 0x0000_0000 Reserved Reserved Reserved INTEN I2CEN Reserved Bits Description [31:8] Reserved Reserved. Enable Interrupt INTEN 0 = I C interrupt Disabled. 1 = I C interrupt Enabled.
  • Page 721 M451 the SCL line. [1:0] Reserved Reserved. May. 4, 2018 Page 721 of 1006 Rev.2.08...
  • Page 722 M451 C Data Register (I2C_DAT) Register Offset Description Reset Value I2C_DAT I2Cn_BA+0x08 C Data Register 0x0000_0000 Reserved Reserved Reserved Bits Description [31:8] Reserved Reserved. C Data [7:0] Bit [7:0] is located with the 8-bit transferred/received data of I C serial port. May.
  • Page 723 M451 C Status Register (I2C_STATUS) Register Offset Description Reset Value I2C_STATUS I2Cn_BA+0x0C C Status Register 0x0000_00F8 Reserved Reserved Reserved STATUS Bits Description [31:8] Reserved Reserved. C Status The three least significant bits are always 0. The five most significant bits contain the status code.
  • Page 724 M451 C Clock Divided Register (I2C_CLKDIV) Register Offset Description Reset Value I2C_CLKDIV I2Cn_BA+0x10 C Clock Divided Register 0x0000_0000 Reserved Reserved Reserved DIVIDER Bits Description [31:8] Reserved Reserved. C Clock Divided Indicates the I C clock rate: Data Baud Rate of I C = (system clock) / (4x [7:0] DIVIDER...
  • Page 725 M451 C Time-out Control Register (I2C_TOCTL) Register Offset Description Reset Value I2C_TOCTL I2Cn_BA+0x14 C Time-out Control Register 0x0000_0000 Reserved Reserved Reserved Reserved TOCEN TOCDIV4 TOIF Bits Description [31:3] Reserved Reserved. Time-out Counter Enable Bit When Enabled, the 14-bit time-out counter will start counting when SI is clear. Setting flag SI to ‘1’...
  • Page 726 M451 C Slave Address Register (ADDRx) Register Offset Description Reset Value I2C_ADDR0 I2Cn_BA+0x04 C Slave Address Register0 0x0000_0000 I2C_ADDR1 I2Cn_BA+0x18 C Slave Address Register1 0x0000_0000 I2C_ADDR2 I2Cn_BA+0x1C C Slave Address Register2 0x0000_0000 I2C_ADDR3 I2Cn_BA+0x20 C Slave Address Register3 0x0000_0000 Reserved Reserved Reserved ADDR...
  • Page 727 M451 C Slave Address Mask Register (ADDRMSKx) Register Offset Description Reset Value I2C_ADDRMSK0 I2Cn_BA+0x24 C Slave Address Mask Register0 0x0000_0000 I2C_ADDRMSK1 I2Cn_BA+0x28 C Slave Address Mask Register1 0x0000_0000 I2C_ADDRMSK2 I2Cn_BA+0x2C C Slave Address Mask Register2 0x0000_0000 I2C_ADDRMSK3 I2Cn_BA+0x30 C Slave Address Mask Register3 0x0000_0000 Reserved Reserved...
  • Page 728 M451 C Wake-up Control Register (I2C_WKCTL) Register Offset Description Reset Value I2C_WKCTL I2Cn_BA+0x3C C Wake-up Control Register 0x0000_0000 Reserved Reserved Reserved Reserved WKEN Bits Description [31:1] Reserved Reserved. C Wake-up Enable Bit WKEN 0= I C wake-up function Disabled. 1= I C wake-up function Enabled.
  • Page 729 M451 C Wake-up Status Register (I2C_WKSTS) Register Offset Description Reset Value I2C_WKSTS I2Cn_BA+0x40 C Wake-up Status Register 0x0000_0000 Reserved Reserved Reserved Reserved WKIF Bits Description [31:1] Reserved Reserved. C Wake-up Flag WKIF When chip is woken up from Power-down mode by I C, this bit is set to 1.
  • Page 730 M451 C Bus Manage Control Register (I2C_BUSCTL) Register Offset Description Reset Value I2C_BUSCTL I2Cn_BA+0x44 C Bus Management Control Register 0x0000_0000 Reserved Reserved Reserved ACKM9SI PECCLR TIDLE PECTXEN BUSEN SCTLOEN SCTLOSTS ALERTEN BMHEN BMDEN PECEN ACKMEN Bits Description [31:12] Reserved Reserved. Acknowledge Manual Enable Extra SI Interrupt [11] ACKM9SI...
  • Page 731 M451 0 = The SUSCON pin in input. 1 = The output enable is active on the SUSCON pin. Suspend/Control Data Output Status SCTLOSTS 0 = The output of SUSCON pin is low. 1 = The output of SUSCON pin is high. Bus Management Alert Enable Bit Device Mode (BMHEN =0).
  • Page 732 M451 C Bus Management Timer Control Register (I2C_BUSTCTL) Register Offset Description Reset Value I2C_BUSTCTL I2Cn_BA+0x48 C Bus Management Timer Control Register 0x0000_0000 Reserved Reserved Reserved Reserved PECIEN TORSTEN CLKTOIEN BUSTOIEN CLKTOEN BUSTOEN Bits Description [31:6] Reserved Reserved. Packet Error Checking Byte Count Done Interrupt Enable Bit 0 = Indicates the byte count done interrupt is Disabled.
  • Page 733 M451 0 = Indicates the bus clock low time-out detection is Disabled. 1 = Indicates the bus clock low time-out detection is Enabled (bus clock is low for more than TTime-out (in BIDLE=0) or high more than TTime-out(in BIDLE =1). May.
  • Page 734 M451 C Bus Management Status Register (I2C_BUSSTS) Register Offset Description Reset Value I2C_BUSSTS I2Cn_BA+0x4C C Bus Management Status Register 0x0000_0000 Reserved Reserved Reserved Reserved CLKTO BUSTO SCTLDIN ALERT PECERR BCDONE BUSY Bits Description [31:6] Reserved Reserved. Clock Low Cumulate Time-out Status 0 = Indicates that the cumulative clock low is no any time-out.
  • Page 735 M451 Byte Count Transmission/Receive Done 0 = Indicates the transmission/ receive is not finished when the PECEN is set. BCDONE 1 = Indicates the transmission/ receive is finished when the PECEN is set. Note: Software can write 1 to clear this bit. Bus Busy Indicates that a communication is in progress on the bus.
  • Page 736 M451 C Byte Number Register (I2C_PKTSIZE) Register Offset R/W Description Reset Value I2C_PKTSIZE I2Cn_BA+0x50 R/W I C Packet Error Checking Byte Number Register 0x0000_0000 Reserved Reserved Reserved PLDSIZE Bits Description [31:8] Reserved Reserved. Transfer Byte Number The transmission or receive byte number in one transaction when the PECEN is set. The [7:0] PLDSIZE maximum transaction or receive byte is 255 Bytes.
  • Page 737 M451 C PEC Value Register (I2C_PKTCRC) Register Offset Description Reset Value I2C_PKTCRC I2Cn_BA+0x54 C Packet Error Checking Byte Value Register 0x0000_0000 Reserved Reserved Reserved PECCRC Bits Description [31:8] Reserved Reserved. Packet Error Checking Byte Value [7:0] PECCRC This byte indicates the packet error checking content after transmission or receive byte count by using the C(x) = x + x + 1.
  • Page 738 M451 C Bus Management Timer Register (I2C_BUSTOUT) Register Offset R/W Description Reset Value I2C_BUSTOUT I2Cn_BA+0x58 R/W I C Bus Management Timer Register 0x0000_0005 Reserved Reserved Reserved BUSTO Bits Description [31:8] Reserved Reserved. Bus Management Time-out Value Indicate the bus time-out value in bus is IDLE or SCLK low. [7:0] BUSTO Note: If the user wants to revise the value of BUSTOUT, the TORSTEN...
  • Page 739 M451 C Clock Low Timer Register (I2C_CLKTOUT) Register Offset R/W Description Reset Value I2C_CLKTOUT I2Cn_BA+0x5C R/W I C Bus Management Clock Low Timer Register 0x0000_0005 Reserved Reserved Reserved CLKTO Bits Description [31:8] Reserved Reserved. Bus Clock Low Timer The field is used to configure the cumulative clock extension time-out. [7:0] CLKTO Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to...

  • Page 740: Serial Peripheral Interface (Spi)

    M451 6.16 Serial Peripheral Interface (SPI) 6.16.1 Overview The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and allows full duplex transfer. Devices communicate in Master/Slave mode with the 4-wire bi- ® direction interface. The NuMicro M451 series contains up to three sets of SPI controllers performing a serial-to-parallel conversion on data received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device.

  • Page 741: Block Diagram

    M451 6.16.3 Block Diagram Interface SPI0_CLK Core Logic Control Peripheral clock SPI0_SS Status / Control Registers Interface SPI0_MOSI0 Control 4-Bit 8-Level TX TX Shift Skew FIFO Buffer Register SPI0_MISO0 Buffer 4-Bit SPI0_MOSI1 8-Level RX RX Shift Skew FIFO Buffer Register SPI0_MISO1 Buffer Note: SPI0_MOSI1 and SPI0_MISO1 are only available in 2-Bit Transfer mode or Quad I/O mode...

  • Page 742: Basic Configuration

    M451 TX FIFO Buffer: The transmit FIFO buffer is a 4-/8-level depth, 32-bit wide, first-in, first-out register buffer. The data can be written to the transmit FIFO buffer in advance through software by writing the SPI_TX register. RX FIFO Buffer: The received FIFO buffer is also a 4-/8-level depth, 32-bit wide, first-in, first-out register buffer.

  • Page 743: Functional Description

    M451  Select the source of SPI2 peripheral clock on SPI2SEL (CLK_CLKSEL2[7:6]).  Enable SPI2 peripheral clock in SPI2CKEN (CLK_APBCLK0[14]).  Reset SPI2 controller in SPI2RST (SYS_IPRST1[14]). SPI/I S Interface Controller Pin description is shown as Table 6-35: SPI Mode S Mode left/right channel...

  • Page 744: Figure 6.16-4 Spi Master Mode Application Block Diagram

    M451 Master/Slave mode This SPI controller can be set as Master or Slave mode by setting the SLAVE (SPI_CTL[18]) to communicate with the off-chip SPI slave or master device. The application block diagrams in Master and Slave mode are shown below. SPI_CLK SPIn_CLK SPIn_MISO...

  • Page 745: Figure 6.16-632-Bit In One Transaction (Master Mode)

    M451 The CLKPOL (SPI_CTL[3]) defines the SPI clock idle state. If CLKPOL = 1, the output of SPI clock is high at idle state; if CLKPOL = 0, it is low at idle state. TXNEG (SPI_CTL[2]) defines the data transmitted out either on negative edge or on positive edge of SPI clock.

  • Page 746: Figure 6.16-7 Automatic Slave Selection (Ssactpol = 0, Spi_Cycle > 0X2)

    M451 selection signal will be kept at active state between two successive transactions. If the AUTOSS bit is cleared, the slave selection output signal will be determined by the SS setting. The active state of the slave selection output signal is specified in SSACTPOL (SPI_SSCTL[2]).

  • Page 747: Figure 6.16-9 Byte Reorder Function

    M451 transmitted/received with MSB first. The rule of 16-bit mode is the same as above. Byte Reorder function is only available when DWIDTH is configured as 16, 24, and 32 bits. SPI_TX/SPI_RX TX/RX FIFO Buffer LSB = 0 (MSB first) MSB first MSB first &...

  • Page 748: Figure 6.16-11 Two-Bit Transfer Mode System Architecture

    M451 Note: This function is only supported in SPI0. 6.16.5.5 PDMA Transfer Function SPI controller supports PDMA transfer function. When TXPDMAEN (SPI_PDMACTL[0]) is set to 1, the controller will issue request to PDMA controller to start the PDMA transmission process automatically. When RXPDMAEN (SPI_PDMACTL[1]) is set to 1, the controller will start the PDMA reception process.

  • Page 749: Figure 6.16-12 Two-Bit Transfer Mode Timing (Master Mode)

    M451 SPI0_SS SPI0_CLK SPI0_MOSI0 TX Data (n) TX Data (n+2) SPI0_MISO0 RX Data (n) RX Data (n+2) SPI0_MOSI1 TX Data (n+1) TX Data (n+3) SPI0_MISO1 RX Data (n+1) RX Data (n+3) Figure 6.16-12 Two-Bit Transfer Mode Timing (Master Mode) 6.16.5.7 Dual I/O Mode The SPI0 controller also supports Dual I/O transfer when setting the DUALIOEN ((SPI_CTL[21]) to 1.

  • Page 750: Figure 6.16-13 Bit Sequence Of Dual Output Mode

    M451 Figure 6.16-13 Bit Sequence of Dual Output Mode SPI0_SS SPI0_CLK SPI0_MOSI0 7 6 5 4 3 2 1 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 Master output Input Slave input SPI0_MISO0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1...

  • Page 751: Figure 6.16-15 Bit Sequence Of Quad Output Mode

    M451 SPI0_SS SPI0_CLK SPI0_MOSI0 7 6 5 4 3 2 1 0 C 8 4 0 C 8 4 0 C 8 4 0 C 8 4 0 Master output Output Slave input SPI0_MISO0 D 9 5 1 D 9 5 1 D 9 5 1 D 9 5 1 Master input Output...

  • Page 752: Figure 6.16-17 Fifo Threshold Comparator

    M451 The data stored in the transmit FIFO buffer will be read and sent out by the transmission control logic. If the transmit FIFO buffer is full, the TXFULL (SPI_STATUS[17]) will be set to 1. When the SPI transmission logic unit draws out the last datum of the transmit FIFO buffer, so that the transmit FIFO buffer is empty, the TXEMPTY (SPI_STATUS[16]) will be set to 1.

  • Page 753: Figure 6.16-18 Transmit Fifo Buffer Example

    M451 TX Skew Buffer TX Shift Register Data 0 Data 0 Example 1 H/W load TX H/W load Shift DWIDTH =0 Write Buffer into Register into LSB = 1 1 Data Shift Register Skew Buffer TX Buffer Data 0 TXEMPTY = 1 TXEMPTY = 0 TXEMPTY = 1 TXEMPTY = 1...

  • Page 754: Figure 6.16-19 Receive Fifo Buffer Example

    M451 RX Skew Buffer 1. H/W load Shift Register Example 1 …………….b0 …………..b32 into RX Buffer RX Shift Register b31|b30...b1|b0 H/W Load 2. H/W Load DWIDTH =0 H/W Load 32 Skew Buffer Skew Buffer LSB = 1 bits into RX FIFO Buffer into Shift into Shift Shift Register...

  • Page 755: Figure 6.16-21 Two-Bit Transfer Mode Fifo Buffer Example

    M451 In 2-Bit Transfer mode, the transmit data is loaded into shift register after 2 datum have been written into the TX FIFO buffer. It uses 2 shift registers and 2 4-level skew buffers concurrently. The detail timing of 2-Bit Transfer mode, please refer to the section of Two-Bit Transfer mode. Example : SPI0_MOSI0 SPI0_MOSI1...

  • Page 756: Figure 6.16-23 Slave Mode Bit Count Error

    M451 SPIn_SS (SSACTPOL = 0) SPIn_CLK DWIDTH = 16 Data width Receive bit count != Reveive Bit DWIDTH Counter SLVBEIF Figure 6.16-23 Slave Mode Bit Count Error When the Slave selection signal is active and the value of SLVTOCNT (SPI_SSCTL[31:16]) is not 0, the Slave time-out counter in the SPI controller logic will start after the serial clock input.
  • Page 757 M451 (SPI_STATUS[1]) will be set to 1. The unit transfer interrupt event will generate an interrupt to CPU if the unit transfer interrupt enable bit UNITIEN (SPI_CTL[17]) is set. The unit transfer interrupt flag can be cleared only by writing 1 to it. ...

  • Page 758: Figure 6.16-25 I 2 S Data Format Timing Diagram

    M451  Transmit FIFO interrupt In FIFO mode, if the valid data count of the transmit FIFO buffer is less than or equal to the setting value of TXTH (SPI_FIFOCTL[30:28]), the transmit FIFO interrupt flag TXTHIF (SPI_STATUS[18]) will be set to 1. The SPI controller will generate a transmit FIFO interrupt to the system if the transmit FIFO interrupt enable bit, TXTHIEN (SPI_FIFOCTL[3]), is set to 1.

  • Page 759: Figure 6.16-26 Msb Justified Data Format Timing Diagram

    M451 In MSB justified data format, the MSB is sent and latched on the first clock of an audio channel. I2S_BCLK I2S_LRCLK I2S_DI / I2S_DO word N-1 word N word N+1 right channel left channel right channel Figure 6.16-26 MSB Justified Data Format Timing Diagram The I2S_LRCLK signal also supports PCM mode A and PCM mode B.

  • Page 760: Figure 6.16-29 Fifo Contents For Various I

    M451 6.16.5.12 S Mode FIFO operation Mono 8-bit data mode Stereo 8-bit data mode, ORDER (I2SCTL[7]) = 0 LEFT+1 RIGHT+1 LEFT RIGHT Stereo 8-bit data mode, ORDER (I2SCTL[7]) = 1 RIGHT+1 LEFT+1 RIGHT LEFT Mono 16-bit data mode Stereo 16-bit data mode, ORDER (I2SCTL[7]) = 0 LEFT RIGHT Stereo 16-bit data mode, ORDER (I2SCTL[7]) = 1...

  • Page 761: Timing Diagram

    M451 6.16.6 Timing Diagram The active state of slave selection signal can be defined by setting the SSACTPOL (SPI_SSCTL[2]). The SPI clock which is in idle state can be configured as high or low state by setting the CLKPOL (SPI_CTL[3]). It also provides the bit length of a transaction word in DWIDTH (SPI_CTL[12:8]), and transmitting/receiving data from MSB or LSB first in LSB bit (SPI_CTL[13]).

  • Page 762: Figure 6.16-32 Spi Timing In Slave Mode

    M451 SSACTPOL=1 SPIn_SS SSACTPOL=0 CLKPOL=0 SPIn_CLK CLKPOL=1 SPIn_MISO TX[6] TX[0] TX[7] TX[6] TX[7] TX[0] SPIn_MOSI RX[6] RX[0] RX[7] RX[6] RX[7] RX[0] Slave Mode: SLVAE=1, LSB=0, DWIDTH=0x08 1. CLKPOL=0, TXNEG=1, RXNEG=0 or 2. CLKPOL=1, TXNEG=0, RXNEG=1 Figure 6.16-32 SPI Timing in Slave Mode SSACTPOL=1 SPIn_SS SSACTPOL=0...

  • Page 763: Programming Examples

    M451 6.16.7 Programming Examples Example 1: The SPI controller is set as a master to access an off-chip slave device with the following specifications:  Data bit is latched on positive edge of SPI bus clock.  Data bit is driven on negative edge of SPI bus clock. ...
  • Page 764 M451  Data bit is latched on positive edge of SPI bus clock.  Data bit is driven on negative edge of SPI bus clock.  Data is transferred from LSB first.  SPI bus clock is high at idle state. ...

  • Page 765: Register Map

    M451 6.16.8 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value SPI Base Address: SPIn_BA = 0x4006_0000 + (0x1000 * n) n= 0,1,2 SPI_CTL SPIn_BA+0x00 R/W SPI Control Register 0x0000_0034 SPI_CLKDIV SPIn_BA+0x04 R/W SPI Clock Divider Register 0x0000_0000...

  • Page 766: Register Description

    M451 6.16.9 Register Description SPI Control Register (SPI_CTL) Register Offset Description Reset Value SPI_CTL SPIn_BA+0x00 SPI Control Register 0x0000_0034 Note: Not supported in I S mode. Reserved Reserved QUADIOEN DUALIOEN QDIODIR REORDER SLAVE UNITIEN TWOBIT Reserved DWIDTH SUSPITV CLKPOL TXNEG RXNEG SPIEN Bits...
  • Page 767 M451 2-bit Transfer Mode Enable Bit (Only Supported in SPI0) 0 = 2-Bit Transfer mode Disabled. 1 = 2-Bit Transfer mode Enabled. [16] TWOBIT Note: When 2-Bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2 serial transmitted bit data is from the second FIFO buffer data.
  • Page 768 M451 Note: Before changing the configurations of SPI_CTL, SPI_CLKDIV, SPI_SSCTL and SPI_FIFOCTL registers, user shall clear the SPIEN (SPI_CTL[0]) and confirm the SPIENSTS (SPI_STATUS[15]) is 0. May. 4, 2018 Page 768 of 1006 Rev.2.08...
  • Page 769 M451 SPI Clock Divider Register (SPI_CLKDIV) Register Offset Description Reset Value SPI_CLKDIV SPIn_BA+0x04 SPI Clock Divider Register 0x0000_0000 Reserved Reserved Reserved DIVIDER Bits Description [31:8] Reserved Reserved. Clock Divider The value in this field is the frequency divider for generating the peripheral clock, f spi_eclk and the SPI bus clock of SPI master.
  • Page 770 M451 SPI Slave Select Control Register (SPI_SSCTL) Register Offset Description Reset Value SPI_SSCTL SPIn_BA+0x08 SPI Slave Select Control Register 0x0000_0000 Note: Not supported in I S mode. SLVTOCNT SLVTOCNT Reserved SSINAIEN SSACTIEN Reserved SLVURIEN SLVBEIEN Reserved SLVTORST SLVTOIEN SLV3WIRE AUTOSS SSACTPOL Reserved Bits...
  • Page 771 M451 Slave 3-wire Mode Enable Bit (Only Supported in SPI0) Slave 3-wire mode is only available in SPI0. In Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPI0_CLK, SPI0_MISO and SPI0_MOSI pins. SLV3WIRE 0 = 4-wire bi-direction interface. 1 = 3-wire bi-direction interface.
  • Page 772 M451 SPI PDMA Control Register (SPI_PDMACTL) Register Offset Description Reset Value SPI_PDMACTL SPIn_BA+0x0C SPI PDMA Control Register 0x0000_0000 Reserved Reserved Reserved Reserved PDMARST RXPDMAEN TXPDMAEN Bits Description [31:3] Reserved Reserved. PDMA Reset 0 = No effect. PDMARST 1 = Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0.
  • Page 773 M451 SPI FIFO Control Register (SPI_FIFOCTL) Register Offset Description Reset Value SPI_FIFOCTL SPIn_BA+0x10 SPI FIFO Control Register 0x4400_0000 Reserved TXTH Reserved RXTH Reserved Reserved TXFBCLR RXFBCLR TXUFIEN TXUFPOL RXOVIEN RXTOIEN TXTHIEN RXTHIEN TXRST RXRST Bits Description [31] Reserved Reserved. Transmit FIFO Threshold If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH [30:28] TXTH...
  • Page 774 M451 TX Underflow Data Polarity 0 = The SPI data out is keep 0 if there is TX underflow event in Slave mode. 1 = The SPI data out is keep 1 if there is TX underflow event in Slave mode. TXUFPOL Note 1: The TX underflow event occurs if there is not any data in TX FIFO when the slave selection signal is active.
  • Page 775 M451 SPI Status Register (SPI_STATUS) Register Offset Description Reset Value SPI_STATUS SPIn_BA+0x14 SPI Status Register 0x0005_0110 Note: Not supported in I S mode. TXCNT RXCNT TXRXRST Reserved TXUFIF TXTHIF TXFULL TXEMPTY SPIENSTS Reserved RXTOIF RXOVIF RXTHIF RXFULL RXEMPTY SLVURIF SLVBEIF SLVTOIF SSLINE SSINAIF...
  • Page 776 M451 Transmit FIFO Buffer Empty Indicator (Read Only) [16] TXEMPTY 0 = Transmit FIFO buffer is not empty. 1 = Transmit FIFO buffer is empty. SPI Enable Status (Read Only) 0 = The SPI controller is disabled. [15] SPIENSTS 1 = The SPI controller is enabled. Note: The SPI peripheral clock is asynchronous with the system clock.
  • Page 777 M451 detected, the slave time-out counter in SPI controller logic will be started. When the value of time-out counter is greater than or equal to the value of SLVTOCNT (SPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted.
  • Page 778 M451 SPI Data Transmit Register (SPI_TX) Register Offset Description Reset Value SPI_TX SPIn_BA+0x20 Data Transmit Register 0x0000_0000 Bits Description Data Transmit Register The data transmit registers pass through the transmitted data into the 8-/4-level transmit FIFO buffer. The number of valid bits depends on the setting of DWIDTH (SPI_CTL[12:8]) in SPI mode or WDWIDTH (SPI_I2SCTL[5:4]) in I S mode.
  • Page 779 M451 SPI Data Receive Register (SPI_RX) Register Offset Description Reset Value SPI_RX SPIn_BA+0x30 Data Receive Register 0x0000_0000 Bits Description Data Receive Register There are 8-/4-level FIFO buffers in this controller. The data receive register holds the data [31:0] received from SPI data input pin. If the RXEMPTY (SPI_STATUS[8] or SPI_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register.
  • Page 780 M451 S Control Register (SPI_I2SCTL) Register Offset Description Reset Value SPI_I2SCTL SPIn_BA+0x60 S Control Register 0x0000_0000 Note: Not supported in SPI mode. Reserved FORMAT Reserved LZCIEN RZCIEN RXLCH Reserved LZCEN RZCEN MCLKEN Reserved SLAVE ORDER MONO WDWIDTH MUTE RXEN TXEN I2SEN Bits Description...
  • Page 781 M451 Right Channel Zero Cross Detection Enable Bit If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPI_I2SSTS register will be set to 1. This function is only available in [16] RZCEN transmit operation.
  • Page 782 M451 S Clock Divider Control Register (SPI_I2SCLK) Register Offset Description Reset Value SPI_I2SCLK SPIn_BA+0x64 S Clock Divider Control Register 0x0000_0000 Note: Not supported in SPI mode. Reserved Reserved BCLKDIV BCLKDIV Reserved MCLKDIV Bits Description [31:17] Reserved Reserved. Bit Clock Divider The I S controller will generate bit clock in Master mode.
  • Page 783 M451 S Status Register (SPI_I2SSTS) Register Offset Description Reset Value SPI_I2SSTS SPIn_BA+0x68 S Status Register 0x0005_0100 Note: Not supported in SPI mode. Reserved TXCNT Reserved RXCNT TXRXRST Reserved LZCIF RZCIF TXUFIF TXTHIF TXFULL TXEMPTY I2SENSTS Reserved RXTOIF RXOVIF RXTHIF RXFULL RXEMPTY Reserved RIGHT...
  • Page 784 M451 value of TXTH. Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI/I S controller will generate a SPI interrupt request. Transmit FIFO Buffer Full Indicator (Read Only) TXFULL [17] 0 = Transmit FIFO buffer is not full. 1 = Transmit FIFO buffer is full.

  • Page 785: Usb Device Controller (Usbd)

    M451 6.17 USB Device Controller (USBD) 6.17.1 Overview There is one set of USB 2.0 full-speed device controller and transceiver in this device. It is compliant with USB 2.0 full-speed device specification and supports Control/Bulk/Interrupt/ Isochronous transfer types. In this device controller, there are two main interfaces: the APB bus and USB bus which comes from the USB PHY transceiver.

  • Page 786: Block Diagram

    M451 6.17.3 Block Diagram Clock NVIC Generator VBUS VBUS Detection Interrupt Detection DPLL Control Control De-bouncing Status Registers USB_D+ APB Bus RXDP Endpoint USB_D- RXDM Control SRAM USB_VBUS Buffer (512 Control bytes) Transceiver Figure 6.17-1 USB Block Diagram 6.17.4 Basic Configuration The role of USB frame is determined by USBROLE (SYS_USBPHY[1:0]).

  • Page 787: Figure 6.17-2 Nevwk Interrupt Operation Flow

    M451 6.17.5.3 Digital Phase Lock Loop (DPLL) The bit rate of USB data is 12 MHz. The DPLL uses the 48 MHz which comes from the clock controller to lock the input data RXDP and RXDM. The 12 MHz bit rate clock is also converted from DPLL.

  • Page 788: Figure 6.17-3 Endpoint Sram Structure

    M451 The USB interrupt is used to notify users of any USB event on the bus, and user can read EPSTS (USBD_EPSTS[31:8]) and EPEVT7~0 (USBD_INTSTS[23:16]) to take necessary responses. Same as USB interrupt, BUS interrupt notifies users of some bus events, like USB reset, suspend, time-out and resume.

  • Page 789: Figure 6.17-4 Setup Transaction Followed By Data In Transaction

    M451 6.17.5.8 Handling Transactions with USB Device Peripheral User can use interrupt or polling USBD_INTSTS to monitor the USB transactions. When transactions occur, USBD_INTSTS will be set by hardware and send an interrupt request to CPU (if related interrupt enabled), or user can polling USBD_INTSTS to get these events without interrupt.

  • Page 790: Register Map

    M451 6.17.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value USBD Base Address: USBD_BA = 0x400C_0000 USBD_INTEN USBD_BA+0x000 R/W USB Device Interrupt Enable Register 0x0000_0000 USBD_INTSTS USBD_BA+0x004 R/W USB Device Interrupt Event Status Register 0x0000_0000 USBD_FADDR USBD_BA+0x008 R/W USB Device Function Address Register...
  • Page 791 M451 USBD_MXPLD4 USBD_BA+0x544 R/W USB Endpoint 4 Maximal Payload Register 0x0000_0000 USBD_CFG4 USBD_BA+0x548 R/W USB Endpoint 4 Configuration Register 0x0000_0000 USB Endpoint 4 Set Stall and Clear In/Out Ready Control USBD_CFGP4 USBD_BA+0x54C R/W 0x0000_0000 Register USBD_BUFSEG5 USBD_BA+0x550 R/W USB Endpoint 5 Buffer Segmentation Register 0x0000_0000 USBD_MXPLD5 USBD_BA+0x554 R/W USB Endpoint 5 Maximal Payload Register...

  • Page 792: Register Description

    M451 6.17.7 Register Description USB Interrupt Enable Register (USBD_INTEN) Register Offset Description Reset Value USBD_INTEN USBD_BA+0x000 R/W USB Device Interrupt Enable Register 0x0000_0000 Reserved Reserved INNAKEN Reserved WKEN Reserved NEVWKIEN VBDETIEN USBIEN BUSIEN Bits Description [31:16] Reserved Reserved. Active NAK Function and Its Status in IN Token 0 = When device responds NAK after receiving IN token, IN NAK status will not be [15] INNAKEN...
  • Page 793 M451 USB Interrupt Event Status Register (USBD_INTSTS) Register Offset Description Reset Value USBD_INTSTS USBD_BA+0x004 R/W USB Device Interrupt Event Status Register 0x0000_0000 SETUP Reserved EPEVT7 EPEVT6 EPEVT5 EPEVT4 EPEVT3 EPEVT2 EPEVT1 EPEVT0 Reserved Reserved NEVWKIF VBDETIF USBIF BUSIF Bits Description Setup Event Status SETUP [31]...
  • Page 794 M451 Endpoint 2’s USB Event Status 0 = No event occurred in endpoint 2. [18] EPEVT2 1 = USB event occurred on Endpoint 2, check USBD_EPSTS[16:14] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[18] or USBD_INTSTS[1].
  • Page 795 M451 USB Device Function Address Register (USBD_FADDR) A 7-bit value is used as the address of a device on the USB BUS. Register Offset Description Reset Value USBD_FADDR USBD_BA+0x008 R/W USB Device Function Address Register 0x0000_0000 Reserved Reserved Reserved Reserved FADDR Bits Description...
  • Page 796 M451 USB Endpoint Status Register (USBD_EPSTS) Register Offset Description Reset Value USBD_EPSTS USBD_BA+0x00C R USB Device Endpoint Status Register 0x0000_0000 EPSTS7 EPSTS6 EPSTS5 EPSTS5 EPSTS4 EPSTS3 EPSTS2 EPSTS2 EPSTS1 EPSTS0 Reserved Bits Description Endpoint 7 Status These bits are used to indicate the current status of this endpoint 000 = In ACK.
  • Page 797 M451 010 = Out Packet Data0 ACK. 011 = Setup ACK. 110 = Out Packet Data1 ACK. 111 = Isochronous transfer end. Endpoint 3 Status These bits are used to indicate the current status of this endpoint 000 = In ACK. 001 = In NAK.
  • Page 798 M451 USB Bus Status and Attribution Register (USBD_ATTR) Register Offset Description Reset Value USBD_ATTR USBD_BA+0x010 R/W USB Device Bus Status and Attribution Register 0x0000_0040 Reserved Reserved Reserved BYTEM PWRDN DPPUEN USBEN Reserved RWAKEUP PHYEN TOUT RESUME SUSPEND USBRST Bits Description [31:11] Reserved Reserved.
  • Page 799 M451 0 = No bus resume. 1 = Resume from suspend. Note: This bit is read only. Suspend Status 0 = Bus no suspend. SUSPEND 1 = Bus idle more than 3 ms, either cable is plugged off or host is sleeping. Note: This bit is read only.
  • Page 800 M451 USB Device VBUS Detection Register (USBD_VBUSDET) Register Offset R/W Description Reset Value USBD_VBUSDET USBD_BA+0x014 R USB Device VBUS Detection Register 0x0000_0000 Reserved Reserved Reserved Reserved VBUSDET Bits Description [31:1] Reserved Reserved. Device VBUS Detection VBUSDET 0 = Controller is not attached to the USB host. 1 = Controller is attached to the USB host.
  • Page 801 M451 USB Setup Token Buffer Segmentation Register (USBD_STBUFSEG) Register Offset R/W Description Reset Value USBD_STBUFSEG USBD_BA+0x018 R/W USB Setup Token Buffer Segmentation Register 0x0000_0000 Reserved Reserved Reserved STBUFSEG STBUFSEG Reserved Bits Description [31:9] Reserved Reserved. SETUP Token Buffer Segmentation It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is [8:3] STBUFSEG...
  • Page 802 M451 USB Device Drive SE0 Register (USBD_SE0) Register Offset Description Reset Value USBD_SE0 USBD_BA+0x090 R/W USB Device Drive SE0 Control Register 0x0000_0001 Reserved Reserved Reserved Reserved Bits Description [31:1] Reserved Reserved. Drive Single Ended Zero in USB Bus The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low.
  • Page 803 M451 USB Endpoint Buffer Segmentation Register (USB_BUFSEGx) Register Offset Description Reset Value USBD_BUFSEG0 USBD_BA+0x500 R/W USB Endpoint 0 Buffer Segmentation Register 0x0000_0000 USBD_BUFSEG1 USBD_BA+0x510 R/W USB Endpoint 1 Buffer Segmentation Register 0x0000_0000 USBD_BUFSEG2 USBD_BA+0x520 R/W USB Endpoint 2 Buffer Segmentation Register 0x0000_0000 USBD_BUFSEG3 USBD_BA+0x530 R/W USB Endpoint 3 Buffer Segmentation Register...
  • Page 804 M451 USB Endpoint Maximal Payload Register (USB_MXPLDx) Register Offset Description Reset Value USBD_MXPLD0 USBD_BA+0x504 R/W USB Endpoint 0 Maximal Payload Register 0x0000_0000 USBD_MXPLD1 USBD_BA+0x514 R/W USB Endpoint 1 Maximal Payload Register 0x0000_0000 USBD_MXPLD2 USBD_BA+0x524 R/W USB Endpoint 2 Maximal Payload Register 0x0000_0000 USBD_MXPLD3 USBD_BA+0x534 R/W USB Endpoint 3 Maximal Payload Register...
  • Page 805 M451 USB Endpoint Configuration Register (USB_CFGx) Register Offset Description Reset Value USBD_CFG0 USBD_BA+0x508 R/W USB Endpoint 0 Configuration Register 0x0000_0000 USBD_CFG1 USBD_BA+0x518 R/W USB Endpoint 1 Configuration Register 0x0000_0000 USBD_CFG2 USBD_BA+0x528 R/W USB Endpoint 2 Configuration Register 0x0000_0000 USBD_CFG3 USBD_BA+0x538 R/W USB Endpoint 3 Configuration Register 0x0000_0000 USBD_CFG4...
  • Page 806 M451 This bit is used to set the endpoint as Isochronous endpoint, no handshaking. 0 = No Isochronous endpoint. 1 = Isochronous endpoint. Endpoint Number EPNUM [3:0] These bits are used to define the endpoint number of the current endpoint May.
  • Page 807 M451 USB Endpoint Extra Configuration Register (USB_CFGPx) Register Offset Description Reset Value USB Endpoint 0 Set Stall and Clear In/Out Ready Control USBD_CFGP0 USBD_BA+0x50C R/W 0x0000_0000 Register USB Endpoint 1 Set Stall and Clear In/Out Ready Control USBD_CFGP1 USBD_BA+0x51C R/W 0x0000_0000 Register USB Endpoint 2 Set Stall and Clear In/Out Ready Control...

  • Page 808: Usb 1.1 Host Controller (Usbh)

    M451 1 = Clear the OUT token had ready to receive the data from USB host. This bit is write 1 only and is always 0 when it is read back. 6.18 USB 1.1 Host Controller (USBH) 6.18.1 Overview This chip is equipped with a USB 1.1 Host Controller (USBH) that supports Open Host Controller Interface (OpenHCI, OHCI) Specification, a register-level description of a host controller, to manage the devices and data transfer of Universal Serial Bus (USB).

  • Page 809: Block Diagram

    M451 6.18.3 Block Diagram AHB Bus AHB Interface Wrapper Control Register Master List Processor Frame Data Management Buffer Interrupts Root Hub Control Clock Generator Port Control USB_D- USB_D+ Figure 6.18-1 USB 1.1 Host Controller Block Diagram May. 4, 2018 Page 809 of 1006 Rev.2.08...

  • Page 810: Basic Configuration

    M451 6.18.4 Basic Configuration The USBH clock source is derived from PLL. User has to set the PLL related configurations before USB host controller is enabled. Set the USBHCKEN (CLK_AHBCLK[4]) bit to enable USBH clock and 4-bit pre-scaler USBDIV (CLK_CLKDIV0[7:4]) to generate the proper USBH clock rate.
  • Page 811 M451 The Root Hub is a collection of ports that are individually controlled and a hub that maintains control/status over functions common to all ports. May. 4, 2018 Page 811 of 1006 Rev.2.08...

  • Page 812: Register Map

    M451 6.18.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value USBH Base Address: USBH_BA = 0x4000_9000 HCREVISION USBH_BA+0x000 Host Controller Revision Register 0x0000_0110 HCCONTROL USBH_BA+0x004 Host Controller Control Register 0x0000_0000 HCCOMMAND USBH_BA+0x008 Host Controller CMD Status Register...
  • Page 813 M451 HCRHPORTS USBH_BA+0x054 Host Controller Root Hub Port Status [1] 0x0000_0000 TATUS1 HCPHYCONT USBH_BA+0x200 Host Controller PHY Control Regsiter 0x0000_0000 HCMISCCONT USBH_BA+0x204 Host Controller Miscellaneous Control Register 0x0000_0000 May. 4, 2018 Page 813 of 1006 Rev.2.08...

  • Page 814: Register Description

    M451 6.18.7 Register Description Host Controller Revision Register (HcRevision) Register Offset Description Reset Value HCREVISION USBH_BA+0x000 R Host Controller Revision Register 0x0000_0110 Reserved Reserved Reserved Bits Description [31:8] Reserved Reserved. Revision Number Indicates the Open HCI Specification revision number implemented by the Hardware. [7:0] Host Controller supports 1.1 specification.
  • Page 815 M451 Host Controller Control Register (HcControl) Register Offset Description Reset Value HCCONTROL USBH_BA+0x004 R/W Host Controller Control Register 0x0000_0000 Reserved Reserved Reserved HCFS CBSR Bits Description [31:8] Reserved Reserved. Host Controller Functional State This field sets the Host Controller state. The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port.
  • Page 816 M451 Periodic List Enable Bit When set, this bit enables processing of the Periodic (interrupt and isochronous) list. The Host Controller checks this bit prior to attempting any periodic transfers in a frame. 0 = Processing of the Periodic (Interrupt and Isochronous) list after next SOF (Start-Of- Frame) Disabled.
  • Page 817 M451 Host Controller CMD Status Register (HcCommandStatus) Register Offset Description Reset Value HCCOMMANDS USBH_BA+0x008 R/W Host Controller CMD Status Register 0x0000_0000 TATUS Reserved Reserved Reserved Reserved Bits Description [31:18] Reserved Reserved. Schedule Overrun Count These bits are incremented on each scheduling overrun error. It is initialized to 00b and [17:16] wraps around at 11b.
  • Page 818 M451 Host Controller Interrupt Status Register (HcInterruptStatus) Register Offset Description Reset Value HCINTERRUPTS USBH_BA+0x00 Host Controller Interrupt Status Register 0x0000_0000 TATUS Reserved Reserved Reserved Reserved RHSC Reserved Bits Description [31:7] Reserved Reserved. Root Hub Status Change This bit is set when the content of HcRhStatus or the content of HcRhPortStatus1 register has changed.
  • Page 819 M451 Scheduling Overrun Set when the List Processor determines a Schedule Overrun has occurred. 0 = Schedule Overrun didn’t occur. 1 = Schedule Overrun has occurred. May. 4, 2018 Page 819 of 1006 Rev.2.08...
  • Page 820 M451 Host Controller Interrupt Enable Register (HcInterruptEnable) Register Offset Description Reset Value HCINTERRUPTE USBH_BA+0x010 R/W Host Controller Interrupt Enable Register 0x0000_0000 NABLE Reserved Reserved Reserved Reserved RHSC Reserved Bits Description Master Interrupt Enable Bit This bit is a global interrupt enable. A write of ‘1’ allows interrupts to be enabled via the specific enable bits listed above.
  • Page 821 M451 Frame Number Overflow Enable Bit Write Operation: 0 = No effect. 1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled. Read Operation: 0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled. 1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled. Reserved Reserved.
  • Page 822 M451 Host Controller Interrupt Disable Register (HcInterruptDisable) Register Offset Description Reset Value HCINTERRUPTD USBH_BA+0x014 R/W Host Controller Interrupt Disable Register 0x0000_0000 ISABLE Reserved Reserved Reserved Reserved RHSC Reserved Bits Description Master Interrupt Disable Bit Global interrupt disable. Writing ‘1’ to disable all interrupts. Write Operation: 0 = No effect.
  • Page 823 M451 Reserved Reserved. Resume Detected Disable Bit Write Operation: 0 = No effect. 1 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled. Read Operation: 0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled. 1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled. Start of Frame Disable Bit Write Operation: 0 = No effect.
  • Page 824 M451 Host Controller Communication Area Register (HcHCCA) Register Offset Description Reset Value HCHCCA USBH_BA+0x018 R/W Host Controller Communication Area Register 0x0000_0000 HCCA HCCA HCCA Reserved Bits Description Host Controller Communication Area [31:8] HCCA Pointer to indicate base address of the Host Controller Communication Area (HCCA). [7:0] Reserved Reserved.
  • Page 825 M451 Host Controller Period Current ED Register (HcPeriodCurrentED) Register Offset Description Reset Value HCPERIODCUR USBH_BA+0x01 Host Controller Period Current ED Register 0x0000_0000 RENTED PCED PCED PCED PCED Reserved Bits Description Periodic Current ED [31:4] PCED Pointer to indicate physical address of the current Isochronous or Interrupt Endpoint Descriptor.
  • Page 826 M451 Host Controller Control Head ED Register (HcControlHeadED) Register Offset Description Reset Value HCCONTROLHE USBH_BA+0x020 R/W Host Controller Control Head ED Register 0x0000_0000 ADED CHED CHED CHED CHED Reserved Bits Description Control Head ED [31:4] CHED Pointer to indicate physical address of the first Endpoint Descriptor of the Control list. [3:0] Reserved Reserved.
  • Page 827 M451 Host Controller Control Current ED Register (HcControlCurrentED) Register Offset Description Reset Value HCCONTROLCU USBH_BA+0x024 R/W Host Controller Control Current ED Register 0x0000_0000 RRENTED CCED CCED CCED CCED Reserved Bits Description Control Current Head ED [31:4] CCED Pointer to indicate the physical address of the current Endpoint Descriptor of the Control list.
  • Page 828 M451 Host Controller Bulk Head ED Register (HcBulkHeadED) Register Offset Description Reset Value HCBULKHEADE USBH_BA+0x028 R/W Host Controller Bulk Head ED Register 0x0000_0000 BHED BHED BHED BHED Reserved Bits Description Bulk Head ED [31:4] BHED Pointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list. [3:0] Reserved Reserved.
  • Page 829 M451 Host Controller Bulk Current Head ED Register (HcBulkCurrentED) Register Offset Description Reset Value HCBULKCURRE USBH_BA+0x02 Host Controller Bulk Current ED Register 0x0000_0000 NTED BCED BCED BCED BCED Reserved Bits Description Bulk Current Head ED [31:4] BCED Pointer to indicate the physical address of the current endpoint of the Bulk list. [3:0] Reserved Reserved.
  • Page 830 M451 Host Controller Done Head Register (HcDoneHead) Register Offset Description Reset Value HCDONEHEAD USBH_BA+0x030 R/W Host Controller Done Head Register 0x0000_0000 Reserved Bits Description Done Head [31:4] Pointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue.
  • Page 831 M451 Host Controller Frame Interval Register (HcFmInterval) Register Offset Description Reset Value HCFMINTERVAL USBH_BA+0x034 R/W Host Controller Frame Interval Register 0x0000_2EDF FSMPS FSMPS Reserved Bits Description Frame Interval Toggle This bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmInterval[13:0]).
  • Page 832 M451 Host Controller Frame Remaining Register (HcFmRemaining) Register Offset Description Reset Value HCFMREMAININ USBH_BA+0x038 R Host Controller Frame Remaining Register 0x0000_0000 Reserved Reserved Reserved Bits Description Frame Remaining Toggle [31] This bit is loaded from the FIT (HcFmInterval[31]) whenever FR (HcFmRemaining[13:0]) reaches 0.
  • Page 833 M451 Host Controller Frame Number Register (HcFmNumber) Register Offset Description Reset Value USBH_BA+0x03 HCFMNUMBER Host Controller Frame Number Register 0x0000_0000 Reserved Reserved Bits Description [31:16] Reserved Reserved. Frame Number [15:0] This 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRemaining[13:0]).
  • Page 834 M451 Host Controller Periodic Start Register (HcPeriodicStart) Register Offset Description Reset Value HCPERIODICST USBH_BA+0x040 R/W Host Controller Periodic Start Register 0x0000_0000 Reserved Reserved Reserved Bits Description [31:14] Reserved Reserved. Periodic Start [13:0] This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin.
  • Page 835 M451 Host Controller Low-speed Threshold Register (HcLSThreshold) Register Offset Description Reset Value HCLSTHRESHO USBH_BA+0x044 R/W Host Controller Low-speed Threshold Register 0x0000_0628 Reserved Reserved Reserved Bits Description [31:12] Reserved Reserved. Low-speed Threshold This field contains a value which is compared to the FR (HcFmRemaining[13:0]) field [11:0] prior to initiating a Low-speed transaction.
  • Page 836 M451 Host Controller Root Hub Descriptor A Register (HcRhDescriptorA) Register Offset Description Reset Value HCRHDESCRIP USBH_BA+0x048 R/W Host Controller Root Hub Descriptor A Register 0x0000_0902 TORA Reserved Reserved Reserved NOCP OCPM Reserved Bits Description [31:13] Reserved Reserved. No over Current Protection This bit describes how the over current status for the Root Hub ports reported.
  • Page 837 M451 Host Controller Root Hub Descriptor B Register (HcRhDescriptorB) Register Offset Description Reset Value HCRHDESCRIP USBH_BA+0x04 Host Controller Root Hub Descriptor B Register 0x0000_0000 TORB PPCM PPCM Reserved Reserved Bits Description Port Power Control Mask Global power switching. This field is only valid if PowerSwitchingMode is set (individual port switching).
  • Page 838 M451 Host Controller Root Hub Status Register (HcRhStatus) Register Offset Description Reset Value HCRHSTATUS USBH_BA+0x050 R/W Host Controller Root Hub Status Register 0x0000_0000 CRWE Reserved Reserved OCIC LPSC DRWE Reserved Reserved Bits Description Clear Remote Wake-up Enable Bit This bit is use to clear DRWE (HcRhStatus[15]). This bit always read as zero.
  • Page 839 M451 [14:2] Reserved Reserved. over Current Indicator This bit reflects the state of the over current status pin. This field is only valid if NOCP (HcRhDesA[12]) and OCPM (HcRhDesA[11]) are cleared. 0 = No over current condition. 1 = Over current condition. Clear Global Power In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to clear all ports’...
  • Page 840 M451 Host Controller Root Hub Port Status (HcRhPrt [1]) Register Offset Description Reset Value HCRHPORTSTA USBH_BA+0x054 R/W Host Controller Root Hub Port Status [1] 0x0000_0000 TUS1 Reserved Reserved PRSC OCIC PSSC PESC Reserved LSDA Reserved POCI Bits Description [31:21] Reserved Reserved.
  • Page 841 M451 Connect Status Change This bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus1[0]) changed). Write 1 to clear this bit to zero. [16] 0 = No connect/disconnect event (CCS (HcRhPortStatus1[0]) didn’t change). 1 = Hardware detection of connect/disconnect event (CCS (HcRhPortStatus1[0]) changed).
  • Page 842 M451 Port Suspend Status This bit indicates the port is suspended Write Operation: 0 = No effect. 1 = Set port suspend. Read Operation: 0 = Port is not suspended. 1 = Port is selectively suspended. Port Enable Status Write Operation: 0 = No effect.
  • Page 843 M451 Host Controller PHY Control Regsiter (HcPhyControl) Register Offset Description Reset Value HCPHYCONTRO USBH_BA+0x200 R/W Host Controller PHY Control Regsiter 0x0000_0000 Reserved STBYEN Reserved Reserved Reserved Reserved Bits Description [31:28] Reserved Reserved. USB Transceiver Standby Enable Bit This bit controls if USB transceiver could enter the standby mode to reduce power consumption.
  • Page 844 M451 Host Controller Miscellaneous Control Register (HcMiscControl) Register Offset Description Reset Value HCMISCCONTR USBH_BA+0x204 R/W Host Controller Miscellaneous Control Register 0x0000_0000 Reserved Reserved DPRT1 Reserved Reserved OCAL Reserved ABORT Reserved Bits Description [31:17] Reserved Reserved. Disable Port 1 This bit controls if the connection between USB host controller and transceiver of port 1 is disabled.

  • Page 845: Usb On-The-Go (Otg)

    M451 6.19 USB On-The-Go (OTG) 6.19.1 Overview The OTG controller interfaces to USB PHY and USB controllers which consist of a USB 1.1 host controller and a USB 2.0 FS device controller. The OTG controller supports HNP and SRP protocols defined in the “On-The-Go and Embedded Host Supplement to the USB 2.0 Revision 1.3 Specification”.

  • Page 846: Block Diagram

    M451 6.19.3 Block Diagram USB_VBUS_EN USB VBUS Power USB_VBUS_ST Switch Enable Status OTG Controller USB_VBUS OTG Registers USB_D- Host 1.1 Controller USB_D+ Host_Device USB PHY Device 2.0 FS Controller USB_VDD33_CAP OTG State USB_ID Machine USBROLE (SYS_USBPHY[1:0]) LDO33EN (SYS_USBPHY[8]) USB 3.3V LDO Figure 6.19-1 USB OTG Block Diagram 6.19.4 Basic Configuration The OTG peripheral clock can be enabled by OTGCKEN (CLK_APBCLK0[26]).

  • Page 847: Figure 6.19-2 Usb Device Mode

    M451 USB_VBUS_EN Enable USB VBUS Power USB_VBUS_ST Switch Status OTG Controller USB_VBUS OTG Registers USB_D- USB_D+ Host_Device USB PHY Device 2.0 FS Controller USB_VDD33_CAP OTG State USB_ID Machine USBROLE (SYS_USBPHY[1:0]) LDO33EN (SYS_USBPHY[8]) USB 3.3V LDO Figure 6.19-2 USB Device Mode USB Host Mode When USBROLE (SYS_USBPHY[1:0]) is set to 1, USB frame acts as USB host.
  • Page 848 M451 When USBROLE (SYS_USBPHY[1:0]) is set to 2, the role of USB frame depends on USB_ID pin status. The ID detection function can be enabled by set IDDETEN (OTG_PHYCTL[1]) to 1. The USB_ID pin status reflects on IDSTS (OTG_STATUS[1]). When USB frame acts as USB host (USB_ID pin is low level), the block diagram is the same as USB Host mode.

  • Page 849: Register Map

    M451 1. A-Host defined in OTG specification sends SetFeature b_hnp_enable command to enable B- device HNP capability. B-device responses ACK to indicate B-device supports HNP. User needs to set HNPREQEN (OTG_CTL[2]) to 1 to enable HNP protocol. 2. A-Host goes to a_suspend state by setting BUSREQ (OTG_CTL[1]) to 0 and put USB bus into J- state (USB_D+ high and USB_D- low) when A-Host has finished all desired operations.

  • Page 850: Register Description

    M451 6.19.7 Register Description OTG Control Register (OTG_CTL) Register Offset Description Reset Value OTG_CTL OTG_BA+0x00 OTG Control Register 0x0000_0000 Reserved Reserved Reserved Reserved WKEN OTGEN Reserved HNPREQEN BUSREQ VBUSDROP Bits Description [31:6] Reserved Reserved. OTG ID Pin Wake-up Enable Bit WKEN 0 = OTG ID pin status change wake-up function Disabled.
  • Page 851 M451 Bits Description device issues ARP in specified interval, defined in OTG specification). This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set IDSTS (OTG_STATUS[1]) changed. 0 = Not launch VBUS in OTG A-device or not request SRP in OTG B-device. 1 = Launch VBUS in OTG A-device or request SRP in OTG B-device.
  • Page 852 M451 OTG PHY Control Register (OTG_PHYCTL) Register Offset Description Reset Value OTG_PHYCTL OTG_BA+0x04 OTG PHY Control Register 0x0000_0000 Reserved Reserved Reserved Reserved VBSTSPOL VBENPOL Reserved IDDETEN OTGPHYEN Bits Description [31:6] Reserved Reserved. Off-chip USB VBUS Power Switch Status Polarity The polarity of off-chip USB VBUS power switch valid signal depends on the selected component.
  • Page 853 M451 OTG Interrupt Enable Register (OTG_INTEN) Register Offset Description Reset Value OTG_INTEN OTG_BA+0x08 OTG Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved SRPDETIEN Reserved SECHGIEN VBCHGIEN AVLDCHGIEN BVLDCHGIEN HOSTIEN PDEVIEN IDCHGIEN GOIDLEIEN HNPFIEN SRPFIEN VBEIEN ROLECHGIEN Bits Description [31:14] Reserved Reserved. SRP Detected Interrupt Enable Bit [13] SRPDETIEN...
  • Page 854 M451 Bits Description 0 = This device as a host interrupt Disabled. 1 = This device as a host interrupt Enabled. Act As Peripheral Interrupt Enable Bit If this bit is set to 1 and the device is changed as a peripheral, a interrupt will be asserted. PDEVIEN 0 = This device as a peripheral interrupt Disabled.
  • Page 855 M451 OTG Interrupt Status Register (OTG_INTSTS) Register Offset Description Reset Value OTG_INTSTS OTG_BA+0x0C OTG Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved SRPDETIF Reserved SECHGIF VBCHGIF AVLDCHGIF BVLDCHGIF HOSTIF PDEVIF IDCHGIF GOIDLEIF HNPFIF SRPFIF VBEIF ROLECHGIF Bits Description [31:14] Reserved Reserved. SRP Detected Interrupt Status 0 = SRP not detected.
  • Page 856 M451 Bits Description Act As Peripheral Interrupt Status 0= This device does not act as a peripheral. PDEVIF 1 = This device acts as a peripheral. Note: Write 1 to clear this flag. ID State Change Interrupt Status 0 = IDSTS (OTG_STATUS[1]) not toggled. IDCHGIF 1 = IDSTS (OTG_STATUS[1]) from high to low or from low to high.
  • Page 857 M451 OTG Functional Status Register (OTG_STATUS) Register Offset Description Reset Value OTG_STATUS OTG_BA+0x10 OTG Status Register 0x0000_0006 Reserved Reserved Reserved Reserved VBUSVLD AVLD BVLD SESSEND IDSTS OVERCUR Bits Description [31:6] Reserved Reserved. VBUS Valid Status When VBUS is larger than 4.7V, this bit will be set to 1. VBUSVLD 0 = VBUS is not valid.

  • Page 858: Controller Area Network (Can)

    M451 6.20 Controller Area Network (CAN) 6.20.1 Overview The C_CAN consists of the CAN Core, Message RAM, Message Handler, Control Registers and Module Interface (Refer to Figure 6.20-1 CAN Peripheral Block Diagram) The CAN Core performs communication according to the CAN protocol version 2.0 part A and B. The bit rate can be programmed to values up to 1MBit/s.

  • Page 859: Functional Description

    M451  Message RAM Stores Message Objects and Identifier Masks  Registers All registers used to control and to configure the C_CAN.  Message Handler State Machine that controls the data transfer between the Rx/Tx Shift Register of the CAN Core and the Message RAM as well as the generation of interrupts as programmed in the Control and Configuration Registers.
  • Page 860 M451 should be cleared. Otherwise, the entire Message Object has to be initialized. Access to the Bit Timing Register and to the Baud Rate Prescaler Extension Register for configuring bit timing is enabled when both the Init and CCE (CAN_CON[6]) bits are set. Resetting the Init bit (by software only) finishes the software initialization.

  • Page 861: Test Mode

    M451 NewDat remains set. • When the transmission completed successfully, bit NewDat is cleared. • When a transmission fails (lost arbitration or error), bit NewDat remains set. • To restart the transmission, the software should set the bit TxRqst again. 6.20.6 Test Mode Test Mode is entered by setting the Test bit (CAN_CON[7]).

  • Page 862: Figure 6.20-3 Can Core In Loop Back Mode

    M451 CAN_TX CAN_RX C_CAN CAN_Core Figure 6.20-3 CAN Core in Loop Back Mode This mode is provided for self-test functions. To be independent from external stimulation, the CAN Core ignores acknowledge errors (recessive bit sampled in the acknowledge slot of a data/ remote frame) in Loop Back Mode.

  • Page 863: Can Communications

    M451 A pending transmission can be aborted at any time by resetting the Busy bit in the IF1 Command Request Register while the IF1 Registers are locked. If the software has reset the Busy bit, a possible retransmission in case of lost arbitration or in case of an error is disabled. The IF2 Registers are used as a Receive Buffer.
  • Page 864 M451 the Message RAM and the IFn Registers. The Message Handler FSM controls the following functions: • Data Transfer from IFn Registers to the Message RAM • Data Transfer from Message RAM to the IFn Registers • Data Transfer from Shift Register to the Message RAM •...

  • Page 865: Figure 6.20-5 Data Transfer Between Ifn Registers And Message

    M451 START Write Command Request Register Busy = 1 WR/RD = 1 Read Message Object to IFn Read Message Object to IFn Write IFn to Message RAM Busy = 0 Figure 6.20-5 Data transfer between IFn Registers and Message After a partial write of a Message Object, the Message Buffer Registers that are not selected in the Command Mask Register will set the actual contents of the selected Message Object.
  • Page 866 M451 6.20.7.5 Acceptance Filtering of Received Messages When the arbitration and control field (Identifier + IDE + RTR + DLC) of an incoming message is completely shifted into the Rx/Tx Shift Register of the CAN Core, the Message Handler FSM starts the scanning of the Message RAM for a matching valid Message Object.

  • Page 867: Table 6-36 Initialization Of A Transmit Object

    M451 6.20.7.6 Receive/Transmit Priority The receive/transmit priority for the Message Objects is attached to the message number. Message Object 1 has the highest priority, while Message Object 32 has the lowest priority. If more than one transmission request is pending, they are serviced due to the priority of the corresponding Message Object 6.20.7.7 Configuring a Transmit Object...

  • Page 868: Table 6-37 Initialization Of A Receive Object

    M451 started. 6.20.7.9 Configuring a Receive Object The Table 6-37 shows how a Receive Object should be initialized. appl. appl. appl. appl. Table 6-37 Initialization of a Receive Object The Arbitration Registers values (ID28-0 (CAN_IFn_ARB1/2) and Xtd bit (CAN_IFn_ARB2[14])) are provided by the application.
  • Page 869 M451 6.20.7.11 Configuring a FIFO Buffer With the exception of the EoB bit (CAN_IFn_MCON[7]), the configuration of Receive Objects belonging to a FIFO Buffer is the same as the configuration of a (single) Receive Object, see Section 6.5.7.9: Configuring a Receive Object. To concatenate two or more Message Objects into a FIFO Buffer, the identifiers and masks (if used) of these Message Objects have to be programmed to matching values.

  • Page 870: Figure 6.20-6 Application Software Handling Of A Fifo Buffer

    M451 START Read Interrupt Pointer Case Interrupt Pointer 0x8000 else 0x0000 Status Change Interrupt Handling Message Num = Interrupt Pointer Write Message Num to IFn Command Register (Read Message to IFn Registers, Reset NewDat = 0, Reset IntPnd = 0) Read IFn to Message Control NewDat = 1 Read Data from IFn Data A,B...
  • Page 871 M451 The value 0x8000 indicates that an interrupt is pending because the CAN Core has updated (not necessarily changed) the Status Register (Error Interrupt or Status Interrupt). This interrupt has the highest priority. The application software can update (reset) the status bits RxOk (CAN_STATUS[4]), TxOk (CAN_STATUS[3]) and LEC (CAN_STATUS[2:0]), but a write access of the software to the Status Register can never generate or reset an interrupt.

  • Page 872: Figure 6.20-7 Bit Timing

    M451 Normal CAN Bit Time Sync_Seg Prop_Seg Phase_Seg1 Phase_Seg2 1 Time Quantum(t Sample Point Figure 6.20-7 Bit Timing Parameter Range Remark [1..32] Defines the length of the time quantum t Sync_Seg Fixed length, synchronization of bus input to APB clock [1..8] t Prop_Seg Compensates for the physical delay time...

  • Page 873: Figure 6.20-8 Propagation Time Segment

    M451 Prop_Seg Sync_Seg Prop_Seg Phase_Seg Node B Delay B_to_A Delay A_to_B Node A Delay A_to_B >= node output delay (A) + bus line delay (A-> B) + node input delay (B) Prop_seg >= Delay A_to_B + Delay B_to_A Prop_Seg >= 2*[max( node output delay + bus line dealy + node input delay )] Figure 6.20-8 Propagation Time Segment In this example, both nodes A and B are transmitters, performing an arbitration for the CAN bus.
  • Page 874 M451 Sync_Seg, the phase error is negative, else it is positive. Two types of synchronization exist, Hard Synchronization and Re-synchronization. A Hard Synchronization is done once at the start of a frame and inside a frame only when Re- synchronizations occur. •...

  • Page 875: Figure 6.20-9 Synchronization On "Late" And "Early" Edges

    M451 recessive dominant Rx-Input Sample-Point Sample-Point Sample-Point Sample-Point Sample-Point Sample-Point recessive “early Edge Rx-Input dominant Sync_Seg Prop_Seg Phase_Seg Prop_Seg Figure 6.20-9 Synchronization on “late” and “early” Edges In the first example an edge from recessive to dominant occurs at the end of Prop_Seg. The edge is “late”...

  • Page 876: Figure 6.20-10 Filtering Of Short Dominant Spikes

    M451 recessive dominant Rx-Input Spike Sample-Point Sample-Point SJW >= Phase Error recessive dominant Rx-Input Spike Sample-Point Sample-Point SJW < Phase Error Prop_Seg Sync_Seg Prop_Seg Phase_Seg Figure 6.20-10 Filtering of Short Dominant Spikes 6.20.7.19 Oscillator Tolerance Range The oscillator tolerance range was increased when the CAN protocol was developed from version 1.1 to version 1.2 (version 1.0 was never implemented in silicon).

  • Page 877: Figure 6.20-11 Structure Of The Can Core's Can Protocol Controller

    M451 10% of the bit time is not suitable for short bit times; it can be used for bit rates of up to 125 Kbit/s (bit time = 8us) with a bus length of 40 m. 6.20.7.20 Configuring the CAN Protocol Controller In most CAN implementations and also in the C_CAN, the bit timing configuration is programmed in two register bytes.
  • Page 878 M451 The BSP translates messages into frames and vice versa. It generates and discards the enclosing fixed format bits, inserts and extracts stuff bits, calculates and checks the CRC code, performs the error management, and decides which type of synchronization is to be used. It is evaluated at the Sample Point and processes the sampled bus input bit.
  • Page 879 M451 Example for Bit Timing at High Baud Rate In this example, the frequency of APB_CLK is 10 MHz, BRP (CAN_BTIME[5:0]) is 0, and the bit rate is 1 MBit/s. 100 ns APB_CLK delay of bus driver delay of receiver circuit 30 delay of bus line (40m) 220 = 6 •...
  • Page 880 M451 Example for Bit Timing at Low Baud Rate In this example, the frequency of APB_CLK is 2 MHz, BRP (CAN_BTIME[5:0]) is 1, and the bit rate is 100 Kbit/s. us = 2 •t APB_CLK delay of bus driver 200 ns delay of receiver circuit 80 delay of bus line (40m) 220 us = 1 •...

  • Page 881: Register Map

    M451 6.20.8 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value CAN Base Address: CAN_BA = 0x400A_0000 CAN_CON CAN_BA+0x00 Control Register 0x0000_0001 CAN_STATUS CAN_BA+0x04 Status Register 0x0000_0000 CAN_ERR CAN_BA+0x08 Error Counter Register 0x0000_0000 CAN_BTIME CAN_BA+0x0C...
  • Page 882 M451 CAN_NDAT2 CAN_BA+0x124 New Data Register 2 0x0000_0000 CAN_IPND1 CAN_BA+0x140 Interrupt Pending Register 1 0x0000_0000 CAN_IPND2 CAN_BA+0x144 Interrupt Pending Register 2 0x0000_0000 CAN_MVLD1 CAN_BA+0x160 Message Valid Register 1 0x0000_0000 CAN_MVLD2 CAN_BA+0x164 Message Valid Register 2 0x0000_0000 CAN_WU_EN CAN_BA+0x168 Wake-up Enable Control Register 0x0000_0000 CAN_WU_STATUS CAN_BA+0x16C Wake-up Status Register...
  • Page 883 M451 Register Map. Additionally the bus-off state is reset and the output CAN_TX is set to recessive (HIGH). The value 0x0001 (Init = ‘1’) in the CAN Control Register enables the software initialization. The C_CAN does not influence the CAN bus until the application software resets the Init bit (CAN_CON[0]) to ‘0’. The data stored in the Message RAM is not affected by a hardware reset.
  • Page 884 M451 CAN Register Map for Each Bit Function Addr Register Offset Name CAN_CON Reserved Init CAN_STATUS Reserved CAN_ERR REC6-0 TEC7-0 CAN_BTIME TSeg2 TSeg1 CAN_IIDR IntId15-8 IntId7-0 CAN_TEST Reserved Reserved CAN_BRPE Reserved BRPE CAN_IF1_CRE Busy Reserved Message Number CAN_IF1_CMA Reserved CAN_IF1_MAS Msk15-0 CAN_IF1_MAS MXtd MDir Res...
  • Page 885 M451 Addr Register Name Offset CAN_IF1_MCO Reserved DLC3-0 CAN_IF1_DAT_ Data(1) Data(0) CAN_IF1_DAT_ Data(3) Data(2) CAN_IF1_DAT_ Data(5) Data(4) CAN_IF1_DAT_ Data(7) Data(6) CAN_IF2_CREQ Busy Reserved Message Number CAN_IF2_CMAS Reserved CAN_IF2_MASK Msk15-0 CAN_IF2_MASK MXtd MDir Res. Msk28-16 CAN_IF2_ARB1 ID15-0 CAN_IF2_ARB2 ID28-16 CAN_IF2_MCO Reserved DLC3-0 CAN_IF2_DAT_ Data(1)

  • Page 886: Table 6-39 Can Register Map For Each Bit Function

    M451 Addr Register Name Offset CAN_IF2_DAT_ Data(3) Data(2) CAN_IF2_DAT_ Data(5) Data(4) CAN_IF2_DAT_ Data(7) Data(6) 100h CAN_TXREQ1 TxRqst16-1 104h CAN_TXREQ2 TxRqst32-17 120h CAN_NDAT1 NewDat16-1 124h CAN_NDAT2 NewDat32-17 140h CAN_IPND1 IntPnd16-1 144h CAN_IPND2 IntPnd32-17 160h CAN_MVLD1 MsgVal16-1 164h CAN_MVLD2 MsgVal32-17 WAKUP 168h CAN_WU_EN Reserved CAN_WU_STAT...

  • Page 887: Register Description

    M451 6.20.9 Register Description The C_CAN allocates an address space of 256 bytes. The registers are organized as 16-bit registers. The two sets of interface registers (IF1 and IF2) control the software access to the Message RAM. They buffer the data to be transferred to and from the RAM, avoiding conflicts between software accesses and message reception/transmission.
  • Page 888 M451 CAN Control Register (CAN_CON) Register Offset Description Reset Value CAN_CON CAN_BA+0x00 Control Register 0x0000_0001 Reserved Reserved Reserved Test Reserved Init Bits Description [31:8] Reserved Reserved. Test Mode Enable Bit Test 0 = Normal Operation. 1 = Test Mode. Configuration Change Enable Bit 0 = No write access to the Bit Timing Register.
  • Page 889 M451 Note: The bus-off recovery sequence (see CAN Specification Rev. 2.0) cannot be shortened by setting or resetting the Init bit (CAN_CON[0]). If the device goes in the bus-off state, it will set Init of its own accord, stopping all bus activities. Once Init has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operations.
  • Page 890 M451 CAN Status Register (CAN_STATUS) Register Offset Description Reset Value CAN_STATUS CAN_BA+0x04 Status Register 0x0000_0000 Reserved Reserved Reserved BOff EWarn EPass RxOK TxOK Bits Description [31:8] Reserved Reserved. Bus-off Status (Read Only) BOff 0 = The CAN module is not in bus-off state. 1 = The CAN module is in bus-off state.

  • Page 891: Table 6-40 Last Error Code

    M451 Error Code Meanings No Error Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. Form Error: A fixed format part of a received frame has the wrong format. AckError: The message this CAN Core transmitted was not acknowledged by another node.
  • Page 892 M451 CAN Error Counter Register (CAN_ERR) Register Offset Description Reset Value CAN_ERR CAN_BA+0x08 Error Counter Register 0x0000_0000 Reserved Reserved Bits Description [31:16] Reserved Reserved. Receive Error Passive 0 = The Receive Error Counter is below the error passive level. [15] 1 = The Receive Error Counter has reached the error passive level as defined in the CAN Specification.
  • Page 893 M451 Bit Timing Register (CAN_BTIME) Register Offset Description Reset Value CAN_BTIME CAN_BA+0x0C Bit Timing Register 0x0000_2301 Reserved Reserved Reserved TSeg2 TSeg1 Bits Description [31:15] Reserved Reserved. Time Segment After Sample Point [14:12] TSeg2 0x0-0x7: Valid values for TSeg2 are [0…7]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

  • Page 894: Table 6-41 Source Of Interrupts

    M451 Interrupt Identify Register (CAN_IIDR) Register Offset Description Reset Value CAN_IIDR CAN_BA+0x10 Interrupt Identifier Register 0x0000_0000 Reserved Reserved IntId IntId Bits Description Interrupt Identifier (Indicates the Source of the Interrupt) If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order.
  • Page 895 M451 Test Register (CAN_TEST) Register Offset Description Reset Value CAN_TEST CAN_BA+0x14 Test Register (Register Map Note 1) 0x0000_0080 Reserved Reserved Reserved LBack Silent Basic Reserved Bits Description [31:8] Reserved Reserved. Monitors the Actual Value of CAN_RX Pin (Read Only) *(1) 0 = The CAN bus is dominant (CAN_RX = ‘0’).
  • Page 896 M451 Baud Rate Prescaler Extension REGISTER (CAN_BRPE) Register Offset Description Reset Value CAN_BRPE CAN_BA+0x18 Baud Rate Prescaler Extension Register 0x0000_0000 Reserved Reserved Reserved Reserved BRPE Bits Description [31:4] Reserved Reserved. BRPE: Baud Rate Prescaler Extension 0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to BRPE [3:0] 1023.

  • Page 897: Table 6-42 If1 And If2 Message Interface Register

    M451 Message Interface Register Sets There are two sets of Interface Registers, which are used to control the CPU access to the Message RAM. The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message reception and transmission by buffering the data to be transferred. A complete Message Object or parts of the Message Object may be transferred between the Message RAM and the IFn Message Buffer registers in one single transfer.
  • Page 898 M451 IFn Command Request Register (CAN_IFn_CREQ) Register Offset Description Reset Value CAN_IFn_CREQ CAN_BA+0x20 + IFn (Register Map Note 2) Command Request Registers 0x0000_0001 (0x60 *(n-1)) n = 1,2 Reserved Reserved Busy Reserved Reserved Message Number Bits Description [31:16] Reserved Reserved. Busy Flag 0 = Read/write action has finished.
  • Page 899 M451 IFn Command Mask Register (CAN_IFn_CMASK) The control bits of the IFn Command Mask Register specify the transfer direction and select which of the IFn Message Buffer Registers are source or target of the data transfer. Register Offset Description Reset Value CAN_IFn_CMASK CAN_BA+0x24 + IFn Command Mask Registers...
  • Page 900 M451 Read Operation: 0 = Control Bits unchanged. 1 = Transfer Control Bits to IFn Message Buffer Register. Clear Interrupt Pending Bit Write Operation: When writing to a Message Object, this bit is ignored. ClrIntPnd Read Operation: 0 = IntPnd bit (CAN_IFn_MCON[13]) remains unchanged. 1 = Clear IntPnd bit in the Message Object.
  • Page 901 M451 IFn Mask 1 Register (CAN_IFn_MASK1) Register Offset Description Reset Value CAN_IFn_MASK1 CAN_BA+0x28 + IFn Mask 1 Registers 0x0000_FFFF (0x60 *(n-1)) n = 1,2 Reserved Reserved Msk[15:8] Msk[7:0] Bits Description [31:16] Reserved Reserved. Identifier Mask 15-0 0 = The corresponding bit in the identifier of the message object cannot inhibit the match in [15:0] Msk[15:0] the acceptance filtering.
  • Page 902 M451 IFn Mask 2 Register (CAN_IFn_MASK2) Register Offset Description Reset Value CAN_IFn_MASK2 CAN_BA+0x2C + IFn Mask 2 Registers 0x0000_FFFF (0x60 *(n-1)) n = 1,2 Reserved Reserved MXtd MDir Reserved Msk[28:24] Msk[23:16] Bits Description [31:16] Reserved Reserved. Mask Extended Identifier 0 = The extended identifier bit (IDE) has no effect on the acceptance filtering. 1 = The extended identifier bit (IDE) is used for acceptance filtering.
  • Page 903 M451 IFn Arbitration 1 Register (CAN_IFn_ARB1) Register Offset Description Reset Value CAN_IFn_ARB1 CAN_BA+0x30 + IFn Arbitration 1 Registers 0x0000_0000 (0x60 *(n-1)) n = 1,2 Reserved Reserved ID[15:8] ID[7:0] Bits Description [31:16] Reserved Reserved. Message Identifier 15-0 ID28 - ID0, 29-bit Identifier (“Extended Frame”). [15:0] ID[15:0] ID28 - ID18, 11-bit Identifier (“Standard Frame”)
  • Page 904 M451 IFn Arbitration 2 Register (CAN_IFn_ARB2) Register Offset Description Reset Value CAN_IFn_ARB2 CAN_BA+0x34 + IFn Arbitration 2 Registers 0x0000_0000 (0x60 *(n-1)) n = 1,2 Reserved Reserved MsgVal ID[28:24] ID[23:16] Bits Description [31:16] Reserved Reserved. Message Valid 0 = The Message Object is ignored by the Message Handler. 1 = The Message Object is configured and should be considered by the Message Handler.
  • Page 905 M451 IFn Message Control Register (CAN_IFn_MCON) Register Offset Description Reset Value CAN_IFn_MCON CAN_BA+0x38 + IFn Message Control Registers 0x0000_0000 (0x60 *(n-1)) n = 1,2 Reserved Reserved NewDat MsgLst IntPnd UMask TxIE RxIE RmtEn TxRqst Reserved Bits Description [31:16] Reserved Reserved. New Data 0 = No new data has been written into the data portion of this Message Object by the Message [15]...
  • Page 906 M451 Remote Enable Bit RmtEn 0 = At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged. 1 = At the reception of a Remote Frame, TxRqst is set. Transmit Request TxRqst 0 = This Message Object is not waiting for transmission. 1 = The transmission of this Message Object is requested and is not yet done.
  • Page 907 M451 IFn Data A1 Register (CAN_IFn_DAT_A1) Register Offset Description Reset Value CAN_IFn_DAT_A1 CAN_BA+0x3C + IFn Data A1 Registers (Register Map Note 3) 0x0000_0000 (0x60 *(n-1)) n = 1,2 Reserved Reserved Data(1) Data(0) Bits Description [31:16] Reserved Reserved. Data Byte 1 [15:8] Data(1) 2nd data byte of a CAN Data Frame...
  • Page 908 M451 IFn Data A2 Register (CAN_IFn_DAT_A2) Register Offset Description Reset Value CAN_IFn_DAT_A2 CAN_BA+0x40 + IFn Data A2 Registers (Register Map Note 3) 0x0000_0000 (0x60 *(n-1)) n = 1,2 Reserved Reserved Data(3) Data(2) Bits Description [31:16] Reserved Reserved. Data Byte 3 [15:8] Data(3) 4th data byte of CAN Data Frame...
  • Page 909 M451 IFn Data B1 Register (CAN_IFn_DAT_B1) Register Offset Description Reset Value CAN_IFn_DAT_B1 CAN_BA+0x44 + IFn Data B1 Registers (Register Map Note 3) 0x0000_0000 (0x60 *(n-1)) n = 1,2 Reserved Reserved Data(5) Data(4) Bits Description [31:16] Reserved Reserved. Data Byte 5 [15:8] Data(5) 6th data byte of CAN Data Frame...
  • Page 910 M451 IFn Data B2 Register (CAN_IFn_DAT_B2) Register Offset Description Reset Value CAN_IFn_DAT_B2 CAN_BA+0x48 + IFn Data B2 Registers (Register Map Note 3) 0x0000_0000 (0x60 *(n-1)) n = 1,2 Reserved Reserved Data(7) Data(6) Bits Description [31:16] Reserved Reserved. Data Byte 7 [15:8] Data(7) 8th data byte of CAN Data Frame.

  • Page 911: Table 6-43 Structure Of A Message Object In The Message Memory

    M451 Message Object in the Message Memory There are 32 Message Objects in the Message RAM. To avoid conflicts between application software access to the Message RAM and CAN message reception and transmission, the CPU cannot directly access the Message Objects, these accesses are handled through the IFn Interface Registers. The Table 6-43 provides an overview of the structures of a Message Object.
  • Page 912 M451 Transmission Request Register 1 (CAN_TXREQ1) These registers hold the TxRqst bits of the 32 Message Objects. By reading the TxRqst bits, the software can check which Message Object in a Transmission Request is pending. The TxRqst bit of a specific Message Object can be set/reset by the application software through the IFn Message Interface Registers or by the Message Handler after reception of a Remote Frame or after a successful transmission.
  • Page 913 M451 Transmission Request Register 2 (CAN_TXREQ2) Register Offset Description Reset Value CAN_TXREQ2 CAN_BA+0x104 Transmission Request Register 2 0x0000_0000 Reserved Reserved TxRqst32-25 TxRqst24-17 Bits Description [31:16] Reserved Reserved. Transmission Request Bits 32-17 (of All Message Objects) 0 = This Message Object is not waiting for transmission. [15:0] TxRqst32-17 1 = The transmission of this Message Object is requested and is not yet done.
  • Page 914 M451 New Data Register 1 (CAN_NDAT1) These registers hold the NewDat bits of the 32 Message Objects. By reading out the NewDat bits, the software can check for which Message Object the data portion was updated. The NewDat bit of a specific Message Object can be set/reset by the software through the IFn Message Interface Registers or by the Message Handler after reception of a Data Frame or after a successful transmission.
  • Page 915 M451 New Data Register 2 (CAN_NDAT2) Register Offset Description Reset Value CAN_NDAT2 CAN_BA+0x124 New Data Register 2 0x0000_0000 Reserved Reserved NewData32-25 NewData24-17 Bits Description [31:16] Reserved Reserved. New Data Bits 32-17 (of All Message Objects) 0 = No new data has been written into the data portion of this Message Object by the [15:0] NewData32-17 Message Handler since the last time this flag was cleared by the application software.
  • Page 916 M451 Interrupt Pending Register 1 (CAN_IPND1) These registers contain the IntPnd bits of the 32 Message Objects. By reading the IntPnd bits, the software can check for which Message Object an interrupt is pending. The IntPnd bit of a specific Message Object can be set/reset by the application software through the IFn Message Interface Registers or by the Message Handler after reception or after a successful transmission of a frame.
  • Page 917 M451 Interrupt Pending Register 2 (CAN_IPND2) Register Offset Description Reset Value CAN_IPND2 CAN_BA+0x144 Interrupt Pending Register 2 0x0000_0000 Reserved Reserved IntPnd32-25 IntPnd24-17 Bits Description [31:16] Reserved Reserved. Interrupt Pending Bits 32-17 (of All Message Objects) IntPnd32-17 0 = This message object is not the source of an interrupt. [15:0] 1 = This message object is the source of an interrupt.
  • Page 918 M451 Message Valid Register 1 (CAN_MVLD1) These registers hold the MsgVal bits of the 32 Message Objects. By reading the MsgVal bits, the application software can check which Message Object is valid. The MsgVal bit of a specific Message Object can be set/reset by the application software via the IFn Message Interface Registers. Register Offset Description...
  • Page 919 M451 Message Valid Register 2 (CAN_MVLD2) Register Offset Description Reset Value CAN_MVLD2 CAN_BA+0x164 Message Valid Register 2 0x0000_0000 Reserved Reserved MsgVal32-25 MsgVal24-17 Bits Description [31:16] Reserved Reserved. Message Valid Bits 32-17 (of All Message Objects) (Read Only) 0 = This Message Object is ignored by the Message Handler. [15:0] MsgVal32-17 1 = This Message Object is configured and should be considered by the Message Handler.
  • Page 920 M451 Wake-up Enable Control Register (CAN_WU_EN) Register Offset Description Reset Value CAN_WU_EN CAN_BA+0x168 Wake-up Enable Control Register 0x0000_0000 Reserved Reserved Reserved Reserved WAKUP_EN Bits Description [31:1] Reserved Reserved. Wake-up Enable Bit 0 = The wake-up function Disabled. WAKUP_EN 1 = The wake-up function Enabled. Note: User can wake-up system when there is a falling edge in the CAN_Rx pin..
  • Page 921 M451 Wake-up Status Register (CAN_WU_STATUS) Register Offset Description Reset Value CAN_WU_STATUS CAN_BA+0x16C Wake-up Status Register 0x0000_0000 Reserved Reserved Reserved Reserved WAKUP_STS Bits Description [31:1] Reserved Reserved. Wake-up Status 0 = No wake-up event occurred. WAKUP_STS 1 = Wake-up event occurred. Note: This bit can be cleared by writing ‘0’.

  • Page 922: Crc Controller (Crc)

    M451 6.21 CRC Controller (CRC) 6.21.1 Overview The Cyclic Redundancy Check (CRC) generator can perform CRC calculation with programmable polynomial settings. 6.21.2 Features  Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32 – CRC-CCITT: X – CRC-8: X + X + 1 –...

  • Page 923: Basic Configuration

    M451 6.21.4 Basic Configuration The CRC peripheral clock is enabled in CRCCKEN (CLK_AHBCLK[7]). After CRC is setting, user can start to perform CRC calculate by control CRC’s registers. 6.21.5 Functional Description CRC generator can perform CRC calculation with programmable polynomial settings. The operation polynomial includes CRC-CCITT, CRC-8, CRC-16 and CRC-32;...

  • Page 924: Register Map

    M451 6.21.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value CRC Base Address: CRC_BA = 0x4003_1000 CRC_CTL CRC_BA+0x00 CRC Control Register 0x2000_0000 CRC_DAT CRC_BA+0x04 CRC Write Data Register 0x0000_0000 CRC_SEED CRC_BA+0x08 CRC Seed Register 0xFFFF_FFFF...

  • Page 925: Register Description

    M451 6.21.7 Register Description CRC Control Register (CRC_CTL) Register Offset Description Reset Value CRC_CTL CRC_BA+0x00 CRC Control Register 0x2000_0000 CRCMODE DATLEN CHKSFMT DATFMT CHKSREV DATREV Reserved Reserved Reserved CRCRST CRCEN Bits Description CRC Polynomial Mode This field indicates the CRC operation polynomial mode. 00 = CRC-CCITT Polynomial mode.
  • Page 926 M451 Checksum Bit Order Reverse This bit is used to enable the bit order reverse function for write data value in CRC_CHECKSUM register. CHKSREV 0 = Bit order reverse for CRC checksum Disabled. [25] 1 = Bit order reverse for CRC checksum Enabled. Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB.
  • Page 927 M451 CRC Write Data Register (CRC_DAT) Register Offset Description Reset Value CRC_DAT CRC_BA+0x04 CRC Write Data Register 0x0000_0000 DATA DATA DATA DATA Bits Description CRC Write Data Bits User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
  • Page 928 M451 CRC Seed Register (CRC_SEED) Register Offset Description Reset Value CRC_SEED CRC_BA+0x08 CRC Seed Register 0xFFFF_FFFF SEED SEED SEED SEED Bits Description CRC Seed Value [31:0] SEED This field indicates the CRC seed value. May. 4, 2018 Page 928 of 1006 Rev.2.08...
  • Page 929 M451 CRC Checksum Register (CRC_CHECKSUM) Register Offset Description Reset Value CRC_CHECKSUM CRC_BA+0x0C CRC Checksum Register 0x0000_0000 CHECKSUM CHECKSUM CHECKSUM CHECKSUM Bits Description CRC Checksum Results [31:0] CHECKSUM This field indicates the CRC checksum result. May. 4, 2018 Page 929 of 1006 Rev.2.08...

  • Page 930: Enhanced 12-Bit Analog-To-Digital Converter (Eadc)

    M451 6.22 Enhanced 12-bit Analog-to-Digital Converter (EADC) 6.22.1 Overview The M451 series contains one 12-bit successive approximation analog-to-digital converter (SAR A/D converter) with 16 external input channels and 3 internal channels. The A/D converter can be started by software trigger, PWM0/1 triggers, timer0~3 overflow pulse triggers, ADINT0, ADINT1 interrupt EOC (End of conversion) pulse trigger and external pin (STADC) input signal.

  • Page 931: Block Diagram

    M451 6.22.3 Block Diagram Analog Macro Internal Reference Voltage Generator INT_VREF VREFCTL (SYS_VREFCTL[4:0]) 12-bit DAC Analog Control Logics Comparator EADC_CH0 EADC_CH15 Successive VTEMPEN Approximations Register (SYS_IVSCTL[0]) Sample and Hold TEMP VBATUGEN (SYS_IVSCTL[1]) A/D result [11:0] CHSEL [4:0] A/D Sample Module 18 Voltage Divide 2 Digatal Control Logics...

  • Page 932: Operation Procedure

    M451 6.22.5 Operation Procedure The EADC controller consists of a 19 channel analog switch , 19 sample modules and a 12-bit successive approximation analog-to-digital converter. The EADC operation is based on sample module 0~18, each of them has its configuration to decide which trigger source to start the conversion, which channel to convert.

  • Page 933: Figure 6.22-3 Sample Module 4~15 Block Diagram

    M451 Sample Module EXTREN (EADC_SCTL4[4]) Sample Module ADC STADC pin signal EXTREN (EADC_SCTL4[5]) Disable hardware Trigger ADINT0 interrupt EOC pulse ADINT1 interrupt EOC pulse Timer0 overflow pulse Timer1 overflow pulse Timer2 overflow pulse Timer3 overflow pulse reset PWM0TG0 EOC4 PWM0TG1 Sample PWM0TG2 CHSEL...

  • Page 934: Figure 6.22-5 Eadc Clock Control

    M451  Write 1 to SWTRGn (EADC_SWTRG[n], n = 0~15)  External pin STADC  Timer0~3 overflow pulse triggers  ADINT0, ADINT1 ADC interrupt EOC (End of conversion) pulse triggers  PWM triggers The ADINT0 or ADINT1 interrupt pulses are generated whenever the specific sample module A/D EOC (End of conversion) pulse is generated.

  • Page 935: Figure 6.22-6 Example Adc Conversion Timing Diagram, N=0~18

    M451 sample module 18 is lowest priority. EADC_CLK Write SWTRG (EADC_SWTRG[n], n=0~18) ADIFn (EADC_STATUS2[n], n=0~3) RESULT (EADC_DATn[15:0], RSLT n=0~18) Figure 6.22-6 Example ADC Conversion Timing Diagram, n=0~18 6.22.5.3 ADC Conversion Priority There is a priority group converter for determining the conversion order when multiple sample module trigger flags are set at the same time.

  • Page 936: Figure 6.22-7 Sample Module Conversion Priority Arbitrator Diagram

    M451 Sample Module 0 Sample Module 1 Sample Module 2 Sample Module SAMPLE Priority Sample module 0 has highest priority, sample module 18 has lowest priority for ADC converter Figure 6.22-7 Sample module Conversion Priority Arbitrator Diagram 6.22.5.4 ADC Sample Module End of Conversion (EOC) Interrupt Operation There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address and ADINT0/ADINT1 can be configured to set multiple sample module EOC pulse (sample module 0~18 End of conversion pulses) as its interrupt trigger source.

  • Page 937: Figure 6.22-8 Specific Sample Module A/D Eoc Signal For Adint0~3 Interrupt

    M451 ADINT3 ADINT0 ADIF0 (EADC_STATUS[0]) Sample module 0 EOC AD0VIF0 SPLIE0 (EADC_STATUS[8]) (EADC_INTSRC0[0]) ADC Interrupt ADINT0 control Logic Sample module 18 EOC SPLIE18 ADCIEN0 (EADC_INTSRC0[18]) (EADC_CTL[2]) Figure 6.22-8 Specific Sample Module A/D EOC Signal for ADINT0~3 Interrupt 6.22.5.5 ADC Trigger by External Pin STADC ,Timer Trigger and PWM Trigger A/D conversion can be triggered by external pin STADC request.

  • Page 938: Figure 6.22-9 Stadc De-Bounce Timing Diagram

    M451 Figure 6.22-9 STADC De-bounce Timing Diagram There are 4 Timer trigger sources and 12 PWM trigger sources (rising, falling PWM edge or center point of PWM) which can be selected to configure sample module 0~15 for ADC start trigger. The detail trigger conditions are descripted at PWM_EADCTS0, PWM_EADCTS1 and TIMER0_CTL ~ TIMER3_CTL register.

  • Page 939: Figure 6.22-12 Conversion Start Delay Timing Diagram

    M451 A/D conversion time A/D conversion start delay time (Td) PCLK Analog input sampling time Synchronous to (X ADC clocks) ADC clock delay 1 ADC clock up to 1 ADC clcok APB Bus Write SWTRGn (EADC_SWTRG[n], n=0~18) A/D Conversion Start First ADC clock A/D Converter Idle state...

  • Page 940: Figure 6.22-13 A/D Extend Sampling Timing Diagram

    M451 Extend Sampling Time A/D Conversion (N ADC clocks) A/D clock A/D converter start A/D converter channel select A/D converter Hold Sampling Hold Sampling Sample/Hold A/D converter finish ADIFn (INTPOS=0) ADIFn (INTPOS=1) (X ADC clocks) (13 ADC clocks) Note: N = SPLTEXT (EADC_SCTLn[31:24], n=0~18) (Extend sampling cycle for each sample module) X = SMPTSEL (EADC_CTL[18:16]) + 1 (ADC internal sampling cycle) ADIFn (EADC_STATUS2[3:0], n=0~3) INTPOS (EADC_SCTLn[22], n=0~15)

  • Page 941: Figure 6.22-14 A/D Conversion Result Monitor Logics Diagram

    M451 CMPCOND(EADC_MPPn[2]) CMPSPL(EADC_CMPn[7:3]) CMPMCNT Control Logic (EADC_CMPn[11:8]) RESULT < CMPDAT RESULT Match (EADC_DATn[11:0] Sample module 0~18 RESULT >= CMPDAT Counter APCMPFn DAT Result Register (EADC_STATUS2[7:4]) ADCMPOn Note: (EADC_STATUS2[15:12]) CMPDAT(EADC_CMPn[27:16]) 12-bit Digital Comparator CMPDAT (EADC_CMPn[27:16] RESULT(EADC_PATn[11:0] Figure 6.22-14 A/D Conversion Result Monitor Logics Diagram The ADC controller supports a window compare mode.

  • Page 942: Figure 6.22-15 A/D Controller Interrupts

    M451 A/D convert finish, the VALID (EADC_DATn[17], n=0~3) will set to high, but VALID[n] (EADC_STATUS0[n], n=0~3) will keep low. And the second time A/D converts finish, VALID (EADC_DDATn[17],n=0~3) will set to high, and VALID (EADC_STATUS0[n], n=0~3) will set to high at the same time.

  • Page 943: Register Map

    M451 6.22.6 Register Map R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written Register Offset R/W Description Reset Value EADC Base Address: EADC_BA = 0x4004_3000 EADC_DAT0 EADC_BA+0x00 A/D Data Register 0 for Sample Module 0 0x0000_0000 EADC_DAT1 EADC_BA+0x04...
  • Page 944 M451 Register Offset R/W Description Reset Value EADC Base Address: EADC_BA = 0x4004_3000 EADC_SCTL2 EADC_BA+0x88 R/W A/D Sample Module 2 Control Register 0x0000_0000 EADC_SCTL3 EADC_BA+0x8C R/W A/D Sample Module 3 Control Register 0x0000_0000 EADC_SCTL4 EADC_BA+0x90 R/W A/D Sample Module 4 Control Register 0x0000_0000 EADC_SCTL5 EADC_BA+0x94...
  • Page 945 M451 Register Offset R/W Description Reset Value EADC Base Address: EADC_BA = 0x4004_3000 EADC_STATUS3 EADC_BA+0xFC A/D Status Register 3 0x0000_001F EADC_DDAT0 EADC_BA+0x100 R A/D Double Data Register 0 for Sample Module 0 0x0000_0000 EADC_DDAT1 EADC_BA+0x104 R A/D Double Data Register 1 for Sample Module 1 0x0000_0000 EADC_DDAT2 EADC_BA+0x108 R...

  • Page 946: Register Description

    M451 6.22.7 Register Description A/D Data Registers (EADC_DAT0~18) Register Offset Description Reset Value EADC_DAT0 EADC_BA+0x00 A/D Data Register 0 for Sample Module 0 0x0000_0000 EADC_DAT1 EADC_BA+0x04 A/D Data Register 1 for Sample Module 1 0x0000_0000 EADC_DAT2 EADC_BA+0x08 A/D Data Register 2 for Sample Module 2 0x0000_0000 EADC_DAT3 EADC_BA+0x0C...
  • Page 947 M451 Bits Description Reserved [31:18] Reserved. Valid Flag This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read. [17] VALID 0 = Data in RESULT[11:0] bits is not valid. 1 = Data in RESULT[11:0] bits is valid.
  • Page 948 M451 EADC PDMA Current Transfer Data Register (EADC_CURDAT) Register Offset Description Reset Value EADC_CURDAT EADC_BA+0x4C EADC PDMA Current Transfer Data Register 0x0000_0000 Reserved Reserved CURDAT CURDAT CURDAT Bits Description [31:18] Reserved Reserved. ADC PDMA Current Transfer Data Register This register is a shadow register of EADC_DATn (n=0~18) for PDMA support. [17:0] CURDAT This is a read only register.
  • Page 949 M451 A/D Control Register (EADC_CTL) Register Offset Description Reset Value EADC_CTL EADC_BA+0x50 A/D Control Register 0x0005_0000 Reserved Reserved SMPTSEL Reserved PDMAEN Reserved DMOF DIFFEN Reserved ADCIEN3 ADCIEN2 ADCIEN1 ADCIEN0 ADCRST ADCEN Bits Description [31:19] Reserved Reserved. ADC Internal Sampling Time Selection ADC internal sampling cycle = SMPTSEL + 1.
  • Page 950 M451 Bits Description Differential Analog Input Mode Enable Bit DIFFEN 0 = Single-end analog input mode. 1 = Differential analog input mode. [7:6] Reserved Reserved. Specific Sample Module A/D ADINT3 Interrupt Enable Bit The A/D converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module A/D conversion.
  • Page 951 M451 A/D Sample Module Software Start Register (EADC_SWTRG) Register Offset Description Reset Value EADC_SWTRG EADC_BA+0x54 A/D Sample Module Software Start Register 0x0000_0000 Reserved Reserved SWTRG SWTRG SWTRG Bits Description [31:19] Reserved Reserved. A/D Sample Module 0~18 Software Force to Start ADC Conversion 0 = No effect.
  • Page 952 M451 A/D Sample Module Start of Conversion Pending Flag Register (EADC_PENDSTS) Register Offset Description Reset Value EADC_PENDST EADC_BA+0x58 A/D Start of Conversion Pending Flag Register 0x0000_0000 Reserved Reserved STPF STPF STPF Bits Description [31:19] Reserved Reserved. A/D Sample Module 0~18 Start of Conversion Pending Flag Read: 0 = There is no pending conversion for sample module.
  • Page 953 M451 A/D Sample Module Overrun Flag Register (EADC_OVSTS) Register Offset Description Reset Value A/D Sample Module Start of Conversion Overrun Flag EADC_OVSTS EADC_BA+0x5C 0x0000_0000 Register Reserved Reserved SPOVF SPOVF SPOVF Bits Description [31:19] Reserved Reserved. A/D SAMPLE0~18 Overrun Flag 0 = No sample module event overrun. [18:0] SPOVF 1 = Indicates a new sample module event is generated while an old one event is pending.
  • Page 954 M451 A/D Sample Module 0~3 Control Registers (EADC_SCTL0~EADC_SCTL3) Register Offset Description Reset Value EADC_SCTL0 EADC_BA+0x80 A/D Sample Module 0 Control Register 0x0000_0000 EADC_SCTL1 EADC_BA+0x84 A/D Sample Module 1 Control Register 0x0000_0000 EADC_SCTL2 EADC_BA+0x88 A/D Sample Module 2 Control Register 0x0000_0000 EADC_SCTL3 EADC_BA+0x8C A/D Sample Module 3 Control Register...
  • Page 955 M451 Bits Description A/D Sample Module Start of Conversion Trigger Source Selection 0H = Disable trigger. 1H = External trigger from STADC pin input. 2H = ADC ADINT0 interrupt EOC (End of conversion) pulse trigger. 3H = ADC ADINT1 interrupt EOC (End of conversion) pulse trigger. 4H = Timer0 overflow pulse trigger.
  • Page 956 M451 Bits Description A/D Sample Module Channel Selection 00H = EADC_CH0. 01H = EADC_CH1. 02H = EADC_CH2. 03H = EADC_CH3. 04H = EADC_CH4. 05H = EADC_CH5. 06H = EADC_CH6. [3:0] CHSEL 07H = EADC_CH7. 08H = EADC_CH8. 09H = EADC_CH9. 0AH = EADC_CH10.
  • Page 957 M451 A/D Sample Module 4~15 Control Registers (EADC_SCTL4~EADC_SCTL15) Register Offset Description Reset Value EADC_SCTL4 EADC_BA+0x90 A/D Sample Module 4 Control Register 0x0000_0000 EADC_SCTL5 EADC_BA+0x94 A/D Sample Module 5 Control Register 0x0000_0000 EADC_SCTL6 EADC_BA+0x98 A/D Sample Module 6 Control Register 0x0000_0000 EADC_SCTL7 EADC_BA+0x9C A/D Sample Module 7 Control Register...
  • Page 958 M451 Bits Description A/D Sample Module Start of Conversion Trigger Source Selection 0H = Disable trigger. 1H = External trigger from STADC pin input. 2H = ADC ADINT0 interrupt EOC pulse trigger. 3H = ADC ADINT1 interrupt EOC pulse trigger. 4H = Timer0 overflow pulse trigger.
  • Page 959 M451 Bits Description A/D Sample Module Channel Selection 00H = EADC_CH0. 01H = EADC_CH1. 02H = EADC_CH2. 03H = EADC_CH3. 04H = EADC_CH4. 05H = EADC_CH5. 06H = EADC_CH6. [3:0] CHSEL 07H = EADC_CH7. 08H = EADC_CH8. 09H = EADC_CH9. 0AH = EADC_CH10.
  • Page 960 M451 A/D Sample Module 16~18 Control Registers (EADC_SCTL16~EADC_SCTL18) Register Offset Description Reset Value EADC_SCTL16 EADC_BA+0xC0 A/D Sample Module 16 Control Register 0x0000_0000 EADC_SCTL17 EADC_BA+0xC4 A/D Sample Module 17 Control Register 0x0000_0000 EADC_SCTL18 EADC_BA+0xC8 A/D Sample Module 18 Control Register 0x0000_0000 EXTSMPT Reserved Reserved...
  • Page 961 M451 A/D Interrupt Source Enable Control Registers (EADC_INTSRC0~EADC_INTSRC3) Register Offset Description Reset Value EADC_INTSRC0 EADC_BA+0xD0 ADC interrupt 0 Source Enable Control Register. 0x0000_0000 EADC_INTSRC1 EADC_BA+0xD4 ADC interrupt 1 Source Enable Control Register. 0x0000_0000 EADC_INTSRC2 EADC_BA+0xD8 ADC interrupt 2 Source Enable Control Register. 0x0000_0000 EADC_INTSRC3 EADC_BA+0xDC...
  • Page 962 M451 Bits Description Sample Module 11 Interrupt Enable Bit [11] SPLIE11 0 = Sample Module 11 interrupt Disabled. 1 = Sample Module 11 interrupt Enabled. Sample Module 10 Interrupt Enable Bit [10] SPLIE10 0 = Sample Module 10 interrupt Disabled. 1 = Sample Module 10 interrupt Enabled.
  • Page 963 M451 A/D Result Compare Register 0/1/2/3 (EADC_CMP0/1/2/3) Register Offset Description Reset Value EADC_CMP0 EADC_BA+0xE0 A/D Result Compare Register 0 0x0000_0000 EADC_CMP1 EADC_BA+0xE4 A/D Result Compare Register 1 0x0000_0000 EADC_CMP2 EADC_BA+0xE8 A/D Result Compare Register 2 0x0000_0000 EADC_CMP3 EADC_BA+0xEC A/D Result Compare Register 3 0x0000_0000 Reserved CMPDAT...
  • Page 964 M451 Bits Description Compare Sample Module Selection 00000 = Sample Module 0 conversion result EADC_DAT0 is selected to be compared. 00001 = Sample Module 1 conversion result EADC_DAT1 is selected to be compared. 00010 = Sample Module 2 conversion result EADC_DAT2 is selected to be compared. 00011 = Sample Module 3 conversion result EADC_DAT3 is selected to be compared.
  • Page 965 M451 A/D Status Register 0 (EADC_STATUS0) Register Offset Description Reset Value EADC_STATUS0 EADC_BA+0xF0 A/D Status Register 0 0x0000_0000 OV[15:8] OV[7:0] VALID[15:8] VALID[7:0] Bits Description EADC_DAT0~15 Overrun Flag [31:16] OV[15:0] It is a mirror to OV bit in sample module A/D result data register EADC_DATn. (n=0~18). EADC_DAT0~15 Data Valid Flag [15:0] VALID[15:0]...
  • Page 966 M451 A/D Status Register 1 (EADC_STATUS1) Register Offset Description Reset Value EADC_STATUS1 EADC_BA+0xF4 A/D Status Register 1 0x0000_0000 Reserved Reserved OV[18:16] Reserved Reserved VALID[18:16] Bits Description [31:19] Reserved Reserved. EADC_DAT16~18 Overrun Flag OV[18:16] [18:16] It is a mirror to OV bit in sample module A/D result data register EADC_DATn. (n=0~18). [15:3] Reserved Reserved.
  • Page 967 M451 A/D Status Register 2 (EADC_STATUS2) Register Offset Description Reset Value EADC_STATUS2 EADC_BA+0xF8 A/D Status Register 2 0x0000_0000 Reserved AVALID STOVF ADOVIF BUSY Reserved CHANNEL ADCMPO3 ADCMPO2 ADCMPO1 ADCMPO0 ADOVIF3 ADOVIF2 ADOVIF1 ADOVIF0 ADCMPF3 ADCMPF2 ADCMPF1 ADCMPF0 ADIF3 ADIF2 ADIF1 ADIF0 Bits Description...
  • Page 968 M451 Bits Description Busy/Idle 0 = EADC is in idle state. [23] BUSY 1 = EADC is busy at conversion. Note: This bit is read only. [22:21] Reserved Reserved. Current Conversion Channel This filed reflects ADC current conversion channel when BUSY=1. It is read only.
  • Page 969 M451 Bits Description ADC Compare 0 Output Status The 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external ADCMPO0 [12] analog input pin voltage status. 0 = Conversion result in EADC_DAT less than CMPDAT0 setting.
  • Page 970 M451 Bits Description ADC Compare 0 Flag When the specific sample module A/D conversion result meets setting condition in EADC_CMP0 then this bit is set to 1. ADCMPF0 0 = Conversion result in EADC_DAT does not meet EADC_CMP0 register setting. 1 = Conversion result in EADC_DAT meets EADC_CMP0 register setting.
  • Page 971 M451 A/D Status Register 3 (EADC_STATUS3) Register Offset Description Reset Value EADC_STATUS3 EADC_BA+0xFC A/D Status Register 3 0x0000_001F Reserved Reserved Reserved Reserved CURSPL Bits Description [31:5] Reserved Reserved. ADC Current Sample Module This register show the current ADC is controlled by which sample module control logic modules.
  • Page 972 M451 A/D Double Data Registers for A/D Data Registers (EADC_DDAT0~3) Register Offset Description Reset Value EADC_DDAT0 EADC_BA+0x100 A/D Double Data Register 0 for Sample Module 0 0x0000_0000 EADC_DDAT1 EADC_BA+0x104 A/D Double Data Register 1 for Sample Module 1 0x0000_0000 EADC_DDAT2 EADC_BA+0x108 A/D Double Data Register 2 for Sample Module 2 0x0000_0000...

  • Page 973: Digital To Analog Converter (Dac)

    M451 6.23 Digital to Analog Converter (DAC) 6.23.1 Overview The DAC module is a 12-bit, voltage output digital-to-analog converter. It can be used in conjunction with the PDMA controller. The DAC integrates a voltage output buffer that can be used to reduce output impendence and drive external loads directly without having to add an external operational amplifier.

  • Page 974: Basic Configuration

    M451 6.23.4 Basic Configuration The DAC output pin is configured in SYS_GPB_MFPL[3:0] Multi-function Register. The DAC Controller clock source is enabled by DACCKEN (CLK_APBCLK1[12]). 6.23.5 Functional Description 6.23.5.1 DAC Output The DAC is a 12-bit voltage output digital-to-analog converter. The DAC integrates a voltage output buffer that can be used to reduce output impendence and drive external loads directly without having to add an external operational amplifier.

  • Page 975: Figure 6.23-3 Dac Conversion Started By Software Write Trigger

    M451 Two adjacent codes conversion settling time is 1us. The DAC controller provides a 10-bit time counter for user to count the conversion time period. In continuous conversion operation, user needs to write appropriate value to SETTLET (DAC_TCTL[9:0]) to define DAC conversion time period.

  • Page 976: Figure 6.23-5 Dac Pdma Underrun Condition Example

    M451 6.23.5.7 DMA Operation DAC DMA request is generated when a hardware trigger event occurs while DMAEN (DAC_CTL[2]) is set. The content of DAC_DAT is transferred to the DAC_DATOUT[11:0] and DAC starts data conversion after one PCLK (APB clock) clock cycle. The new transferred data by PDMA in DAC_DAT will be converted when next trigger event arrives.

  • Page 977: Figure 6.23-6 Dac Continuous Conversion With Software Pdma Mode

    M451 PCLK 0x250 DAC_DAT 0x123 0x240 DAC_DATOUT 0x123 0x240 DACEN DAC_CTL[0] PDMA Request PDMA Acknowledge FINISH DAC_STATUS[0] SETTLING Figure 6.23-6 DAC Continuous Conversion with Software PDMA Mode 6.23.5.8 Interrupt Sources There are two interrupt sources in DAC controller, one is DAC data conversion finish interrupt and the other is DMA under-run interrupt.

  • Page 978: Register Map

    M451 6.23.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value DAC Base Address: DAC_BA = 0x4004_7000 DAC_CTL DAC_BA+0x00 DAC Control Register 0x0000_0000 DAC_SWTRG DAC_BA+0x04 DAC Software Trigger Control Register 0x0000_0000 DAC_DAT DAC_BA+0x08 DAC Data Holding Register...

  • Page 979: Register Description

    M451 6.23.7 Register Description DAC Control Register (DAC_CTL) Register Offset Description Reset Value DAC_CTL DAC_BA+0x00 DAC Control Register 0x0000_0000 Reserved Reserved Reserved ETRGSEL Reserved LALIGN Reserved BYPASS TRGSEL TRGEN DMAURIEN DMAEN DACIEN DACEN Bits Description [31:14] Reserved Reserved. External Pin Trigger Selection 00 = Low level trigger.
  • Page 980 M451 1 = DAC event trigger mode Enabled. DMA Under-run Interrupt Enable Bit DMAURIEN 0 = DMA underrun interrupt Disabled. 1 = DMA underrun interrupt Enabled. DMA Mode Enable Bit DMAEN 0 = DMA mode Disabled. 1 = DMA mode Enabled. DAC Interrupt Enable Bit DACIEN 0 = Interrupt is Disabled.
  • Page 981 M451 DAC Software Trigger Control Register (DAC_SWTRG) Register Offset Description Reset Value DAC_SWTRG DAC_BA+0x04 DAC Software Trigger Control Register 0x0000_0000 Reserved Reserved Reserved Reserved SWTRG Bits Description [31:1] Reserved Reserved. Software Trigger 0 = Software trigger Disabled. SWTRG 1 = Software trigger Enabled. User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically;...
  • Page 982 M451 DAC Data Holding Register (DAC_DAT) Register Offset Description Reset Value DAC_DAT DAC_BA+0x08 DAC Data Holding Register 0x0000_0000 Reserved Reserved DAC_DAT DAC_DAT Bits Description [31:16] Reserved Reserved. DAC 12-bit Holding Data These bits are written by user software which specifies 12-bit conversion data for DAC output.
  • Page 983 M451 DAC Data Output Register (DAC_DATOUT) Register Offset Description Reset Value DAC_DATOU DAC_BA+0x0C DAC Data Output Register 0x0000_0000 Reserved Reserved Reserved DATOUT DATOUT Bits Description Reserved [31:12] Reserved. DAC 12-bit Output Data [11:0] DATOUT These bits are current digital data for DAC output conversion. It is loaded from DAC_DAT register and user cannot write it directly.
  • Page 984 M451 DAC Status Register (DAC_STATUS) Register Offset Description Reset Value DAC_STATUS DAC_BA+0x10 DAC Status Register 0x0000_0000 Reserved Reserved Reserved BUSY Reserved DMAUDR FINISH Bits Description [31:9] Reserved Reserved. DAC Busy Flag (Read Only) 0 = DAC is ready for next conversion. BUSY 1 = DAC is busy in conversion.
  • Page 985 M451 DAC Timing Control Register (DAC_TCTL) Register Offset Description Reset Value DAC_TCTL DAC_BA+0x14 DAC Timing Control Register 0x0000_0000 Reserved Reserved Reserved SETTLET SETTLET Bits Description [31:10] Reserved Reserved. DAC Output Settling Time User software needs to write appropriate value to these bits to meet DAC conversion [9:0] SETTLET settling time base on PCLK (APB clock) speed.

  • Page 986: Analog Comparator Controller (Acmp)

    M451 6.24 Analog Comparator Controller (ACMP) 6.24.1 Overview The M451 contains two comparators. The comparator output is logic 1 when positive input is greater than negative input; otherwise, the output is 0. Each comparator can be configured to generate an interrupt when the comparator output value changes. 6.24.2 Features ...

  • Page 987: Block Diagram

    M451 6.24.3 Block Diagram ACMPEN OUTSEL ACMPOINV ACMP0_P0 (ACMP_CTL0[0]) (ACMP_CTL0[12]) (ACMP_CTL0[3]) ACMP0_P1 ACMP0_P2 ACMP0_N CMP0 ACMP0_O Filter ACMP0_P3 Block ACMPO0 HYSEN POSSEL (ACMP_STATUS[4]) (ACMP_CTL0[2]) DAC_OUT (ACMP_CTL0[7:6]) FILTSEL NEGSEL (ACMP_CTL0[15:13]) INTPOL (ACMP_CTL0[5:4]) (ACMP_CTL0[9:8]) OUTSEL (ACMP_CTL1[12]) ACMPEN ACMPOINV ACMPO1 ACMP1_P0 (ACMP_CTL1[0]) (ACMP_CTL1[3]) (ACMP_STATUS[5]) ACMP1_P1 ACMP1_P2...

  • Page 988: Basic Configuration

    M451 6.24.4 Basic Configuration ACMP clock source is PCLK and can be enabled by setting ACMP01CKEN (CLK_APBCLK0[7]). The ACMP pin functions are configured in SYS_GPB_MFPL, SYS_GPB_MFPH, SYS_GPC_MFPL, SYS_GPD_MFPL and SYS_GPD_MFPH registers. It is recommended to disable the digital input path of the analog input pins to avoid the leakage current. The digital input path can be disabled by configuring PB_DINOFF and PD_DINOFF registers.

  • Page 989: Figure 6.24-3 Comparator Hysteresis Function

    M451 High threshold voltage Negative input voltage Low threshold voltage Positive input voltage Comparator output Figure 6.24-3 Comparator Hysteresis Function 6.24.5.3 Filter Function The analog comparator provides filter function to avoid the un-stable state of comparator output. By setting FILTSEL (ACMP_CTL0[15:13], ACMP_CTL1[15:13]), the comparator output would be sampled by consecutive PCLKs.

  • Page 990: Register Map

    M451 6.24.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value ACMP Base Address: ACMP01_BA = 0x4004_5000 ACMP_CTL0 ACMP01_BA+0x00 R/W Analog Comparator 0 Control Register 0x0000_0000 ACMP_CTL1 ACMP01_BA+0x04 R/W Analog Comparator 1 Control Register 0x0000_0000 ACMP_STATUS ACMP01_BA+0x08...

  • Page 991: Register Description

    M451 6.24.7 Register Description Analog Comparator 0 Control Register (ACMP_CTL0) Register Offset R/W Description Reset Value ACMP_CTL0 ACMP01_BA+0x00 R/W Analog Comparator 0 Control Register 0x0000_0000 Reserved Reserved WKEN FILTSEL OUTSEL Reserved INTPOL POSSEL NEGSEL ACMPOINV HYSEN ACMPIE ACMPEN Bits Description Reserved [31:17] Reserved.
  • Page 992 M451 01 = Input from ACMP0_P1. 10 = Input from ACMP0_P2. 11 = Input from ACMP0_P3. Comparator Negative Input Selection 00 = ACMP0_N pin. [5:4] NEGSEL 01 = Internal comparator reference voltage (CRV). 10 = Band-gap voltage. 11 = DAC output. Comparator Output Inverse ACMPOINV 0 = Comparator 0 output inverse Disabled.
  • Page 993 M451 Analog Comparator 1 Control Register (ACMP_CTL1) Register Offset R/W Description Reset Value ACMP_CTL1 ACMP01_BA+0x04 R/W Analog Comparator 1 Control Register 0x0000_0000 Reserved Reserved WKEN FILTSEL OUTSEL Reserved INTPOL POSSEL NEGSEL ACMPOINV HYSEN ACMPIE ACMPEN Bits Description [31:17] Reserved Reserved. Power-down Wakeup Enable Bit [16] WKEN...
  • Page 994 M451 Bits Description 10 = Input from ACMP1_P2. 11 = Input from ACMP1_P3. Comparator Negative Input Selection 00 = ACMP1_N pin. [5:4] NEGSEL 01 = Internal comparator reference voltage (CRV). 10 = Band-gap voltage. 11 = DAC output. Comparator Output Inverse Control ACMPOINV 0 = Comparator 1 output inverse Disabled.
  • Page 995 M451 Analog Comparator Status Register (ACMP_STATUS) Register Offset Description Reset Value ACMP_STATUS ACMP01_BA+0x08 Analog Comparator Status Register 0x0000_0000 Reserved Reserved Reserved WKIF1 WKIF0 Reserved ACMPO1 ACMPO0 Reserved ACMPIF1 ACMPIF0 Bits Description [31:10] Reserved Reserved. Comparator 1 Power-down Wake-up Interrupt Flag This bit will be set to 1 when ACMP1 wake-up interrupt event occurs.
  • Page 996 M451 Bits Description Note: Write 1 to clear this bit to 0. May. 4, 2018 Page 996 of 1006 Rev.2.08...
  • Page 997 M451 ACMP Reference Voltage Control Register (ACMP_VREF) Register Offset R/W Description Reset Value ACMP_VREF ACMP01_BA+0x0C R/W Analog Comparator Reference Voltage Control Register 0x0000_0000 Reserved Reserved Reserved Reserved CRVSSEL Reserved CRVCTL Bits Description [31:7] Reserved Reserved. CRV Source Voltage Selection 0 = AV is selected as CRV source voltage.

  • Page 998: Application Circuit

    M451 APPLICATION CIRCUIT AVCC USB_VBUS USB_D- USB OTG Slot USB_D+ DVCC USB_ID USB_VDD33_CAP DDIO 0.1uF Power DVCC 0.1uF SPI_SS SPI Device SPI_CLK SPI_MISO MISO SPI_MOSI MOSI DVCC DVCC ICE_DAT ICE_ CLK Interface nRESET 4.7K 4.7K M451 Series I2C_SCL C Device XT1_IN I2C_SDA 4~ 20 MHz...

  • Page 999: Electrical Characteristics

    M451 ELECTRICAL CHARACTERISTICS ® For information on the M451 series electrical characteristics, please refer to NuMicro M451 Series Datasheet. May. 4, 2018 Page 999 of 1006 Rev.2.08...

  • Page 1000: Package Dimensions

    M451 PACKAGE DIMENSIONS LQFP 100L (14x14x1.4 mm footprint 2.0 mm) May. 4, 2018 Page 1000 of 1006 Rev.2.08...

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