Nuvoton NuMicro MS51XB9AE Manuals

Manuals and User Guides for Nuvoton NuMicro MS51XB9AE. We have 1 Nuvoton NuMicro MS51XB9AE manual available for free PDF download: Technical Reference Manual

Nuvoton NuMicro MS51XB9AE Technical Reference Manual (316 pages)

8-bit Microcontroller

Brand: Nuvoton | Category: Microcontrollers | Size: 3 MB

Table of Contents
2
General Description
8
Features
9
Parts Information
12
Package Type
12
MS51 Series Selection Guide
12
MS51 Series Selection Code
13
Pin Configuration
14
MS51 16KB Series Multi Function Pin Diagram
14
TSSOP 20-Pin Package Pin Diagram
14
Figure 4.1-1 Pin Assignment of TSSOP-20 Package
14
QFN 20-Pin Package Pin Diagram
15
Figure 4.1-2 Pin Assignment of QFN-20 Package
15
Figure 4.1-3 Pin Assignment of QFN-20 Package
16
MS51 16KB Series Pin Description
17
Block Diagram
20
MS51 16KB Series Block Diagram
20
Figure 5.1-1 Functional Block Diagram
20
Function Description
21
Memory Organization
21
Program Memory
21
Figure 6.1-1 MS51 Program Memory Map and Boot Select
22
Data Flash
23
Security Protection Memory (SPROM)
23
Config Bytes
23
Figure 6.1-2 SPROM Memory Mapping and SPROM Security Mode
23
Figure 6.1-3 CONFIG0 any Reset Reloading
24
Figure 6.1-4 CONFIG2 Power-On Reset Reloading
26
Data Memory
28
Figure 6.1-5 Data Memory Map
28
Figure 6.1-6 Internal 256 Bytes RAM Addressing
29
Special Function Register (SFR)
30
Table 6.1-1 Special Function Register Memory Map
34
Table 6.1-2 SFR Definitions and Reset Values
38
System Manager
153
Clock System
153
Figure 6.2-1 Clock System Block Diagram
153
Power Management
158
Power Monitoring and Reset
160
Power-On Reset and Low Voltage Reset
160
Brown-Out Detect and Reset
160
External Reset and Hard Fault Reset
161
Watchdog Timer Reset
162
Software Reset
163
Boot Select
164
Figure 6.2-2 Boot Selecting Diagram
164
Reset State
165
Interrupt System
165
Enabling Interrupts
166
Table 6.2-1 Interrupt Vectors
166
Interrupt Priorities
167
Table 6.2-2 Interrupt Priority Level Setting
167
Interrupt Service
168
Table 6.2-3 Characteristics of each Interrupt Source
168
Interrupt Latency
169
Table 6.3-1 IAP Modes and Command Codes
181
Table 6.4-1 Configuration for Different I/O Modes
193
Figure 6.4-1 Quasi-Bidirectional Mode Structure
194
Figure 6.4-2 Push-Pull Mode Structure
194
Figure 6.4-3 Input-Only Mode Structure
194
Figure 6.4-4 Open-Drain Mode Structure
195
Figure 6.4-5 Pin Interface Block Diagram
200
Figure 6.5-1 Timer/Counters 0 and 1 in Mode 0
205
Figure 6.5-2 Timer/Counters 0 and 1 in Mode 1
206
Figure 6.5-3 Timer/Counters 0 and 1 in Mode 2
206
Figure 6.5-4 Timer/Counter 0 in Mode 3
207
Figure 6.5-5 Timer 2 Full Function Block Diagram
211
Figure 6.5-6 Timer 2 Auto-Reload Mode Block Diagram
212
Figure 6.5-7 Timer 2 Compare Mode Block Diagram
213
Figure 6.5-8 Timer 3 Block Diagram
225
Table 6.6-1 Watchdog Timer-Out Interval under Different Pre-Scalars
228
Figure 6.6-1 WDT as a Time-Out Reset Timer
229
Figure 6.6-2 Watchdog Timer Block Diagram
229
Figure 6.7-1 Self Wake-Up Timer Block Diagram
232
Figure 6.8-1 Serial Port Mode 0 Timing Diagram
235
Figure 6.8-2 Serial Port Mode 1 Timing Diagram
236
Figure 6.8-3 Serial Port Mode 2 and 3 Timing Diagram
237
Table 6.8-1 Serial Port UART0 Mode / Baudrate Description
238
Table 6.8-2 Serial Port UART1 Mode / Baudrate Description
239
Figure 6.9-1 SPI Block Diagram
255
Figure 6.9-2 SPI Multi-Master, Multi-Slave Interconnection
256
Figure 6.9-3 SPI Single-Master, Single-Slave Interconnection
256
Table 6.9-1 Slave Select Pin Configurations
257
Figure 6.9-4 SPI Clock Formats
258
Figure 6.9-5 SPI Clock and Data Format with CPHA = 0
259
Figure 6.9-6 SPI Clock and Data Format with CPHA = 1
259
Figure 6.9-7 SPI Overrun Waveform
261
Figure 6.9-8 SPI Interrupt Request
261
Figure 6.10-1 I 2 C Bus Interconnection
265
Figure 6.10-2 I 2 C Bus Protocol
266
Figure 6.10-3 START, Repeated START, and STOP Conditions
266
Figure 6.10-4 Master Transmits Data to Slave by 7-Bit
267
Figure 6.10-5 Master Reads Data from Slave by 7-Bit
267
Figure 6.10-6 Data Format of One I C Transfer
267
Figure 6.10-7 Acknowledge Bit
268
Figure 6.10-8 Arbitration Procedure of Two Masters
268
Figure 6.10-9 Control I
269
Figure 6.10-10 Flow and Status of Master Transmitter Mode
270
Figure 6.10-11 Flow and Status of Master Receiver Mode
271
Figure 6.10-12 Flow and Status of Slave Receiver Mode
272
Figure 6.10-13 Flow and Status of General Call Mode
273
Figure 6.10-14 I 2 C Time-Out Counter
275
Figure 6.10-15 Hold Time Extend Enable
276
Figure 6.11-1 PWM Block Diagram
284
Figure 6.11-2 PWM and Fault Brake Output Control Block Diagram
285
Figure 6.11-3 PWM Edge-Aligned Type Waveform
286
Figure 6.11-4 PWM Center-Aligned Type Waveform
287
Figure 6.11-5 PWM Complementary Mode with Dead-Time Insertion
288
Figure 6.11-6 Fault Brake Function Block Diagram
288
Figure 6.11-7 PWM Interrupt Type
289
Figure 6.12-112-Bit ADC Block Diagram
297
Figure 6.12-2 External Triggering ADC Circuit
299
Figure 6.12-3 ADC Result Comparator
299
Figure 7.1-1 TSSOP-20 Package Dimension
307
Figure 7.2-1 QFN-20 Package Dimension for MS51XB9AE
309
Figure 7.3-1 QFN-20 Package Dimension for MS51XB9BE
310
Table 8.1-1 Instructions that Affect Flag Settings
311
Table 8.2-1 Instruction Set
314

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Nuvoton NuMicro MS51XB9AE Technical Reference Manual (316 pages)

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