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Nuvoton NuMicro MS51 32K Series Technical Reference Manual

Nuvoton NuMicro MS51 32K Series Technical Reference Manual

8-bit microcontroller

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Technical Reference Manual

The information described in this document is the exclusive intellectual property of

Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.

Nuvoton is providing this document only for reference purposes of NuMicro

system design. Nuvoton assumes no responsibility for errors or omissions.

All data and specifications are subject to change without notice.

For additional information or questions, please contact: Nuvoton Technology Corporation.

Nov. 28, 2019

®

NuMicro

Family

MS51 32K Series

MS51FC0AE

MS51XC0BE

MS51EC0AE

MS51TC0AE

MS51PC0AE

www.nuvoton.com

Page 1 of 491

1T 8051

8-bit Microcontroller

®

microcontroller based

MS51

Rev 1.00

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Page 1 MS51PC0AE Technical Reference Manual The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. ® Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system design.
Page 2: Table Of Contents
MS51 TABLE OF CONTENTS 1 GENERAL DESCRIPTION ................10 2 FEATURES ....................11 3 PARTS INFORMATION ................. 15 3.1 Package Type ......................15 3.2 MS51 Series Selection Gude ..................15 3.3 MS51 Series Selection Code ..................16 4 PIN CONFIGURATION .................. 17 4.1 MS51 32K Series Multi Function Pin Diagram ............
Page 3 MS51 6.3.5 CONFIG Bytes ......................267 6.4 General Purpose I/O (GPIO) ................... 272 6.4.1 Gpio Mode ........................272 6.4.2 Read-Modify-Write Instructions .................. 274 6.4.3 Pin Interrupt (PIT) ......................275 6.4.4 Control Registers of GPIO ..................276 6.5 Timer ..........................287 6.5.1 Timer/Counter 0 And 1 ....................
Page 4 MS51 6.11.1 Overview ........................408 6.11.2 Functional Description ....................408 6.11.3 Typical Structure of I C Interrupt Service Routine ........... 418 6.11.4 I C Time-Out ........................421 6.11.5 I C Interrupt ........................422 6.11.6 Control Registers of I C ....................423 6.12 Serial Peripheral Interface (SPI)................
Page 5 MS51 11.2 Instruction Set ...................... 486 12 REVISION HISTORY ................... 490 Nov. 28, 2019 Page 5 of 491 Rev 1.00...
Page 6 MS51 LIST OF FIGURES Figure 4.1-1 Pin Assignment of LQFP-32 Package ............... 17 Figure 4.1-2 Pin Assignment of LQFP-32 Package ............... 18 Figure 4.1-3 Pin Assignment of TSSOP28 Package ..............19 Figure 4.1-4 Pin Assignment of TSSOP20 Package ..............19 Figure 4.1-5 Pin Assignment of QFN20 Package ................
Page 7 MS51 Figure 6.6-7 PWM0 Complementary Mode with Dead-time Insertion ......... 325 Figure 6.6-8 Fault Brake Function Block Diagram ............... 326 Figure 6.6-9 PWM Interrupt Type ....................329 Figure 6.7-1 WDT as A Time-Out Reset Timer ................355 Figure 6.7-2 Watchdog Timer Block Diagram ................355 Figure 6.8-1 Self Wake-Up Timer Block Diagram ................
Page 8 MS51 Figure 6.12-7 SPI Overrun Waveform..................435 Figure 6.12-8 SPI Interrupt Request .................... 435 Figure 6.13-1 12-bit ADC Block Diagram ..................441 Figure 6.13-2 External Triggering ADC Circuit ................444 Figure 6.13-3 ADC Result Comparator ..................444 Figure 6.13-4 ADC Continues mode with DMA ................445 ®...
Page 9 MS51 List of Tables Table 6.1-1 Special Function Register Memory Map ..............39 Table 6.1-2 SFR Definitions and Reset Values ................47 Table 6.1-3 Instructions That Affect Flag Settings ............... 133 Table 6.2-1 BOF Reset Value ...................... 215 Table 6.2-2 Minimum Brown-out Detect Pulse Width ..............218 Table 6.2-3 Interrupt Vectors .......................
Page 10: General Description
MS51 GENERAL DESCRIPTION The MS51 is an embedded Flash type, 8-bit high performance 1T 8051-based microcontroller. The instruction set is fully compatible with the standard 80C51 and performance enhanced. The MS51 contains a up to 32 Kbytes of main Flash called APROM, in which the contents of User Code resides.
Page 11: Features
MS51 FEATURES Core and System  Fully static design 8-bit high performance 1T 8051-based CMOS microcontroller.  Instruction set fully compatible with MCS-51. 8051  4-priority-level interrupts capability.  Dual Data Pointers (DPTRs).  4-level selection, with brown-out interrupt and reset option. Brown-out Detector (BOD) (4.4V / 3.7V / 2.7V / 2.2V) ...
Page 12 MS51 by software from high-speed internal oscillator Timers  Two 16-bit Timers/Counters 0 and 1 compatible with standard 8051.  One 16-bit Timer2 with three-channel input capture module 16-bit Timer and 9 input pin can be selected.  One 16-bit auto-reload Timer3, which can be the baud rate clock source of UART0 and UART1.
Page 13 MS51  Software Write 1 to ADCS bit.  External pin (STADC) trigger  PWM trigger.  Support continues convert function auto store the A/D conversion result in XRAM. Communication Interfaces  Supports up to 2 UARTs: UART0, UART1,  Three sets ISO 7816-3 device configuration as UART ...
Page 14 MS51 trigger setting ̅̅̅̅̅̅̅ and INT1 ̅̅̅̅̅̅̅ .  Standard interrupt pins INT0  Supports high drive and high sink current I/O  I/O pin internal pull-up or pull-down resistor enabled in input mode.  Maximum I/O Speed is 24 MHz ...
Page 15: Parts Information
MS51 PARTS INFORMATION Package Type MSOP10 TSSOP14 TSSOP20 QFN20 TSSOP28 LQFP32 QFN33 MS51BA9AE MS51DA9AE MS51FB9AE MS51XB9AE MS51EC0AE MS51PC0AE MS51TC0AE Part MS51FC0AE MS51XB9BE MS51XC0BE 3.2 MS51 Series Selection Gude Connectivity Part Number MS51BA9AE 5-ch MSOP10 MS51DA9AE 7-ch TSSOP14 MS51XB9AE 8-ch QFN20 MS51XB9BE 8-ch QFN20...
Page 16: 3.3 Ms51 Series Selection Code
MS51 3.3 MS51 Series Selection Code Core Line Package Flash SRAM Reserve Temperature 1T 8051 51: Base B: MSOP10 (3x3 mm) A: 8 KB 0: 2 KB E:-40 ~ 105°C Industry D: TSSOP14 (4.4x5.0 mm) B: 16 KB 1: 4 KB E: TSSOP28 (4.4x9.7 mm) C: 32 KB 2: 8/12 KB...
Page 17: Pin Configuration
Users can find pin configuaration informations by using NuTool - PinConfigure. The NuTool - ® PinConfigure contains all Nuvoton NuMicro Family chip series with all part number, and helps users configure GPIO multi-function correctly and handily. MS51 32K Series Multi Function Pin Diagram 4.1.1...
Page 18: Lqfp 32-Pin Package Pin Diagram
MS51 4.1.2 LQFP 32-pin Package Pin Diagram Corresponding Part Number: MS51PC0AE PWM0_BRAKE / CLKO / PWM0_CH0 / P3.3 P2.1 / ADC_CH9 / PWM2_CH0 UART1_RXD / I2C0_SCL / ICE_CLK / P0.2 P2.2 / ADC_CH10 / PWM1_CH1 / UART4_RXD PWM3_CH1 / UART2_TXD / PWM0_CH5 / IC5 / ADC_CH6 / P0.3 P2.3 / ADC_CH11 / PWM1_CH0 / UART4_TXD PWM2_CH1 / UART2_RXD / STADC / PWM0_CH3 / IC3 / ADC_CH5 / P0.4 P2.4 / ADC_CH12 / T0...
Page 19: Tssop 28-Pin Package Pin Diagram
MS51 4.1.3 TSSOP 28-pin Package Pin Diagram Corresponding Part Number: MS51EC0AE P1.7 / ADC_CH0 / INT1 / UART2_RXD / SPI0_CLK UART1_TXD / I2C0_SDA / ICE_DAT / P1.6 P3.0 / ADC_CH1 / OSCIN / INT0 / UART2_TXD / SPI0_MOSI P2.0 / nRESET PWM3_CH1 / UART3_TXD / IC7 / SPI0_SS / PWM0_CH5 / P1.5 P3.4 / PWM3_CH1 / UART3_RXD SPI0_MISO / UART3_RXD / ADC_CH15 / P2.5...
Page 20: Qfn 20-Pin Package Pin Diagram
MS51 4.1.5 QFN 20-pin Package Pin Diagram Corresponding Part Number: MS51XC0BE PWM3_CH1 / UART2_TXD / PWM0_CH5 / IC5 / ADC_CH6 / P0.3 P1.2 / PWM0_CH0 / IC0 / UART3_TXD / PWM1_CH0 Top transparent view PWM2_CH1 / UART2_RXD / STADC / PWM0_CH3 / IC3 / ADC_CH5 / P0.4 P1.3 / STADC / I2C0_SCL / ADC_CH13 QFN20 PWM2_CH0 / UART3_TXD / T0 / PWM0_CH2 / IC6 / ADC_CH4 / P0.5...
Page 21: Ms51 32K Series Pin Description
MS51 MS51 32K Series Pin Description Pin Number MS51PC0AE Symbol Multi-Function Description MS51XC0BE MS51FC0AE MS51EC0AE LQFP 32 QFN 20 TSSOP20 TSSOP28 MS51TC0AE QFN 33 Supply voltage V for operation. Ground potential. P0.0 Port 0 bit 0. PWM0_CH3 PWM0 output channel 3. PWM2_CH1 PWM2 output channel 1.
Page 22 MS51 Pin Number MS51PC0AE Symbol Multi-Function Description MS51XC0BE MS51FC0AE MS51EC0AE LQFP 32 QFN 20 TSSOP20 TSSOP28 MS51TC0AE QFN 33 ADC_CH3 ADC input channel 3. UART0_TXD UART0 transmit data output. P0.7 Port 0 bit 7. ADC_CH2 ADC input channel 2. UART0_RXD UART0 transmit data output.
Page 23 MS51 Pin Number MS51PC0AE Symbol Multi-Function Description MS51XC0BE MS51FC0AE MS51EC0AE LQFP 32 QFN 20 TSSOP20 TSSOP28 MS51TC0AE QFN 33 INT1 External interrupt 1 input. Port 2 bit 0 input pin available when RPD P2.0 (CONFIG0.2) is programmed as 0. It is a Schmitt trigger input pin for hardware device reset.
Page 24 MS51 Pin Number MS51PC0AE Symbol Multi-Function Description MS51XC0BE MS51FC0AE MS51EC0AE LQFP 32 QFN 20 TSSOP20 TSSOP28 MS51TC0AE QFN 33 UART1_TXD UART1 transmit data output. Port 3 bit 7. P3.7 UART1 receive input. UART1_RXD Note: 1. All I/O pins can be configured as a interrupt pin. This feature is not listed in multi-function description. See Chapter 6.4.3 Pin Interrupt (PIT) 2.
Page 25: Block Diagram
MS51 BLOCK DIAGRAM MS51 32K Series Block Diagram Figure 5.1-1 Functional Block Diagram shows the MS51 functional block diagram and gives the outline of the device. User can find all the peripheral functions of the device in the diagram. Power 1T High POR / LVR / BOD Performance...
Page 26: Functional Description
MS51 FUNCTIONAL DESCRIPTION 6.1 Memory Organization 6.1.1 Overview A standard 80C51 based microcontroller divides the memory into two different sections, Program Memory and Data Memory. The Program Memory is used to store the instruction codes, whereas the Data Memory is used to store data or variations during the program execution. The Data Memory occupies a separate address space from Program Memory.
Page 27: Figure 6.1-1 Ms51 Program Memory Map
MS51 CONFIG1 LDSIZE[2:0] Factory default value: 1111 1111b Name Description LDSIZE[2:0] LDROM size select This field selects the size of LDROM. 111 = No LDROM. APROM is 32 Kbytes. 110 = LDROM is 1 Kbytes. APROM is 31 Kbytes. 101 = LDROM is 2 Kbytes. APROM is 30 Kbytes. 100 = LDROM is 3 Kbytes.
Page 28: Data Flash Memory
MS51 6.1.3 Data Flash Memory MS51 Series Data Flash is shared with APROM or LDROM. Any page of APROM or LDROM can be used as non-volatile data Flash storage and size no need special configuration. The base address of Data Flash is determined by applying IAP, For IAP details, please see Chapter 6.3.1In-Application- Programming (IAP).
Page 29: Figure 6.1-3. Config0 Any Reset Reloading
MS51 CONFIG0 OCDPWM OCDEN LOCK Factory default value: 1111 1111b Name Description CONFIG boot select This bit defines from which block that MCU re-boots after resets except software reset. 1 = MCU will re-boot from APROM after resets except software reset. 0 = MCU will re-boot from LDROM after resets except software reset.
Page 30 MS51 CONFIG1 LDSIZE[2:0] Factory default value: 1111 1111b Name Description LDSIZE[2:0] LDROM size select Part number is MS51: 111 = No LDROM. APROM is 32 Kbytes. 110 = LDROM is 1 Kbytes. APROM is 31 Kbytes. 101 = LDROM is 2 Kbytes. APROM is 30 Kbytes. 100 = LDROM is 3 Kbytes.
Page 31: Figure 6.1-4. Config2 Power-On Reset Reloading
MS51 CONFIG2 CBODEN CBOV[1:0] BOIAP CBORST Factory default value: 1111 1111b Name Description CBODEN CONFIG brown-out detect enable 1 = Brown-out detection circuit on. 0 = Brown-out detection circuit off. Reserved CBOV[1:0] CONFIG brown-out voltage select 11 = V is 2.2V. 10 = V is 2.7V.
Page 32 MS51 CONFIG3 CKFS[1:0] Factory default value: 1111 1111b Name Description CKFS[1:0] Clock filter time select Enable clock filter. It increases noise immunity and EMC capacity. 11 = 15 ns. 10 = 15 ns. 01 = 15 ns. 00 = Clock filter Disabled. Reserved Nov.
Page 33 MS51 CONFIG4 WDTEN[3:0] Factory default value: 1111 1111b Name Description WDTEN[3:0] WDT enable This field configures the WDT behavior after MCU execution. 1111 = WDT is Disabled. WDT can be used as a general purpose timer via software control. 0101 = WDT is Enabled as a time-out reset timer and it stops running during Idle or Power-down mode.
Page 34: Data Memory
MS51 6.1.6 Data Memory 6.1.6.1 internal Data Memory 07FFH Upper 128 Bytes internal RAM (direct addressing) (indirect addressing) Lower 128 Bytes internal RAM 2 KBytes XRAM (direct or indirect (MOVX addressing) addressing) 0000H Figure 6.1-5 Data Memory Map Figure 6.1-5 Data Memory Map shows the internal Data Memory spaces available on MS51. Internal Data Memory occupies a separate address space from Program Memory.
Page 35: Figure 6.1-6 Internal 256 Bytes Ram Addressing
MS51 Indirect Accessing RAM Direct or Indirect Accessing RAM Bit-addressable Register Bank 3 Register Bank 2 General Purpose General Purpose Registers Registers Register Bank 1 Register Bank 0 Figure 6.1-6 Internal 256 Bytes RAM Addressing Nov. 28, 2019 Page 35 of 491 Rev 1.00...
Page 36 MS51 6.1.6.2 On-Chip XRAM The MS51 provides additional on-chip 2 Kbytes auxiliary RAM called XRAM to enlarge the RAM space. It occupies the address space from 00H through FFH. The 2 Kbytes of XRAM are indirectly accessed by move external instruction MOVX @DPTR or MOVX @Ri. (See the demo code below.) Note that the stack pointer cannot be located in any part of XRAM.
Page 37: Special Function Register (Sfr)
MS51 6.1.7 Special Function Register (SFR) The MS51 uses Special Function Registers (SFR) to control and monitor peripherals and their modes. The SFR reside in the register locations 80 to FFH and are accessed by direct addressing only. SFR those end their addresses as 0H or 8H are bit-addressable. It is very useful in cases where user would like to modify a particular bit directly without changing other bits via bit-field instructions.
Page 38 MS51 SFRS – SFR Page Selection Register SFR Address Reset Value SFRS 91H, All page 0000_0000 b SFRPAGE1 SFRPAGE0 Name Description SFRPAGE[1:0] SFR page select 0 = Instructions access SFR page 0. 1 = Instructions access SFR page 1. 2 = Instructions access SFR page 2. Switch SFR page demo code: SFRS,#01H SFRS,#00H...
Page 39: Table 6.1-1 Special Function Register Memory Map
MS51 6.1.7.2 SFR Memory Map Addr Page PWM0DTEN PWM0DTCNT PWM0MEN PWM0MD PORDIS EIP1 EIPH1 SCON_1 LVRDIS PIPS0 PIPS1 PIPS2 PIPS3 PIPS4 PIPS5 PIPS6 CAPCON3 CAPCON4 SPCR SPSR SPDR AINDIDS0 EIPH SPCR2 SC0CR0 SC0CR1 SC1CR0 SC1CR1 SC2CR0 SC2CR1 PIPS7 PICON PINEN PIPEN ADCCON0 SC2DR...
Page 40 MS51 6.1.7.3 SFR Description and Reset Values Reset Register Definition Value Extensive interrupt EIPH1 PPWM3H PPWM2H PPWM1H PWKTH PT3H PSH_1 0000 0000b priority high 1 LVRDIS LVR Disable LVRDIS[7:0] 0000 0000b Pin Interrupt Control PIPS6 BSEL2 BSEL1 BSEL0 BSEL2 BSEL1 BSEL0 0000 0000b Extensive interrupt...
Page 41 MS51 Reset Register Definition Value SC2 Transfer Status SC2TSR TXEMPTY TXOV RXEMPTY RXOV 0000 1010b Register Input capture 2 high C2H[7:0] 0000 0000b byte SC2 Interrupt Status SC2IS ACERRIF BGTIF TERRIF TBEIF RDAIF 0000 0010b Register Input capture 2 low C2L[7:0] 0000 0000b byte...
Page 42 MS51 Reset Register Definition Value PWM0 channel 3 PWM0C3L PWM0_CH3[7:0] 0000 0000b duty low byte DDH 1 SC0 Interrupt Enable SC0IE ACERRIEN BGTIEN TERRIEN TBEIEN RDAIEN 0000 0000b Control Register PWM0 channel 2 PWM0C2L PWM0_CH2[7:0] 0000 0000b duty low byte DCH 1 SC0ETUR SC0 ETU Rate...
Page 43 MS51 Reset Register Definition Value PWM3ME PWM3 mask enable PMEN1 PMEN0 0000 0000b Timer 2 low byte CCH 0 TL2[7:0] 0000 0000b PWM0 channel 4 PWM0C4L PWM0C4[7:0] 0000 0000b duty low byte CCH 2 PWM3MD PWM3 mask data PMD1 PMD0 0000 0000b Timer 2 compare RCMP2H...
Page 44 MS51 Reset Register Definition Value SADDR_1 Slave 1 address SADDR_1[7:0] 0000 0000b PWM2 period high PWM2PH PWM2P[15:8] 0000 0000b byte Slave 1 address SADEN_1 SADEN_1[7:0] 0000 0000b mask Slave 0 address SADEN SADEN[7:0] 0000 0000b mask Interrupt priority PADC PBOD 0000 0000b Interrupt priority high B7H PADCH...
Page 45 MS51 Reset Register Definition Value PWM1_C PWM1 channel 0 PWM1_CH015:8] 0000 0000b duty high byte POR, 0000 0111b Watchdog Timer WDT, WDCON WDTR WDCLR WDTF WIDPD WDTRF WDPS2 WDPS1 WDPS0 control 0000 1UUUb Others, 0000 UUUUb PWM1 period high PWM1PH PWM1P[15:8] 0000 0000b byte...
Page 46 MS51 Reset Register Definition Value Port 3 Pull-Down P3DW P3DW.7 P3DW.6 P3DW.5 P3DW.4 P3DW.3 P3DW.2 P3DW.1 P3DW.0 0000 0000b resister control Extensive interrupt EIE1 EPWM3 EPWM2 EPWM1 EWKT ES_1 0000 0000b enable 1 Port 2 Pull-Down P2DW P2DW.5 P2DW.4 P2DW.3 P2DW.2 P2DW.1 P2DW.0...
Page 47: Table 6.1-2 Sfr Definitions And Reset Values
MS51 Reset Register Definition Value Port 2 Slew Rate P2SR P2SR.7 P2SR.6 P2SR.5 P2SR.4 P2SR.3 P2SR.2 P2SR.1 P2SR.0 0000 0000b Control Timer 0 low byte TL1[7:0] 0000 0000b P2M2 P2 Mode Select 2 P2M2.7 P2M2.6 P2M2.5 P2M2.4 P2M2.3 P2M2.2 P2M2.1 P2M2.0 0000 0000b TMOD...
Page 48 MS51 6.1.7.4 All SFR Description Note: 1. All SFRs reset value show as following means U-unchanged; C-initialized by CONFIG; X- base on real chip status. Pn – Port (Bit-addressable) Register SFR Address Reset Value 80H, All pages, Bit-addressable 1111_1111 b 1111_1111 b 90H, All pages, Bit-addressable 0011_1111 b...
Page 49 MS51 SP – Stack Pointer Register SFR Address Reset Value 81H, All pages 0000_0111b SP[7:0] Name Description SP[7:0] Stack pointer The Stack Pointer stores the scratch-pad RAM address where the stack begins. It is incremented before data is stored during PUSH or CALL instructions. Note that the default value of SP is 07H. This causes the stack to begin at location 08H.
Page 50 MS51 DPL – Data Pointer Low Byte Register SFR Address Reset Value 82H, All pages 0000_0000b DPL[7:0] Name Description DPL[7:0] Data pointer low byte This is the low byte of 16-bit data pointer. DPL combined with DPH serve as a 16-bit data pointer DPTR to access indirect addressed RAM or Program Memory.
Page 51 MS51 DPH – Data Pointer High Byte Register SFR Address Reset Value 83H, All pages 0000_0000b DPH[7:0] Name Description DPH[7:0] Data pointer high byte This is the high byte of 16-bit data pointer. DPH combined with DPL serve as a 16-bit data pointer DPTR to access indirect addressed RAM or Program Memory.
Page 52 MS51 RWKL – Self Wake-up Timer Reload Low Byte Register SFR Address Reset Value RWKL 86H, Page 0 0000 0000b RWK[7:0] Name Description RWK[7:0] WKT reload low byte The RWKL register is the low byte of the 16-bit reload value of WKT. Note that RWK should not be FFFFH if the pre-scale is 1/1 for implement limitation.
Page 53 MS51 RWKH – Self Wake-up Timer Reload High Byte Register SFR Address Reset Value RWKH 97H, Page 2 0000 0000b RWK[15:8] Name Description RWK[15:8] WKT reload high byte The RWKH register is the low byte of the 16-bit reload value of WKT. Note that RWK should not be FFFFH if the pre-scale is 1/1 for implement limitation.
Page 54 MS51 PCON – Power Control Register SFR Address Reset Value POR: 0001_0000b PCON 87H, All pages Others: 000U _0000b SMOD SMOD0 Name Description SMOD Serial port 0 double baud rate enable Setting this bit doubles the serial port baud rate when UART0 is in Mode 2 or when Timer 1 overflow is used as the baud rate source of UART0 Mode 1 or 3.
Page 55 MS51 TCON – Timer 0 and 1 Control Register SFR Address Reset Value TCON 88H, All pages, Bit-addressable 0000_0000b R (level) R (level) R/W (edge) R/W (edge) Name Description Timer 1 overflow flag This bit is set when Timer 1 overflows. It is automatically cleared by hardware when the program executes the Timer 1 interrupt service routine.
Page 56 MS51 Name Description External interrupt 0 type select ̅̅̅̅̅̅̅ is triggered. This bit selects by which type that INT0 ̅̅̅̅̅̅̅ is low level triggered. 0 = INT0 ̅̅̅̅̅̅̅ is falling edge triggered. 1 = INT0 Nov. 28, 2019 Page 56 of 491 Rev 1.00...
Page 57 MS51 TMOD – Timer 0 and 1 Mode Register SFR Address Reset Value TMOD 89H, Page0 0000_0000b C/T ̅ C/T ̅ GATE GATE Name Description GATE Timer 1 gate control ̅̅̅̅̅̅̅ logic level. 0 = Timer 1 will clock when TR1 is 1 regardless of INT1 ̅̅̅̅̅̅̅...
Page 58 MS51 TL0 – Timer 0 Low Byte Register SFR Address Reset Value 8AH, Page0 0000_0000b TL0[7:0] Name Description TL0[7:0] Timer 0 low byte The TL0 register is the low byte of the 16-bit counting register of Timer 0. Nov. 28, 2019 Page 58 of 491 Rev 1.00...
Page 59 MS51 TL1 – Timer 1 Low Byte Register SFR Address Reset Value 8BH, Page0 0000_0000b TL1[7:0] Name Description TL1[7:0] Timer 1 low byte The TL1 register is the low byte of the 16-bit counting register of Timer 1. Nov. 28, 2019 Page 59 of 491 Rev 1.00...
Page 60 MS51 TH0 – Timer 0 High Byte Register SFR Address Reset Value 8CH, Page0 0000_0000b TH0[7:0] Name Description TH0[7:0] Timer 0 high byte The TH0 register is the high byte of the 16-bit counting register of Timer 0. Nov. 28, 2019 Page 60 of 491 Rev 1.00...
Page 61 MS51 TH1 – Timer 1 High Byte Register SFR Address Reset Value 8DH, Page0 0000_0000b TH1[7:0] Name Description TH1[7:0] Timer 1 high byte The TH1 register is the high byte of the 16-bit counting register of Timer 1. Nov. 28, 2019 Page 61 of 491 Rev 1.00...
Page 62 MS51 CKCON – Clock Control Register SFR Address Reset Value CKCON 8EH, Page0 0000_0000b PWMCKS CLOEN Name Description PWMCKS PWM clock source select 0 = The clock source of PWM is the system clock F 1 = The clock source of PWM is the overflow of Timer 1. Timer 1 clock mode select 0 = The clock source of Timer 1 is the system clock divided by 12.
Page 63 MS51 WKCON – Self Wake-up Timer Control Register SFR Address Reset Value WKCON 8FH, Page0 0000_0000b WKTF WKTR WKPS[2:0] Name Description WKTF WKT overflow flag This bit is set when WKT overflows. If the WKT interrupt and the global interrupt are enabled, setting this bit will make CPU execute WKT interrupt service routine.
Page 64 MS51 SFRS – SFR Page Selection Register SFR Address Reset Value SFRS 91H, All page 0000_0000b SFRPAGE1 SFRPAGE0 Name Description SFRPAGE[1:0] SFR page select 0 = Instructions access SFR page 0. 1 = Instructions access SFR page 1. 2 = Instructions access SFR page 2. Nov.
Page 65 MS51 CAPCON0 – Input Capture Control 0 Register SFR Address Reset Value CAPCON0 92H, Page 0 0000_0000b CAPEN2 CAPEN1 CAPEN0 CAPF2 CAPF1 CAPF0 Name Description CAPEN2 Input capture 2 enable 0 = Input capture channel 2 Disabled. 1 = Input capture channel 2 Enabled. CAPEN1 Input capture 1 enable 0 = Input capture channel 1 Disabled.
Page 66 MS51 CAPCON1 – Input Capture Control 1 Register SFR Address Reset Value CAPCON1 93H, Page 0 0000_0000b CAP2LS[1:0] CAP1LS[1:0] CAP0LS[1:0] Name Description CAP2LS[1:0] Input capture 2 level select 00 = Falling edge. 01 = Rising edge. 10 = Either Rising or falling edge. 11 = Reserved.
Page 67 MS51 CAPCON2 – Input Capture Control 2 Register SFR Address Reset Value CAPCON2 94H, Page0 0000_0000b ENF2 ENF1 ENF0 Name Description ENF2 Enable noise filer on input capture 2 0 = Noise filter on input capture channel 2 Disabled. 1 = Noise filter on input capture channel 2 Enabled. ENF1 Enable noise filer on input capture 1 0 = Noise filter on input capture channel 1 Disabled.
Page 68 MS51 CKDIV – Clock Divider Register SFR Address Reset Value CKDIV 95H, Page0 0000_0000b CKDIV[7:0] Name Description CKDIV[7:0] Clock divider The system clock frequency F follows the equation below according to CKDIV value. , while CKDIV = 00H, and × CKDIV , while CKDIV = 01H to FFH.
Page 69 MS51 CKSWT – Clock Switch Register SFR Address Reset Value CKSWT 96H, PAGE 0, TA protected 0011 _0000 b HXTST ECKP00ST HIRCST LIRCST ECKP30ST OSC[1:0] Name Description HXTST High-speed external crystal 4 MHz to 24 MHz status 0 = High-speed external crystal is not stable or disabled. 1 = High-speed external crystal is enabled and stable.
Page 70 MS51 CKEN – Clock Enable Register SFR Address Reset Value CKEN 97H, PAGE 0, TA protected 0011_0000 b EXTEN[1:0] HIRCEN CKSWTF Name Description EXTEN[1:0] External clock source enable 11 = External clock input via OSCIN (P30) Enabled 10 = External clock input via HXTIN (P00) Enabled 01 = External crystal 4~24 MHz Enabled 00 = external clock input is disable.
Page 71 MS51 SCON – Serial Port Control Register SFR Address Reset Value SCON 98H, All page, Bit addressable 0000_0000 b SM0/FE Name Description SM0/FE Serial port mode select SMOD0 (PCON.6) = 0: See Table 6.9-1 Serial Port UART0 Mode / baudrate Description for details. SMOD0 (PCON.6) = 1: SM0/FE bit is used as frame error (FE) status flag.
Page 72 MS51 Name Description received bit The bit identifies the logic level of the 9 received bit in serial port 0 Mode 2 or 3. In Mode 1, RB8 is the logic level of the received stop bit. SM2 bit as logic 1 has restriction for exception. RB8 is not used in Mode 0.
Page 73 MS51 SBUF – Serial Port 0 Data Buffer Register SFR Address Reset Value SBUF 99H, Page 0 0000_0000 b SBUF[7:0] Name Description SBUF[7:0] Serial port 0 data buffer This byte actually consists two separate registers. One is the receiving resister, and the other is the transmitting buffer.
Page 74 MS51 SBUF_1 – Serial Port 1 Data Buffer Register SFR Address Reset Value SBUF_1 9AH, Page 0 0000 _0000 b SBUF _ 1[7:0] Name Description SBUF _ 1[7:0] Serial port 1 data buffer This byte actually consists two separate registers. One is the receiving resister, and the other is the transmitting buffer.
Page 75 MS51 EIE – Extensive Interrupt Enable Register SFR Address Reset Value 9BH, Page 0 0000 _0000 b ESPI EWDT EPWM0 ECAP Name Description Enable Timer 2 interrupt 0 = Timer 2 interrupt Disabled. 1 = Interrupt generated by TF2 (T2CON.7) Enabled. ESPI Enable SPI interrupt 0 = SPI interrupt Disabled.
Page 76 MS51 EIE1 – Extensive Interrupt Enable 1 Register SFR Address Reset Value EIE1 9CH, Page 0 0000 _0000 b ES _ 1 EPWM3 EPWM2 EPWM1 EWKT Name Description EPWM3 Enable PWM3 interrupt 0 = PWM3 interrupt Disabled. 1 = Interrupt generated by PWM3F (PWM3CON0.5) Enabled. EPWM2 Enable PWM2 interrupt 0 = PWM2 interrupt Disabled.
Page 77 MS51 RSR – Reset Flag Register Register SFR Address Reset Value 9DH, Page 0 00XX_XXXX b HardF RSTPINF BORF WDTRF SWRF Name Description Reserved HardF mirrored from AUXR1.5 Clear this bit by write AUXR1.5=0 or RSR.5=0 mirrored from PCON.4 Clear this bit by write PCON.4=0 or RSR.4=0 RSTPINF mirrored from AUXR1.6 Clear this bit by write AUXR1.6=0 or RSR.3=0...
Page 78 MS51 CHPCON – Chip Control Register SFR Address Reset Value Software 0000_00U0 b CHPCON 9FH, Page 0, TA protected Others 0000_00C0 b SWRST IAPFF IAPEN Name Description IAPFF IAP fault fla The hardware will set this bit after IAPGO (ISPTRG.0) is set if any of the following condition is met: (1) The accessing address is oversize.
Page 79 MS51 AUXR1 – Auxiliary Register 1 Register SFR Address Reset Value POR: 0000 0000b, Software reset: 1U00 0000b, AUXR1 A2H , Page 0 nRESET pin: U100 0000b, Others: UUU0 0000b SWRF RSTPINF HardF SLOW UART0PX Name Description SWRF Software reset flag When the MCU is reset via software reset, this bit will be set via hardware.
Page 80 MS51 Name Description Data pointer select 0 = Data pointer 0 (DPTR) is active by default. 1 = Data pointer 1 (DPTR1) is active. After DPS switches the activated data pointer, the previous inactivated data pointer remains its original value unchanged. Nov.
Page 81 MS51 AUXR2 – Auxiliary Register 2 Register SFR Address Reset Value AUXR2 A1H, Page 2 0000_0000 b UART2TXP UART2RXP UART1TXP UART1RXP Name Description UART2TXP UART2 TX pin select 00 = Reserved by default 01 = Assign UART2 TX to P0.3 10 = Assign UART2 TX to P3.0 11 = Reserved UART2RXP...
Page 82 MS51 AUXR3 – Auxiliary Register 3 Register SFR Address Reset Value AUXR3 A2H, Page 2 0000_0000 b UART4TXP UART4RXP UART3TXP UART3RXP Name Description UART4TXP UART4 TX pin select 00 = Reserved by default 01 = Assign UART4 TX to P2.3 10 = Reserved 11 = Reserved UART4RXP...
Page 83 MS51 AUXR4 – Auxiliary Register 4 Register SFR Address Reset Value AUXR4 A3H, Page 2 0000_0000 b PWM2_CH1P PWM2_CH0P PWM1_CH1P PWM1_CH0P Name Description PWM2_CH1P PWM2 channel 1 pin select 00 = Assign PWM2_CH1 to P3.0 01 = Assign PWM2_CH1 to P3.1 10 = Assign PWM2_CH1 to P0.0 11 = Assign PWM2_CH1 to P0.4 PWM2_CH0P...
Page 84 MS51 AUXR5 – Auxiliary Register 5 Register SFR Address Reset Value AUXR5 A4H, Page 2 0000_0000 b CLOP PWM3_CH1P PWM3_CH0P Name Description CLOP CLK Output pin select 0 = Assign CLO to P1.1 while CLO output enabled 1 = Assign CLO to P3.3 while CLO output enabled T0 pin select 0 = Assign T0 to P0.5 1 = Assign T0 to P2.4...
Page 85 MS51 AUXR6 – Auxiliary Register 6 Register SFR Address Reset Value AUXR6 A5H, Page 2 0000_0000 b UART4DG UART3DG UART2DG UART1DG UART0DG Name Description UART4DG UART4 RX Deglitch Control 1: Deglitch is Enabled 0: Deglitch is Disabled UART3DG UART3 RX Deglitch Control 1: Deglitch is Enabled 0: Deglitch is Disabled UART2DG...
Page 86 MS51 AUXR7 – Auxiliary Register 7 Register SFR Address Reset Value AUXR7 A6H, Page 2 0000_0000 b SPI0NSSP SPIMOSIP SPIMISOP SPICKP Name Description SPI0NSSP SPI0_SS pin select 00 = Assign SPI0_SS to P1.5 01 = Reserved 10 = Assign SPI0_SS to P3.5 11 = Reserved SPI0MOSIP SPI0_MOSI pin select...
Page 87 MS51 AUXR8 – Auxiliary Register 8 Register SFR Address Reset Value AUXR8 A7H, Page 2, TA protected 0000_0000 b CLODIV[3:0] CKTESTOEN[3:0] Name Description CLODIV[3:0] Clock output divider The system clock output follows the equation below according to CLODIV value.  , while CLODIV = 00H, and ...
Page 88 MS51 BODCON0 – Brown-out Detection Control 0 Register SFR Address Reset Value POR,CCCC XC0X b BODCON0 A3H, Page 0, TA protected BOD, UUUU XU1X b Others,UUUU XUUX b BODEN BOV[1:0] BORST BORF Name Description BODEN Brown-out detection enable 0 = Brown-out detection circuit off. 1 = Brown-out detection circuit on.
Page 89 MS51 IAPTRG – IAP Trigger Register SFR Address Reset Value IAPTRG A4H, Page 0, TA protected 0000 _0000 b IAPGO Name Description IAPGO IAP go IAP begins by setting this bit as logic 1. After this instruction, the CPU holds the Program Counter (PC) and the IAP hardware automation takes over to control the progress.
Page 90 MS51 IAPUEN – IAP Updating Enable Register SFR Address Reset Value IAPUEN A5H, Page 0, TA protected 0000 _0000 b CFUEN LDUEN APUEN Name Description CFUEN CONFIG bytes updated enable 0 = Inhibit erasing or programming CONFIG bytes by IAP. 1 = Allow erasing or programming CONFIG bytes by IAP.
Page 91 MS51 IAPAL – IAP Address Low Byte Register SFR Address Reset Value IAPAL A6H, Page 0 0000 _0000 b IAPA[7:0] Name Description IAPA[7:0] IAP address low byte IAPAL contains address IAPA[7:0] for IAP operations. Nov. 28, 2019 Page 91 of 491 Rev 1.00...
Page 92 MS51 IAPAH – IAP Address High Byte Register SFR Address Reset Value IAPAH A7H, Page 0 0000 _0000 b IAPA[15:8] Name Description IAPA[15:8] IAP address high byte IAPAH contains address IAPA[15:8] for IAP operations. Nov. 28, 2019 Page 92 of 491 Rev 1.00...
Page 93 MS51 IE – Interrupt Enable Register SFR Address Reset Value A8H, All pages, Bit addressable 0000 _0000 b EADC EBOD Name Description Enable all interrupt This bit globally enables/disables all interrupts that are individually enabled. 0 = All interrupt sources Disabled. 1 = Each interrupt Enabled depending on its individual mask setting.
Page 94 MS51 SADDR – Slave 0 Address Register SFR Address Reset Value SADDR A9H, Page 0 0000 _0000 b SADDR[7:0] Name Description SADDR[7:0] Slave 0 address This byte specifies the microcontroller’s own slave address for UATR0 multi-processor communication. Nov. 28, 2019 Page 94 of 491 Rev 1.00...
Page 95 MS51 WDCON – Watchdog Timer Control Register SFR Address Reset Value POR 0000_0111 b WDCON AAH, Page 0, TA protected WDT 0000_1UUU b Others 0000_UUUU b WDTR WDCLR WDTF WIDPD WDTRF WDPS[2:0] Name Description WDTR WDT run This bit is valid only when control bits in WDTEN[3:0] (CONFIG4[7:4]) are all 1. At this time, WDT works as a general purpose timer.
Page 96 MS51 BODCON1 – Brown-out Detection Control 1 Register SFR Address Reset Value POR 0000 0001 b BODCON1 ABH, Page 0, TA protected Others 0000 0UUU b LPBOD[1:0] BODFLT Name Description Reserved LPBOD[1:0] Low power BOD enable 00 = BOD normal mode. BOD circuit is always enabled. 01 = BOD low power mode 1 by turning on BOD circuit every 1.6 ms periodically.
Page 97 MS51 IAPFD – IAP Flash Data Register SFR Address Reset Value IAPFD AEH, Page 0 0000 _0000 b IAPFD[7:0] Name Description IAPFD[7:0] IAP Flash data This byte contains Flash data, which is read from or is going to be written to the Flash Memory. User should write data into IAPFD for program mode before triggering IAP processing and read data from IAPFD for read/verify mode after IAP processing is finished.
Page 98 MS51 IAPCN – IAP Control Register SFR Address Reset Value IAPCN AFH, Page 0 0011_0000 b IAPB[1:0] FOEN FCEN FCTRL[3:0] Name Description IAPB[1:0] IAP control This byte is used for IAP command. For details, see Table 6.3-1 IAP Modes and Command Codes.
Page 99 MS51 PnM1 – Port n Mode Select 1 Register SFR Address Reset Value P0M1 B1H, Page 0 1111_1111 b P1M1 B3H, Page 0 1111_1111 b P2M1 89H, Page 2 0011_1111 b P3M1 ACH, Page 0 1111_1111 b PnM1.7 PnM1.6 PnM1.5 PnM1.4 PnM1.3 PnM1.2...
Page 100 MS51 PnM2 – Port Mode Select 2 Register SFR Address Reset Value P0M2 B2H, Page 0 0000_0000 b P1M2 B4H, Page 0 0000_0000 b P2M2 8AH, Page 2 0000_0000 b P3M2 ADH, Page 0 0000_0000 b PnM2.7 PnM2.6 PnM2.5 PnM2.4 PnM2.3 PnM2.2 PnM2.1...
Page 101 MS51 PnS – Port n Schmitt Triggered Input Register SFR Address Reset Value B1H, Page 1 0000_0000 b B3H, Page 1 0000_0000 b 8CH, Page 2 0000_0000 b ACH, Page 1 0000_0000 b PnS.7 PnS.6 PnS.5 PnS.4 PnS.3 PnS.2 PnS.1 PnS.0 Name Description...
Page 102 MS51 TOE – Timer01 Output Enable Register SFR Address Reset Value B5H, Page 0 0000_0000 b T1OE T0OE Name Description T1OE Timer 1 output enable 0 = Timer 1 output Disabled. 1 = Timer 1 output Enabled from T1 pin. Note that Timer 1 output should be enabled only when operating in its “Timer”...
Page 103 MS51 IPH – Interrupt Priority High Register SFR Address Reset Value B7H, Page 0 0000_0000 b PADCH PBODH PT1H PX1H PT0H PX0H Name Description PADC ADC interrupt priority high bit PBOD Brown-out detection interrupt priority high bit Serial port 0 interrupt priority high bit PT1H Timer 1 interrupt priority high bit PX1H...
Page 104 MS51 PWMnINTC – PWM Interrupt Control Register SFR Address Reset Value PWM0INTC B7H, page 1 0000_0000 b 0000_0000 b B6H, page 2 PWM1INTC 0000_0000 b PWM2INTC C6H, page 2 0000_0000 b PWM3INTC D6H, page 2 INTTYP1 INTTYP0 INTSEL2 INTSEL1 INTSEL0 Name Description INTTYP[1:0]...
Page 105 MS51 IP – Interrupt Priority Register SFR Address Reset Value B8H, All pages, Bit addressable 0000_0000 b PADC PBOD Name Description PADC ADC interrupt priority low bit PBOD Brown-out detection interrupt priority low bit Serial port 0 interrupt priority low bit Timer 1 interrupt priority low bit External interrupt 1 priority low bit Timer 0 interrupt priority low bit...
Page 106 MS51 SADEN – Slave 0 Address Mask Register SFR Address Reset Value SADEN B9H, Page 0 0000_0000 b SADEN[7:0] Name Description SADEN[7:0] Slave 0 address mask This byte is a mask byte of UART0 that contains “don’t-care” bits (defined by zeros) to form the device’s “Given”...
Page 107 MS51 SADEN_1 – Slave 1 Address Mask Register SFR Address Reset Value SADEN_1 BAH, Page 0 0000_0000 b SADEN _ 1[7:0] Name Description SADEN _ 1[7:0] Slave 1 address mask This byte is a mask byte of UART1 that contains “don’t-care” bits (defined by zeros) to form the device’s “Given”...
Page 108 MS51 SADDR_1 – Slave 1 Address Register SFR Address Reset Value SADDR_1 BBH, Page 0 0000_0000 b SADDR _ 1[7:0] Name Description SADDR _ 1[7:0] Slave 1 address This byte specifies the microcontroller’s own slave address for UART1 multi-processor communication. Nov.
Page 109 MS51 I2DAT – I C Data Register SFR Address Reset Value I2DAT BCH, Page 0 0000_0000 b I2DAT[7:0] Name Description I2DAT[7:0] C data I2DAT contains a byte of the I C data to be transmitted or a byte, which has just received. Data in I2DAT remains as long as SI is logic 1.
Page 110 MS51 I2STAT – I C Status Register SFR Address Reset Value I2STAT BDH, Page 0 1111 1000 b I2STAT[7:3] Name Description I2STAT[7:3] C status code The MSB five bits of I2STAT contains the status code. There are 27 possible status codes. When I2STAT is F8H, no relevant state information is available and SI flag keeps 0.
Page 111 MS51 I2CLK – I C Clock Register SFR Address Reset Value I2CLK BEH, Page 0 0000_1001 b I2CLK[7:0] Name Description I2CLK[7:0] C clock setting In master mode: This register determines the clock rate of I C bus when the device is in a master mode. The clock rate follows the equation, ×...
Page 112 MS51 I2TOC – I C Time-out Counter Register SFR Address Reset Value I2TOC BFH, Page 0 0000_0000 b I2TOCEN I2TOF Name Description I2TOCEN C time-out counter enable 0 = I C time-out counter Disabled. 1 = I C time-out counter Enabled. C time-out counter clock divider 0 = The clock of I C time-out counter is F...
Page 113 MS51 I2CON – I C Control Register SFR Address Reset Value I2CON C0H, All pages, Bit addressable 0000_0000 b I2CEN I2CPX Name Description I2CEN C bus enable 0 = I C bus Disabled. 1 = I C bus Enabled. Before enabling the I C, I2C0_SCL and I2C0_SDA port latches should be set to logic 1.
Page 114 MS51 Name Description Acknowledge assert flag If the AA flag is set, an ACK (low level on I2C0_SDA) will be returned during the acknowledge clock pulse of the I2C0_SCL line while the I C device is a receiver or an own-address-matching slave. If the AA flag is cleared, a NACK (high level on I2C0_SDA) will be returned during the acknowledge clock pulse of the I2C0_SCL line while the I C device is a receiver or an own-address-matching...
Page 115 MS51 I2ADDR – I C Own Slave Address Register SFR Address Reset Value I2ADDR C1H, Page 0 0000_0000 b I2ADDR[7:1] Name Description I2ADDR[7:1] C device’s own slave address In master mode: These bits have no effect. In slave mode: These 7 bits define the slave address of this I C device by user.
Page 116 MS51 ADCRL – ADC Result Low Byte Register SFR Address Reset Value ADCRL C2H, Page 0 0000_0000 b ADCR[3:0] Name Description ADCR[3:0] ADC result low byte The least significant 4 bits of the ADC result stored in this register. Nov. 28, 2019 Page 116 of 491 Rev 1.00...
Page 117 MS51 ADCRH – ADC Result High Byte Register SFR Address Reset Value ADCRH C3H, Page 0 0000_0000 b ADCR[11:4] Name Description ADCR[11:4] ADC result high byte The most significant 8 bits of the ADC result stored in this register. Nov. 28, 2019 Page 117 of 491 Rev 1.00...
Page 118 MS51 T3CON – Timer 3 Control Register SFR Address Reset Value T3CON C4H, Page 0 0000_0000 b SMOD _ 1 SMOD0 _ 1 BRCK T3PS[2:0] Name Description SMOD _ 1 Serial port 1 double baud rate enable Setting this bit doubles the serial port baud rate when UART1 is in Mode 2. See Table 6.9-2 Serial Port UART1 Mode / baudrate Description for details.
Page 119 MS51 RL3 – Timer 3 Reload Low Byte Register SFR Address Reset Value C5H, Page 0 0000_0000 b RL3[7:0] Name Description RL3[7:0] Timer 3 reload low byte It holds the low byte of the reload value of Timer 3. Nov. 28, 2019 Page 119 of 491 Rev 1.00...
Page 120 MS51 RH3 – Timer 3 Reload High Byte Register SFR Address Reset Value C6H, Page 0 0000_0000 b RH3[7:0] Name Description RH3[7:0] Timer 3 reload high byte It holds the high byte of the reload value of Time 3. Nov. 28, 2019 Page 120 of 491 Rev 1.00...
Page 121 MS51 PIOCON1 – PWM or I/O Select Register SFR Address Reset Value PIOCON1 C6H, Page 1 0000_0000 b PIO17 PIO15 PIO04 PIO05 PIO14 Name Description PIO17 P1.7/PWM 3C0 pin function select 0 = P1.7/PWM3_CH0 pin functions as P1.7. 1 = P1.7/PWM3_CH0 pin functions as PWM0C5/PWM3_CH1 output. PIO15 P1.5/PWM pin function select 0 = P1.5/PWM pin functions as P1.5.
Page 122 MS51 PIOCON2 – PWM or I/O Select Register SFR Address Reset Value PIOCON2 B7H, Page 2 0000_0000 b PIO34 PIO33 PIO32 PIO31 PIO30 PIO23 PIO22 PIO21 Name Description PIO34 P3.4/PWM3_CH1 pin function select 0 = P3.4/PWM3_CH1 pin functions as P3.4. 1 = P3.4/PWM3_CH1 pin functions as PWM3_CH1 output.
Page 123 MS51 TA – Timed Access Register SFR Address Reset Value C7H, Page 0 0000_0000 b TA[7:0] Name Description TA[7:0] Timed access The timed access register controls the access to protected SFRs. To access protected bits, user should first write AAH to the TA and immediately followed by a write of 55H to TA. After these two steps, a writing permission window is opened for 4 clock cycles during this period that user may write to protected SFRs.
Page 124 MS51 T2CON – Timer 2 Control Register SFR Address Reset Value T2CON C8H, All pages, Bit addressable 0000_0000 b ̅̅̅̅̅̅ CM/RL2 Name Description Timer 2 overflow flag This bit is set when Timer 2 overflows or a compare match occurs. If the Timer 2 interrupt and the global interrupt are enable, setting this bit will make CPU execute Timer 2 interrupt service routine.
Page 125 MS51 T2MOD – Timer 2 Mode Register SFR Address Reset Value T2MOD C9H, Page 0 0000_0000 b LDEN T2DIV[2:0] CAPCR CMPCR LDTS[1:0] Name Description LDEN Enable auto-reload 0 = Reloading RCMP2H and RCMP2L to TH2 and TL2 Disabled. 1 = Reloading RCMP2H and RCMP2L to TH2 and TL2 Enabled. T2DIV[2:0] Timer 2 clock divider 000 = Timer 2 clock divider is 1/1.
Page 126 MS51 RCMP2L – Timer 2 Reload/Compare Low Byte Register SFR Address Reset Value RCMP2L CAH, Page 0 0000_0000 b RCMP2L[7:0] Name Description RCMP2L[7:0] Timer 2 reload/compare low byte This register stores the low byte of compare value when Timer 2 is configured in compare mode.
Page 127 MS51 RCMP2H – Timer 2 Reload/Compare High Byte Register SFR Address Reset Value RCMP2H CBH, Page 0 0000_0000 b RCMP2H[7:0] Name Description RCMP2H[7:0] Timer 2 reload/compare high byte This register stores the high byte of compare value when Timer 2 is configured in compare mode.
Page 128 MS51 TL2 – Timer 2 Low Byte Register SFR Address Reset Value CCH, Page 0 0000_0000 b TL2[7:0] Name Description TL2[7:0] Timer 2 low byte The TL2 register is the low byte of the 16-bit counting register of Timer 2. Nov.
Page 129 MS51 TH2 – Timer 2 High Byte Register SFR Address Reset Value CDH, Page 0 0000_0000 b TH2[7:0] Name Description TH2[7:0] Timer 2 high byte The TH2 register is the high byte of the 16-bit counting register of Timer 2. Nov.
Page 130 MS51 ADCMPL – ADC Compare Low Byte Register SFR Address Reset Value ADCMPL CEH, Page 0 0000_0000 b ADCMP[3:0] Name Description ADCMP[3:0] ADC compare low byte The least significant 4 bits of the ADC compare value stores in this register. Nov.
Page 131 MS51 ADCMPH – ADC Compare High Byte Register SFR Address Reset Value ADCMPH CFH, Page 0 0000_0000 b ADCMP[11:4] Name Description ADCMP[11:4] ADC compare high byte The most significant 8 bits of the ADC compare value stores in this register. Nov.
Page 132 MS51 PSW – Program Status Word Register SFR Address Reset Value D0H, All pages, Bit addressable 0000_0000 b Name Description Carry flag For a adding or subtracting operation, CY will be set when the previous operation resulted in a carry-out from or a borrow-in to the Most Significant bit, otherwise cleared. If the previous operation is MUL or DIV, CY is always 0.
Page 133: Table 6.1-3 Instructions That Affect Flag Settings
MS51 Name Description Parity flag Set to 1 to indicate an odd number of ones in the accumulator. Cleared for an even number of ones. It performs even parity check. Instruction Instruction CLR C ADDC CPL C SUBB ANL C, bit ANL C, /bit ORL C, bit DA A...
Page 134 MS51 PWMnPH – PWM Period High Byte, n = 0,1,2,3 Register SFR Address Reset Value PWM0PH D1H, Page 0 0000_0000 b PWM1PH A9H, Page 2 0000_0000 b PWM2PH B9H, Page 2 0000_0000 b PWM3PH C9H, Page 2 0000_0000 b PWM0P[15:8] Name Description PWM0P[15:8]...
Page 135 MS51 PNP – PWM Negative Polarity Register SFR Address Reset Value D6H, Page 0 0000_0000 b PNP5 PNP4 PNP3 PNP2 PNP1 PNP0 Name Description PNPn PWMn negative polarity output enable 0 = PWMn signal outputs directly on PWMn pin. 1 = PWMn signal outputs inversely on PWMn pin. Nov.
Page 136 MS51 PWM0FBD – PWM Fault Brake Data Register SFR Address Reset Value PWM0FBD D7H, Page 0 0000_0000 b FBINLS FBD5 FBD4 FBD3 FBD2 FBD1 FBD0 Name Description Fault Brake flag This flag is set when FBINEN is set as 1 and FB pin detects an edge, which matches FBINLS (PWM0FBD.6) selection.
Page 137 MS51 PWMnCON0 – PWMn Control 0, n = 1,2,3 Register SFR Address Reset Value PWM1CON0 B4H, Page 2 0000_0000 b PWM2CON0 C4H, Page 2 0000_0000 b PWM3CON0 D4H, Page 2 0000_0000 b PWMRUN LOAD PWMF CLRPWM Name Description PWMRUN PWM run enable 0 = PWM stays in idle.
Page 138 MS51 PWM0CON0 – PWM0 Control 0 (Bit-addressable) Register SFR Address Reset Value PWM0CON0 D8H, Page0 0000_0000 b PWM0RUN LOAD PWMF CLRPWM PWM3RUN PWM2RUN PWM1RUN P33FBINEN Name Description PWM0RUN PWM0 run enable 0 = PWM0 stays in idle. 1 = PWM0 starts running. Note: This bit is only for PWM0CON0.
Page 139 MS51 Name Description PWM2RUN PWM2 run enable 0 = PWM2 stays in idle. 1 = PWM2 starts running. Note: This bit is only for PWM0CON0. PWM1RUN PWM1 run enable 0 = PWM1 stays in idle. 1 = PWM1 starts running. Note: This bit is only for PWM0CON0.
Page 140 MS51 PWMnPL – PWM Period Low Byte, n = 0,1,2,3 Register SFR Address Reset Value PWM0PL D9H, Page 0 0000_0000 b PWM1PL B1H, Page 2 0000_0000 b PWM2PL C1H, Page 2 0000_0000 b PWM3PL D1H, Page 2 0000_0000 b PWMnP[7:0] Name Description PWMnP[7:0]...
Page 141 MS51 PWMnCxH – PWMn Channel x Duty High Byte, n = 0,1,2,3; x = 0,1,2,3,4,5 Register SFR Address Description Reset Value PWM0 Channel 0 Duty High Byte PWM0C0H D2H, Page 0 0000_0000 b PWM0 Channel 1 Duty High Byte PWM0C1H D3H, Page 0 0000_0000 b PWM0 Channel 2 Duty High Byte...
Page 142 MS51 PWMnCxL – PWMn Channel x Duty Low Byte, n = 0,1,2,3; x = 0,1,2,3,4,5 Register SFR Address Description Reset Value PWM0 Channel 0 Duty Low Byte PWM0C0L DAH, Page 0 0000_0000 b PWM0 Channel 1 Duty Low Byte PWM0C1L DBH, Page 0 0000_0000 b PWM0 Channel 2 Duty Low Byte...
Page 143 MS51 PIOCON0 – PWM or I/O Select Register SFR Address Reset Value PIOCON0 DEH, Page 0 0000_0000 b PIO03 PIO01 PIO00 PIO10 PIO11 PIO12 Name Description PIO03 P0.3/PWM pin function select 0 = P0.3/PWM pin functions as P0.3. 1 = P0.3/PWM pin functions as PWM0C5/PWM3_CH1 output. (PWM3_CH1P=11b, select PWM3_CH1;...
Page 144 MS51 PWMnCON1 – PWM Control 1 Register SFR Address Reset Value PWM0CON1 DFH, Page 0 0000_0000 b B5H, page 2 0000_0000 b PWM1CON1 0000_0000 b PWM2CON1 C5H, page 2 0000_0000 b D5H, page 2 PWM3CON1 PWMMOD[1:0] PWMTYP FBINEN PWMDIV[2:0] Name Description PWMMOD[1:0] PWM mode select...
Page 145 MS51 Name Description PWMDIV[2:0] PWM clock divider This field decides the pre-scale of PWM clock source. 000 = 1/1. 001 = 1/2 010 = 1/4. 011 = 1/8. 100 = 1/16. 101 = 1/32. 110 = 1/64. 111 = 1/128. Nov.
Page 146 MS51 A or ACC – Accumulator Register SFR Address Reset Value E0H, All pages, Bit addressable 0000_0000 b ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 Name Description ACC[7:0] Accumulator The A or ACC register is the standard 80C51 accumulator for arithmetic operation. Nov.
Page 147 MS51 ADCCON1 – ADC Control 1 Register SFR Address Reset Value ADCCON1 E1H, Page 0 0000_0000 b OCEN STADCPX ADCDIV[1:0] ETGTYP[1:0] ADCEX ADCEN Name Description OCEN ADC Offset Calibration Enable register This field is used to enable offset calibration function. 0: ADC Offset Calibration is enabled, auto-calibration by ADC hardware.
Page 148 MS51 ADCCON2 – ADC Control 2 Register SFR Address Reset Value ADCCON2 E2H, Page 0 0000_0000 b ADFBEN ADCMPOP ADCMPEN ADCMPO ADCAQT1[2:0] ADCDLY.8 Name Description ADFBEN ADC compare result asserting Fault Brake enable 0 = ADC asserting Fault Brake Disabled. 1 = ADC asserting Fault Brake Enabled.
Page 149 MS51 ADCCON3 – ADC Control 3 Register SFR Address Reset Value ADCCON3 86H, Page 2 0000_0000 b CONT ADCAQT2[2:0] SLOW Name Description Reserved ADC Half Done Interrupt Enable 0 = ADC interrupt is not set while half of A/D conversions are complete in continue mode 1 = ADC interrupt is set while half of A/D conversions are complete in continue mode CONT ADC Continue Sampling select...
Page 150 MS51 ADCDLY – ADC Trigger Delay Counter Register SFR Address Reset Value ADCDLY E3H, Page 0 0000_0000 b ADCDLY[7:0] Name Description ADCDLY[7:0] ADC external trigger delay counter low byte This 8-bit field combined with ADCCON2.0 forms a 9-bit counter. This counter inserts a delay after detecting the external trigger.
Page 151 MS51 CnL – Capture Low Byte, n = 0,1,2 Register SFR Address Reset Value E4H, Page 0 0000_0000 b E6H, Page 0 0000_0000 b EDH, Page 0 0000_0000 b CnL[7:0] Name Description CnL[7:0] Input capture n result low byte The CnL register is the low byte of the 16-bit result captured by input capture n. Nov.
Page 152 MS51 CnH – Capture n High Byte, n = 1,2,3 Register SFR Address Reset Value E5H, Page 0 0000_0000 b E7H, Page 0 0000_0000 b EEH, Page 0 0000_0000 b CnH[7:0] Name Description CnH[7:0] Input capture n result high byte The CnH register is the high byte of the 16-bit result captured by input capture n.
Page 153 MS51 ADCCON0 – ADC Control 0 (Bit-addressable) Register SFR Address Reset Value ADCCON0 E8H, all page 0000_0000b ADCF ADCS ETGSEL1 ETGSEL0 ADCHS3 ADCHS2 ADCHS1 ADCHS0 Name Description ADCF ADC flag This flag is set when an A/D conversion is completed. The ADC result can be read. While this flag is 1, ADC cannot start a new converting.
Page 154 MS51 Name Description ADCHS[3:0] A/D converting channel select This filed selects the activating analog input source of ADC. If ADCEN is 0, all inputs are disconnected. 0000 = ADC_CH0 0001 = ADC_CH1. 0010 = ADC_CH2. 0011 = ADC_CH3. 0100 = ADC_CH4. 0101 = ADC_CH5.
Page 155 MS51 PICON – Pin Interrupt Control Register SFR Address Reset Value PICON E9H, PAGE 0, 0011 _0100 b PIT7 PIT6 PIT5 PIT4 PIT3 PIT2 PIT1 PIT0 Name Description PIT7 Pin interrupt channel 7 type select This bit selects which type that pin interrupt channel 7 is triggered. 0 = Level triggered.
Page 156 MS51 Name Description PIT0 Pin interrupt channel 0 type select This bit selects which type that pin interrupt channel 0 is triggered. 0 = Level triggered. 1 = Edge triggered. Nov. 28, 2019 Page 156 of 491 Rev 1.00...
Page 157 MS51 PINEN – Pin Interrupt Negative Polarity Enable. Register SFR Address Reset Value PINEN EAH, Page 0 0000_0000 b PINEN7 PINEN6 PINEN5 PINEN4 PINEN3 PINEN2 PINEN1 PINEN0 Name Description PINENn Pin interrupt channel n negative polarity enable This bit enables low-level/falling edge triggering pin interrupt channel n. The level or edge triggered selection depends on each control bit PITn in PICON.
Page 158 MS51 PIPEN – Pin Interrupt Positive Polarity Enable. Register SFR Address Reset Value PIPEN EBH, Page 0 0000_0000 b PIPEN7 PIPEN6 PIPEN5 PIPEN4 PIPEN3 PIPEN2 PIPEN1 PIPEN0 Name Description PIPENn Pin interrupt channel n positive polarity enable This bit enables high-level/rising edge triggering pin interrupt channel n. The level or edge triggered selection depends on each control bit PITn in PICON.
Page 159 MS51 PIF – Pin Interrupt Flags Register SFR Address Reset Value ECH, Page 0 0000_0000 b PIF7 PIF6 PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 R (level) R (level) R (level) R (level) R (level) R (level) R (level) R (level) R/W (edge) R/W (edge) R/W (edge)
Page 160 MS51 EIP – Extensive Interrupt Priority Register SFR Address Reset Value EFH, Page 0 0000_0000 b PSPI PWDT PPWM PCAP Name Description Timer 2 interrupt priority low bit PSPI SPI interrupt priority low bit Fault Brake interrupt priority low bit PWDT WDT interrupt priority low bit PPWM...
Page 161 MS51 LDOTRIM – LDO Trim Register SFR Address Reset Value LDOTRIM EFH, Page 1 0000_0000 b uLDOTRIM[2:0] LDOTRIM[4:0] Name Description Uldotrim[2:0] Suspend LDO output voltage trim This field is used to adjust the output voltage of suspend LDO. 000 = Maximum voltage. •...
Page 162 MS51 B – B Register Register SFR Address Reset Value F0H, All pages, Bit addressable 0000_0000 b Name Description B[7:0] B register The B register is the other accumulator of the standard 80C51 .It is used mainly for MUL and DIV instructions.
Page 163 MS51 CAPCON3 – Input Capture Control 3 Register SFR Address Reset Value CAPCON3 F1H, Page 0 0000_0000 b CAP13 CAP12 CAP11 CAP10 CAP03 CAP02 CAP01 CAP00 Name Description [7:4] CAP1[3:0] Input capture channel 0 input pin select 0000 = P1.2/IC0 0001 = P1.1/IC1 0010 = P1.0/IC2 0011 = P0.0/IC3...
Page 164 MS51 CAPCON4 – Input Capture Control 4 Register SFR Address Reset Value CAPCON4 F2H, Page 0 0000_0000 b CAP23 CAP22 CAP21 CAP20 Name Description [3:0] CAP2[3:0] Input capture channel 0 input pin select 0000 = P1.2/IC0 0001 = P1.1/IC1 0010 = P1.0/IC2 0011 = P0.0/IC3 0100 = P0.4/IC3 0101 = P0.1/IC4...
Page 165 MS51 SPCR – Serial Peripheral Control Register Register SFR Address Reset Value SPCR F3H, Page 0 0000_0000 b SSOE SPIEN LSBFE MSTR CPOL CPHA SPR1 SPR0 Name Description SSOE Slave select output enable ̅̅̅̅ pin This bit is used in combination with the DISMODF (SPSR.3) bit to determine the feature of SS as shown in ̅̅̅̅...
Page 166 MS51 Name Description SPR[1:0] SPI clock rate select These two bits select four grades of SPI clock divider. The clock rates below are illustrated under = 16 MHz condition. Fsys = 16 MHz SPR1 SPR0 Divider SPI clock rate 8M bit/s 4M bit/s WM bit/s 1 M bit/s...
Page 167 MS51 SPCR2 – Serial Peripheral Control Register 2 Register SFR Address Reset Value SPCR2 F3H, Page 1 0000_0000 b SPIS1 SPIS0 Name Description Reserved SPIS[1:0] SPI Interval time selection between adjacent bytes SPIS[1:0] and CPHA select eight grades of SPI interval time selection between adjacent bytes. As below table: CPHA SPIS1...
Page 168 MS51 SPSR – Serial Peripheral Status Register Register SFR Address Reset Value SPSR F4H, Page 0 0000_0000 b SPIF WCOL SPIOVF MODF DISMODF TXBUF Name Description SPIF SPI complete flag This bit is set to logic 1 via hardware while an SPI data transfer is complete or an receiving data has been moved into the SPI read buffer.
Page 169 MS51 SPDR – Serial Peripheral Data Register Register SFR Address Reset Value SPDR F5H, Page 0 0000_0000 b SPDR[7:0] Name Description SPDR[7:0] Serial peripheral data This byte is used for transmitting or receiving data on SPI bus. A write of this byte is a write to the shift register.
Page 170 MS51 AINDIDS0 – ADC Channel Digital Input Disconnect Register SFR Address Reset Value AINDIDS0 F6H, Page 0 0000_0000 b P11DIDS P03DIDS P04DIDS P05DIDS P06DIDS P07DIDS P30DIDS P17DIDS Name Description PnnDIDS ADC Channel digital input disable 0 = ADC channel n digital input Enabled. 1 = ADC channel n digital input Disabled.
Page 171 MS51 AINDIDS1 – ADC Channel Digital Input Disconnect Register SFR Address Reset Value AINDIDS1 99H, Page 2 0000_0000 b P25DIDS P14DIDS P13DIDS P24DIDS P23DIDS P22DIDS P21DIDS Name Description PnnDIDS ADC Channel digital input disable 0 = ADC channel n digital input Enabled. 1 = ADC channel n digital input Disabled.
Page 172 MS51 EIPH – Extensive Interrupt Priority High Register SFR Address Reset Value EIPH F7H, Page 0 0000_0000 b PT2H PSPIH PFBH PWDTH PPWMH PCAPH PPIH PI2CH Name Description PT2H Timer 2 interrupt priority high bit PSPIH SPI interrupt priority high bit PFBH Fault Brake interrupt priority high bit PWDTH...
Page 173 MS51 SCON _ 1 – Serial Port 1 Control Register SFR Address Reset Value SCON _ 1 F8H, All pages, Bit addressable 0000_0000 b SM0 _ 1/FE _ 1 SM1 _ 1 SM2 _ 1 REN _ 1 TB8 _ 1 RB8 _ 1 TI _ 1 RI _ 1...
Page 174 MS51 Name Description TI _ 1 Transmission interrupt flag This flag is set by hardware when a data frame has been transmitted by the serial port 1 after the 8 bit in Mode 0 or the last data bit in other modes. When the serial port 1 interrupt is enabled, setting this bit causes the CPU to execute the serial port 1 interrupt service routine.
Page 175 MS51 PWM0DTEN – PWM Dead-time Enable Register SFR Address Reset Value PWM0DTEN F9H, Page 0, TA protected 0000_0000 b PWM0DTCNT. PDT45EN PDT23EN PDT01EN Name Description PWM0DTCNT.8 PWM dead-time counter bit 8 See PWM0DTCNT register. PDT45EN PWM0_CH4/ PWM0_CH5 pair dead-time insertion enable This bit is valid only when PWM4/5 is under complementary mode.
Page 176 MS51 PWM0DTCNT – PWM Dead-time Counter Register SFR Address Reset Value PWM0DTCNT FAH, Page 0, TA protected 0000_0000 b PWM0DTCNT[7:0] Name Description PWM0DTCNT[7:0] PWM dead-time counter low byte This 8-bit field combined with PWM0DTEN.4 forms a 9-bit PWM dead-time counter PWM0DTCNT.
Page 177 MS51 PWMxMEN – PWMnCx Mask Enable, n=0,1,2,3;x=0,1,2,3,4,5 Register SFR Address Description Reset Value PWM0Cx Mask Enable PWM0MEN FBH, Page 0 0000_0000 b ADH, Page 2 PWM1Cx Mask Enable PWM1MEN 0000_0000 b BDH, Page 2 PWM2Cx Mask Enable PWM2MEN 0000_0000 b CDH, Page 2 PWM3Cx Mask Enable PWM3MEN...
Page 178 MS51 PWMnMD – PWMnCx Mask Data Register SFR Address Description Reset Value PWM0Cx Mask Data PWM0MD FCH, Page 0 0000_0000 b ACH, Page 2 PWM1Cx Mask Data PWM1MD 0000_0000 b BCH, Page 2 PWM2Cx Mask Data PWM2MD 0000_0000 b CCH, Page 2 PWM3Cx Mask Data PWM3MD 0000_0000 b...
Page 179 MS51 PORDIS – POR Disable Register SFR Address Reset Value PORDIS FDH, Page 0, TA protected 0000_0000 b PORDIS[7:0] Name Description PORDIS[7:0] POR disable To first writing 5AH to the PORDIS and immediately followed by a writing of A5H will disable POR.
Page 180 MS51 EIP1 – Extensive Interrupt Priority 1 Register SFR Address Reset Value EIP1 FEH, Page 0 0000_0000 b PS _ 1 PPWM3 PPWM2 PPWM1 PWKT Name Description PPWM3 PWM3 interrupt priority low bit PPWM2 PWM2 interrupt priority low bit PPWM1 PWM1 interrupt priority low bit PWKT WKT interrupt priority low bit...
Page 181 MS51 EIPH1 – Extensive Interrupt Priority High 1 Register SFR Address Reset Value EIPH1 FFH, Page 0 0000_0000 b PSH _ 1 PPWM3H PPWM2H PPWM1H PWKTH PT3H Name Description PPWM3H PWM3 interrupt priority high bit PPWM2H PWM2 interrupt priority high bit PPWM1H PWM1 interrupt priority high bit PWKTH...
Page 182 MS51 LVRDIS – LVR disable Register SFR Address Reset Value EIPH1 FFH, Page 1, TA protected 0000_0000 b LVRDIS[7:0] Name Description LVRDIS[7:0] LVR disable To first writing 5AH to the LVRDIS and immediately followed by a writing of A5H will disable LVR. Nov.
Page 183 MS51 EIP2 – Extensive Interrupt Priority 2 Register SFR Address Reset Value EIP2 CEH, Page 2 0000_0000 b PUART4 PUART3 PUART2 Name Description PUART4 UART4 interrupt priority low bit PUART3 UART3 interrupt priority low bit PUART2 UART2 interrupt priority low bit Note: EIP2 is used in combination with the EIPH2 to determine the priority of each interrupt source.
Page 184 MS51 EIPH2 – Extensive Interrupt Priority High 2 Register SFR Address Reset Value EIPH2 CFH, Page 2 0000_0000 b PSC2H PSC1H PSC0H Name Description PSC2H SC2 / UART4 interrupt priority high bit PSC1H SC1 / UART3 interrupt priority high bit PSC0H SC0 / UART2 interrupt priority high bit Note: EIPH2 is used in combination with the EIP2 to determine the priority of each interrupt source.
Page 185 MS51 PIPSn – Pin Interrupt Control Register SFR Address Reset Value PIPS7 F7H, page 2 0000_0000 b 0000_0000 b FFH, page 2 PIPS6 PIPS5 FEH, page 2 0000_0000 b 0000_0000 b FDH, page 2 PIPS4 PIPS3 FCH, page 2 0000_0000 b 0000_0000 b PIPS2 FBH, page 2...
Page 186 MS51 SCnCR0 – SC Control Register 0 Register SFR Address Reset Value SC0CR0 F1H, Page 2 0000_0000 b SC1CR0 F3H, Page 2 0000_0000 b SC2CR0 F5H, Page 2 0000_0000 b RXBGTEN CONSEL AUTOCEN TXOFF RXOFF SCEN Name Description Stop Bit Length This field indicates the length of stop bit.
Page 187 MS51 Name Description AUTOCEN Auto Convention Enable Bit 0 = Auto-convention Disabled. 1 = Auto-convention Enabled. When hardware receives TS in answer to reset state and the TS is direct convention, CONSEL(SCnCR0[4]) will be set to 0 automatically, otherwise if the TS is inverse convention, and CONSEL (SCnCR0[4]) will be set to 1.
Page 188 MS51 SCnCR1 – SC Control Register Register SFR Address Reset Value SC0CR1 F2H, Page 2 0000_0000 b SC1CR1 F4H, Page 2 0000_0000 b SC2CR1 F6H, Page 2 0000_0000 b PBOFF TXDMAEN RXDMAEN CLKKEEP UARTEN Name Description Odd Parity Enable Bit 0 = Even number of logic 1’s are transmitted or check the data word and parity bits in receiving mode.
Page 189 MS51 Name Description UARTEN UART Mode Enable Bit 0 = ISO 7816-3 mode. 1 = UART mode. Note 1:When operating in UART mode, user must set CONSEL (SCnCR0[4]) = 0 and AUTOCEN(SCnCR0[3]) = 0. Note 2:When operating in ISO 7816-3 mode, user must set UARTEN(SCnCR1 [0]) = 0. Note 3:When UART is enabled, hardware will generate a reset to reset FIFO and internal state machine.
Page 190 MS51 SCnDR – SC Data Register Register SFR Address Reset Value SC0DR D9H, Page 2 0000_0000 b SC1DR E1H, Page 2 0000_0000 b SC2DR E9H, Page 2 0000_0000 b SCnDR[7:0] Name Description SCnDR[7:0] SC / UART buffer data This byte is used for transmitting or receiving data on SC / UART bus. A write of this byte is a write to the shift register.
Page 191 MS51 SCnEGT – SC Extra Guard Time Register Register SFR Address Reset Value SC0EGT DAH, Page 2 0000_0000 b SC1EGT E2H, Page 2 0000_0000 b SC2EGT EAH, Page 2 0000_0000 b SCnEGT[7:0] Name Description SCnEGT[7:0] SC Extra Guard Time This field indicates the extra guard timer value. Note: The counter is ETU base .
Page 192 MS51 SCnETURD0 – SCn ETU Rate Divider Register Register SFR Address Reset Value SC0ETURD0 DBH, Page 2 0111_0011 b SC1ETURD0 E3H, Page 2 0111_0011 b SC2ETURD0 EBH, Page 2 0111_0011 b ETURDIV[7:0] Name Description ETURDIV[7:0] LSB bits of ETU Rate Divider The field indicates the LSB of clock rate divider.
Page 193 MS51 SCnETURD1 –SC ETU Rate Divider Register Register SFR Address Reset Value SC0ETURD1 DCH, Page 2 0011_0001 b SC1ETURD1 E4H, Page 2 0011_0001 b SC2ETURD1 ECH, Page 2 0011_0001 b SCDIV[2:0] ETURDIV[11:8] Name Description Reserved SCDIV SC clock divider [2:0] 000 = F is F 001 = F...
Page 194 MS51 ScnIE – SC Interrupt Enable Control Register Register SFR Address Reset Value SC0IE DDH, Page 2 0000_0000 b SC1IE E5H, Page 2 0000_0000 b SC2IE EDH, Page 2 0000_0000 b ACERRIEN BGTIEN TERRIEN TBEIEN RDAIEN Name Description Reserved ACERRIEN Auto Convention Error Interrupt Enable Bit This field is used to enable auto-convention error interrupt.
Page 195 MS51 ScnIS – SC Interrupt Status Register Register SFR Address Reset Value SC0IS DEH, Page 2 0000_0010 b SC1IS E6H, Page 2 0000_0010 b SC2IS EEH, Page 2 0000_0010 b ACERRIF BGTIF TERRIF TBEIF RDAIF Name Description Reserved ACERRIF Auto Convention Error Interrupt Status Flag (Read Only) This field indicates auto convention sequence error.
Page 196 MS51 SCnTSR – SC Transfer Status Register Register SFR Address Reset Value SC0TSR DFH, Page 2 0000_1010 b SC1TSR E7H, Page 2 0000_1010 b SC2TSR EFH, Page 2 0000_1010 b TXEMPTY TXOV RXEMPTY RXOV Name Description Transmit /Receive in Active Status Flag (Read Only) 0 = This bit is cleared automatically when TX/RX transfer is finished 1 = This bit is set by hardware when TX/RX transfer is in active.
Page 197 MS51 Name Description RXOV RX Overflow Error Status Flag (Read Only) This bit is set when RX buffer overflow. Note: This bit is read only, but it can be cleared by writing 0 to it. Nov. 28, 2019 Page 197 of 491 Rev 1.00...
Page 198 MS51 XTLCON – XLT Clock Control (TA Protected) Register SFR Address Reset Value D7H, Page 2 0111_0111 b XTLCON HXSG Name Description Reserved HXSG HXT gain value select 000 = L0 mode (smallest value) 001 = L1 mode 010 = L2 mode 011 = L3 mode 100 = L4 mode 101 = L5 mode...
Page 199 MS51 PnDW – Port n Pull-down Resister Control Register SFR Address Reset Value 9AH, page 2 P0DW 0000_0000 b 9BH, page 2 P1DW 0000_0000 b 9CH, page 2 P2DW 0000_0000 b 9DH, page 2 P3DW 0000_0000 b PnDW.7 PnDW.6 PnDW.5 PnDW.4 PnDW.3 PnDW.2...
Page 200 MS51 PnUP – Port n Pull-up Resister Control Register SFR Address Reset Value P0UP 92H, page 2 0000_0000 b P1UP 93H, page 2 0000_0000 b P2UP 94H, page 2 0000_0000 b P3UP 95H, page 2 0000_0000 b PnUP.7 PnUP.6 PnUP.5 PnUP.4 PnUP.3 PnUP.2...
Page 201: System Manager
MS51 System Manager 6.2.1 Clock System 6.2.1.1 Overview The MS51 has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. The MS51 provides three options of the system clock sources including internal oscillator, or external clock from pin via software.
Page 202 MS51 HIRC speed slower about 40 kHz. Following shows two Byte combine the 9-bit internal RC trim value. And HIRC 24 MHz define bit. Nov. 28, 2019 Page 202 of 491 Rev 1.00...
Page 203 MS51 RCTRIM0 –High Speed Internal Oscillator 16 MHz Trim 0 Register SFR Address Reset Value 0000_0000b RCTRIM0 84H, Page0, TA protected HIRCTRIM[8:1] Nov. 28, 2019 Page 203 of 491 Rev 1.00...
Page 204 MS51 RCTRIM1 –High Speed Internal Oscillator 16 MHz Trim 1 Register SFR Address Reset Value 0000_0000b RCTRIM1 85H, All pages, TA protected HIRC24 HIRCTRIM.0 Note: since defaut RCTRIM0 and RCTRIM1 value is base on 16 MHz, if base on this value then modify HIRC24(RCTIM1.4) to enable 24 MHz HIRC mode, the real HIRC deviation will more than 1%.
Page 205 MS51 XTLCON – XLT Clock Control (TA Protected) Register SFR Address Reset Value D7H, Page 2 0111_0111 b XTLCON HXSG Name Description Reserved HXSG HXT gain value select 000 = L0 mode (smallest value) 001 = L1 mode 010 = L2 mode 011 = L3 mode 100 = L4 mode 101 = L5 mode...
Page 206 MS51 3. Once user switches the system clock source to an enabled but still instable one, the hardware will wait for stabilization of the target clock source and then switch to it in the background. During this waiting period, the device will continue executing the program with the original clock source and CKSWTF will be set as 1.
Page 207 MS51 CKSWT – Clock Switch Register SFR Address Reset Value CKSWT 96H, PAGE 0, TA protected 0011_0000 b HXTST ECKP00ST HIRCST LIRCST ECKP30ST OSC[1:0] Name Description HXTST High-speed external crystal 4 MHz to 24 MHz status 0 = High-speed external crystal is not stable or disabled. 1 = High-speed external crystal is enabled and stable.
Page 208 MS51 CKEN – Clock Enable Register SFR Address Reset Value CKSWT 97H, PAGE 0, TA protected 0011_0000 b EXTEN[1:0] HIRCEN LIRCEN CKSWTF Name Description EXTEN[1:0] External clock source enable 11 = External clock input via OSCIN (P30) Enabled 10 = External clock input via HXTIN (P00) Enabled 01 = External crystal 4~24 MHz Enabled 00 = external clock input is disable.
Page 209 MS51 CKDIV – Clock Divider Register SFR Address Reset Value CKDIV 95H, Page0 0000_0000b CKDIV[7:0] Name Description CKDIV[7:0] Clock divider The system clock frequency FSYS follows the equation below according to CKDIV value. , while CKDIV = 00H, and × CKDIV , while CKDIV = 01H to FFH.
Page 210 MS51 CKCON – Clock Control Register SFR Address Reset Value CKCON 8EH, Page0 0000_0000b PWMCKS CLOEN Name Description CLOEN System clock output enable 0 = System clock output Disabled. 1 = System clock output Enabled from CLO pin). Note: CLO pin decide by AUXR5.7. Nov.
Page 211: Power Management
MS51 6.2.2 Power Management 6.2.2.1 Overview The MS51 has several features that help user to control the power consumption of the device. The power reduced feature has two option modes: Idle mode and Power-down mode, to save the power consumption. For a stable current consumption, the state and mode of each pin should be taken care of.
Page 212 MS51 exit. It will automatically clear the IDL bit, terminate Idle mode, and the interrupt service routine (ISR) will be executed. After using the RETI instruction to jump out of the ISR, execution of the program will be the one following the instruction, which put the CPU into Idle mode. The second way to terminate Idle mode is with any reset other than software reset.
Page 213: Power Monitoring
MS51 6.2.3 Power Monitoring 6.2.3.1 Overview To prevent incorrect execution during power up and power drop, The MS51 provide three power monitor functions, power-on detection and brown-out detection. 6.2.3.2 Power-On Detection The power-on detection function is designed for detecting power up after power voltage reaches to a level where system can work.
Page 214: Figure 6.2-2 Brown-Out Detection Block Diagram
MS51 functionality with limited detection response. By setting LPBOD[1:0] (BODCON1[2:1]), the BOD circuit can be periodically enabled to sense the power voltage nominally every 1.6 ms, 6.4 ms, or 25.6 ms. It saves much power but also provides low-speed power voltage sensing. Note that the hysteresis feature will disappear in low power BOD mode.
Page 215: Table 6.2-1 Bof Reset Value
MS51 CONFIG2 CBODEN CBOV[2:0] BOIAP CBORST Factory default value: 1111 1111b Name Description CBODEN CONFIG brown-out detect enable 1 = Brown-out detection circuit on. 0 = Brown-out detection circuit off. CBOV[1:0] CONFIG brown-out voltage select 11 = V is 2.2V. 10 = V is 2.7V.
Page 216 MS51 BODCON0 – Brown-out Detection Control 0 Register SFR Address Reset Value POR,CCCC XC0X b BODCON0 A3H, Page 0, TA protected BOD, UUUU XU1X b Others,UUUU XUUX b BODEN BOV[2:0] BORST BORF Name Description BODEN Brown-out detection enable 0 = Brown-out detection circuit off. 1 = Brown-out detection circuit on.
Page 217 MS51 BODCON1 – Brown-out Detection Control 1 Register SFR Address Reset Value POR 0000 0001 b BODCON1 ABH, Page 0, TA protected Others 0000 0UUU b LPBOD[1:0] BODFLT Name Description Reserved LPBOD[1:0] Low power BOD enable 00 = BOD normal mode. BOD circuit is always enabled. 01 = BOD low power mode 1 by turning on BOD circuit every 1.6 ms periodically.
Page 218: Table 6.2-2 Minimum Brown-Out Detect Pulse Width
MS51 BODFLT Minimum Brown-Out Detect Pulse BOD Operation Mode System Clock Source (BODCON1.1) Width Normal mode Any clock source Typ. 1μs (LPBOD[1:0] = [0,0]) Low power mode 1 Any clock source 16 (1/FLIRC) (LPBOD[1:0] = [0,1]) Low power mode 2 Any clock source 64 (1/FLIRC) (LPBOD[1:0] = [1,0])
Page 219: Reset
MS51 6.2.4 Reset 6.2.4.1 Overview The MS51 has several options to place device in reset condition. It also offers the software flags to indicate the source, which causes a reset. In general, most SFR go to their Reset value irrespective of the reset condition, but there are several reset source indicating flags whose state depends on the source of reset.
Page 220 MS51 BODCON0 – Brown-out Detection Control 0 Register SFR Address Reset Value POR,CCCC XC0X b BODCON0 A3H, Page 0, TA protected BOD, UUUU XU1X b Others,UUUU XUUX b BODEN BOV[2:0] BORST BORF Name Description BORF Brown-out reset flag When the MCU is reset by brown-out event, this bit will be set via hardware. This flag is recommended to be cleared via software.
Page 221 MS51 AUXR1 – Auxiliary Register 1 Register SFR Address Reset Value POR: 0000 0000b, Software reset: 1U00 0000b, AUXR1 A2H , Page 0 nRESET pin: U100 0000b, Others: UUU0 0000b SWRF RSTPINF HardF SLOW UART0PX Name Description RSTPINF External reset flag When the MCU is reset by the external reset, this bit will be set via hardware.
Page 222 MS51 Name Description WDTRF WDT reset flag When the CPU is reset by WDT time-out event, this bit will be set via hardware. This flag is recommended to be cleared via software after reset. 6.2.4.6 Software Reset The MS51 provides a software reset, which allows the software to reset the whole system just similar to an external reset, initializing the MCU as it reset state.
Page 223 MS51 CHPCON – Chip Control Register SFR Address Reset Value Software 0000_00U0 b CHPCON 9FH, All page, TA protected Others 0000_00C0 b SWRST IAPFF IAPEN Name Description SWRST Software reset To set this bit as logic 1 will cause a software reset. It will automatically be cleared via hardware after reset is finished.
Page 224: Figure 6.2-3 Boot Selecting Diagram
MS51 AUXR1 – Auxiliary Register 1 Register SFR Address Reset Value POR: 0000 0000b, Software reset: 1U00 0000b, AUXR1 A2H , Page 0 nRESET pin: U100 0000b, Others: UUU0 0000b SWRF RSTPINF HardF SLOW UART0PX Name Description SWRF Software reset flag When the MCU is reset via software reset, this bit will be set via hardware.
Page 225 MS51 CONFIG0 OCDPWM OCDEN LOCK Factory default value: 1111 1111b Name Description CONFIG boot select This bit defines from which block that MCU re-boots after resets except software reset. 1 = MCU will re-boot from APROM after resets except software reset. 0 = MCU will re-boot from LDROM after resets except software reset.
Page 226 MS51 CHPCON – Chip Control Register SFR Address Reset Value Software 0000_00U0 b CHPCON 9FH, All page, TA protected Others 0000_00C0 b SWRST IAPFF IAPEN Name Description Boot select This bit defines from which block that MCU re-boots after all resets. 0 = MCU will re-boot from APROM after all resets.
Page 227: Timed Access Protection (Ta)
MS51 6.2.5 Timed Access Protection (TA) 6.2.5.1 Overview The MS51 has several features such as WDT and Brown-out detection that are crucial to proper operation of the system. If leaving these control registers unprotected, errant code may write undetermined value into them and results in incorrect operation and loss of control. To prevent this risk, the MS51 has a protection scheme, which limits the write access to critical SFR.
Page 228 MS51 TA – Timed Access Register SFR Address Reset Value C7H, All page 0000_0000 b TA[7:0] Name Description TA[7:0] Timed access The timed access register controls the access to protected SFR. To access protected bits, user should first write AAH to the TA and immediately followed by a write of 55H to TA. After these two steps, a writing permission window is opened for 4 clock cycles during this period that user may write to protected SFR.
Page 229 MS51 Example 3, TA,#0AAH ;3 clock cycles TA,#55H ;3 clock cycles WDCON,#data1 ;3 clock cycles BODCON0,#data2 ;4 clock cycles Example 4, TA,#0AAH ;3 clock cycles ;1 clock cycle TA,#55H ;3 clock cycles BODCON0,#data ;4 clock cycles In the first example, the writing to the protected bits is done before the 3-clock-cycle window closes. In example 2, however, the writing to BODCON0 does not complete during the window opening, there will be no change of the value of BODCON0.
Page 230: Interrupt System
MS51 6.2.6 Interrupt System 6.2.6.1 Overview The purpose of the interrupt is to make the software deal with unscheduled or asynchronous events. The MS51 has a four-priority-level interrupt structure with 24 interrupt sources. Each of the interrupt sources has an individual priority setting bits, interrupt vector and enable bit. In addition, the interrupts can be globally enabled or disabled.
Page 231 MS51 interrupts can also be set via software. Thereby software initiated interrupts can be generated. Note that every interrupts, if enabled, is generated by a setting as logic 1 of its interrupt flag no matter by hardware or software. User should take care of each interrupt flag in its own interrupt service routine (ISR).
Page 232 MS51 IE – Interrupt Enable Register SFR Address Reset Value A8H, All pages, Bit addressable 0000 _0000 b EADC EBOD Name Description Enable all interrupt This bit globally enables/disables all interrupts that are individually enabled. 0 = All interrupt sources Disabled. 1 = Each interrupt Enabled depending on its individual mask setting.
Page 233 MS51 EIE – Extensive Interrupt Enable Register SFR Address Reset Value 9BH, Page 0 0000 _0000 b ESPI EWDT EPWM0 ECAP Name Description Enable Timer 2 interrupt 0 = Timer 2 interrupt Disabled. 1 = Interrupt generated by TF2 (T2CON.7) Enabled. ESPI Enable SPI interrupt 0 = SPI interrupt Disabled.
Page 234 MS51 EIE1 – Extensive Interrupt Enable 1 Register SFR Address Reset Value EIE1 9CH, Page 0 0000 _0000 b EPWM3 EPWM2 EPWM1 EWKT ES_1 Name Description EPWM3 Enable PWM3 interrupt 0 = PWM3 interrupt Disabled. 1 = Interrupt generated by PWM3F (PWM3CON0.5) Enabled. EPWM2 Enable PWM2 interrupt 0 = PWM2 interrupt Disabled.
Page 235 MS51 6.2.6.3 Interrupt Priorities There are four priority levels for all interrupts. They are level highest, high, low, and lowest; and they are represented by level 3, level 2, level 1, and level 0. The interrupt sources can be individually set to one of four priority levels by setting their own priority bits.
Page 236: Table 6.2-4 Interrupt Priority Level Setting
MS51 . It also summarizes the interrupt sources, flag bits, vector addresses, enable bits, priority bits, natural priority and the permission to wake up the CPU from Power-down mode. For details of waking CPU up from Power-down mode, please see Section 6.2.2.3 “Power-Down Mode” Interrupt Priority Control Bits Interrupt Priority Level IPH / EIPH / EIPH1...
Page 237 MS51 Vector Natural Priority Control Power-Down Interrupt Source Interrupt Flag(S) Enable Bit Address Priority Bits Wake-Up Reset 0000H Always Highest Enabled External interrupt 0 0003H IE0[1] PX0, PX0H Brown-out 0043H BOF (BODCON0.3) EBOD PBOD, PBODH Watchdog Timer 0053H WDTF (WDCON.5) EWDT PWDT, PWDTH Timer 0...
Page 238: Table 6.2-5 Characteristics Of Each Interrupt Source
MS51 Vector Natural Priority Control Power-Down Interrupt Source Interrupt Flag(S) Enable Bit Address Priority Bits Wake-Up SC1 interrupt ACERR+BGT+TERR+TBE+ SC1IE PSC1, PSC1H 00B3H RDA (SC1IS[4:0]) SC2 interrupt ACERR+BGT+TERR+TBE+ SC2IE PSC2, PSC2H 00BBH RDA (SC2IS[4:0]) Note: 1. While the external interrupt pin is set as edge triggered (Itx = 1), its own flag Iex will be automatically cleared if the interrupt service routine (ISR) is executed.
Page 239 MS51 IP – Interrupt Priority Register SFR Address Reset Value B8H, All pages, Bit addressable 0000_0000 b PADC PBOD Name Description PADC ADC interrupt priority low bit PBOD Brown-out detection interrupt priority low bit Serial port 0 interrupt priority low bit Timer 1 interrupt priority low bit External interrupt 1 priority low bit Timer 0 interrupt priority low bit...
Page 240 MS51 IPH – Interrupt Priority High Register SFR Address Reset Value B7H, Page 0 0000_0000 b PADCH PBODH PT1H PX1H PT0H PX0H Name Description PADC ADC interrupt priority high bit PBOD Brown-out detection interrupt priority high bit Serial port 0 interrupt priority high bit PT1H Timer 1 interrupt priority high bit PX1H...
Page 241 MS51 EIP – Extensive Interrupt Priority Register SFR Address Reset Value EFH, Page 0 0000_0000 b PSPI PWDT PPWM PCAP Name Description Timer 2 interrupt priority low bit PSPI SPI interrupt priority low bit Fault Brake interrupt priority low bit PWDT WDT interrupt priority low bit PPWM...
Page 242 MS51 EIPH – Extensive Interrupt Priority High Register SFR Address Reset Value EIPH F7H, Page 0 0000_0000 b PT2H PSPIH PFBH PWDTH PPWMH PCAPH PPIH PI2CH Name Description PT2H Timer 2 interrupt priority high bit PSPIH SPI interrupt priority high bit PFBH Fault Brake interrupt priority high bit PWDTH...
Page 243 MS51 EIP1 – Extensive Interrupt Priority 1 Register SFR Address Reset Value EIP1 FEH, Page 0 0000_0000 b PPWM3 PPWM2 PPWM1 PWKT PS _ 1 Name Description PPWM3 PWM3 interrupt priority low bit PPWM2 PWM2 interrupt priority low bit PPWM1 PWM1 interrupt priority low bit PWKT WKT interrupt priority low bit...
Page 244 MS51 EIPH1 – Extensive Interrupt Priority High 1 Register SFR Address Reset Value EIPH1 FFH, Page 0 0000_0000 b PPWM3H PPWM2H PPWM1H PWKTH PT3H PSH _ 1 Name Description PPWM3H PWM3 interrupt priority high bit PPWM2H PWM2 interrupt priority high bit PPWM1H PWM1 interrupt priority high bit PWKTH...
Page 245 MS51 EIP2 – Extensive Interrupt Priority 2 Register SFR Address Reset Value EIP2 CEH, Page 2 0000_0000 b PSC2 PSC1 PSC0 Name Description PSC2 SC2 / UART4 interrupt priority low bit PSC1 SC1 / UART3 interrupt priority low bit PSC0 SC0 / UART2 interrupt priority low bit Note: EIP2 is used in combination with the EIPH2 to determine the priority of each interrupt source.
Page 246 MS51 EIPH2 – Extensive Interrupt Priority High 2 Register SFR Address Reset Value EIPH2 CFH, Page 2 0000_0000 b PUART4H PUART3H PUART2H Name Description PUART4H UART4 interrupt priority high bit PUART3H UART3 interrupt priority high bit PUART2H UART2 interrupt priority high bit Note: EIPH2 is used in combination with the EIP2 to determine the priority of each interrupt source.
Page 247 MS51 6.2.6.5 Interrupt Latency The response time for each interrupt source depends on several factors, such as the nature of the interrupt and the instruction underway. Each interrupt flags are polled and priority decoded each system clock cycle. If a request is active and all three previous conditions are met, then the hardware generated LCALL is executed.
Page 248 MS51 TCON – Timer 0 and 1 Control Register SFR Address Reset Value TCON 88H, All pages, Bit-addressable 0000_0000b R (level) R (level) R/W (edge) R/W (edge) Name Description External interrupt 1 edge flag If IT1 = 1 (falling edge trigger), this flag will be set by hardware when a falling edge is detected. It remain set until cleared via software or cleared by hardware in the beginning of its interrupt service routine.
Page 249: Flash Memory Control
MS51 Flash Memory Control 6.3.1 In-Application-Programming (IAP) Unlike RAM’s real-time operation, to update Flash data often takes long time. Furthermore, it is a quite complex timing procedure to erase, program, or read Flash data. The MS51 carried out the Flash operation with convenient mechanism to help user re-programming the Flash content by In- Application-Programming (IAP).
Page 250: Table 6.3-1 Iap Modes And Command Codes
MS51 IAPCN IAPA[15:0] IAP Mode IAPFD[7:0] FCTRL {IAPAH, IAPAL} IAPB FOEN FCEN [1:0] [3:0] CONFIG byte-program 0001 CONFIG0: 0000H Data in CONFIG1: 0001H CONFIG2: 0002H CONFIG4: 0004H CONFIG6: 0005H CONFIG byte-read 0000 CONFIG0: 0000H Data out CONFIG1: 0001H CONFIG2: 0002H CONFIG4: 0004H CONFIG6: 0005H Note:...
Page 251 MS51 CONFIG2 CBODEN CBOV[2:0] BOIAP CBORST Factory default value: 1111 1111b Name Description BOIAP Brown-out inhibiting IAP This bit decide whether IAP erasing or programming is inhibited by brown-out status. This bit is valid only when brown-out detection is enabled. 1 = IAP erasing or programming is inhibited if V is lower than V 0 = IAP erasing or programming is allowed under any workable V...
Page 252 MS51 CHPCON – Chip Control Register SFR Address Reset Value Software 0000_00U0 b CHPCON 9FH, All page, TA protected Others 0000_00C0 b SWRST IAPFF IAPEN Name Description IAPFF IAP fault flag The hardware will set this bit after IAPGO (IAPTRG.0) is set if any of the following condition is met: (1) The accessing address is oversize.
Page 253 MS51 IAPUEN – IAP Updating Enable Register SFR Address Reset Value IAPUEN A5H, Page 0, TA protected 0000 _0000 b SPMEN SPUEN CFUEN LDUEN APUEN Name Description Reserved SPMEN SPROM Memory space mapping enable 0 = CPU memory address 0xff80~0xffff is mapping to APROM memory 1 = CPU memory address 0xff80~0xffff is mapping to SPROM memory SPUEN SPROM Memory space updated enable(TA protected)
Page 254 MS51 IAPCN – IAP Control Register SFR Address Reset Value IAPCN AFH, Page 0 0011_0000 b Name Description IAPB[1:0] FOEN IAP control This byte is used for IAP command. For details, see Table 6.3-1 IAP Modes and Command Codes. FCEN FCTRL[3:0] Nov.
Page 255 MS51 IAPAH – IAP Address High Byte Register SFR Address Reset Value IAPAH A7H, Page 0 0000 _0000 b Name Description IAPA[15:8] IAP address high byte IAPAH contains address IAPA[15:8] for IAP operations. Nov. 28, 2019 Page 255 of 491 Rev 1.00...
Page 256 MS51 IAPAL – IAP Address Low Byte Register SFR Address Reset Value IAPAL A6H, Page 0 0000 _0000 b IAPA[7:0] Name Description IAPA[7:0] IAP address low byte IAPAL contains address IAPA[7:0] for IAP operations. Nov. 28, 2019 Page 256 of 491 Rev 1.00...
Page 257 MS51 IAPFD – IAP Flash Data Register SFR Address Reset Value IAPFD AEH, Page 0 0000 _0000 b IAPFD[7:0] Name Description IAPFD[7:0] IAP Flash data This byte contains Flash data, which is read from or is going to be written to the Flash Memory. User should write data into IAPFD for program mode before triggering IAP processing and read data from IAPFD for read/verify mode after IAP processing is finished.
Page 258 MS51 IAPTRG – IAP Trigger Register SFR Address Reset Value IAPTRG A4H, Page 0, TA protected 0000 _0000 b IAPGO Name Description Reserved IAPGO IAP go IAP begins by setting this bit as logic 1. After this instruction, the CPU holds the Program Counter (PC) and the IAP hardware automation takes over to control the progress.
Page 259 MS51 supports IAP function and any byte in the Flash Memory array may be read using the MOVC instruction and thus is suitable for use as non-volatile data storage. IAP provides erase and program function that makes it easy for one or more bytes within a page to be erased and programmed in a routine.
Page 260 MS51 MOVC A,@A+DPTR ;Read content of address 201h P0,A SJMP C language demo code: //************************************************************************* ***** This code illustrates how to use IAP to make APROM 201h as a byte of Data Flash when user code is executed in APROM. //************************************************************************* ***** #define PAGE_ERASE_AP...
Page 261 User Code to MCU through serial port. Then Boot Code receives it and re-programs into User Code through IAP commands. Nuvoton provides ISP firmware and PC application for MS51. It makes user quite easy perform ISP through UART port. Please visit Nuvoton 8-bit Microcontroller website: Nuvoton 80C51 Microcontroller Technical Support.
Page 262 MS51 CALL Enable_AP_Update CALL Erase_AP ;erase AP data CALL Program_AP ;programming AP data CALL Disable_AP_Update CALL Program_AP_Verify ;verify Programmed AP data CALL Read_CONFIG ;read back CONFIG2 CALL Enable_CONFIG_Update CALL Erase_CONFIG ;erase CONFIG bytes CALL Program_CONFIG ;programming CONFIG2 with new data CALL Disable_CONFIG_Update CALL...
Page 263 MS51 TA,#55h IAPUEN,#00000100b ;CFUEN = 1, enable CONFIG update Disable_CONFIG_Update: TA,#0Aah TA,#55h IAPUEN,#11111011b ;CFUEN = 0, disable CONFIG update Trigger_IAP: TA,#0Aah ;IAPTRG is TA protected TA,#55h IAPTRG,#00000001b ;write ‘1’ to IAPGO to trigger IAP process ;******************************************************************** IAP APROM Function ;******************************************************************** Erase_AP: IAPCN,#PAGE_ERASE_AP IAPFD,#0FFh...
Page 264 MS51 IAPAH,#00h IAPAL,#00h DPTR,#AP_code Program_AP_Verify_Loop: CALL Trigger_IAP MOVC A,@A+DPTR A,IAPFD CJNE A,B,Program_AP_Verify_Error DPTR IAPAL A,IAPAL CJNE A,#14,Program_AP_Verify_Loop Program_AP_Verify_Error: CALL Disable_IAP P0,#00h SJMP ;******************************************************************** IAP CONFIG Function ;******************************************************************** Erase_CONFIG: IAPCN,#ALL_ERASE_CONFIG IAPAH,#00h IAPAL,#00h IAPFD,#0FFh CALL Trigger_IAP Read_CONFIG: IAPCN,#BYTE_READ_CONFIG IAPAH,#00h IAPAL,#02h CALL Trigger_IAP R7,IAPFD Program_CONFIG: IAPCN,#BYTE_PROGRAM_CONFIG...
Page 265: In-Circuit-Programming (Icp)
VSS pins on the circuit board to make ICP possible. Nuvoton provides ICP tool for MS51, which enables user to easily perform ICP through Nuvoton ICP programmer. The ICP programmer developed by Nuvoton has been optimized according to the electric characteristics of MCU.
Page 266 MS51 memory map and does not share any on-chip peripherals. When the OCDEN (CONFIG0.4) is programmed as 0 and LOCK (CONFIG0.1) remains un- programmed as 1, the OCD is activated. The OCD cannot operate if chip is locked. The OCD system uses a two-wire serial interface, ICE_DAT and ICE_CLK, to establish communication between the target device and the controlling debugger host.
Page 267: 96-Bit Unique Code
MS51 CONFIG0 OCDPWM OCDEN LOCK Factory default value: 1111 1111b Name Description OCDPWM PWM output state under OCD halt This bit decides the output state of PWM when OCD halts CPU. 1 = Tri-state pins those are used as PWM outputs. 0 = PWM continues.
Page 268: Figure 6.3-1 Config0 Any Reset Reloading
MS51 CONFIG0 OCDPWM OCDEN LOCK Factory default value: 1111 1111b Name Description CONFIG boot select This bit defines from which block that MCU re-boots after resets except software reset. 1 = MCU will re-boot from APROM after resets except software reset. 0 = MCU will re-boot from LDROM after resets except software reset.
Page 269 MS51 CONFIG1 LDSIZE[2:0] Factory default value: 1111 1111b Name Description LDSIZE[2:0] LDROM size select This field selects the size of LDROM. 111 = No LDROM. APROM is 32 Kbytes. 110 = LDROM is 1 Kbytes. APROM is 31 Kbytes. 101 = LDROM is 2 Kbytes. APROM is 30 Kbytes. 100 = LDROM is 3 Kbytes.
Page 270: Figure 6.3-2 Config2 Power-On Reset Reloading
MS51 CONFIG2 CBODEN CBOV[2:0] BOIAP CBORST Factory default value: 1111 1111b Name Description CBODEN CONFIG brown-out detect enable 1 = Brown-out detection circuit on. 0 = Brown-out detection circuit off. CBOV[1:0] CONFIG brown-out voltage select 11 = V is 2.2V. 10 = V is 2.7V.
Page 271 MS51 CONFIG4 WDTEN[3:0] Factory default value: 1111 1111b Name Description WDTEN[3:0] WDT enable This field configures the WDT behavior after MCU execution. 1111 = WDT is Disabled. WDT can be used as a general purpose timer via software control. 0101 = WDT is Enabled as a time-out reset timer and it stops running during Idle or Power- down mode.
Page 272: Table 6.4-1 Configuration For Different I/O Modes
MS51 General Purpose I/O (GPIO) 6.4.1 Gpio Mode The MS51 has a maximum of 30 general purpose I/O pins which 29 bit-addressable general I/O pins grouped as 4 ports, P0 to P3, and 1 input only pin as P20. Each port has its port control register (Px register).
Page 273: Figure 6.4-1 Quasi-Bidirectional Mode Structure
MS51 2-CPU-clock Very Strong delay Weak Port Pin Port Latch Input Figure 6.4-1 Quasi-Bidirectional Mode Structure 6.4.1.2 Push-Pull Mode The push-pull mode has the same pull-low structure as the quasi-bidirectional mode, but provides a continuous strong pull-high when the port latch is written by logic 1. The push-pull mode is generally used as output pin when more source current is needed for an output driving.
Page 274: Figure 6.4-3 Input-Only Mode Structure
MS51 Input Port Pin Figure 6.4-3 Input-Only Mode Structure 6.4.1.4 Open-Drain Mode The open-drain mode turns off all pull-high transistors and only drives the pull-low of the port pin when the port latch is given by logic 0. If the port latch is logic 1, it behaves as if in input-only mode. To be used as an output pin generally as I C lines, an open-drain pin should add an external pull-high, typically a resistor tied to V...
Page 275: Figure 6.4-5 Pin Interface Block Diagram
MS51 the entire port latch value, modify the changed bit, and then write the new value back to the port latch. 6.4.3 Pin Interrupt (PIT) The MS51 provides pin interrupt input for each I/O pin to detect pin state if button or keypad set is used.
Page 276 MS51 6.4.4 Control Registers of GPIO The MS51 has a lot of I/O control registers to provide flexibility in all kinds of applications. The SFR related with I/O ports can be categorized into four groups: input and output control, output mode control, input type and sink current control, and output slew rate control.
Page 277 MS51 PnM1 – Port Mode Select 1 Register SFR Address Reset Value P0M1 B1H, Page 0 1111_1111 b P1M1 B3H, Page 0 1111_1111 b P2M1 89H, Page 2 0011_1111 b P3M1 ACH, Page 0 1111_1111 b PnM1.7 PnM1.6 PnM1.5 PnM1.4 PnM1.3 PnM1.2 PnM1.1...
Page 278 MS51 PnM2 – Port Mode Select 2 Register SFR Address Reset Value P0M2 B2H, Page 0 0000_0000 b P1M2 B4H, Page 0 0000_0000 b P2M2 8AH, Page 2 0000_0000 b P3M2 ADH, Page 0 0000_0000 b PnM2.7 PnM2.6 PnM2.5 PnM2.4 PnM2.3 PnM2.2 PnM2.1...
Page 279 MS51 Note that all PxSR registers are accessible by switching SFR page to Page 1. Nov. 28, 2019 Page 279 of 491 Rev 1.00...
Page 280 MS51 PnSR –Port n Slew Rate Control Register SFR Address Reset Value P0SR B2H, Page 1 0000_0000 b P1SR B4H, Page 1 0000_0000 b P2SR 8BH, Page 2 0000_0000 b P3SR ADH, Page 1 0000_0000 b PnSR.7 PnSR.6 PnSR.5 PnSR.4 PnSR.3 PnSR.2 PnSR.1...
Page 281 MS51 PICON – Pin Interrupt Control Register SFR Address Reset Value PICON E9H, PAGE 0, 0011 _0100 b PIT7 PIT6 PIT5 PIT4 PIT3 PIT2 PIT1 PIT0 Name Description PIT7 Pin interrupt channel 7 type select This bit selects which type that pin interrupt channel 7 is triggered. 0 = Level triggered.
Page 282 MS51 Name Description PIT0 Pin interrupt channel 0 type select This bit selects which type that pin interrupt channel 0 is triggered. 0 = Level triggered. 1 = Edge triggered. Nov. 28, 2019 Page 282 of 491 Rev 1.00...
Page 283 MS51 PINEN – Pin Interrupt Negative Polarity Enable. Register SFR Address Reset Value PINEN EAH, Page 0 0000_0000 b PINEN7 PINEN6 PINEN5 PINEN4 PINEN3 PINEN2 PINEN1 PINEN0 Name Description PINENn Pin interrupt channel n negative polarity enable This bit enables low-level/falling edge triggering pin interrupt channel n. The level or edge triggered selection depends on each control bit PITn in PICON.
Page 284 MS51 PIPEN – Pin Interrupt Positive Polarity Enable. Register SFR Address Reset Value PIPEN EBH, Page 0 0000_0000 b PIPEN7 PIPEN6 PIPEN5 PIPEN4 PIPEN3 PIPEN2 PIPEN1 PIPEN0 Name Description PIPENn Pin interrupt channel n positive polarity enable This bit enables high-level/rising edge triggering pin interrupt channel n. The level or edge triggered selection depends on each control bit PITn in PICON.
Page 285 MS51 PIF – Pin Interrupt Flags Register SFR Address Reset Value ECH, Page 0 0000_0000 b PIF7 PIF6 PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 R (level) R (level) R (level) R (level) R (level) R (level) R (level) R (level) R/W (edge) R/W (edge) R/W (edge)
Page 286 MS51 PIPSn – Pin Interrupt Control Register SFR Address Reset Value PIPS7 F7H, page 2 0000_0000 b 0000_0000 b PIPS6 FFH, page 2 PIPS5 FEH, page 2 0000_0000 b 0000_0000 b PIPS4 FDH, page 2 PIPS3 FCH, page 2 0000_0000 b 0000_0000 b FBH, page 2 PIPS2...
Page 287 MS51 Timer 6.5.1 Timer/Counter 0 And 1 6.5.1.1 Overview Timer/Counter 0 and 1 on MS51 are two 16-bit Timers/Counters. Each of them has two 8-bit registers those form the 16-bit counting register. For Timer/Counter 0 they are TH0, the upper 8-bit register, and TL0, the lower 8-bit register.
Page 288: Figure 6.5-1 Timer/Counters 0 And 1 In Mode 0
MS51 Figure 6.5-1 Timer/Counters 0 and 1 in Mode 0 6.5.1.3 Mode 1 (16-Bit Timer) Mode 1 is similar to Mode 0 except that the counting registers are fully used as a 16-bit counter. Roll- over occurs when a count moves FFFFH to 0000H. The Timer overflow flag TF0 (TF1) of the relevant Timer/Counter is set and an interrupt will occurs if enabled.
Page 289: Figure 6.5-4 Timer/Counter 0 In Mode 3
MS51 6.5.1.5 Mode 3 (Two Separate 8-Bit Timers) Mode 3 has different operating methods for Timer 0 and Timer 1. For Timer/Counter 1, Mode 3 simply freezes the counter. Timer/Counter 0, however, configures TL0 and TH0 as two separate 8 bit count registers in this mode.
Page 290 MS51 Name Description C/T ̅ Timer 1 Counter/Timer select 0 = Timer 1 is incremented by internal system clock. 1 = Timer 1 is incremented by the falling edge of the external pin T1. Timer 1 mode select Timer 1 Mode Mode 0: 13-bit Timer/Counter Mode 1: 16-bit Timer/Counter Mode 2: 8-bit Timer/Counter with auto-reload from TH1...
Page 291 MS51 TCON – Timer 0 and 1 Control Register SFR Address Reset Value TCON 88H, All pages, Bit-addressable 0000_0000b Name Description Timer 1 overflow flag This bit is set when Timer 1 overflows. It is automatically cleared by hardware when the program executes the Timer 1 interrupt service routine.
Page 292 MS51 TL0 – Timer 0 Low Byte Register SFR Address Reset Value 8AH, Page0 0000_0000b TL0[7:0] Name Description TL0[7:0] Timer 0 low byte The TL0 register is the low byte of the 16-bit counting register of Timer 0. Nov. 28, 2019 Page 292 of 491 Rev 1.00...
Page 293 MS51 TH0 – Timer 0 High Byte Register SFR Address Reset Value 8CH, Page0 0000_0000b TH0[7:0] Name Description TH0[7:0] Timer 0 high byte The TH0 register is the high byte of the 16-bit counting register of Timer 0. Nov. 28, 2019 Page 293 of 491 Rev 1.00...
Page 294 MS51 TL1 – Timer 1 Low Byte Register SFR Address Reset Value 8BH, Page0 0000_0000b TL1[7:0] Name Description TL1[7:0] Timer 1 low byte The TL1 register is the low byte of the 16-bit counting register of Timer 1. Nov. 28, 2019 Page 294 of 491 Rev 1.00...
Page 295 MS51 TH1 – Timer 1 High Byte Register SFR Address Reset Value 8DH, Page0 0000_0000b TH1[7:0] Name Description TH1[7:0] Timer 1 high byte The TH1 register is the high byte of the 16-bit counting register of Timer 1. Nov. 28, 2019 Page 295 of 491 Rev 1.00...
Page 296 MS51 CKCON – Clock Control Register SFR Address Reset Value CKCON 8EH, Page0 0000_0000b PWMCKS T0OE CLOEN Name Description Timer 1 clock mode select 0 = The clock source of Timer 1 is the system clock divided by 12. It maintains standard 8051 compatibility.
Page 297: Figure 6.5-5 Timer 2 Block Diagram
MS51 1000 P1.5/IC7 CAPF0 CAPF0 0111 P0.5/IC6 [00] 0110 P0.3/IC5 0101 CAPF1 P0.1/IC4 CAP0 Noise Input Capture Interrupt P0.4/IC3 0100 [01] P0.0/IC3 Filter 0011 P1.0/IC2 0010 CAPF2 CAP1 P1.1/IC1 0001 ENF0 [10] P1.2/IC0 0000 (CAPCON2.4) CAPEN0 CAP2 (CAPCON0.4) CAP0LS[1:0] (CAPCON1[1:0]) Input Capture 0 Module Input Capture 1 Module Input Capture 2 Module...
Page 298: Figure 6.5-6 Timer 2 Auto-Reload Mode And Input Capture Module Functional Block Diagram
MS51 6.5.2.2 Auto-Reload Mode ̅̅̅̅̅̅ . In this mode RCMP2H and The Timer 2 is configured as auto-reload mode by clearing CM/RL2 RCMP2L registers store the reload value. The contents in RCMP2H and RCMP2L transfer into TH2 and TL2 once the auto-reload event occurs if setting LDEN bit. The event can be the Timer 2 overflow or one of the triggering event on any of enabled input capture channel depending on the LDTS[1:0] (T2MOD[1:0]) selection.
Page 299: Figure 6.5-7 Timer 2 Compare Mode And Input Capture Module Functional Block Diagram
MS51 6.5.2.3 Compare Mode ̅̅̅̅̅̅ . In this mode RCMP2H and Timer 2 can also be configured as the compare mode by setting CM/RL2 RCMP2L registers serve as the compare value registers. As Timer 2 up counting, TH2 and TL2 match RCMP2H and RCMP2L, TF2 (T2CON.7) will be set by hardware to indicate a compare match event.
Page 300 MS51 6.5.2.4 Input Capture Module The input capture module along with Timer 2 implements the input capture function. The input capture module is configured through CAPCON0~2 registers. The input capture module supports 3-channel inputs (CAP0, CAP1, and CAP2). Each input channel consists its own noise filter, which is enabled via setting ENF0~2 (CAPCON2[6:4]).
Page 301 MS51 T2CON – Timer 2 Control Register SFR Address Reset Value T2CON C8H, All pages, Bit addressable 0000_0000 b ̅̅̅̅̅̅ CM/RL2 Name Description Timer 2 overflow flag This bit is set when Timer 2 overflows or a compare match occurs. If the Timer 2 interrupt and the global interrupt are enable, setting this bit will make CPU execute Timer 2 interrupt service routine.
Page 302 MS51 T2MOD – Timer 2 Mode Register SFR Address Reset Value T2MOD C9H, Page 0 0000_0000 b LDEN T2DIV[2:0] CAPCR CMPCR LDTS[1:0] Name Description LDEN Enable auto-reload 0 = Reloading RCMP2H and RCMP2L to TH2 and TL2 Disabled. 1 = Reloading RCMP2H and RCMP2L to TH2 and TL2 Enabled. T2DIV[2:0] Timer 2 clock divider 000 = Timer 2 clock divider is 1/1.
Page 303 MS51 RCMP2L– Timer 2 Reload/Compare Low Byte Register SFR Address Reset Value RCMP2L CAH, Page 0 0000_0000 b RCMP2L[7:0] Name Description RCMP2L[7:0] Timer 2 reload/compare low byte This register stores the low byte of compare value when Timer 2 is configured in compare mode.
Page 304 MS51 RCMP2H – Timer 2 Reload/Compare High Byte Register SFR Address Reset Value RCMP2H CBH, Page 0 0000_0000 b RCMP2H[7:0] Name Description RCMP2H[7:0] Timer 2 reload/compare high byte This register stores the high byte of compare value when Timer 2 is configured in compare mode.
Page 305 MS51 TL2 – Timer 2 Low Byte Register SFR Address Reset Value CCH, Page 0 0000_0000 b TL2[7:0] Name Description TL2[7:0] Timer 2 low byte The TL2 register is the low byte of the 16-bit counting register of Timer 2. Nov.
Page 306 MS51 TH2 – Timer 2 High Byte Register SFR Address Reset Value CDH, Page 0 0000_0000 b TH2[7:0] Name Description TH2[7:0] Timer 2 high byte The TH2 register is the high byte of the 16-bit counting register of Timer 2. Note that the TH2 and TL2 are accessed separately.
Page 307 MS51 CAPCON0 – Input Capture Control 0 Register SFR Address Reset Value CAPCON0 92H, Page 0 0000_0000b CAPEN2 CAPEN1 CAPEN0 CAPF2 CAPF1 CAPF0 Name Description Reserved CAPEN2 Input capture 2 enable 0 = Input capture channel 2 Disabled. 1 = Input capture channel 2 Enabled. CAPEN1 Input capture 1 enable 0 = Input capture channel 1 Disabled.
Page 308 MS51 CAPCON1 – Input Capture Control 1 Register SFR Address Reset Value CAPCON1 93H, Page 0 0000_0000b CAP2LS[1:0] CAP1LS[1:0] CAP0LS[1:0] Name Description Reserved CAP2LS[1:0] Input capture 2 level select 00 = Falling edge. 01 = Rising edge. 10 = Either rising or falling edge. 11 = Reserved.
Page 309 MS51 CAPCON2 – Input Capture Control 2 Register SFR Address Reset Value CAPCON2 94H, Page0 0000_0000b ENF2 ENF1 ENF0 Name Description ENF2 Enable noise filer on input capture 2 0 = Noise filter on input capture channel 2 Disabled. 1 = Noise filter on input capture channel 2 Enabled. ENF1 Enable noise filer on input capture 1 0 = Noise filter on input capture channel 1 Disabled.
Page 310 MS51 CnL – Capture Low Byte, n = 0,1,2 Register SFR Address Reset Value E4H, Page 0 0000_0000 b E6H, Page 0 0000_0000 b EDH, Page 0 0000_0000 b CnL[7:0] Name Description CnL[7:0] Input capture n result low byte The CnL register is the low byte of the 16-bit result captured by input capture n. Nov.
Page 311 MS51 CnH – Capture n High Byte, n = 1,2,3 Register SFR Address Reset Value E5H, Page 0 0000_0000 b E7H, Page 0 0000_0000 b EEH, Page 0 0000_0000 b CnH[7:0] Name Description CnH[7:0] Input capture n result high byte The CnH register is the high byte of the 16-bit result captured by input capture n.
Page 312 MS51 CAPCON3 – Input Capture Control 3 Register SFR Address Reset Value CAPCON3 F1H, Page 0 0000_0000 b CAP13 CAP12 CAP11 CAP10 CAP03 CAP02 CAP01 CAP00 Name Description [7:4] CAP1[3:0] Input capture channel 1 input pin select 0000 = P1.2/IC0 0001 = P1.1/IC1 0010 = P1.0/IC2 0011 = P0.0/IC3...
Page 313 MS51 CAPCON4 – Input Capture Control 4 Register SFR Address Reset Value CAPCON4 F2H, Page 0 0000_0000 b CAP23 CAP22 CAP21 CAP20 Name Description [3:0] CAP2[3:0] Input capture channel 2 input pin select 0000 = P1.2/IC0 0001 = P1.1/IC1 0010 = P1.0/IC2 0011 = P0.0/IC3 0100 = P0.4/IC3 0101 = P0.1/IC4...
Page 314: Figure 6.5-8 Timer 3 Block Diagram
MS51 6.5.3 TIMER 3 6.5.3.1 Overview Timer 3 is implemented simply as a 16-bit auto-reload, up-counting timer. The user can select the pre- scale with T3PS[2:0] (T3CON[2:0]) and fill the reload value into RH3 and RL3 registers to determine its overflow rate. User then can set TR3 (T3CON.3) to start counting. When the counter rolls over FFFFH, TF3 (T3CON.4) is set as 1 and a reload is generated and causes the contents of the RH3 and RL3 registers to be reloaded into the internal 16-bit counter.
Page 315 MS51 Name Description T3PS[2:0] Timer 3 pre-scalar These bits determine the scale of the clock divider for Timer 3. 000 = 1/1. 001 = 1/2. 010 = 1/4. 011 = 1/8. 100 = 1/16. 101 = 1/32. 110 = 1/64. 111 = 1/128.
Page 316 MS51 RL3 – Timer 3 Reload Low Byte Register SFR Address Reset Value C5H, Page 0 0000_0000 b RL3[7:0] Name Description RL3[7:0] Timer 3 reload low byte It holds the low byte of the reload value of Timer 3. Nov. 28, 2019 Page 316 of 491 Rev 1.00...
Page 317 MS51 RH3 – Timer 3 Reload High Byte Register SFR Address Reset Value C6H, Page 0 0000_0000 b RH3[7:0] Name Description RH3[7:0] Timer 3 reload high byte It holds the high byte of the reload value of Time 3. Nov. 28, 2019 Page 317 of 491 Rev 1.00...
Page 318 MS51 6.6 pulse Width Modulated (PWM) 6.6.1 Overview The PWM (Pulse Width Modulation) signal is a useful control solution in wide application field. It can used on motor driving, fan control, backlight brightness tuning, LED light dimming, or simulating as a simple digital to analog converter output through a low pass filter circuit.
Page 319: Table 6.6-1 Pwm Pin Define And Enable Control Register
MS51 Control register 1 Control register2 Output PWM Channel SFR Byte Name Bit name Value SFR Byte Name Bit name Value P3.1 PIOCON2[4] PIO31 P0.0 PIOCON0[3] PIO00 P0.4 PIOCON1[3] PIO04 P3.2 PIOCON2[5] PIO32 PWM3_CH0 P0.1 PIOCON0[4] PIO01 AUXR5[1:0] PWM3C0P- P1.7 PIOCON1[7] PIO17 P3.4...
Page 320: Figure 6.6-1 Pwm0 Block Diagram
MS51 PWM0P 0-to-1 (PWM0PH, PWM0PL) registers LOAD (PWM0CON0.6) PWM0P buffer Counter Matching(edgealigned)/ underflow(venter aligned) PWMF PWM0 interrupt (PWM0CON0.5) PWMRUN 16-bit (PWM0CON0.7) clear counter up/down Interrupt CLRPWM INTSEL[1:0], INTTYP[1:0] counter select/type (PWMnCON0.4) (PWMnCON0[3:0]) Pre-scalar edge/center Timer 1 overflow PWMTYP P0G0 PWMCKS PWMDIV0[2:0] PWM0_CH0 (PWM0CON1.4)
Page 321: Figure 6.6-2 Pwm1/2/3 Block Diagram
MS51 PWM mode, mask output and PWM polarity. The last stage is a multiplexer of PWM1/2/3 output or I/O function. PWMnP 0-to-1 (PWMnPH, PWMnPL) registers LOAD (PWMnCON0.6) PWMnP buffer Counter Matching(edgealigned)/ underflow(venter aligned) PWMF PWMn interrupt (PWMnCON0.5) PWMRUNn 16-bit clear counter up/down Interrupt CLRPWM...
Page 322: Figure 6.6-3 Pwm0 And Fault Brake Output Control Block Diagram
MS51 PWM0 and Fault Brake output control Dead Mask Brake mode time output control polarity select insertion PMEN0 PNP0 P0G0_DT P0G0 PMD0 FBD0 PWM0_CH0 PWM0C PWM0C dead mode P0G1 time P0G1_DT PMD1 FBD1 PWM0_CH1 PMEN1 PNP1 PMEN2 P0G2_DT PNP2 P0G2 PMD2 PWM0C FBD2...
Page 323: Figure 6.6-4 Pwm1/2/3 Control Block Diagram
MS51 PWM1/2/3 output control Mask mode output select PWMnMEN0 PnG0 PWMn_CH0 PWMnMD0 PWMnC0/1 mode PnG1 PWMn_CH1 PWMnMD1 PWMnMEN1 PWMnMOD[1:0] PWMnMEN, (PWMnCON1[7:6]) PWMnMD Figure 6.6-4 PWM1/2/3 Control Block Diagram NOTE: A loading of new period and duty by setting LOAD should be ensured complete by monitoring it and waiting for a hardware automatic clearing LOAD bit.
Page 324: Figure 6.6-5 Pwm Edge-Aligned Type Waveform
MS51 PWMnP (2nd) PWMnP (1st) 12-bit counter PWMnCH01 (2nd) PWMnCH01 (1st) PWMnCH01 (2nd) duty valid PG01 output PWMnP (2nd) period valid Load Load PWMnCH01 PWMnP (2nd) (2nd) Figure 6.6-5 PWM Edge-aligned Type Waveform The output frequency and duty cycle for edge-aligned PWM are given by following equations: PWM frequency = is the PWM clock source frequency divided by ...
Page 325: Figure 6.6-7 Pwm0 Complementary Mode With Dead-Time Insertion
MS51 The output frequency and duty cycle for center-aligned PWM are given by following equations: PWM frequency = is the PWM clock source frequency divided by  PWMnPH PWMnPL PWMDIV). PWMnCHxH PWMnCHxL PWM high level duty = PWMnPH PWMnPL 6.6.2.5 Operation Modes After PnGx signals pass through the first stage of the PWM.
Page 326: Figure 6.6-8 Fault Brake Function Block Diagram
MS51 PnG0/2/4 correspondingly. 6.6.2.9 Mask Output Control Each PWM signal can be software masked by driving a specified level of PWM signal. The PWM mask output function is quite useful when controlling Electrical Commutation Motor like a BLDC. PWMnMEN determine which channel of PWM signal will be masked. PWMnMD set the individual mask level of each PWM channel.
Page 327 MS51 6.6.3 PWM Interrupt The PWM module has a flag PWMF (PWMnCON0.5) to indicate certain point of each complete PWM period. The indicating PWM channel and point can be selected by INTSEL[2:0] and INTTYP[1:0] (PWMnINTC[2:0] and [5:4]). Note that the center point and the end point interrupts are only available when PWM operates in its center-aligned type.
Page 328 MS51 PWMnINTC – PWM Interrupt Control Register SFR Address Reset Value PWM0INTC B7H, page 1 0000_0000 b 0000_0000 b PWM1INTC B6H, page 2 0000_0000 b PWM2INTC C6H, page 2 0000_0000 b PWM3INTC D6H, page 2 INTTYP1 INTTYP0 INTSEL2 INTSEL1 INTSEL0 Name Description INTTYP[1:0]...
Page 329: Figure 6.6-9 Pwm Interrupt Type
MS51 The PWM interrupt related with PWM waveform is shown as figure below. Edge-aligned PWM Center-aligned PWM Central point 12-bit PWM counter End point Dead time PWM channel 0/2/4 pin output PWMF (falling edge) Software (INTTYP[1:0] = [0:0]) clear PWMF (rising edge) (INTTYP[1:0] = [0:1]) PWMF (central point) Reserved...
Page 330 MS51 6.6.4 Control Register of PWM PWM0CON0 – PWM0 Control 0 (Bit-addressable) Register SFR Address Reset Value PWM0CON0 D8H, Page0 0000_0000 b PWM0RUN LOAD PWMF CLRPWM PWM3RUN PWM2RUN PWM1RUN P33FBINEN Name Description PWM0RUN PWM0 run enable 0 = PWM0 stays in idle. 1 = PWM0 starts running.
Page 331 MS51 Name Description PWM3RUN PWM3 run enable 0 = PWM3 stays in idle. 1 = PWM3 starts running. Note: This bit is only for PWM0CON0. PWM2RUN PWM2 run enable 0 = PWM2 stays in idle. 1 = PWM2 starts running. Note: This bit is only for PWM0CON0.
Page 332 MS51 PWMnCON0 – PWMn Control 0, n = 1,2,3 Register SFR Address Reset Value PWM1CON0 B4H, Page 2 0000_0000 b PWM2CON0 C4H, Page 2 0000_0000 b PWM3CON0 D4H, Page 2 0000_0000 b PWMRUN LOAD PWMF CLRPWM Name Description PWMRUN PWM run enable 0 = PWM stays in idle.
Page 333 MS51 PWMnCON1 – PWM Control 1 Register SFR Address Reset Value PWM0CON1 DFH, page 0 0000_0000 b B5H, page 2 0000_0000 b PWM1CON1 0000_0000 b C5H, page 2 PWM2CON1 0000_0000 b D5H, page 2 PWM3CON1 PWMMOD[1:0] PWMTYP FBINEN PWMDIV[2:0] Name Description PWMMOD[1:0] PWM mode select...
Page 334 MS51 Name Description PWMDIV[2:0] PWM clock divider This field decides the pre-scale of PWM clock source. 000 = 1/1. 001 = 1/2 010 = 1/4. 011 = 1/8. 100 = 1/16. 101 = 1/32. 110 = 1/64. 111 = 1/128. Nov.
Page 335 MS51 CKCON – Clock Control Register SFR Address Reset Value CKCON 8EH, Page0 0000_0000b PWMCKS T0OE CLOEN Name Description PWMCKS PWM clock source select 0 = The clock source of PWM is the system clock FSYS. 1 = The clock source of PWM is the overflow of Timer 1. Nov.
Page 336 MS51 PWMnPL – PWM Period Low Byte, n = 0,1,2,3 Register SFR Address Reset Value PWM0PL D9H, Page 0 0000_0000 b PWM1PL B1H, Page 2 0000_0000 b PWM2PL C1H, Page 2 0000_0000 b PWM3PL D1H, Page 2 0000_0000 b PWM0P[7:0] Name Description PWMnP[7:0]...
Page 337 MS51 PWMnPH – PWM Period High Byte, n = 0,1,2,3 Register SFR Address Reset Value PWM0PH D1H, Page 0 0000_0000 b PWM1PH A9H, Page 2 0000_0000 b PWM2PH B9H, Page 2 0000_0000 b PWM3PH C9H, Page 2 0000_0000 b PWM0P[15:8] Name Description PWM0P[15:8]...
Page 338 MS51 PWMnCxH – PWMn Channel x Duty High Byte, n = 0,1,2,3; x = 0,1,2,3,4,5 Register SFR Address Description Reset Value PWM0 Channel 0 Duty High Byte PWM0C0H D2H, Page 0 0000_0000 b PWM0 Channel 1 Duty High Byte PWM0C1H D3H, Page 0 0000_0000 b PWM0 Channel 2 Duty High Byte...
Page 339 MS51 PWMnCxL – PWMn Channel x Duty Low Byte, n = 0,1,2,3; x = 0,1,2,3,4,5 Register SFR Address Description Reset Value PWM0 Channel 0 Duty Low Byte PWM0C0L DAH, Page 0 0000_0000 b PWM0 Channel 1 Duty Low Byte PWM0C1L DBH, Page 0 0000_0000 b PWM0 Channel 2 Duty Low Byte...
Page 340 MS51 PWM0DTEN – PWM Dead-time Enable Register SFR Address Reset Value PWM0DTEN F9H, Page 0, TA protected 0000_0000 b PWM0DTCNT. PDT45EN PDT23EN PDT01EN Name Description PDTCNT8 PWM0 dead-time counter bit 8 See PWM0DTCNT register. PDT45EN PWM0C4/5 pair dead-time insertion enable This bit is valid only when PWM0C4/5 is under complementary mode.
Page 341 MS51 PWM0DTCNT – PWM Dead-time Counter Register SFR Address Reset Value PWM0DTCNT FAH, Page 0, TA protected 0000_0000 b PWM0DTCNT[7:0] Name Description PWM0DTCNT[7:0] PWM0 dead-time counter low byte This 8-bit field combined with PWM0DTEN.4 forms a 9-bit PWM0 dead-time counter PWM0DTCNT.
Page 342 MS51 PWMxMEN – PWMnCx Mask Enable, n=0,1,2,3;x=0,1,2,3,4,5 Register SFR Address Description Reset Value PWM0Cx Mask Enable PWM0MEN FBH, Page 0 0000_0000 b ADH, Page 2 PWM1Cx Mask Enable PWM1MEN 0000_0000 b BDH, Page 2 PWM2Cx Mask Enable PWM2MEN 0000_0000 b CDH, Page 2 PWM3Cx Mask Enable PWM3MEN...
Page 343 MS51 PWMnMD –PWMnCx Mask Data Register SFR Address Description Reset Value PWM0Cx Mask Data PWM0MD FCH, Page 0 0000_0000 b ACH, Page 2 PWM1Cx Mask Data PWM1MD 0000_0000 b BCH, Page 2 PWM2Cx Mask Data PWM2MD 0000_0000 b CCH, Page 2 PWM3Cx Mask Data PWM3MD 0000_0000 b...
Page 344 MS51 PWM0CON1 – PWM Control 1 Register SFR Address Reset Value PWM0CON1 DFH, Page 0 0000_0000 b PWMMOD[1:0] PWMTYP FBINEN PWMDIV[2:0] Name Description FBINEN FB pin input enable 0 = PWM output Fault Braked by FB pin input Disabled. 1 = PWM output Fault Braked by FB pin input Enabled. Once an edge, which matches FBINLS (PWM0FBD.6) selection, occurs on FB pin, PWM0 channel 0~5 output Fault Brake data in PWM0FBD register and PWM6/7 remains their states.
Page 345 MS51 PWM0FBD – PWM Fault Brake Data Register SFR Address Reset Value PWM0FBD D7H, Page 0 0000_0000 b FBINLS FBD5 FBD4 FBD3 FBD2 FBD1 FBD0 Name Description Fault Brake flag This flag is set when FBINEN is set as 1 and FB pin detects an edge, which matches FBINLS (PWM0FBD.6) selection.
Page 346 MS51 PNP – PWM Negative Polarity Register SFR Address Reset Value D6H, Page 0 0000_0000 b PNP5 PNP4 PNP3 PNP2 PNP1 PNP0 Name Description PNPn PWMn negative polarity output enable 0 = PWMn signal outputs directly on PWMn pin. 1 = PWMn signal outputs inversely on PWMn pin. Nov.
Page 347 MS51 PIOCON0 – PWM or I/O Select Register SFR Address Reset Value PIOCON0 DEH, Page 0 0000_0000 b PIO05 PIO04 PIO03 PIO02 PIO01 PIO00 Name Description PIO05 P0.3/PWM pin function select 0 = P0.3/PWM pin functions as P0.3. 1 = P0.3/PWM pin functions as PWM0C5/PWM3_CH1 output. (PWM3_CH1P=11, select PWM3_CH1;...
Page 348 MS51 PIOCON1 – PWM or I/O Select Register SFR Address Reset Value PIOCON1 C6H, Page 1 0000_0000 b PIO17 PIO15 PIO04 PIO05 PIO14 Name Description PIO17 P1.7/PWM pin function select 0 = P1.7/PWM3_CH0 pin functions as GPIO P1.7. 1 = P1.7/PWM3_CH0 pin functions as PWM3_CH0 output. PIO15 P1.5/PWM pin function select 0 = P1.5/PWM pin functions as P1.5.
Page 349 MS51 PIOCON2 – PWM or I/O Select Register SFR Address Reset Value PIOCON2 B7H, Page 2 0000_0000 b PIO34 PIO33 PIO32 PIO31 PIO30 PIO23 PIO22 PIO21 Name Description PIO34 P3.4/PWM3_CH1 pin function select 0 = P3.4/PWM3_CH1 pin functions as P3.4. 1 = P3.4/PWM3_CH1 pin functions as PWM3_CH1 output.
Page 350 MS51 AUXR4 – Auxiliary Register 4 Register SFR Address Reset Value AUXR4 A3H, Page 2 0000_0000 b PWM2_CH1P PWM2_CH0P PWM1_CH1P PWM1_CH0P Name Description PWM2_CH1P PWM2 channel 1 pin select 00 = Assign PWM2_CH1 to P3.0 01 = Assign PWM2_CH1 to P3.1 10 = Assign PWM2_CH1 to P0.0 11 = Assign PWM2_CH1 to P0.4 PWM2_CH0P...
Page 351 MS51 AUXR5 – Auxiliary Register 5 Register SFR Address Reset Value AUXR5 A4H, Page 2 0000_0000 b CLOP PWM3_CH1P PWM3_CH0P Name Description PWM3_CH1P PWM3 channel 1 pin select 00 = Reserved by default 01 = Assign PWM3_CH1 to P3.4 10 = Assign PWM3_CH1 to P1.5 11 = Assign PWM3_CH1 to P0.3 PWM3_CH0P PWM3 channel 0 pin select...
Page 352: Table 6.7-1 Watchdog Timer-Out Interval Under Different Pre-Scalars
MS51 6.7 Watchdog Timer (WDT) 6.7.1 Overview The MS51 provides one Watchdog Timer (WDT). It can be configured as a time-out reset timer to reset whole device. Once the device runs in an abnormal status or hangs up by outward interference, a WDT reset recover the system.
Page 353 MS51 Name Description WDTEN[3:0] WDT enable This field configures the WDT behavior after MCU execution. 1111 = WDT is Disabled. WDT can be used as a general purpose timer via software control. 0101 = WDT is Enabled as a time-out reset timer and it stops running during Idle or Power- down mode.
Page 354 MS51 WDCON – Watchdog Timer Control Register SFR Address Reset Value POR 0000_0111 b WDCON AAH, Page 0, TA protected WDT 0000_1UUU b Others 0000_UUUU b WDTR WDCLR WDTF WIDPD WDTRF WDPS[2:0] Name Description WDTR WDT run This bit is valid only when control bits in WDTEN[3:0] (CONFIG4[7:4]) are all 1. At this time, WDT works as a general purpose timer.
Page 355: Figure 6.7-1 Wdt As A Time-Out Reset Timer
MS51 When the CONFIG bits WDTEN[3:0] (CONFIG4[7:4]) is not FH, the WDT is initialized as a time-out reset timer. If WDTEN[3:0] is not 5H, the WDT is allowed to continue running after the system enters Idle or Power-down mode. Note that when WDT is initialized as a time-out reset timer, WDTR and WIDPD has no function.
Page 356 MS51 be set while the WDT completes the selected time interval. The software polls the WDTF flag to detect a time-out. An interrupt will occur if the individual interrupt EWDT (EIE0.4) and global interrupt enable EA is set. WDT will continue counting. User should clear WDTF and wait for the next overflow by polling WDTF flag or waiting for the interrupt occurrence.
Page 357 MS51 6.7.4 Control Registers of Watchdog Timer CONFIG4 WDTEN[3:0] Factory default value: 1111 1111b Name Description WDTEN[3:0] WDT enable This field configures the WDT behavior after MCU execution. 1111 = WDT is Disabled. WDT can be used as a general purpose timer via software control. 0101 = WDT is Enabled as a time-out reset timer and it stops running during Idle or Power- down mode.
Page 358 MS51 WDCON – Watchdog Timer Control Register SFR Address Reset Value POR 0000_0111 b WDCON AAH, Page 0, TA protected WDT 0000_1UUU b Others 0000_UUUU b WDTR WDCLR WDTF WIDPD WDTRF WDPS[2:0] Name Description WDTR WDT run This bit is valid only when control bits in WDTEN[3:0] (CONFIG4[7:4]) are all 1. At this time, WDT works as a general purpose timer.
Page 359: Figure 6.8-1 Self Wake-Up Timer Block Diagram
MS51 6.8 Self Wake-Up Timer (WKT) 6.8.1 Overview The MS51 has a dedicated Self Wake-up Timer (WKT), which serves for a periodic wake-up timer in low power mode or for general purpose timer. WKT remains counting in Idle or Power-down mode. When WKT is being used as a wake-up timer, a start of WKT can occur just prior to entering a power management mode.
Page 360 MS51 6.8.2 Control register of WKT WKCON – Self Wake-up Timer Control Register SFR Address Reset Value WKCON 8FH, Page0 0000_0000b WKTF WKTR WKPS[2:0] Name Description Reserved WKTF WKT overflow flag This bit is set when WKT overflows. If the WKT interrupt and the global interrupt are enabled, setting this bit will make CPU execute WKT interrupt service routine.
Page 361 MS51 RWKL – Self Wake-up Timer Reload Low Byte Register SFR Address Reset Value RWKL 86H, Page 0 0000 0000b RWK[7:0] Name Description RWK[7:0] WKT reload low byte The RWKL register is the low byte of the 16-bit reload value of WKT. Note that RWK should not be FFFFH if the pre-scale is 1/1 for implement limitation.
Page 362 MS51 RWKH – Self Wake-up Timer Reload High Byte Register SFR Address Reset Value RWKH 97H, Page 2 0000 0000b RWK[15:8] Name Description RWK[15:8] WKT reload high byte The RWKH register is the low byte of the 16-bit reload value of WKT. Note that RWK should not be FFFFH if the pre-scale is 1/1 for implement limitation.
Page 363: Figure 6.9-1 Serial Port Mode 0 Timing Diagram
MS51 6.9 Serial Port (UART0 & UART1) 6.9.1 Overview The MS51 includes two enhanced full duplex serial ports enhanced with automatic address recognition and framing error detection. As control bits of these two serial ports are implemented the same. Generally speaking, in the following contents, there will not be any reference to serial port 1, but only to serial port 0.
Page 364: Figure 6.9-2 Serial Port Mode 1 Timing Diagram
MS51 received. Then the received flag RI will be set as 1. User can clear RI to triggering the next byte reception. 6.9.2.2 Mode 1 Mode 1 supports asynchronous, full duplex serial communication. The asynchronous mode is commonly used for communication with PCs, modems or other similar interfaces. In Mode 1, 10 bits are transmitted through TXD or received through RXD including a start bit (logic 0), 8 data bits (LSB first) and a stop bit (logic 1).
Page 365: Figure 6.9-3 Serial Port Mode 2 And 3 Timing Diagram
MS51 Figure 6.9-3 Serial Port Mode 2 and 3 Timing Diagram Transmission is initiated by any writing instructions to SBUF. Transmission takes place on TXD pin. First the start bit comes out, the 8-bit data and bit TB8 (SCON.3) follows to be shifted out and then ends with a stop bit.
Page 366 MS51 Following shows all UART mode and baudrate fomula: Frame SM0 / SM1 SMOD Mode Baud Rate Bits (SCON[7:6]) (SCON[5]) (PCON[7]) FSYS divided by 12 FSYS divided by 2 Time1     TM1 CKCON[3] = 0 Time1  ...
Page 367: Table 6.9-1 Serial Port Uart0 Mode / Baudrate Description
MS51 Note: Timer 1 should configured as a timer in auto-reload mode (Mode 2). Table 6.9-1 Serial Port UART0 Mode / baudrate Description Frame SM0_1 / SM1_1 SMOD_1 Mode Baud Rate Bits (S1CON[7:6]) (T3CON[7]) FSYS divided by 12  Timer 3 ...
Page 368 MS51 RL3 = value low byte T3CON|= 0x08; //Trigger Timer3 Serial port 1 (UART1) use Timer 3 as baudrate generator: Fomula is       scale 65536 (256 RL3) SCON_1 = 0x52; //UART1 Mode1,REN_1=1,TI_1=1 T3CON = 0xF8; //T3PS2=0,T3PS1=0,T3PS0=0(Prescale=1), RH3 = value high byte RL3 = value low byte...
Page 369 MS51 Fsys Value Baud Rate TH1 Value (Hex) RH3,RL3 Value (Hex) Baudrate Deviation 200000 FFFB 0.000000% 250000 FFFC 0.000000% 333333 FFFD 0.000100% 500000 FFFE 0.000000% 1000000 FFFF 0.000000% 6.9.4 Framing Error Detection Framing error detection is provided for asynchronous modes. (Mode 1, 2, or 3.) The framing error occurs when a valid stop bit is not detected due to the bus noise or contention.
Page 370 MS51 6. SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit. For Mode 1 reception, if SM2 is 1, the receiving interrupt will not be issue unless a valid stop bit is received.
Page 371 MS51 In a more complex system the following could be used to select slaves 1 and 2 while excluding slave Example 1, slave 0: SADDR = 11000000b SADEN = 11111001b Given = 11000XX0b Example 2, slave 1: SADDR = 11100000b SADEN = 11111010b Given = 11100X0Xb Example 3, slave 2:...
Page 372 MS51 6.9.7 Control Register of Serial Port SCON – Serial Port Control Register SFR Address Reset Value SCON 98H, All page, Bit addressable 0000_0000 b SM0/FE Name Description SM0/FE Serial port mode select SMOD0 (PCON.6) = 0: See Table 6.9-1 Serial Port UART0 Mode / baudrate Description for details. SMOD0 (PCON.6) = 1: SM0/FE bit is used as frame error (FE) status flag.
Page 373 MS51 Name Description 9th received bit The bit identifies the logic level of the 9th received bit in serial port 0 Mode 2 or 3. In Mode 1, RB8 is the logic level of the received stop bit. SM2 bit as logic 1 has restriction for exception. RB8 is not used in Mode 0.
Page 374 MS51 SCON _ 1 – Serial Port 1 Control Register SFR Address Reset Value SCON _ 1 F8H, All pages, Bit addressable 0000_0000 b SM0_1/FE_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 Name Description SM0_1/FE_1 Serial port 1 mode select SMOD0_1 (T3CON.6) = 0: SM1_1 See Table 6.9-2 Serial Port UART1 Mode / baudrate Description for details.
Page 375 MS51 Name Description TI_1 Transmission interrupt flag This flag is set by hardware when a data frame has been transmitted by the serial port 1 after the 8 bit in Mode 0 or the last data bit in other modes. When the serial port 1 interrupt is enabled, setting this bit causes the CPU to execute the serial port 1 interrupt service routine.
Page 376 MS51 PCON – Power Control Register SFR Address Reset Value POR: 0001_0000b PCON 87H, All pages Others: 000U _0000b SMOD SMOD0 Name Description SMOD Serial port 0 double baud rate enable Setting this bit doubles the serial port baud rate when UART0 is in Mode 2 or when Timer 1 overflow is used as the baud rate source of UART0 Mode 1 or 3.
Page 377 MS51 T3CON – Timer 3 Control Register SFR Address Reset Value T3CON C4H, Page 0 0000_0000 b SMOD_1 SMOD0_1 BRCK T3PS[2:0] Name Description SMOD_1 Serial port 1 double baud rate enable Setting this bit doubles the serial port baud rate when UART1 is in Mode 2. See Table 6.9-1 Serial Port UART0 Mode / baudrate Description for details.
Page 378 MS51 SBUF_1 – Serial Port 1 Data Buffer Register SFR Address Reset Value SBUF_1 9AH, Page 0 0000 _0000 b SBUF_1[7:0] Name Description SBUF_1[7:0] Serial port 1 data buffer This byte actually consists two separate registers. One is the receiving resister, and the other is the transmitting buffer.
Page 379 MS51 IE – Interrupt Enable Register SFR Address Reset Value A8H, All pages, Bit addressable 0000 _0000 b EADC EBOD Name Description Enable serial port 0 interrupt 0 = Serial port 0 interrupt Disabled. 1 = Interrupt generated by TI (SCON.1) or RI (SCON.0) Enabled. Nov.
Page 380 MS51 EIE1 – Extensive Interrupt Enable 1 Register SFR Address Reset Value EIE1 9CH, Page 0 0000 _0000 b EPWM3 EPWM2 EPWM1 EWKT ES _ 1 Name Description Enable serial port 1 interrupt 0 = Serial port 1 interrupt Disabled. 1 = Serial port 1Interrupt Enable.
Page 381 MS51 SADDR – Slave 0 Address Register SFR Address Reset Value SADDR A9H, Page 0 0000 _0000 b SADDR[7:0] Name Description SADDR[7:0] Slave 0 address This byte specifies the microcontroller’s own slave address for UATR0 multi-processor communication. Nov. 28, 2019 Page 381 of 491 Rev 1.00...
Page 382 MS51 SADEN – Slave 0 Address Mask Register SFR Address Reset Value SADEN B9H, Page 0 0000_0000 b SADEN[7:0] Name Description SADEN[7:0] Slave 0 address mask This byte is a mask byte of UART0 that contains “don’t-care” bits (defined by zeros) to form the device’s “Given”...
Page 383 MS51 SADDR_1 – Slave 1 Address Register SFR Address Reset Value SADDR_1 BBH, Page 0 0000_0000 b SADDR _ 1[7:0] Name Description SADDR _ 1[7:0] Slave 1 address This byte specifies the microcontroller’s own slave address for UART1 multi-processor communication. Nov.
Page 384 MS51 SADEN_1 – Slave 1 Address Mask Register SFR Address Reset Value SADEN_1 BAH, Page 0 0000_0000 b SADEN _ 1[7:0] Name Description SADEN _ 1[7:0] Slave 1 address mask This byte is a mask byte of UART1 that contains “don’t-care” bits (defined by zeros) to form the device’s “Given”...
Page 385 MS51 AUXR1 – Auxiliary Register 1 Register SFR Address Reset Value POR: 0000 0000b, Software reset: 1U00 0000b, AUXR1 A2H , Page 0 nRESET pin: U100 0000b, Others: UUU0 0000b SWRF RSTPINF HardF SLOW UART0PX Name Description UART0PX Serial port 0 pin exchange 0 = Assign RXD to P0.7 and TXD to P0.6 by default.
Page 386 MS51 AUXR2 – Auxiliary Register 2 Register SFR Address Reset Value AUXR2 A1H, Page 2 0000_0000 b UART2TXP UART2RXP UART1TXP UART1RXP Name Description UART1TXP UART1 TX pin select 00 = Reserved by default 01 = Assign UART1 TX to P1.6 10 = Assign UART1 TX to P3.6 11 = Assign UART1 TX to P1.0 UART1RXP...
Page 387: Figure 6.10-1 Sc Controller Block Diagram
MS51 6.10 ISO 7816-3 Interface (SC0~2 & UART2 ~ 4) 6.10.1 Overview The MS51 32K series provides ISO 7816-3 Interface controller (SC controller) with asynchronous protocal based on ISO/IEC 7816-3 standard. Software controls GPIO pins as the smartcard reset function and card detection function. This controller also provides UART emulation for high precision baud rate communication.
Page 388: Table 6.10-1 Smart Card Or Uart Pin Define And Enable Control Register
MS51 SFR Define URAT Pin SC Pin Pin Name SFR Byte Name SFR Bit Name Value P1.7 P1.2 UART3_TXD SC1_CLK P1.5 AUXR3[3:2] UART3TXP P0.5 P1.1 UART3_RXD SC1_DAT P2.5 AUXR3[1:0] UART3RXP P3.4 UART4_TXD SC2_CLK P2.3 AUXR3[7:6] UART4TXP UART4_RXD SC2_DAT P2.2 AUXR3[5:4] UART4RXP Table 6.10-1 Smart Card or UART Pin Define And Enable Control Register 6.10.2 Operating Modes...
Page 389 MS51 Smart Card SC_CLK SC_CLK PORT SC_DAT SC_DAT SC_RST SC_RST SC Power Control Circuit SC_PWR SC_PWR PORT Card Detect SC_CD Mechanism Figure 6.10 SC Interface Connection Activation and Cold Reset The activation and cold reset sequence is shown in Figure 15.3-2 1.
Page 390 MS51 The warm reset sequence is showed in Figure 15.3-3 1. Set SCn_RST to low by software programming to ‘0’ before timing T4. 2. Set SCn_DAT to high by software programming to ‘1’ period of timing T4. 3. Set SCn_RST to high by software programming to ‘1’ after timing T5. 4.
Page 391: Figure 6.10-2 Sc Data Character
MS51 SC_PWR SC_CLK SC_RST Undefined SC_DAT Time Comment Unit SC Clock Deactivation Trigger to SC_RST Low SMC_ RST Low to Stop SC _CLK Stop SC_CLK to Stop SC_PWR Figure 6.10 SC Deactivation Sequence 6.10.2.2 UART Mode When the UARTEN (SCnCR2[0]) bit is set, the ISO 7816-3 Interface controller can also be used as basic UART function.
Page 392: Figure 6.10-3 Initial Character Ts
MS51 received TS of answer to request (ATR). If auto convention function is enabled by setting AUTOCEN (SCnCR1[3]) register, the setting step must be done before Answer to Request state and the first data must be 0x3B or 0x3F. After hardware received first data and stored it at buffer, the hardware will decided the convention and change the CONSEL (SCnCR1[4]) register automatically.
Page 393: Figure 6.10-5 Transmit Direction Block Guard Time Operation
MS51 In transmit direction, the ISO 7816 sends data to ISO 7816-3 host controller, first. After the period is greater than (16.5 or 22.5, by T bit setting), the ISO 7816-3 host controller begin to send the data. Last Receiver Data Transmitter Data Block Guard Time Figure 6.10-5 Transmit Direction Block Guard Time Operation...
Page 394 MS51 6.10.7 Control Registers of SC Controller SCnCR0 – SC Control Register 0 Register SFR Address Reset Value SC0CR0 F1H, Page 2 0000_0000 b SC1CR0 F3H, Page 2 0000_0000 b SC2CR0 F5H, Page 2 0000_0000 b RXBGTEN CONSEL AUTOCEN TXOFF RXOFF SCEN Name...
Page 395 MS51 Name Description AUTOCEN Auto Convention Enable Bit 0 = Auto-convention Disabled. 1 = Auto-convention Enabled. When hardware receives TS in answer to reset state and the TS is direct convention, CONSEL(SCnCR0[4]) will be set to 0 automatically, otherwise if the TS is inverse convention, and CONSEL (SCnCR0[4]) will be set to 1.
Page 396 MS51 SCnCR1 – SC Control Register Register SFR Address Reset Value SC0CR1 F2H, Page 2 0000_0000 b SC1CR1 F4H, Page 2 0000_0000 b SC2CR1 F6H, Page 2 0000_0000 b PBOFF TXDMAEN RXDMAEN CLKKEEP UARTEN Name Description Odd Parity Enable Bit 0 = Even number of logic 1’s are transmitted or check the data word and parity bits in receiving mode.
Page 397 MS51 Name Description UARTEN UART Mode Enable Bit 0 = ISO 7816-3 mode. 1 = UART mode. Note 1:When operating in UART mode, user must set CONSEL (SCnCR0[4]) = 0 and AUTOCEN(SCnCR0[3]) = 0. Note 2:When operating in ISO 7816-3 mode, user must set UARTEN(SCnCR1 [0]) = 0. Note 3:When UART is enabled, hardware will generate a reset to reset FIFO and internal state machine.
Page 398 MS51 SCnDR – SC Data Register Register SFR Address Reset Value SC0DR D9H, Page 2 0000_0000 b SC1DR E1H, Page 2 0000_0000 b SC2DR E9H, Page 2 0000_0000 b SCnDR[7:0] Name Description SCnDR[7:0] SC / UART buffer data This byte is used for transmitting or receiving data on SC / UART bus. A write of this byte is a write to the shift register.
Page 399 MS51 SCnEGT – SC Extra Guard Time Register Register SFR Address Reset Value SC0EGT DAH, Page 2 0000_0000 b SC1EGT E2H, Page 2 0000_0000 b SC2EGT EAH, Page 2 0000_0000 b SCnEGT[7:0] Name Description SCnEGT[7:0] SC Extra Guard Time This field indicates the extra guard timer value. Note: The counter is ETU base .
Page 400 MS51 SCnETURD0 – SCn ETU Rate Divider Register Register SFR Address Reset Value SC0ETURD0 DBH, Page 2 0111_0011 b SC1ETURD0 E3H, Page 2 0111_0011 b SC2ETURD0 EBH, Page 2 0111_0011 b ETURDIV[7:0] Name Description ETURDIV[7:0] LSB bits of ETU Rate Divider The field indicates the LSB of clock rate divider.
Page 401 MS51 SCnETURD1 –SC ETU Rate Divider Register Register SFR Address Reset Value SC0ETURD1 DCH, Page 2 0011_0001 b SC1ETURD1 E4H, Page 2 0011_0001 b SC2ETURD1 ECH, Page 2 0011_0001 b SCDIV[2:0] ETURDIV[11:8] Name Description Reserved SCDIV SC clock divider [2:0] 000 = F is F 001 = F...
Page 402 MS51 ScnIE – SC Interrupt Enable Control Register Register SFR Address Reset Value SC0IE DCH, Page 2 0000_0000 b SC1IE E4H, Page 2 0000_0000 b SC2IE ECH, Page 2 0000_0000 b ACERRIEN BGTIEN TERRIEN TBEIEN RDAIEN Name Description Reserved ACERRIEN Auto Convention Error Interrupt Enable Bit This field is used to enable auto-convention error interrupt.
Page 403 MS51 ScnIS – SC Interrupt Status Register Register SFR Address Reset Value SC0IS DEH, Page 2 0000_0010 b SC1IS E6H, Page 2 0000_0010 b SC2IS EEH, Page 2 0000_0010 b ACERRIF BGTIF TERRIF TBEIF RDAIF Name Description Reserved ACERRIF Auto Convention Error Interrupt Status Flag (Read Only) This field indicates auto convention sequence error.
Page 404 MS51 SCnTSR – SC Transfer Status Register Register SFR Address Reset Value SC0TSR DFH, Page 2 0000_1010 b SC1TSR E7H, Page 2 0000_1010 b SC2TSR EFH, Page 2 0000_1010 b TXEMPTY TXOV RXEMPTY RXOV Name Description Transmit /Receive in Active Status Flag (Read Only) 0 = This bit is cleared automatically when TX/RX transfer is finished 1 = This bit is set by hardware when TX/RX transfer is in active.
Page 405 MS51 Name Description RXOV RX Overflow Error Status Flag (Read Only) This bit is set when RX buffer overflow. Note: This bit is read only, but it can be cleared by writing 0 to it. Nov. 28, 2019 Page 405 of 491 Rev 1.00...
Page 406 MS51 AUXR2 – Auxiliary Register 2 Register SFR Address Reset Value AUXR2 A1H, Page 2 0000_0000 b UART2TXP UART2RXP UART1TXP UART1RXP Name Description UART2TXP UART2 TX pin select 00 = Reserved by default 01 = Assign UART2 TX to P0.3 10 = Assign UART2 TX to P3.0 11 = Reserved UART2RXP...
Page 407 MS51 AUXR3 – Auxiliary Register 3 Register SFR Address Reset Value AUXR3 A2H, Page 2 0000_0000 b UART4TXP UART4RXP UART3TXP UART3RXP Name Description UART4TXP UART4 TX pin select 00 = Reserved by default 01 = Assign UART4 TX to P2.3 10 = Reserved 11 = Reserved UART4RXP...
Page 408: Figure 6.11-1 I 2 C Bus Interconnection
MS51 6.11 Inter-Integrated Circuit (I 6.11.1 Overview The MS51 provides two Inter-Integrated Circuit (I C) bus to serves as an serial interface between the microcontrollers and the I C devices such as EEPROM, LCD module, temperature sensor, and so on. The I C bus used two wires design (a serial data line I2C0_SDA and a serial clock line I2C0_SCL) to transfer information between devices.
Page 409: Figure 6.11-2 I 2 C Bus Protocol
MS51 START STOP condition condition Figure 6.11-2 I C Bus Protocol 6.11.2.1 START and STOP Condition The protocol of the I C bus defines two states to begin and end a transfer, START (S) and STOP (P) conditions. A START condition is defined as a high-to-low transition on the I2C0_SDA line while I2C0_SCL line is high.
Page 410: Figure 6.11-4 Master Transmits Data To Slave By 7-Bit
MS51 SLAVE ADDRESS DATA DATA data transfer ‘0’ : write (n bytes + acknowlegde) from master to slave A = acknowledge (SDA low) A = not acknowledge (SDA high) S = START condition from slave to master P = STOP condition Figure 6.11-4 Master Transmits Data to Slave by 7-bit Figure 6.11-5 shows a master read data from slave by 7-bit.
Page 411: Figure 6.11-7 Acknowledge Bit
MS51 I2C0_SDA line should be left high by the slave so that the mater can generate a STOP or a repeated START condition. If a slave-receiver does acknowledge the slave address, it switches itself to not addressed slave mode and cannot receive any more data bytes. This slave leaves the I2C0_SDA line high. The master should generate a STOP or a repeated START condition.
Page 412: Figure 6.11-9 Control I
MS51 Since control of the I C bus is decided solely on the address or master code and data sent by competing masters, there is no central master, nor any order of priority on the bus. Slaves are not involved in the arbitration procedure. 6.11.2.5 Operation Modes The on-chip I...
Page 413: Figure 6.11-10 Flow And Status Of Master Transmitter Mode
MS51 to terminate the transmission. A repeated START condition can also be generated without sending STOP condition to immediately initial another transmission. ACK STATUS=0x18 ACK STATUS=0x28 STATUS=0x08 NAK STATUS=0x20 NAK STATUS=0x30 I2CnDAT ACK/ I2CnDAT ACK/ (SLA+W) (Data) I2CnDAT =SLA+W I2CnDAT =Data (STA,STO,SI,AA)=(1,0,1,x) (STA,STO,SI,AA)=(0,0,1,x) (STA,STO,SI,AA)=(0,0,1,x)
Page 414: Figure 6.11-11 Flow And Status Of Master Receiver Mode
MS51 Master Receiver Mode In the master receiver mode, several bytes of data are received from a slave transmitter. The transaction is initialized just as the master transmitter mode. Following the START condition, I2CnDAT should be loaded with the target slave address and the data direction bit “read” (SLA+R). After the SLA+R byte is transmitted and an acknowledge bit has been returned, the SI flag is set again and I2CnSTAT is read as 40H.
Page 415 MS51 Slave Receiver In the slave receiver mode, several bytes of data are received form a master transmitter. Before a transmission is commenced, I2CnADDRx should be loaded with the address to which the device will respond when addressed by a master. I2CnCLK does not affect in slave mode. The AA bit should be set to enable acknowledging its own slave address.
Page 416: Figure 6.11-12 Flow And Status Of Slave Receiver Mode
MS51 Switch to not addressed mode STATUS=0x60 STATUS=0x80 Own SLA will be recognized I2CnDAT I2CnDAT (Data) (SLA+W) STATUS=0x88 (STA,STO,SI,AA)=(0,0,1,1) (STA,STO,SI,AA)=(0,0,1,1) (Arbitration Lost) STATUS=0x68 I2CnDAT I2CnDAT (Data) (SLA+W) (STA,STO,SI,AA)=(0,0,1,0) STATUS=0xA8 STATUS=0xA0 I2CnDAT (SLA+R) (STA,STO,SI,AA)=(0,0,1,X) (Arbitration Lost) STATUS=0xA0 STATUS=0xB0 I2CnDAT (SLA+R) (STA,STO,SI,AA)=(0,0,1,1) (STA,STO,SI,AA)=(0,0,1,X) STATUS=0xB8 Switch to not addressed mode...
Page 417: Figure 6.11-13 Flow And Status Of General Call Mode
MS51 Switch to not addressed mode Address 0x0 will be recognized STATUS=0x70 STATUS=0x90 I2CnDAT I2CnDAT (SLA+W=0x00) (Data) (STA,STO,SI,AA)=(0,0,1,1) GC=1 (STA,STO,SI,AA)=(0,0,1,1) (Arbitration Lost) STATUS=0x98 STATUS=0x78 I2CnDAT I2CnDAT (SLA+W=0x00) (Data) (STA,STO,SI,AA)=(0,0,1,0) STATUS=0xA0 (STA,STO,SI,AA)=(0,0,1,X) STATUS=0xA0 (STA,STO,SI,AA)=(0,0,1,X) (STA,STO,SI,AA)=(0,0,1,1) Switch to not addressed mode Own SLA will be recognized Send START when bus free Become I C Master...
Page 418 MS51 There is a special case if a START or a repeated START condition is not successfully generated for C bus is obstructed by a low level on I2C0_SDA line e.g. a slave device out of bit synchronization, the problem can be solved by transmitting additional clock pulses on the I2C0_SCL line. The I hardware transmits additional clock pulses when the STA bit is set, but no START condition can be generated because the I2C0_SDA line is pulled low.
Page 419 MS51 STO = 1; //recover from bus error break; //=========== //Master Mode //=========== case 0x08: /*08H, a START transmitted*/ STA = 0; //STA bit should be cleared by software I2DAT = SLA_ADDR1; //load SLA+W/R break; case 0x10: /*10H, a repeated START transmitted*/ STA = 0;...
Page 420 MS51 STO = 1; AA = 1; break; //==================================== //Slave Receiver and General Call Mode //==================================== case 0x60: /*60H, own SLA+W received, ACK returned*/ AA = 1; break; case 0x68: /*68H, arbitration lost in SLA+W/R own SLA+W received, ACK returned */ AA = 0;...
Page 421 MS51 AA = 1; break; //====================== //Slave Transmitter Mode //====================== case 0Xa8: /*A8H, own SLA+R received, ACK returned*/ I2DAT = NEXT_SEND_DATA3; AA = 1; //when AA is “1”, not last data to be //transmitted break; case 0Xb0: /*B0H, arbitration lost in SLA+W/R own SLA+R received, ACK returned */ I2DAT = DUMMY_DATA;...
Page 422: Figure 6.11-14 I 2 C Time-Out Counter
MS51 14-bit I C Time-out Counter I2TOF Clear Counter I2CEN I2TOCEN Figure 6.11-14 I C Time-Out Counter 6.11.5 I C Interrupt There are two I C flags, SI and I2TOF. Both of them can generate an I C event interrupt requests. If C interrupt mask is enabled via setting EI C and EA as 1, CPU will execute the I C interrupt service...
Page 423 MS51 6.11.6 Control Registers of I There are five control registers to interface the I C bus including I2CON, I2STAT, I2DAT, I2ADDR, and I2CLK. These registers provide protocol control, status, data transmitting and receiving functions, and clock rate configuration. For application flexibility, I2C0_SDA and I2C0_SCL pins can be exchanged by I2CPX (I2CON.0).
Page 424: Figure 6.11-15 Hold Time Extend Enable
MS51 Name Description C interrupt flag SI flag is set by hardware when one of 26 possible I C status (besides F8H status) is entered. After SI is set, the software should read I2STAT register to determine which step has been passed and take actions for next step.
Page 425 MS51 I2STAT – I C Status Register SFR Address Reset Value I2STAT BDH, Page 0 1111 1000 b I2STAT[7:3] Name Description I2STAT[7:3] C status code The MSB five bits of I2STAT contains the status code. There are 27 possible status codes. When I2STAT is F8H, no relevant state information is available and SI flag keeps 0.
Page 426 MS51 I2ADDR – I C Own Slave Address Register SFR Address Reset Value I2ADDR C1H, Page 0 0000_0000 b I2ADDR[7:1] Name Description I2ADDR[7:1] C device’s own slave address In master mode: These bits have no effect. In slave mode: These 7 bits define the slave address of this I C device by user.
Page 427 MS51 I2CLK – I C Clock Register SFR Address Reset Value I2CLK BEH, Page 0 0000_1001 b I2CLK[7:0] Name Description I2CLK[7:0] C clock setting In master mode: This register determines the clock rate of I C bus when the device is in a master mode. The clock rate follows the equation, ×...
Page 428 MS51 I2TOC – I C Time-out Counter Register SFR Address Reset Value I2TOC BFH, Page 0 0000_0000 b I2TOCEN I2TOF Name Description I2TOCEN C time-out counter enable 0 = I C time-out counter Disabled. 1 = I C time-out counter Enabled. Note: please always enable I C interrupt when enable I C time-out counter function...
Page 429: Figure 6.12-1 Spi Block Diagram
MS51 6.12 Serial Peripheral Interface (SPI) 6.12.1 Overview The MS51 provides two Serial Peripheral Interface (SPI) block to support high-speed serial communication. SPI is a full-duplex, high-speed, synchronous communication bus between microcontrollers or other peripheral devices such as serial EEPROM, LCD driver, or D/A converter. It provides either Master or Slave mode, high-speed rate up to , transfer complete and write collision flag.
Page 430: Figure 6.12-2 Spi Multi-Master, Multi-Slave Interconnection
MS51 Respectively, the MISO is used to receive a serial data from the Slave to the Master. The SPCLK pin is the clock output in Master mode, but is the clock input in Slave mode. The shift clock is used to synchronize the data movement both in and out of the devices through their MOSI and MISO pins.
Page 431 MS51 Figure 6.12-3 shows the simplest SPI system interconnection, single-master and signal-slave. During a transfer, the Master shifts data out to the Slave via MOSI line. While simultaneously, the Master shifts data in from the Slave via MISO line. The two shift registers in the Master MCU and the Slave MCU can be considered as one 16-bit circular shift register.
Page 432: Figure 6.12-4 Spi Clock Formats
MS51 Clock Phase (CPHA) CPHA = 0 CPHA = 1 sample sample sample sample Figure 6.12-4 SPI Clock Formats In SPI, a Master device always initiates the transfer. If SPI is selected as Master mode (MSTR = 1) and enabled (SPIEN = 1), writing to the SPI data register (SPInDR) by the Master device starts the SPI clock and data transfer.
Page 433: Figure 6.12-5 Spi Clock And Data Format With Cpha = 0
MS51 SPCLK Cycles SPCLK Cycles SPCLK (CPOL=0) SPCLK (CPOL=1) Transfer Progress (internal signal) MOSI MISO Input to Slave SS SS output of Master SPIF (Master) SPIF (Slave) Transfer progress starts by a writing SPDR of Master MCU. SS automatic output affects when MSTR = DISMODF = SSOE = 1. Figure 6.12-5 SPI Clock and Data Format with CPHA = 0 SPCLK Cycles SPCLK Cycles...
Page 434 MS51 6.12.4 Slave Select Pin Configuration ̅̅̅̅̅ The MS51 SPI gives a flexible SS pin feature for different system requirements. When the SPI ̅̅̅̅̅ ̅̅̅̅̅ operates as a Slave, SS pin always rules as Slave select input. When the Master mode is enabled, SS has three different functions according to DISMODF (SPInSR.3) and SSOE (SPInCR.7).
Page 435: Figure 6.12-7 Spi Overrun Waveform
MS51 Data[n] Receiving Begins Data[n+1] Receiving Begins Data[n+2] Receiveing Begins Shift Register Shifting Data[n] in Shifting Data[n+1] in Shifting Data[n+2] in SPIF Read Data Buffer Data[n] Data[n] Data[n+2] SPIOVF When Data[n] is received, the SPIF will be set. If SPIF is not clear before Data[n+1] progress done, the SPIOVF will be set.
Page 436 MS51 6.12.9 Control Register of SPI SPCR – Serial Peripheral Control Register Register SFR Address Reset Value SPCR F3H, Page 0 0000_0000 b SSOE SPIEN LSBFE MSTR CPOL CPHA SPR1 SPR0 Name Description Slave select output enable ̅̅̅̅ pin as This bit is used in combination with the DISMODF (SPSR.3) bit to determine the feature of SS shown in Table 6.12-1 Slave Select Pin Configurations.
Page 437 MS51 Name Description SPR[1:0] SPI clock rate select These two bits select four grades of SPI clock divider. The clock rates below are illustrated under F = 16 MHz condition. Fsys = 16 MHz SPR1 SPR0 Divider SPI clock rate 8M bit/s 4M bit/s 2M bit/s...
Page 438: Table 6.12-1 Slave Select Pin Configurations
MS51 SPCR2 – Serial Peripheral Control Register 2 Register SFR Address Reset Value SPCR2 F3H, Page 1 0000_0000 b SPIS1 SPIS0 Name Description Reserved SPIS[1:0] SPI Interval time selection between adjacent bytes SPIS[1:0] and CPHA select eight grades of SPI interval time selection between adjacent bytes.
Page 439 MS51 SPSR – Serial Peripheral Status Register Register SFR Address Reset Value SPSR F4H, Page 0 0000_0000 b SPIF WCOL SPIOVF MODF DISMODF TXBUF Name Description SPIF SPI complete flag This bit is set to logic 1 via hardware while an SPI data transfer is complete or an receiving data has been moved into the SPI read buffer.
Page 440 MS51 SPDR – Serial Peripheral Data Register Register SFR Address Reset Value SPDR F5H, Page 0 0000_0000 b SPDR[7:0] Name Description SPDR[7:0] Serial peripheral data This byte is used for transmitting or receiving data on SPI bus. A write of this byte is a write to the shift register.
Page 441: Figure 6.13-1 12-Bit Adc Block Diagram
MS51 6.13 12-Bit Analog-To-Digital Converter (ADC) 6.13.1 Overview The MS51 32K series is embedded with a 12-bit SAR ADC. The ADC (analog-to-digital converter) allows conversion of an analog input signal to a 12-bit binary representation of that signal. The MS51 32K series is selected as 8-channel inputs in single end mode.
Page 442 MS51 selected ADC analog input pins pure analog inputs to allow external feeding of the analog voltage signals. Also, the ADC clock rate needs to be considered carefully. The ADC maximum clock frequency is listed in ADC Analog Electrical Characteristics. Clock above the maximum clock frequency degrades ADC performance unpredictably.
Page 443 MS51 Following shows the multi function define of ADC. Group Pin Name GPIO Description ADC_CH0 P1.7 ADC_ channel analog input. ADC_CH1 P3.0 ADC_ channel analog input. ADC_CH2 P0.7 ADC_ channel analog input. ADC_CH3 P0.6 ADC_ channel analog input. ADC_CH4 P0.5 ADC_ channel analog input.
Page 444: Figure 6.13-2 External Triggering Adc Circuit
MS51 [00] PWM0CH0 [01] PWM0CH2 External ADCDLY PWM0CH4 Trigger [10] STADC [11] PTRGSEL[1:0] (ADCCON0[5:4]) PTRGTYP[1:0] (ADCCON1[3:2]) Figure 6.13-2 External Triggering ADC Circuit 6.13.2.3 ADC Conversion Result Comparator The MS51 32K series ADC has a digital comparator, which compares the A/D conversion result with a 12-bit constant value given in ACMPH and ACMPL registers.
Page 445: Figure 6.13-4 Adc Continues Mode With Dma
MS51 Formula as following For example: Read the 2 bytes value after the UID address, wherein the first byte value is 0x64, and the second byte value is 0x0E, merged as 0x64E = 1614. The conversion result is as follows: Band-gap as ADC input to calculate the V value: MS51 internal embedded band-gap voltage also can be the internal ADC input.
Page 446 MS51 2. Set CONT (ADCCON1.4)to one for set ADC into continues conversion mode. 3. Set ADCBAH and ADCBAL registers to configure store address of conversion result. 4. Set ADCCN register to configure ADC conversion count. 5. Set HIE/FIE (ADCCON1[5]) to enable ADC conversion half done interrupt. (optional) 6.
Page 447 MS51 6.13.3 Control Registers of ADC ADCCON0 – ADC Control 0 (Bit-addressable) Register SFR Address Reset Value ADCCON0 E8H, all page 0000_0000b ADCF ADCS ETGSEL1 ETGSEL0 ADCHS3 ADCHS2 ADCHS1 ADCHS0 Name Description ADCF ADC flag This flag is set when an A/D conversion is completed. The ADC result can be read. While this flag is 1, ADC cannot start a new converting.
Page 448 MS51 Name Description ADCHS[3:0] A/D converting channel select This filed selects the activating analog input source of ADC. If ADCEN is 0, all inputs are disconnected. 0000 = ADC_CH0 0001 = ADC_CH1. 0010 = ADC_CH2. 0011 = ADC_CH3. 0100 = ADC_CH4. 0101 = ADC_CH5.
Page 449 MS51 ADCCON1 – ADC Control 1 Register SFR Address Reset Value ADCCON1 E1H, Page 0 0000_0000 b OCEN STADCPX ADCDIV[1:0] ETGTYP[1:0] ADCEX ADCEN Name Description OCEN ADC Offset Calibration Enable register This field is used to enable offset calibration function. 0: ADC Offset Calibration is enabled, auto-calibration by ADC hardware.
Page 450 MS51 ADCCON2 – ADC Control 2 Register SFR Address Reset Value ADCCON2 E2H, Page 0 0000_0000 b ADFBEN ADCMPOP ADCMPEN ADCMPO ADCAQT0[2:0] ADCDLY.8 Name Description ADFBEN ADC compare result asserting Fault Brake enable 0 = ADC asserting Fault Brake Disabled. 1 = ADC asserting Fault Brake Enabled.
Page 451 MS51 ADCCON3 – ADC Control 3 Register SFR Address Reset Value ADCCON3 86H, Page 2 0000_0000 b CONT ADCAQT1[2:0] SLOW Name Description ADC Half Done Interrupt Enable 0 = ADC interrupt is not set while half of A/D conversions are complete in continue mode 1 = ADC interrupt is set while half of A/D conversions are complete in continue mode CONT ADC Continue Sampling select...
Page 452 MS51 ADCDLY – ADC Trigger Delay Counter Register SFR Address Reset Value ADCDLY E3H, Page 0 0000_0000 b ADCDLY[7:0] Name Description ADCDLY[7:0] ADC external trigger delay counter low byte This 8-bit field combined with ADCCON2.0 forms a 9-bit counter. This counter inserts a delay after detecting the external trigger.
Page 453 MS51 AINDIDS0 – ADC Channel Digital Input Disconnect Register SFR Address Reset Value AINDIDS0 F6H, Page 0 0000_0000 b P11DIDS P03DIDS P04DIDS P05DIDS P06DIDS P07DIDS P30DIDS P17DIDS Name Description AINnDIDS ADC Channel digital input disable 0 = Enabled digital input at ADC channel n. 1 = Disabled digital input at ADC channel n .
Page 454 MS51 AINDIDS1 – ADC Channel Digital Input Disconnect Register SFR Address Reset Value AINDIDS1 99H, Page 2 0000_0000 b P25DIDS P14DIDS P13DIDS P24DIDS P23DIDS P22DIDS P21DIDS Name Description PnnDIDS ADC Channel digital input disable 0 = ADC channel n digital input Enabled. 1 = ADC channel n digital input Disabled.
Page 455 MS51 ADCRH – ADC Result High Byte Register SFR Address Reset Value ADCRH C3H, Page 0 0000_0000 b ADCR[11:4] Name Description ADCR[11:4] ADC result high byte The most significant 8 bits of the ADC result stored in this register. Nov. 28, 2019 Page 455 of 491 Rev 1.00...
Page 456 MS51 ADCRL – ADC Result Low Byte Register SFR Address Reset Value ADCRL C2H, Page 0 0000_0000 b ADCR[3:0] Name Description Reserved ADCR[3:0] ADC result low byte The least significant 4 bits of the ADC result stored in this register. Nov.
Page 457 MS51 ADCMPH – ADC Compare High Byte Register SFR Address Reset Value ADCMPH CFH, Page 0 0000_0000 b ADCMP[11:4] Name Description ADCMP[11:4] ADC compare high byte The most significant 8 bits of the ADC compare value stores in this register. Nov.
Page 458 MS51 ADCMPL – ADC Compare Low Byte Register SFR Address Reset Value ADCMPL CEH, Page 0 0000_0000 b ADCMP[3:0] Name Description Reserved ADCMP[3:0] ADC compare low byte The least significant 4 bits of the ADC compare value stores in this register. Nov.
Page 459 MS51 ADCBAH – ADC RAM Base Address High Byte Register SFR Address Reset Value ADCBAH 84H, Page 2 0000_0000 b ADCBAH[3:0] Name Description Reserved ADCBAH[3:0] ADC RAM base address (High byte) The most significant 4 bits of RAM base address to store ADC continue sampling data. RAM base address ADCBA[11:0] = {ADCBAH[3:0], ADCBAL[7:0]} Nov.
Page 460 MS51 ADCBAL – ADC RAM Base Address Low Byte Register SFR Address Reset Value ADCBAL 85H, Page 2 0000_0000 b ADCBAL[7:0] Name Description ADCBAL[7:0] ADC RAM base address (Low byte) The least significant 8 bits of RAM base address to store ADC continue sampling data. RAM base address ADCBA[11:0] = {ADCBAH[3:0], ADCBAL[7:0]} Nov.
Page 461 MS51 ADCSN – ADC Sampling Number Register SFR Address Reset Value ADCSN 8DH, Page 2 0000_0000 b ADCSN[7:0] Name Description ADCSN[7:0] ADC Sampling Number The total sampling numbers for ADC continue sampling select. Total sampling number= ADCSN[7:0] + 1 Nov. 28, 2019 Page 461 of 491 Rev 1.00...
Page 462 MS51 ADCCN – ADC Current Sampling Number Register SFR Address Reset Value ADCCN 8EH, Page 2 0000_0000 b ADCCN[7:0] Name Description ADCCN[7:0] ADC Current Sampling Number The current sampling numbers for ADC continue sampling select. The current sampling number= ADCCN[7:0] + 1 Nov.
Page 463 MS51 ADCSR – ADC Status Register Register SFR Address Reset Value ADCSR 8FH, Page 2 0000_0000 b CMPHIT HDONE FDONE Description [7:3] Reserved Reserved CMPHIT ADC comparator Hit Flag This bit is set by hardware when ADCMPO (ADCCON2.4) flag rising Note: This bit can be cleared by writing 0 to it.
Page 464 MS51 AUXR1 – Auxiliary Register 1 Register SFR Address Reset Value POR: 0000 0000b, Software reset: 1U00 0000b, AUXR1 A2H , Page 0 nRESET pin: U100 0000b, Others: UUU0 0000b SWRF RSTPINF HardF SLOW UART0PX Name Description ADC Slow Speed Selection SLOW This bit is used to select ADC low speed.
Page 465 MS51 6.14 Auxiliary Features 6.14.1 Dual DPTRs The original 8051 contains one DPTR (data pointer) only. With single DPTR, it is difficult to move data form one address to another with wasting code size and low performance. The MS51 provides two data pointers.
Page 466 MS51 DPL – Data Pointer Low Byte Register SFR Address Reset Value 82H, All pages 0000_0000b DPL[7:0] Name Description DPL[7:0] Data pointer low byte This is the low byte of 16-bit data pointer. DPL combined with DPH serve as a 16-bit data pointer DPTR to access indirect addressed RAM or Program Memory.
Page 467 MS51 DPH – Data Pointer High Byte Register SFR Address Reset Value 83H, All pages 0000_0000b DPH[7:0] Name Description DPH[7:0] Data pointer high byte This is the high byte of 16-bit data pointer. DPH combined with DPL serve as a 16-bit data pointer DPTR to access indirect addressed RAM or Program Memory.
Page 468 MS51 AUXR1 – Auxiliary Register 1 Register SFR Address Reset Value POR: 0000 0000b, Software reset: 1U00 0000b, AUXR1 A2H , Page 0 nRESET pin: U100 0000b, Others: UUU0 0000b SWRF RSTPINF HardF SLOW UART0PX Name Description General purpose flag 2 The general purpose flag that can be set or cleared by the user via software.
Page 469: Figure 7.1-1 Numicro Ms51 Power Supply Circuit
MS51 APPLICATION CIRCUIT Power Supply Scheme EXT_PWR 10uF+0.1uF MS51 Series as close to the EXT_PWR as possible EXT_VSS 0.1uF*N as close to VDD as possible ® Figure 7.1-1 NuMicro MS51 Power supply circuit Nov. 28, 2019 Page 469 of 491 Rev 1.00...
Page 470: Figure 7.2-1 Numicro
MS51 7.2 Peripheral Application Scheme DVCC SPI_SS DVCC SPI_CLK Device ICE / ICP SPI_MISO MISO Interface SPI_MOSI MOSI 100K 100K ICE_DAT 100 * DVCC 100 * ICE_CLK DVCC nRESET MS51 Series 4.7K 4.7K Device I2C_SCL DVCC I2C_SDA nRESET Reset 10 uF Circuit RS 232 Transceiver UART_RXD...
Page 471 MS51 7.3 System Reset The system reset can be issued by one of the events listed below. These reset event flags can be read from several register to determine the reset source. Hardware reset sourcces are from peripheral signals. Software reset can trigger reset through setting control registers. ...
Page 472: Figure 7.3-1 Nreset Reset Waveform
MS51 Name Description Power-on reset flag This bit will be set as 1 after a power-on reset. It indicates a cold reset, a power-on reset complete. This bit remains its value after any other resets. This flag is recommended to be cleared via software.
Page 473: Figure 7.3-2 Low Voltage Reset (Lvr) Waveform
MS51 ( < LVRDGSEL) ( =LVRDGSEL) ( =LVRDGSEL) Low Voltage Reset 200 us Delay for LVR stable LVREN Figure 7.3-2 Low Voltage Reset (LVR) Waveform 7.3.1.4 Brown-Out Reset The brown-out detection circuit is used for monitoring the V level during execution. When V drops to the selected brown-out trigger level (V ), the brown-out detection logic will reset the MCU if...
Page 474 MS51 7.3.1.5 External Reset and Hard Fault Reset The external reset pin nRESET is an input with a Schmitt trigger. An external reset is accomplished by holding the nRESET pin low for at least 24 system clock cycles to ensure detection of a valid hardware reset signal.
Page 475 MS51 Name Description HardF Hard Fault reset flag Once CPU fetches instruction address over Flash size while EHFI (EIE1.4)=0, MCU will reset and this bit will be set via hardware. It is recommended that the flag be cleared via software. Note: If MCU run in OCD debug mode and OCDEN = 0, Hard fault reset will disable.
Page 476: Figure 7.3-3 Power-On Reset (Por) Waveform
MS51 0.1V Power-on Reset Figure 7.3-3 Power-on Reset (POR) Waveform 7.3.1.8 Low Voltage Reset (LVR) If the Low Voltage Reset function is enabled by setting the Low Voltage Reset Enable Bit LVREN (SYS_BODCTL[7]) to 1, after 200us delay, LVR detection circuit will be stable and the LVR function will be active.
Page 477: Figure 7.3-5 Brown-Out Detector (Bod) Waveform
MS51 default value of BODEN, BODVL and BODRSTEN (SYS_BODCTL[3]) is set by Flash controller user configuration register CBODEN (CONFIG0 [19]), CBOV (CONFIG0 [23:21]) CBORST(CONFIG0[20]) respectively. User can determine the initial BOD setting by setting the CONFIG0 register. Figure 7.3-5 shows the Brown-out Detector waveform. BODH Hysteresis BODL...
Page 478 MS51 ELECTRICAL CHARACTERISTICS Please refer to the relative Datasheet for detailed information about the MS51 electrical characteristics. Nov. 28, 2019 Page 478 of 491 Rev 1.00...
Page 479: Figure 9.1-1 Qfn-33 Package Dimension
MS51 PACKAGE DIMENSIONS QFN 33-pin (4.0 x 4.0 x 0.8 mm) Figure 9.1-1 QFN-33 Package Dimension Nov. 28, 2019 Page 479 of 491 Rev 1.00...
Page 480: Figure 9.2-1 Lqfp-32 Package Dimension
MS51 LQFP 32-pin (7.0 x 7.0 x 1.4 mm) Figure 9.2-1 LQFP-32 Package Dimension Nov. 28, 2019 Page 480 of 491 Rev 1.00...
Page 481: Figure 9.3-1 Tssop-28 Package Dimension
MS51 TSSOP 28-pin (4.4 x 9.7 x 1.0 mm) Figure 9.3-1 TSSOP-28 Package Dimension Nov. 28, 2019 Page 481 of 491 Rev 1.00...
Page 482: Figure 9.4-1 Tssop-20 Package Dimension
MS51 TSSOP 20-pin (4.4 x 6.5 x 0.9 mm) Figure 9.4-1 TSSOP-20 Package Dimension Nov. 28, 2019 Page 482 of 491 Rev 1.00...
Page 483: Figure 9.5-1 Qfn-20 Package Dimension
MS51 QFN 20-pin (3.0 x 3.0 x 0.5mm) Figure 9.5-1 QFN-20 Package Dimension Nov. 28, 2019 Page 483 of 491 Rev 1.00...
Page 484: Table 10.1-1 List Of Abbreviations
MS51 10 ABBREVIATIONS 10.1 Abbreviations List Acronym Description Analog-to-Digital Converter Brown-out Detection GPIO General-Purpose Input/Output Fsys Frequency of system clock HIRC 12 MHz Internal High Speed RC Oscillator In Application Programming In Circuit Programming In System Programming Low Dropout Regulator LIRC 10 kHz internal low speed RC oscillator (LIRC) Low Voltage $eset...
Page 485: Table 10.1-1 Instruction Set And Addressing Modes
MS51 11 INSTRUCTION SET The MS51 executes all the instructions of the standard 80C51 family fully compatible with MCS-51. However, the timing of each instruction is different for it uses high performance 1T 8051 core. The architecture eliminates redundant bus states and implements parallel execution of fetching, decode, and execution phases.
Page 486 MS51 11.2 Instruction Set Clock MS51 V.S. Tradition Instruction OPCODE Bytes Cycles 80C51 Speed Ratio A, Rn 28~2F A, direct A, @Ri 26, 27 A, #data ADDC A, Rn 38~3F ADDC A, direct ADDC A, @Ri 36, 37 ADDC A, #data SUBB A, Rn 98~9F...
Page 487 MS51 Clock MS51 V.S. Tradition Instruction OPCODE Bytes Cycles 80C51 Speed Ratio A, #data direct, A direct, #data A, Rn 48~4F A, direct A, @Ri 46, 47 A, #data direct, A direct, #data A, Rn 68~6F A, direct A, @Ri 66, 67 A, #data direct, A...
Page 488 MS51 Clock MS51 V.S. Tradition Instruction OPCODE Bytes Cycles 80C51 Speed Ratio direct, A direct, Rn 88~8F direct, direct direct, @Ri 86, 87 direct, #data @Ri, A F6, F7 @Ri, direct A6, A7 @Ri, #data 76, 77 DPTR, #data16 MOVC A, @A+DPTR MOVC A, @A+PC...
Page 489: Table 10.1-2 Instruction Set
MS51 Clock MS51 V.S. Tradition Instruction OPCODE Bytes Cycles 80C51 Speed Ratio C, bit C, /bit C, bit bit, C ACALL addr11 11, 31, 51, 71, 91, B1, D1, F1 LCALL addr16 RETI AJMP addr11 01, 21, 41, 61, 81, A1, C1, E1 LJMP addr16 SJMP...
Page 490 MS51 12 REVISION HISTORY Date Revision Description 2019.11.28 1.00 Initial release Nov. 28, 2019 Page 490 of 491 Rev 1.00...
Page 491 MS51 Important Notice Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”.

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