Section 4: Firmware Configuration; Endianness; Generic Bus Chip Selects And Memory Map; Gpio Pins - Broadcom BCM91125E User Manual

BCM91125E
S e c ti o n 4 : F ir m wa r e C o n f ig ur a t i on
This section contains information that is useful to software and firmware developers working with the board.
E
NDIANNESS
The firmware image in the flash is bi-endian, so it supports both big and little-endian operation. This can be
selected by Switch 4, Bit 2.
G B C
ENERIC US
Table 5 describes how the generic bus devices are connected to chip selects, and the default memory
addresses and sizings used by CFE. Programmers can alter the sizing of the blocks and the location in
memory of each chip select except CS0 by modifying CFE.
Chip Select
CS0
CS1
CS6
* Intel® E28F128J3A boot flash memory or ROM emulator, depending on Switch 4 bit 0 setting (see Table 4).
GPIO P
INS
Table 6 lists the wiring and firmware configuration for the BCM1125H GPIO pins.
GPIO Pin #
0
1
6
7
8
9
Note: All GPIO[15:0] pins are routed to the mezzanine connector as well. See Table 15 for details.
Page 10 Firmware Configuration
S
HIP ELECTS AND

Table 5: Generic Bus Chip Selects and Memory Map

Description
Boot ROM *
Alternate Boot ROM *
HP HDLO-2416 LED display
BCM1125H
Description
Pin Direction
Output Debug LED.
Input OUT from RTC.
Input HyperTransport interrupt, HT_INT_L.
Input PHY_INT_L (ORed PHY interrupt from both BCM5421 PHY chips).
Input NMI_L from switch SW3.
Input TEMP_ALERT_L from the temperature sensor.
B roadc om C or por ati on
M M
EMORY AP
Physical Memory Address
0x1FC0_0000
0x1EC0_0000
0x1D0A_0000

Table 6: GPIO Map

User Manual
04/27/05
Size
16 MB
16 MB
64 KB
Document 91125E-UM100-R