32-Bit Addition And Subtraction; Math Overflow Selection Bit S:2/14 - Allen-Bradley SLC 500 Series Reference Manual

4-6 Math Instructions
32-Bit Addition and
Subtraction
Fixed SLC SLC SLC
5/01 5/02 5/03
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Publication 1747-RM001G-EN-P - November 2008
You have the option of performing 16-bit or 32-bit signed integer addition and
subtraction. This is facilitated by status file bit S:2/14 (math overflow selection
bit).

Math Overflow Selection Bit S:2/14

Set this bit when you intend to use 32-bit addition and subtraction. When
SLC SLC
5/04 5/05
S:2/14 is set, and the result of an ADD, SUB, MUL, DIV, or NEG instruction
cannot be represented in the destination address (due to math underflow or
• •
overflow.:
• The overflow bit S:0/1 is set
• The overflow trap bit S:5/0 is se.
• The destination address contains the unsigned, truncated, least
significant 16 bits of the result
TIP
When S:2/14 is reset (default condition), and the result of an ADD, SUB,
MUL, DIV, or NEG instruction cannot be represented in the destination
address (due to math underflow or overflow).
• The overflow bit S:0/1 is set
• The overflow trap bit S:5/0 is set
• The destination address contains 32767 if the result is positive or -32768
if the result is negative
TIP
Note that the status of bit S:2/14 has no effect on the DDV instruction. Also,
it has no effect on the math register content when using MUL and DIV
instructions.
TIP
For MUL, DIV, integer, and all floating point
instructions with an integer destination, when S:2/14
is set, the state change takes effect immediately.
Additionally, the SLC 5/03 and higher processors
only assert the state of bit S:2/14 at the end of scan
for the ADD, SUB, and NEG instructions.
The SLC 5/03 and higher processors only interrogate
the S:2/14 bit upon going to the Run mode and
end-of-scan. Use the Data Monitor function to make
this selection prior to entering the Run mode.