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Allen-Bradley SLC 500 Series Reference Manual

Allen-Bradley SLC 500 Series Reference Manual

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SLC 500 Instruction

Set

Catalog Numbers 1747-L20x,

1747-L30x, 1747-L40x, 1747-L511,

1747-L514, 1747-L524, 1747-L531,

1747-L532, 1747-L533, 1747-L541,

1747-L542, 1747-L543, 1747-L551,

1747-L552, 1747-L553

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Summary of Contents for Allen-Bradley SLC 500 Series

Page 1 SLC 500 Instruction Catalog Numbers 1747-L20x, 1747-L30x, 1747-L40x, 1747-L511, 1747-L514, 1747-L524, 1747-L531, 1747-L532, 1747-L533, 1747-L541, 1747-L542, 1747-L543, 1747-L551, 1747-L552, 1747-L553 Reference Manual...
Page 2 Solid state equipment has operational characteristics differing from those of Important User Information electromechanical equipment. Safety Guidelines for the Application, Installation and Maintenance of Solid State Controls, publication SGI-1.1, available from your local Rockwell Automation sales office or online at http://www.literature.rockwellautomation.com), describes some important differences between solid state equipment and hard-wired electromechanical devices.
Page 3 The table below lists the sections that document new features and additional or updated information about existing features. For This Information See Page Addition of a powerup error to Table 16.1. 16-4 Revision of the company name from "Allen-Bradley" to "Rockwell Automation". Publication 1747-RM001G-EN-P - November 2008...
Page 4 Summary of Changes Notes: Publication 1747-RM001G-EN-P - November 2008...
Page 5: Table Of Contents
Table of Contents Who Should Use This Manual....... P-1 Preface Purpose of This Manual.
Page 6 Table of Contents High-speed Counter Operation ......2-17 Reset (RES)..........2-20 Chapter 3 About the Comparison Instructions .
Page 7 Table of Contents Updates to Arithmetic Status Bits......4-12 Square Root (SQR)........4-12 Updates to Arithmetic Status Bits.
Page 8 Table of Contents Chapter 5 Convert to BCD (TOD) ........5-2 Data Handling Instructions Updates to Arithmetic Status Bits.
Page 9 Table of Contents Effects on Index Register S:24 ......5-26 FIFO Load (FFL) and FIFO Unload (FFU) ....5-26 FFL Instruction Operation .
Page 10 Table of Contents Sequencer Output (SQO) Sequencer Compare (SQC) ....... . . 7-6 Enter Parameters .
Page 11 Table of Contents Scaled Error ......... . 9-9 Auto / Manual (AM) .
Page 12 viii Table of Contents Number of ASCII Characters In Buffer (ACB) ....10-7 Entering Parameters ........10-7 String to Integer (ACI).
Page 13 Table of Contents STD/STE Zone Example ......11-16 Selectable Timed Start (STS) ......11-17 Discrete Input Interrupt Overview .
Page 14 Table of Contents Rung Goes True........12-37 Next End of Scan .
Page 15 Table of Contents DF1 Half-duplex Communications......13-55 DF1 Half-duplex Master Broadcast ..... 13-55 DF1 Half-duplex Slave Broadcast.
Page 16 Table of Contents Using RSLinx Classic, version 2.50 and higher, with SLC 5/03 Passthru ..........14-5 SLC 5/03 Passthru Error Codes .
Page 17 Table of Contents xiii Network Message Example: SLC 5/04 to SLC 5/03 via KA5 ......... . . 15-30 Network Message Example: SLC 5/04 to SLC 5/05 via DHRIO and ENET.
Page 18 Table of Contents OS400, Series A, FRN 1 released: August 1994........A-3 Original Release .
Page 19 Table of Contents OS302, Series B, FRN 12 released: November 1998 OS401, Series B, FRN 9 released: July 1999 OS501, Series A, FRN 4 released: February 1999 ........A-6 Enhancements .
Page 20 Table of Contents OS302, Series C, FRN 8 OS401, Series C, FRN 8 OS501, Series C, FRN 8 released: May 2004 ........A-16 Enhancements .
Page 21 Table of Contents xvii Appendix D Valid Addressing Modes and File Types..... . D-1 Programming Instruction Understanding the Different Addressing Modes ... . D-2 References Appendix E Understanding File Organization .
Page 22 xviii Table of Contents On/Off Circuit Application Example..... . . G-16 On/Off Circuit Ladder Program......G-17 Interfacing with Enhanced Bar Code Decoders Over DH-485 Network Using the MSG Instruction .
Page 23: Preface
Preface Read this preface to familiarize yourself with the rest of the manual. It provides information concerning: • who should use this manual. • the purpose of this manual. • related documentation. • common techniques used in this manual Use this manual if you are responsible for designing, installing, programming, Who Should Use This or troubleshooting control systems that use SLC 500 programmable Manual...
Page 24: Related Documentation
A description on how to install and use your Fixed SLC 500 Installation & Operation Manual for Fixed 1747-6.21 programmable controller. Hardware Style Programmable Controllers In-depth information on grounding and wiring Allen-Bradley Allen-Bradley Programmable Controller 1770-4.1 programmable controllers. Grounding and Wiring Guidelines...
Page 25: Processor Files
Chapter Processor Files SLC 500 user memory is comprised of Data Files and Program Files. File Structure The file types shown below for data files 3 through 8 are the default values. Files 9 to 255 can be configured to be bit, timer, counter, control, integer, floating point, ASCII, or String files.
Page 26: Output And Input Data Files (Files O0: And I1:)
Processor Files Output and Input Data Files (Files O0: and I1:) Data Files 0 and 1 represent external outputs and inputs, respectively. Bits in file 1 are used to represent external inputs. In most cases, a single 16-bit word in these files will correspond to a slot location in your controller, with bit numbers corresponding to input or output terminal numbers.
Page 27: Status File (File S2:)
Processor Files Status File (File S2:) You cannot add to or delete from the status file. See Table 1.2 to understand how to address various bits and words within the status file. You can address various bits and words as follows. Table 1.2 Status File Addressing Format Format Explanation...
Page 28: Timer Data File (T4:)
Processor Files Table 1.3 Bit File Addressing Format Format Explanation Bf:e/b Bit type file File number. Number 3 is the default file. A file number between 9-255 can be used if additional storage is required. Element delimiter Element number Ranges from 0-255. These are 1-word elements. 16 bits per element.
Page 29: Addressing Structure
Processor Files Table 1.4 Timer Control Fields Word Internal Use Preset Value (PRE) Accumulator Value (ACC) Bits labeled “Internal Use” are not addressable. Table 1.5 Timer Elements Addressable Bits Addressable Words EN = Enable (Bit 15) PRE = Preset Value TT = Timer Timing (Bit 14) ACC = Accumulated Value DN = Done (Bit 13)
Page 30: Counter Data File Elements (C5:)
Processor Files Counter Data File Elements (C5:) Each Counter address is made of a 3-word data file element. Word 0 is the control word, containing the status bits of the instruction. Word 1 is the preset value. Word 2 is the accumulated value. The control word for counter instructions includes five status bits, as indicated below.
Page 31: Entering Parameters
Processor Files Entering Parameters There are several parameters associated with Counter instructions. The following parameters detail the operations of the counter. Accumulator Value (ACC) This is the number of false-to-true transitions that have occurred since the counter was last reset. Preset Value (PRE) Specifies the value which the counter must reach before the controller sets the done bit (DN).
Page 32: Control Data File (R6:)
Processor Files Table 1.9 Counter File Addressing Format Explanation C5:0/11 or C5:0/UN Underflow bit C5:0/10 or C5:0/UA Update accum. bit (use with HSC in fixed controller only) C5:0.1 or C5:0.PRE Preset value of the counter C5:0.2 or C5:0.ACC Accumulated value of the counter C5:0.1/0 or Bit 0 of the preset value C5:0.PRE/0...
Page 33 Processor Files Table 1.11 Control Elements DN = Done EM = Stack Empty ER = Error UL = Unload IN = Inhibit FD = Found Assign control addresses as follows. Table 1.12 Control File Addressing Format Format Explanation Control file Rf:e File number.
Page 34: Integer Data File (N7:)
1-10 Processor Files Integer Data File (N7:) Use these addresses as your program requires. These are 1-word elements, addressable at the element and bit level. Assign integer addresses as follows. Table 1.13 Integer File Addressing Format Format Explanation Integer file Nf:e/b File number.
Page 35: Float Data File (F8:)
Processor Files 1-11 Float Data File (F8:) Use these addresses as your program requires. These are 2-word elements, addressable at the element and bit level. Assign float addresses as follows. Table 1.14 Float File Addressing Format Format Explanation Integer file Ff:e File number.
Page 36 1-12 Processor Files Notes: Publication 1747-RM001G-EN-P - November 2008...
Page 37: Basic Instructions
Chapter Basic Instructions This chapter contains general information about the basic instructions and explains how they function in your application program. Each of the basic instructions includes information on: • the instruction symbol. • the instruction format. • the instruction usage. The Basic Instructions detailed in this chapter are listed in Table 2.1.
Page 38: About The Basic Instructions
Basic Instructions Basic instructions, when used in ladder programs, represent hardwired logic About the Basic circuits used for the control of a machine or equipment. Instructions The basic instructions are separated into three groups: bit, timer, and counter. Before you learn about the instructions in each of these groups, we suggest that you read the overviews that follow: •...
Page 39: Examine If Closed (Xic)
Basic Instructions Use the XIC instruction in your ladder program to determine if a bit is On. Examine if Closed (XIC) When the instruction is executed, if the bit addressed is on (1), then the instruction is evaluated as true. When the instruction is executed, if the bit addressed is off (0), then the instruction is evaluated as false.
Page 40: Output Energize (Ote)
Basic Instructions Use the OTE instruction in your ladder program to turn on a bit when rung Output Energize (OTE) conditions are evaluated as true. An example of a device that turns on or off is an output wired to a pilot light (addressed as O:0/4).
Page 41: Using Otu
Basic Instructions When enabled, the latch instruction tells the controller to turn on the addressed bit. Thereafter, the bit remains on, regardless of the rung condition, until the bit is turned off (typically by a OTU instruction in another rung). Using OTU When you assign an address to the OTU instruction that corresponds to the address of a physical output, the output device wired to this screw terminal is...
Page 42 Basic Instructions The bit address you use for this instruction must be unique. Do not use it elsewhere in the program. Do not use an input or output address to program the address parameter of the OSR instruction. Examples The following rungs illustrate the use of the OSR instruction. The first four rungs apply to SLC 500 and SLC 5/01 processors.
Page 43: Timer Instructions Overview
Basic Instructions The SLC 500 and SLC 5/01 processors allow you to use only one OSR instruction per rung. When using a SLC 500 or SLC 5/01 processor, do not ATTENTION place input conditions after the OSR instruction in a rung.
Page 44 Basic Instructions Timebase The timebase determines the duration of each timebase interval. For Fixed and SLC 5/01 processors, the timebase is set at 0.01 second. If the timer base is set to 0.01, it would take 100 EXAMPLE counts as the preset value (PRE) to equal 1 seconds worth of timing.
Page 45: Timer On-Delay (Ton)
Basic Instructions Use the TON instruction to turn an output on or off after the timer has been Timer On-delay (TON) on for a preset time interval. The TON instruction begins to count timebase intervals when rung conditions become true. As long as rung conditions remain true, the timer adjusts its accumulated value (ACC) each evaluation until it reaches the preset value (PRE).
Page 46: Timer Off-Delay (Tof)
2-10 Basic Instructions Use the TOF instruction to turn an output on or off after its rung has been off Timer Off-delay (TOF) for a preset time interval. The TOF instruction begins to count timebase intervals when the rung makes a true-to-false transition. As long as rung conditions remain false, the timer increments its accumulated value (ACC) based on the timebase for each scan until it reaches the preset value (PRE).
Page 47: Retentive Timer (Rto)
Basic Instructions 2-11 The Reset (RES) instruction cannot be used with the ATTENTION TOF instruction because RES always clears the status bits as well as the accumulated value. (See 2-20) The TOF timer times inside an inactive MCR Pair. Use the RTO instruction to turn an output on or off after its timer has been on Retentive Timer (RTO) for a preset time interval.
Page 48: Using Status Bits
2-12 Basic Instructions Using Status Bits Table 2.8 Setting RTO Status Bits This Bit Is Set When And Remains Set Until One of the Following Timer Done Bit DN (Bit 13) accumulated value is equal the appropriate RES to or greater than the preset instruction is enabled value Timer Timing Bit TT (Bit 14)
Page 49: Counter Instructions Overview
Basic Instructions 2-13 Counter Instructions How Counters Work Overview The figure below demonstrates how a counter works. The count value must remain in the range of − 32768 to + 32767. If the count value goes above + 32767 or below − 32768, the counter status overflow (OV) or underflow (UN) bit is set.
Page 50: Using Status Bits
2-14 Basic Instructions Using Status Bits Table 2.10 Setting CTU Status Bits This Bit Is Set When And Remains Set Until One of the Following Count Up Overflow Bit OV accumulated value wraps a RES instruction having the (Bit 12) around to -32,768 (from same address as the CTU +32,767) and continues...
Page 51: Using Status Bits
Basic Instructions 2-15 Using Status Bits Table 2.11 Setting CTD Status Bits This Bit Is Set When And Remains Set Until One of the Following Count Down Underflow Bit accumulated value wraps a RES instruction having the UN (Bit 11) around to +32,767 (from same address as the CTD -32,768) and continues...
Page 52: High-Speed Counter Data Elements
2-16 Basic Instructions This instruction provides high-speed counting for fixed I/O controllers with 24 VDC inputs. One HSC instruction is allowed per controller. To use the instruction, you must cut the jumper as shown below. A shielded cable is recommended to reduce noise to the input. High-speed Counter Data Elements Address C5:0 is the HSC counter 3-word element.
Page 53: High-Speed Counter Operation
Basic Instructions 2-17 High-speed Counter Operation For high-speed counter operation you must: 1. Turn off power to the fixed controller. 2. Remove the SLC 500 cover. 3. Locate and cut jumper wire J2. Do not remove completely but make certain that the ends of the cut jumper wire are not touching each other. The High-speed Counter jumper is located either beneath the battery connector OR to the right of the battery connector.
Page 54 2-18 Basic Instructions The HSC differs from the CTU and CTD counters. The CTU and CTD are software counters. The HSC is a hardware counter and operates asynchronously to the ladder program scan. The HSC accumulated value (C5:0.ACC) is normally updated each time the HSC rung is evaluated in the ladder program.
Page 55 Basic Instructions 2-19 Application Example - File 2 (Poll for DN Bit in Main Program) C5:0 JUMP TO SUBROUTINE Rung Rung • • • Rung C5:0 JUMP TO SUBROUTINE Rung Rung • • • Rung C5:0 JUMP TO SUBROUTINE Rung Rung Application Example - File 3 (Execute HSC Logic) Rung...
Page 56: Reset (Res)
2-20 Basic Instructions Use a RES instruction to reset a timer or counter. When the RES instruction is Reset (RES) enabled, it resets the Timer On Delay (TON), Retentive Timer (RTO), Count Up (CTU), or Count Down (CTD) instruction having the same address as the RES instruction.
Page 57: Comparison Instructions
Chapter Comparison Instructions This chapter contains general information about comparison instructions and explains how they function in your application program. Each of the comparison instructions includes information on: • the instruction symbol. • instruction usage. Table 3.1 Comparison Instructions Instruction Mnemonic Instruction Name Purpose Page...
Page 58: Comparison Instructions Overview
Comparison Instructions The following general information applies to comparison instructions. Comparison Instructions Overview Using Indexed Word Addresses When using comparison instructions, you have the option of using indexed word addresses for instruction parameters specifying word addresses. Using Indirect Word Addresses You have the option of using indirect word-level and bit-level addresses for instructions specifying word addresses when using an SLC 5/03 OS302, SLC 5/04 OS401, or SLC 5/05 processors.
Page 59: Less Than (Les)
Comparison Instructions Less Than (LES) Use the LES instruction to test whether one value (source A) is less than another (source B). If source A is less than the value at source B, the Less Than (A<B) instruction is logically true. If the value at source A is greater than or equal to Source A N7:4 0<...
Page 60: Greater Than Or Equal (Geq)
Comparison Instructions Greater Than or Equal (GEQ) Use the GEQ instruction to test whether one value (source A) is greater than or equal to another (source B). If the value at source A is greater than or equal Grtr Than or Eql (A>=B) to the value at source B, the instruction is logically true.
Page 61: Limit Test (Lim)
Comparison Instructions Limit Test (LIM) Use the LIM instruction to test for values within or outside a specified range, depending on how you set the limits. Limit Test Low Lim 5< Test N7:13 7< Entering Parameters High Lim 8< The Low Limit, Test, and High Limit values can be word addresses or Fixed SLC constants, restricted to the following combinations: 5/01...
Page 62 Comparison Instructions Notes: Publication 1747-RM001G-EN-P - November 2008...
Page 63: Math Instructions
Chapter Math Instructions This chapter contains general information about math instructions and explains how they function in your logic program. Each of the math instructions includes information on: • instruction symbol. • instruction usage. Table 4.1 Math Instructions Instruction Purpose Page Mnemonic Name...
Page 64: About The Math Instructions
Math Instructions The majority of the instructions take two input values, perform the specified About the Math Instructions arithmetic function, and output the result to an assigned memory location. For example, both the ADD and SUB instructions take a pair of input values, add or subtract them, and place the result in the specified destination.
Page 65: Updates To Arithmetic Status Bits
Math Instructions Updates to Arithmetic Status Bits The arithmetic status bits are found in Word 0, bits 0 to 3 in the controller status file. After an instruction is executed, the arithmetic status bits in the status file are updated. Table 4.2 Processor Function With this Bit The Controller...
Page 66: Using Floating Point Data File (F8:)
Math Instructions Using Floating Point Data File (F8:) This file type is valid for SLC 5/03 (OS301 and higher), SLC 5/04, and SLC 5/05 processors. These are 2-word elements and addressable only at the element level. Assign floating point addresses as follows. Table 4.3 Addressing Format Format Explanation...
Page 67: Add (Add)
Math Instructions Use the ADD instruction to add one value (source A) to another value (source Add (ADD) B) and place the result in the destination. Updates to Arithmetic Status Bits Source A N7:14 The arithmetic status bits are found in Word 0, bits 0 to 3 in the status file. 6<...
Page 68: 32-Bit Addition And Subtraction
Math Instructions You have the option of performing 16-bit or 32-bit signed integer addition and 32-Bit Addition and subtraction. This is facilitated by status file bit S:2/14 (math overflow selection Subtraction bit). Math Overflow Selection Bit S:2/14 Set this bit when you intend to use 32-bit addition and subtraction. When Fixed SLC 5/01 5/02...
Page 69 Math Instructions Example of 32-bit Addition The following example shows how a 16-bit signed integer is added to a 32-bit signed integer. Remember that S:2/14 must be set for 32-bit addition. Note that the value of the most significant 16 bits (B3:3) of the 32-bit number is increased by 1 if the carry bit S:0/0 is set and it is decreased by 1 if the number being added (B3:1) is negative.
Page 70: Multiply (Mul)
Math Instructions When rung goes true for a single scan, B3:1 is added to [OSR] B3:2. The result is placed in Source A B3:1 B3:2 0101010110101000 Source B B3:2 0001100101000000 Dest B3:2 0001100101000000 If a carry is generated (S:0/0 set), 1 is added to B3:3. Source A Source B B3:3...
Page 71: Updates To The Math Register, S:13 And S:14
Math Instructions Table 4.7 Processor Function With this Bit The Processor S:0/0 Carry (C) always resets. S:0/1 Overflow (V) sets if overflow is detected at destination; otherwise resets. On overflow, the minor error flag is also set. The value -32,768 or 32,767 is placed in the destination.
Page 72: Updates To The Math Registers, S:13 And S:14
4-10 Math Instructions Table 4.8 Processor Function With this Bit The Processor S:0/0 Carry (C) always resets. S:0/1 Overflow (V) sets if division by zero or overflow is detected; otherwise resets. On overflow, the minor error flag is also set. The value 32,767 is placed in the destination.
Page 73: Double Divide (Ddv)
Math Instructions 4-11 The 32-bit content of the math register is divided by the 16-bit source value Double Divide (DDV) and the rounded quotient is placed in the destination. If the remainder is 0.5 or greater, the destination is rounded up. Double Divide Source N7:26...
Page 74: Clear (Clr)
4-12 Math Instructions Use the CLR instruction to set the destination value of a word to zero. Clear (CLR) Updates to Arithmetic Status Bits Clear Dest N7:27 The arithmetic status bits are found in Word 0, bits 0 to 3 in the status file. 0<...
Page 75: Scale With Parameters (Scp)
Math Instructions 4-13 Use the SCP instruction to produce a scaled output value that has a linear Scale with Parameters relationship between the input and scaled values. This instruction supports (SCP) integer and floating point values. Use this instruction with SLC 5/03 (OS302), SLC 5/04 (OS401), and SLC 5/05 processors.
Page 76: Updates To Arithmetic Status Bits
4-14 Math Instructions Updates to Arithmetic Status Bits The arithmetic status bits are found in Word 0, bits 0 to 3 in the status file. After an instruction is executed, the arithmetic status bits in the status file are updated. Table 4.12 Processor Function With this Bit The Processor...
Page 77: Scale Data (Scl)
Math Instructions 4-15 Example 2 In the second example, an analog I/O combination module (1746-NIO4I) is in slot 1 of the chassis. We want to control the proportional valve connected to output 0. The valve takes a 4 to 20 mA signal to control how far it opens (0 to 100%). (Assume that additional logic is present in the program that calculates how far to open the valve in percent and places a number between 0 and 100 into N7:21.) The analog module provides a 4 to 20 mA output signal for a number between...
Page 78: Entering Parameters
4-16 Math Instructions Anytime an underflow or overflow occurs in the destination file, minor error bit S:5/0 must be reset by the program. This must occur before the end of the current scan to prevent major error code 0020 from being declared. This instruction can overflow before the offset is added.
Page 79: Application Example 1 - Converting 4 To 20 Ma Analog Input Signal To Pid Process Variable
Math Instructions 4-17 Application Example 1 - Converting 4 to 20 mA Analog Input Signal to PID Process Variable 16,383 (Scaled MAX.) Scaled Value (Scaled MIN.) 16,384 3,277 Input Value (Input MAX.) (Input MIN.) Calculating the Linear Relationship Use the following equations to express the linear relationship between the input value and the resulting scaled value.
Page 80: Application Example 2 - Scaling An Analog Input To Control An Analog Output
4-18 Math Instructions Application Example 2 - Scaling an Analog Input to Control an Analog Output 32,764 10V (Scaled MAX.) Scaled Value 0 0V (Scaled MIN.) 3,277 4 mA 16,384 20 mA (Input MIN.) (Input MAX.) Input Value Calculating the Linear Relationship Use the following equations to calculate the scaled units.
Page 81 Math Instructions 4-19 Notice that an overflow occurred even though the final value was correct. This happens because the overflow condition occurred during the rate calculation. The following graph shows the shifted linear relationship. The input minimum value of 3,277 is subtracted from the input maximum value of 16,384, resulting in the value of 13,107.
Page 82: Ramp Instruction (Rmp)
4-20 Math Instructions In this example, the SCL instruction is entered in the ladder logic program as follows. Apply the Shift SUBTRACT Analog Input Source I:1.0 Source 3277 Dest N7:0 Scale Shifted Analog Value SCALE Source N7:0 Rate [/10000] 24997 Offset Analog Output Dest...
Page 83 Math Instructions 4-21 Table 4.14 Ramp Instruction Control Structure Word 0 Ramp Algorithm Type Waveform Word 1 Desired Time Word 2 Current Time Word 3 Beginning Output Value Word 4 Ending Output Value Words Internal use only 5 and 6 TB = 0, Timebase = 0.01 seconds TB = 1, Timebase = 1.0 second Waveform = 00 Linear...
Page 84: Instruction Operation
4-22 Math Instructions Instruction Operation When the rung state is true all parameters are validated to be in range. If the parameters are valid, the ramp function places the calculated output value in the destination register. The parameters are validated for every scan when the rung state is true.
Page 85: Rmp Equation
Math Instructions 4-23 RMP Equation The Ramp instruction is defined based on the following equations. × × -- - -- - Output × Linear: Output -- - Acceleration: – – ⎛ ⎞ – – × × ------------ - ------------ - Output Deceleration: –...
Page 86: Absolute (Abs)
4-24 Math Instructions Use the ABS instruction to calculate the absolute value of the Source and place Absolute (ABS) the result in the Destination. This instruction supports integer and floating point values. Use this instruction with SLC 5/03 (OS302), SLC 5/04 (OS401), and SLC 5/05 processors.
Page 87: Compute (Cpt)
Math Instructions 4-25 The CPT instruction performs copy, arithmetic, logical, and conversion Compute (CPT) operations. You define the operation in the Expression and the result is written in the Destination. The CPT uses functions to operate on one or more values in the Expression to perform operations such as: •...
Page 88: Updates To Arithmetic Status Bits
4-26 Math Instructions Updates to Arithmetic Status Bits The arithmetic status bits are found in Word 0, bits 0 to 3 in the status file. After an instruction is executed, the arithmetic status bits in the status file are updated. Table 4.16 Processor Function With this Bit The Processor...
Page 89 Math Instructions 4-27 Rung 2:0 uses standard math instructions to implement Pythagorean’s theorem. Rung 2:1 uses the CPT instruction to obtain the same calculation. | Rung 2:0 +XPY–––––––––––––––+ |–––––––––––––––––––––––––––––––––––––––––––––––––––––+–+X TO POWER OF Y +–+–| | |Source A N7:1| | | 3| | | | |Source B 2| | |...
Page 90: Swap (Swp)
4-28 Math Instructions Use this instruction to swap the low and high bytes of a specified number of Swap (SWP) words in a bit, integer, ASCII, or string file. Use this instruction with SLC 5/03 (OS302), SLC 5/04 (OS401), and SLC 5/05 processors. Entering Parameters Swap Enter the following parameters when programming this instruction.
Page 91: Arc Sine (Asn)
Math Instructions 4-29 Use the ASN instruction to take the arc sine of a number and store the result Arc Sine (ASN) (in radians) in the destination. The source must be greater than or equal to -1 and less than or equal to 1. The resulting value in the destination is always greater than or equal to -Pi/2 and less than or equal to Pi/2, where Pi = 3.141592.
Page 92: Arc Tangent (Atn)
4-30 Math Instructions Use the ATN instruction to take the arc tangent of a number (source) and Arc Tangent (ATN) store the result (in radians) in the destination. The resulting value in the destination is always greater than or equal to -Pi/2 and less than or equal to Pi/2, where Pi = 3.141592.
Page 93: Natural Log (Ln)
Math Instructions 4-31 Use the LN instruction to take the natural log of the value in the source and Natural Log (LN) store the result in the destination. The source must be greater than zero. The resulting value in the destination is always greater than or equal to -87.33654 and less than or equal to 88.72284.
Page 94: Sine (Sin)
4-32 Math Instructions Use the SIN instruction to take the sine of a number (source in radians) and Sine (SIN) store the result in the destination. The source must be greater than or equal to -205887.4 and less than or equal to 205887.4. The greatest accuracy is achieved when the source is greater than -2 Pi and less than 2 Pi, where Pi = 3.141592.
Page 95: To The Power Of Y (Xpy)
Math Instructions 4-33 Use the XPY instruction to raise a value (source A) to a power (source B) and X to the Power of Y (XPY) store the result in the destination. If the value in source A is negative, the exponent (source B) should be a whole number.
Page 96 4-34 Math Instructions Notes: Publication 1747-RM001G-EN-P - November 2008...
Page 97: Data Handling Instructions
Chapter Data Handling Instructions This chapter contains general information about the data handling instructions and explains how they function in your application program. Each of the instructions includes information on: • what the instruction symbol looks like. • how to use the instruction. Table 5.1 Data Handling Instructions Instruction Purpose...
Page 98: Convert To Bcd (Tod)
Data Handling Instructions Use this instruction to convert 16-bit integers into BCD values. Convert to BCD (TOD) With Fixed and SLC 5/01 processors, the destination can only be the math register. With SLC 5/02 and higher processors, the destination parameter can To BCD be a word address in any data file, or it can be the math register, S:13 and S:14.
Page 99: Updates To The Math Register, S:13 And S:14
Data Handling Instructions Updates to the Math Register, S:13 and S:14 Contains the 5-digit BCD result of the conversion. This result is valid at overflow. Example 1 The integer value 9760 stored at N7:3 is converted to BCD and the BCD equivalent is stored in N10:0.
Page 100 Data Handling Instructions N7:3 Decimal S:13 & S:14 5-digit BCD S:14 S:13 This example will output the absolute value (0 to 32767) contained in N7:3 as 5 BCD digits in output slots 2 and 3. TO BCD Source N7:3 S:13 and S:14 are 32760 displayed in BCD Dest...
Page 101: Convert From Bcd (Frd)
Data Handling Instructions Use this instruction to convert BCD values to integer values. With Fixed and Convert from BCD (FRD) SLC 5/01 processors, the source can only be the math register. With SLC 5/02 and higher processors, the source parameter can be a word address in any data file, or it can be the math register, S:13.
Page 102: Changes To The Math Register, S:13 And S:14
Data Handling Instructions To convert numbers larger than 9999 BCD, the source must be the Math Register (S:13). You must reset the Minor Error bit (S:5/0) to prevent an error. Changes to the Math Register, S:13 and S:14 Used as the source for converting the entire number range of a register. Example 1 The BCD value 9760 at source N7:3 is converted and stored in N10:0.
Page 103 Data Handling Instructions Example 2 The BCD value 32760 in the math register is converted and stored in N7:0. The maximum source value is 32767, BCD. FROM BCD S:13 and S:14 are displayed in Source S:13 BCD format. 00032760 Dest N7:0 32760 S:14...
Page 104: Radian To Degrees (Deg)
Data Handling Instructions Clearing S:14 before executing the FRD instruction is shown. MOVE 0001 0010 0011 0100 Source N7:2 4660 Dest S:13 4660 CLEAR Dest S:14 S:13 and S:14 are FROM BCD Source S:13 displayed in BCD 00001234 format. Dest N7:0 1234 0000 0100 1101 0010...
Page 105: Updates To Arithmetic Status Bits
Data Handling Instructions Updates to Arithmetic Status Bits The arithmetic status bits are found in Word 0, bits 0 to 3 in the status file. After an instruction is executed, the arithmetic status bits in the status file are updated. Table 5.4 Processor Function With this Bit The Processor...
Page 106: Updates To Arithmetic Status Bits
5-10 Data Handling Instructions Updates to Arithmetic Status Bits The arithmetic status bits are found in Word 0, bits 0 to 3 in the status file. After an instruction is executed, the arithmetic status bits in the status file are updated.
Page 107: Entering Parameters
Data Handling Instructions 5-11 Entering Parameters • Source is the address that contains the bit decode information. Only the first four bits (0 to 3) are used by the DCD instruction. The remaining bits may be used for other application specific needs. Change the value of the first four bits of this word to select one bit of the destination word.
Page 108: Entering Parameters
5-12 Data Handling Instructions Entering Parameters • Source is the address of the word to be encoded. Only one bit of this word should be on at any time. If more than one bit in the source is set, the destination bits are set based on the least significant bit that is set. If a source of zero is used, all of the destination bits are reset and the arithmetic status zero bit (S:0/2) is set.
Page 109: Copy File (Cop) And Fill File (Fll) Instructions
Data Handling Instructions 5-13 The destination file type determines the number of words that an instruction Copy File (COP) and transfers. For example, if the destination file type is a counter and the source Fill File (FLL) Instructions file type is an integer, three integer words are transferred for each element in the counter-type file.
Page 110: Using Fll
5-14 Data Handling Instructions All elements are copied from the source file into the destination file each time the instruction is executed. Elements are copied in ascending order. If your destination file type is a timer, counter, or control file, be sure that the source words corresponding to the status words of your destination file contains zeros.
Page 111 Data Handling Instructions 5-15 Entering Parameters Enter the following parameters when programming this instruction. • Source is the program constant or element address. The file indicator (#) is not required for an element address. When using either an SLC 5/03 (OS301 or higher), SLC 5/04 (OS401), or SLC 5/05 processor, floating point and string values are supported.
Page 112: Move And Logical Instructions Overview
5-16 Data Handling Instructions The following general information applies to move and logical instructions. Move and Logical Instructions Overview Entering Parameters • Source is the address of the value on which the logical or move operation is to be performed. The source can be a word address or a program constant, unless otherwise described.
Page 113: Updates To The Math Register, S:13 And S:14
Data Handling Instructions 5-17 Updates to the Math Register, S:13 and S:14 Move and logical instructions do not affect the math register. Entering Mask Values When entering constants, you can use ‘b’ or ‘h’ to change the radix of your entry. For example, instead of entering -1 as a constant, you could enter 1111111111111111b or FFFFh.
Page 114: Masked Move (Mvm)
5-18 Data Handling Instructions Table 5.7 Controller Function With this Bit The Controller S:0/0 Carry (C) always resets. S:0/1 Overflow (V) always resets. S:0/2 Zero (Z) sets if result is zero; otherwise resets. S:0/3 Sign (S) sets if result is negative (most significant bit is set); otherwise resets.
Page 115 Data Handling Instructions 5-19 Operation When the rung containing this instruction is true, data at the source address passes through the mask to the destination address. See the figure below. MASKED MOVE Source B3:0 Mask F0F0 Dest B3:2 B3:2 before move 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 source B3:0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1...
Page 116: And (And)
5-20 Data Handling Instructions This instruction performs a bit-by-bit logical AND. The operation is And (AND) performed using the value at source A and the value at source B. The result is stored in the destination. Bitwise AND Table 5.9 Truth Table for A AND B = Dest Source A B3:1 C0E0h<...
Page 117: Or (Or)
Data Handling Instructions 5-21 Or (OR) This instruction performs a bit-by-bit logical OR. The operation is performed using the value at source A and the value at source B. The result is stored in Bitwise Inclusive OR the destination. Source A B3:2 16C8h<...
Page 118: Exclusive Or (Xor)
5-22 Data Handling Instructions This instruction performs a bit-by-bit logical XOR. The operation is Exclusive Or (XOR) performed using the value at source A and the value at source B. The result is stored in the destination. Bitwise Exclusive OR Table 5.13 Truth Table for A XOR B = Dest Source A B3:2...
Page 119: Not (Not)
Data Handling Instructions 5-23 This instruction performs a bit-by-bit logical NOT. The operation is Not (NOT) performed using the value at source A. The result (one’s complement of A) is stored in the destination. Table 5.15 Truth Table for A Not = Dest Source B3:2 0001011011001000<...
Page 120: Negate (Neg)
5-24 Data Handling Instructions Use the NEG instruction to change the sign of the source and then place it in Negate (NEG) the destination. The destination contains the two’s complement of the source. For example, if the source is 5, the destination would be -5. The source and destination must be word addresses.
Page 121: Fifo And Lifo Instructions Overview
Data Handling Instructions 5-25 FIFO (First in First out) instructions load words into a file and unload them in FIFO and LIFO Instructions the same order as they were loaded. The first word in is the first word out. Overview LIFO (Last in First out) instructions load words into a file and unload them in the opposite order as they were loaded.
Page 122: Effects On Index Register S:24
5-26 Data Handling Instructions Effects on Index Register S:24 The value present in S:24 is overwritten with the position value when a false-to-true transition of the FFL/FFU or LFL/LFU rung occurs. For the FFL/LFL, the position value determined at instruction entry is placed in S:24. For the FFU/LFU, the position value determined at instruction exit is placed in S:24.
Page 123: Ffl Instruction Operation
Data Handling Instructions 5-27 Table 5.19 Instruction Function Destination Position N7:11 N7:12 FIFO LOAD (EN) Source N7:10 (DN) FIFO #N7:12 N7:13 (EM) Control R6:0 Length FFU instruction N7:14 Position unloads data from stack #N7:12 at position 0, N7:12 (EU) FIFO UNLOAD FIFO #N7:12 (DN)
Page 124: Lifo Load (Lfl) And Lifo Unload (Lfu)
5-28 Data Handling Instructions LFL and LFU instructions are used in pairs. The LFL instruction loads words LIFO Load (LFL) and LIFO into a user-created file called a LIFO stack. The LFU instruction unloads Unload (LFU) words from the LIFO stack in the opposite order as they were entered. Instruction parameters have been programmed in the LFL - LFU instruction pair shown below.
Page 125: Lfl Instruction Operation
Data Handling Instructions 5-29 LFL Instruction Operation When rung conditions change from false-to-true, the LFL enable bit (EN) is set. This loads the contents of the source, N7:10, into the stack element indicated by the position number, 9. The position value then increments. The LFL instruction loads an element at each false-to-true transition of the rung, until the stack is filled (34 elements).
Page 126 5-30 Data Handling Instructions Notes: Publication 1747-RM001G-EN-P - November 2008...
Page 127: Program Flow Instructions
Chapter Program Flow Instructions This chapter contains general information about the program flow instructions and explains how they function in your application program. Each of the instructions includes information on: • what the instruction symbol looks like. • how to use the instruction. Table 6.1 Program Flow Instructions Instruction Mnemonic Instruction Name...
Page 128: Jump To Label (Jmp) And Label (Lbl)
Program Flow Instructions Use these instructions in pairs to skip portions of the ladder program. Jump to Label (JMP) and Label (LBL) (JMP) Table 6.2 Program Function If the Rung Then the Program ]LBL[ Containing the Jump Instruction Fixed SLC 5/01 5/02 5/03...
Page 129: Using Lbl
Program Flow Instructions Using LBL This input instruction is the target of JMP instructions having the same label number. You must program this instruction as the first instruction of a rung. This instruction has no control bits. You can program multiple jumps to the same label by assigning the same label number to multiple JMP instructions.
Page 130: Nesting Subroutine Files
Program Flow Instructions Nesting Subroutine Files Nesting subroutines allows you to direct program flow from the main program to a subroutine and then on to another subroutine. The following rules apply when nesting subroutines. • With Fixed and SLC 5/01 processors, you can nest subroutines up to four levels •...
Page 131: Using Sbr
Program Flow Instructions You must program each subroutine in its own program file by assigning a unique file number (3 to 255) Fixed and SLC 5/01 specific - The JSR instruction IMPORTANT cannot be programmed in nested output branches. A compiler error will occur if a rung containing multiple outputs with conditional logic and a JSR instruction is encountered.
Page 132: Master Control Reset (Mcr)
Program Flow Instructions Use MCR instructions in pairs to create program zones that turn off all the Master Control Reset (MCR) non-retentive outputs in the zone. Rungs within the MCR zone are still scanned, but scan time is reduced due to the false state of non-retentive outputs.
Page 133: Temporary End (Tnd)
Program Flow Instructions If you start instructions such as timers or counters in ATTENTION an MCR zone, instruction operation ceases when the zone is disabled. Re-program critical operations outside the zone if necessary. The TOF timer activates when placed inside of a false MCR zone.
Page 134: Suspend (Sus)
Program Flow Instructions When this instruction is executed, it causes the processor to enter the Suspend Suspend (SUS) Idle mode and stores the Suspend ID in word 7 (S:7) of the status file. All outputs are de-energized. Use this instruction to trap and identify specific conditions for program debugging and system troubleshooting.
Page 135: Entering Parameters
Program Flow Instructions Refer to Entering Mask Values on page 5-17 for information about entering mask. Length - For SLC 5/03 and higher processors, this parameter is used to transfer more than one word per slot. Valid value is from 1 to 32. This instruction allows you to update the outputs prior to the normal output Immediate Output with scan.
Page 136: I/O Refresh (Ref)
6-10 Program Flow Instructions I/O Refresh (REF) Using an SLC 5/02 Processor The REF instruction has no programming parameters. When it is evaluated as true, the program scan is interrupted to execute the I/O scan and service (REF) communication portions of the operating cycle (write outputs, service comms, SLC 5/02 Processor read inputs).
Page 137 Chapter Application Specific Instructions This chapter contains general information about the application specific instructions and explains how they function in your application program. Each of the instructions includes information on: • what the instruction symbol looks like. • how to use the instruction. Table 7.1 Application Specific Instructions Instruction Mnemonic Instruction Name...
Page 138: Application Specific Instructions
Application Specific Instructions These instructions simplify your ladder program by allowing you to use a About the Application single instruction or pair of instructions to perform common complex Specific Instructions operations. In this chapter you will find a general overview preceding groups of instructions.
Page 139 Application Specific Instructions Status bits of the control element may be addressed by mnemonic. They include: – Unload Bit UL (bit 10) stores the status of the bit exited from the array each time the instruction is enabled. – Error Bit ER (bit 11), when set, indicates the instruction detected an error such as entering a negative number for the length or position.
Page 140: Effects On Index Register S:24
Application Specific Instructions Effects on Index Register S:24 The shift operation clears the index register S:24 to zero. BSL and BSR are output instructions that load data into a bit array one bit at a Bit Shift Left (BSL) time. The data is shifted through the array, then unloaded one bit at a time. Bit Shift Right (BSR) Use BSL Bit Shift Left...
Page 141: Bit Shift Right (Bsr)
Application Specific Instructions Use BSR When the rung goes from false-to-true, the enable bit (EN bit 15) is set and the data block is shifted to the right (to a lower bit number) one bit position. The specified bit at the bit address is shifted into the last bit position. The first bit is shifted out of the array and stored in the unload bit (UL bit 10) in the status byte of the control element.
Page 142: Applications Requiring More Than 16 Bits
Application Specific Instructions Applications Requiring More than 16 Bits When your application requires more than 16 bits, use parallel multiple sequencer instructions. If a String element address is used for the file parameter, the maximum length for SLC 5/03 and higher processors is 41 words.
Page 143 Application Specific Instructions You can address the mask, source, or destination of a sequencer instruction as a word or file. If you address it as a file, the instruction automatically steps through the source, mask, or destination file. • Control (SQO, SQC) is the control structure that stores the status byte of the instruction, the length of the sequencer file, and the instantaneous position in the file.
Page 144: Use Sqo
Application Specific Instructions If you alter a length value with your ladder program, make certain that the altered value is valid. • Position is the word location or step in the sequencer file from/to which the instruction moves data. A position value that points past the end of the programmed file causes a runtime major error to occur.
Page 145 Application Specific Instructions The bits mask data when reset and pass data when set. The instruction will not change the value in the destination word unless you set mask bits. The mask can be fixed or variable. If you enter a hexadecimal code, it is fixed. If you enter an element address or a file address for changing the mask with each step, it is variable.
Page 146: Use Sqc
7-10 Application Specific Instructions Use SQC When the status of all non-masked bits in the source word match those of the corresponding reference word, the instruction sets the found bit (FD) in the control word. Otherwise, the found bit (FD) is cleared. The bits mask data when reset and pass data when set.
Page 147 Application Specific Instructions 7-11 Applications of the SQC instruction include machine diagnostics. The following figure explains how the SQC instruction works. (EN) SEQUENCER COMPARE File #B10:11 (DN) Mask FFF0 (FD) Source I:3.0 Control R6:21 Length Position Input Word I:3.0 0010 0100 1001 1101...
Page 148: Sequencer Load (Sql)
7-12 Application Specific Instructions The SQL instruction stores 16-bit data into a sequencer load file at each step Sequencer Load (SQL) of sequencer operation. The source of this data can be an I/O or storage word address, a file address, or a constant. Enter Parameters Sequencer Load File...
Page 149 Application Specific Instructions 7-13 • Control is a control file address. The status bits, length value, and position value are stored in this element. Do not use the control file address for any other instruction. The control element is shown below. Table 7.5 Control File Structure Word 0 Not Used...
Page 150: Operation
7-14 Application Specific Instructions Operation Instruction parameters have been programmed in the SQL instruction shown below. Input word I:1.0 is the source. Data in this word is loaded into integer file #N7:30 by the sequencer load instruction. SEQUENCER LOAD (EN) File #N7:30 (DN)
Page 151: Read High-Speed Clock And Compute Time Difference Overview
Application Specific Instructions 7-15 TDF and RHC instructions are used together. The RHC is used to record the Read High-speed Clock and start and stop time of an event. The TDF is used to calculate the time Compute Time Difference difference between the recorded start and stop times from the RHC Overview instruction.
Page 152: Tdf Instruction Operation
7-16 Application Specific Instructions Measurements were calculated with both communication channels active and no devices connected to the processor. Worst case accuracy is improved by shutting down an unused communication channel. TDF Instruction Operation When the TDF is evaluated with a true rung state, the instruction calculates the number of 10 µs ticks that have elapsed from the Start value to the Stop value and places the result into the Destination location.
Page 153: Read High-Speed Clock Instruction (Rhc)
Application Specific Instructions 7-17 The Read High-speed Clock Instruction (RHC) provides a high performance Read High-speed Clock timestamp for performance diagnostics and performing calculations such as Instruction (RHC) velocity. Enter Parameters Read High Speed Clock Destination - The address to store the current value of the 10 µs free running Dest N7:0 clock.
Page 154: File Bit Comparison (Fbc) And Diagnostic Detect (Ddt)
7-18 Application Specific Instructions The FBC and DDT diagnostic instructions are output instructions that you File Bit Comparison (FBC) use to monitor machine or process operations to detect malfunctions. and Diagnostic Detect (DDT) File Bit Comparison Table 7.7 Available Diagnostic Instructions Source #B3:0 Reference...
Page 155 Application Specific Instructions 7-19 After the instruction compares the last bit in two files, the done bit (bit 13 DN on the compare control element) is set. Then, when the rung goes false, the instruction resets the: • enable bit. •...
Page 156: Enter Parameters
7-20 Application Specific Instructions Enter Parameters To program these instructions, you need to provide the processor with the following information. • Source - The indexed address of your input file. • Reference - The indexed address of the file that contains the data with which you compare your input file.
Page 157: Use Status Bits
Application Specific Instructions 7-21 Use Status Bits To use the FBC or DDT instruction correctly, examine the control bits in both the comparison and result control elements. You address these bits by mnemonic. Table 7.8 FBC and DDT Status Bits Function Comparison Enable EN (bit 15)
Page 158 7-22 Application Specific Instructions Result File Reference File Source (mismatched bit #s) #B3:10 bit 3 File #B3:0 #N7:0 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1...
Page 159: Read Program Checksum (Rpc)
Application Specific Instructions 7-23 The Read Program Checksum (RPC) instruction copies the checksum of the Read Program Checksum user ladder program from either the processor’s RAM memory or from the (RPC) installed memory module into the designated destination integer file location. The program checksum is a 16-bit value that is calculated for the entire ladder logic image, excluding the data table values.
Page 160 7-24 Application Specific Instructions Notes: Publication 1747-RM001G-EN-P - November 2008...
Page 161 64 words to or from a remote device over an Allen-Bradley Remote I/O (RIO) link. A Block Transfer Read (BTR) is used to receive data from a remote device. A Block Transfer Write (BTW) is used to send data to a remote device.
Page 162: Block Transfer Instructions
Block Transfer Instructions A BTR or BTW instruction writes information into its control structure address (a three-word integer Control Block) when the instruction is entered. The processor uses these values to execute the transfer. You must enter an M1 file address into BTR Instructions and an M0 file address into BTW Instructions.
Page 163: Control Status Bits
Block Transfer Instructions • Control - The control block is an integer data file address that stores all the block transfer control and status information. The control block is three words in length. Note that these integer file addresses should not be used for any other instructions.
Page 164 Block Transfer Instructions Figure 8.1 Successful Block Transfer Control Information Control Bits Status Information Status Bits Successful Block Transfer Read/Write Figure 8.1 illustrates a successful BT operation. 1. The SLC control program copies new data to the data file (BTW only) and solves the BT rung true, which sets the enable (EN) bit.
Page 165 Block Transfer Instructions Except for the time-out bit, TO (bit 08), do not modify any controller status bits while the block transfer is in progress. The BTR/BTW instruction must be scanned (true or IMPORTANT false) in order to update the control and status bits. In order to conserve scan time, place each block transfer instruction in its own subroutine and only call the subroutine while the block transfer...
Page 166 Block Transfer Instructions In addition to the control and status bits, the control block contains two other parameters the processor uses to execute the block transfer instructions. Requested Word Count, Word 1 (RLEN) This is used to configure BTR/BTW length information (0 to 64). Length is the number of BTR/BTW words read from or written to the RIO device.
Page 167: Instruction Operation
Block Transfer Instructions Instruction Operation 1. The scanner processes the BTR/BTW when it detects that the SLC control program rung, which contains the BTR/BTW, goes true. If the RIO scanner detects any problem at this point (such as invalid block transfer control field, or unconfigured device), the control structure word 2 fills with the error code and the ER bit (bit 12) is set.
Page 168: Programming Examples
Block Transfer Instructions To prevent configuration conflicts, it is highly IMPORTANT recommended that each M-file buffer (My:e.x00) should be used by only one block transfer instruction. Programming Examples Table 8.5 Block Transfer Programming Examples Figure 8.2, "Directional" on page 8-8 Figure 8.3, "Directional Repeating"...
Page 169 Block Transfer Instructions Figure 8.3 Directional Repeating Figure 8.4 Directional Continuous Figure 8.5 Bi-directional Continuous Publication 1747-RM001G-EN-P - November 2008...
Page 170 8-10 Block Transfer Instructions Figure 8.6 Bi-directional Alternating Figure 8.7 Bi-directional Alternating Repeating Publication 1747-RM001G-EN-P - November 2008...
Page 171: Comparison To The Plc-5 Btr And Btw
Block Transfer Instructions 8-11 Comparison to the PLC-5 BTR and BTW BTR/BTW in SLC processors are quite similar to the instructions in the PLC-5. However, some differences exist between them, as shown in the table below. Table 8.6 Block Transfer Comparison Parameter PLC-5 Control Block...
Page 172 8-12 Block Transfer Instructions Notes: Publication 1747-RM001G-EN-P - November 2008...
Page 173: Proportional Integral Derivative Instruction
Chapter Proportional Integral Derivative Instruction This chapter describes the Proportional Integral Derivative (PID) instruction. This is an output instruction that controls physical properties such as Overview temperature, pressure, liquid level, or flow rate using process loops. The PID instruction normally controls a closed loop using inputs from an analog input module and provides an output to an analog output module.
Page 174: The Pid Equation
Proportional Integral Derivative Instruction The PID equation controls the process by sending an output signal to the control valve. The greater the error between the setpoint and process variable input, the greater the output signal, and vice versa. An additional value (feed forward/bias) can be added to the control output as an offset.
Page 175: The Pid Instruction
Proportional Integral Derivative Instruction The figure below shows a PID instruction with typical addresses for these The PID Instruction parameters entered. Control Block N10:0 Process Variable N10:28 Control Variable N10:29 Control Block Length Place the PID instruction on a rung without any conditional logic. If a PID instruction goes false, the integral term is cleared.
Page 176 Proportional Integral Derivative Instruction • Process Variable PV is an element address that stores the process input value. This address can be the location of the analog input word where the value of the input A/D is stored. This value could also be an integer value if you choose to pre-scale your input value to the range 0 to 16383.
Page 177: Pid Control Block Layout
Proportional Integral Derivative Instruction The control block length is fixed at 23 words and should be programmed as an PID Control Block Layout integer file. PID instruction flags (word 0) and other parameters are listed in the following table. Table 9.2 Control Block Structure Word 0 Word 1 PID Sub Error Code (MSbyte)
Page 178: Controller Gain (Kc)
Proportional Integral Derivative Instruction Controller Gain (K Table 9.3 Controller Gain Parameter Tuning Parameter Address Data Format Range Type User Descriptions Program Access KC - Controller Gain Word 3 word (INT) 0 to 32,767 control read/write Gain K (word 3) is the proportional gain, ranging from 0 to 3276.7 (when RG = 0), or 0 to 327.67 (when RG = 1).
Page 179: Rate Term (Td)
Proportional Integral Derivative Instruction Rate Term (T Table 9.5 Rate Term Parameter Tuning Parameter Address Data Format Range Type User Program Descriptions Access TD - Rate Term - T Word 5 word (INT) 0 to 32,767 control read/write Rate T (word 5) is the Derivative term.
Page 180: Loop Update
Proportional Integral Derivative Instruction When set for STI mode, the PID executes and updates the CV every time the PID instruction is scanned in the control program. When you select STI, program the PID instruction in the STI interrupt subroutine. The STI routine should have a time interval equal to the setting of the PID “loop update”...
Page 181: Scaled Error
Proportional Integral Derivative Instruction The deadband extends above and below the setpoint by the value entered. The deadband is entered at the zero crossing of the process variable and the setpoint. This means that the deadband is in effect only after the process variable enters the deadband and passes through the setpoint.
Page 182: Control (Cm)
9-10 Proportional Integral Derivative Instruction Control (CM) Table 9.11 Control Mode Parameter Tuning Parameter Address Data Format Range Type User Program Descriptions Access CM - Control Mode Word 0, Bit 2 binary (bit) 0 or 1 control read/write Control mode, or forward-/reverse-acting, toggles the values E=SP-PV and E=PV-SP.
Page 183: Setpoint Scaling (Sc)
Proportional Integral Derivative Instruction 9-11 Example with the RG bit set: The reset term (TI) of 1 indicates that the integral value of 0.01 minutes/repeat (0.6 seconds/repeat) is applied to the PID integral algorithm. The gain value (KC) of 1 indicates that the error is multiplied by 0.01 and applied to the PID algorithm.
Page 184: Derivative Rate Action Bit (Da)
9-12 Proportional Integral Derivative Instruction Derivative Rate Action Bit (DA) Table 9.16 Derivative Rate Action Bit Parameter Tuning Parameter Address Data Format Range Type User Descriptions Program Access DA - Derivative Action Bit Word 0, Bit binary (bit) 0 or 1 control read/write When set (1), the derivative (rate) action (DA) bit causes the derivative (rate)
Page 185: Setpoint Out Of Range (Sp)
Proportional Integral Derivative Instruction 9-13 Setpoint Out Of Range (SP) Table 9.19 Setpoint Out Of Range Parameter Tuning Parameter Address Data Format Range Type User Descriptions Program Access SP - Setpoint Out of Range Word 0, Bit binary (bit) 0 or 1 status read/write This bit is set (1) when the setpoint:...
Page 186: Pid Rational Approximation Bit (Ra)
9-14 Proportional Integral Derivative Instruction PID Rational Approximation Bit (RA) Table 9.22 PID Rational Approximation Parameter Tuning Parameter Address Data Format Range Type User Program Descriptions Access RA - Rational Word 0, binary (bit) 0 or 1 control read/write Approximation Bit 14 When the RA bit is set, rational approximation method is used for PID computation, resulting in a more accurate output.
Page 187: Input Parameters
Proportional Integral Derivative Instruction 9-15 The table below shows the input parameter addresses, data formats, and types Input Parameters of user program access. See the indicated pages for descriptions of each parameter. Table 9.25 Input Parameters Input Parameter Descriptions Address Range Type User Program...
Page 188: Scaled Process Variable (Spv)
9-16 Proportional Integral Derivative Instruction Scaled Process Variable (SPV) Table 9.27 Scaled Process Variable Parameter Input Address Data Range Type User Program Parameter Format Access Descriptions SPV - Scaled Word 14 word (INT) 0 to 16383 control read/write Process Variable The SPV (Scaled Process Variable) is the analog input variable.
Page 189: Setpoint Minimum Scaled (Smin)
Proportional Integral Derivative Instruction 9-17 Setpoint Minimum Scaled (SMIN) Table 9.29 Setpoint Minimum Scaled Parameter Input Address Data Range Type User Parameter Format Program Descriptions Access SMIN - Word 8 word -32,768 to control read/write Minimum (INT) +32,766 Scaled SLC 5/02 valid range is -16383 to +16382. If the SPV is read in engineering units, then the SMIN (Setpoint Minimum) parameter corresponds to the value of the setpoint in engineering units when the control input is at its minimum value.
Page 190: Output Parameters
9-18 Proportional Integral Derivative Instruction The table below shows the output parameter addresses, data formats, and Output Parameters types of user program access. See the indicated pages for descriptions of each parameter. Table 9.30 Output Parameters Output Parameter Descriptions Address Data Format Range Type User Program...
Page 191: Control Variable Percent (Cv%)
Proportional Integral Derivative Instruction 9-19 Control Variable Percent (CV%) Table 9.32 Control Variable Percent Parameter Output Parameter Address Data Range Type User Descriptions Format Program Access CV% - Control Word 16 word 0 to 100 status read only Variable Percent (INT) CV% (Control Variable Percent) displays the control variable as a percentage.
Page 192: Output Maximum (Cvh)
9-20 Proportional Integral Derivative Instruction Output Maximum (CVH) Table 9.34 Output Maximum Parameter Output Parameter Address Data Range Type User Descriptions Format Program Access CVH - Output Word 11 word (INT) 0 to 100% control read/write Maximum When the output limiting bit (OL) word 0, bit 3 of PID Control Block is enabled (1), the CVH (Control Value High) you enter is the maximum output (in percent) that the control variable attains.
Page 193: Runtime Errors
Proportional Integral Derivative Instruction 9-21 Error code 0036 appears in the status file when a PID instruction runtime Runtime Errors error occurs. Code 0036 covers the following PID error conditions, each of which has been assigned a unique single byte code value that appears in the MS byte of the second word of the control block.
Page 194 9-22 Proportional Integral Derivative Instruction Table 9.36 PID Instruction Runtime Errors Error Code Description of Error Condition or Conditions Corrective Action Scaling Selected Scaling Deselected Scaling Selected Scaling Deselected 1. Deadband < 0, or 1. Deadband < 0, or Change deadband to Change deadband to 0 <...
Page 195: Pid And Analog I/O Scaling
Proportional Integral Derivative Instruction 9-23 For the SLC 500 PID instruction, the numerical scale for both the process PID and Analog I/O Scaling variable (PV) and the control variable (CV) is 0 to 16383. To use engineering units, such as PSI or degrees, you must first scale your analog I/O ranges within the above numerical scale.
Page 196: Using The Scl Instruction
9-24 Proportional Integral Derivative Instruction Using the SCL Instruction Use the following values in an SCL instruction to scale common analog input ranges to PID process variables Table 9.37 SLC Instruction Parameter 4 to 20mA 0 to 5V 0 to 10V Rate/10,000 12,499 10,000...
Page 197 Proportional Integral Derivative Instruction 9-25 Use the following values in an SCP instruction to scale control variables to common analog outputs. Table 9.40 SCP Instruction Parameter 4 to 20mA 0 to 5V 0 to 10V Input minimum Input maximum 16383 16383 16383 Scaled minimum...
Page 198 9-26 Proportional Integral Derivative Instruction This rung immediately updates the analog input used for PV. Rung IMMEDIATE IN w MASK Slot I:1.0 Mask FFFF These two rungs ensure the analog input value to be scaled remains within the limits of 3277 to 16384. This is necessary to prevent “out of range”...
Page 199: Application Notes
Proportional Integral Derivative Instruction 9-27 The following sections discuss: Application Notes • input/output ranges. • scaling to engineering units. • output alarms. • output limiting with anti-reset windup. • the manual mode. • PID rung state. • time proportioning outputs. Input/Output Ranges The input module measuring the process variable (PV) must have a full scale binary range of 0 to 16383.
Page 200: Output Alarms
9-28 Proportional Integral Derivative Instruction For example, if measuring a full scale temperature range of -270°C (PV=0) to + 1000°C (PV=16383), enter a value of -270 for Smin and 1000 for Smax. Remember that inputs to the PID instruction must be 0 to 16383.
Page 201: Output Limiting With Anti-Reset Windup
Proportional Integral Derivative Instruction 9-29 Output Limiting with Anti-Reset Windup You may set an output limit (percent of output) on the control output. When the instruction detects that the output (CO) has exceeded a limit, it sets an alarm bit (bit 10 for lower limit, bit 9 for upper limit) in word 0 of the PID control block, and prevents the output (CO) from exceeding either limit value.
Page 202: Pid Rungstate
9-30 Proportional Integral Derivative Instruction PID Rungstate If the PID rung is false, the integral sum (words 17 and 18) is cleared and CV remains in its last state. N7:10 I:2.0 N7:10 I:2.0 N7:10 I:2.0 FROM BCD [OSR] Source I1:1.0 Dest N7:0 LIMIT...
Page 203 Proportional Integral Derivative Instruction 9-31 In this program, cycle time is the preset of timer T4:0. Cycle time relates to % on-time as follows: T4:0.PRE is the cycle time % on-time 100% output on-time Example - Time proportioning outputs Control Block N7:2 Process...
Page 204 9-32 Proportional Integral Derivative Instruction Notes: Publication 1747-RM001G-EN-P - November 2008...
Page 205 Chapter ASCII Instructions This chapter contains general information about the ASCII instructions and explains how they function in your application program. Each of the instructions includes information on: • what the instruction symbol looks like. • how to use the instruction. Table 10.1 ASCII Instruction Instruction Mnemonic Instruction Name...
Page 206: Ascii Instructions
10-2 ASCII Instructions ASCII instructions are available in SLC 5/03 OS301 and above processors, ASCII Instruction Overview and all SLC 5/04 and SLC 5/05 processors. There are two types of ASCII instructions. • ASCII port control - these include instructions that use or alter the communication channel for receiving or transmitting data.
Page 207 ASCII Instructions 10-3 Table 10.2 ASCII Protocol Parameters Description Specification Data Bits Toggles between 7 and 8. The default is 8. Termination Characters Allows you to configure up to 2 ASCII characters. The default is CR. Append Characters Allows you to configure up to 2 ASCII characters. The AWA instruction adds the characters to the end of every string to serve as termination characters for the receiving device.
Page 208 10-4 ASCII Instructions You configure append or end-of-line characters via the Channel Configuration screen. The default append characters are carriage return and line feed; the default end-of-line (termination) character is a carriage return. All instructions except ACL and AHL will error if the port is disabled.
Page 209: Entering Parameters
ASCII Instructions 10-5 Entering Parameters The control element for ASCII instructions includes eight status bits, an error code byte, and two character words. Table 10.5 ASCII Control Element Word 0 Error Code Word 1 Number of Characters For Sending or Receiving (LEN) Word 2 Number of Characters Sent or Received (POS) EN = Enable Bit...
Page 210: Test Ascii Buffer For Line (Abl)
10-6 ASCII Instructions Use the ABL instruction to determine the total number of characters in the Test ASCII Buffer for Line input buffer, up to and including the end-of-line characters (termination). This (ABL) instruction looks for two termination characters that you configure via the ASCII port configuration screen.
Page 211: Number Of Ascii Characters In Buffer (Acb)
ASCII Instructions 10-7 The Error bit (ER) is set during the execution of the instruction if: • the instruction is aborted - serial port not in User mode. • the instruction is aborted due to channel mode change. • the Unload bit (UL) is set and the instruction is not executed. Use the ACB instruction to determine the total characters in the buffer.
Page 212: String To Integer (Aci)
10-8 ASCII Instructions The Error bit (ER) is set during the execution of the instruction if: • the instruction is aborted - serial port not in User mode. • the instruction is aborted due to channel mode change. • the Unload bit (UL) is set and the instruction is not executed. Use the ACI instruction to convert a numeric ASCII string to an integer value String to Integer (ACI) between -32,768 and 32,767.
Page 213: Ascii Clear Receive And/Or Transmit Buffer (Acl)
ASCII Instructions 10-9 Use this instruction to clear an ASCII buffer. ASCII instructions are removed ASCII Clear Receive and/or from the queue and then the Error bit (ER) is set. This instruction clears the Transmit Buffer (ACL) ASCII buffers immediately upon the rung transitioning to a true state. The instruction works when the channel is in User Mode or System Mode Ascii Clear Buffers configured for DF1 Full-duplex or Half-duplex drivers.
Page 214: Entering Parameters
10-10 ASCII Instructions For SLC 5/03 with OS302, Series C, FRN 7 and higher, IMPORTANT when the ACL instruction is executed with: • the receive buffer set to No and the Transmit buffer set to Yes while channel 0 is in System Mode and configured for DF1.
Page 215: String Concatenate (Acn)
ASCII Instructions 10-11 The ACN instruction combines two strings using ASCII strings as operands. String Concatenate (ACN) The second string is appended to the first and the result stored in the destination. Entering Parameters Enter the following parameters when programming this instruction. •...
Page 216: String Extract (Aex)
10-12 ASCII Instructions Use the AEX instruction to create a new string by taking a portion of an String Extract (AEX) existing string and linking it to a new string. Entering Parameters String Extract Source ST28:0 Enter the following parameters when programming this instruction. Index Number Dest...
Page 217: Ascii Handshake Lines (Ahl)
ASCII Instructions 10-13 ASCII Handshake Lines (AHL) Use the AHL instruction to set or reset the RS-232 Data Terminal Ready (DTR) and Request to Send (RTS) handshake control lines for your modem. Ascii Handshake Lines On a false-to-true transition, the processor uses the two masks to determine Channel AND Mask 0FF03h...
Page 218: Integer To String (Aic)
10-14 ASCII Instructions Example The following shows the channel status as 001F. Table 10.7 Control Block Structure Channel Status Reserved Line Channel Status Example The Error bit (ER) is set during the execution of the instruction if: • the instruction is aborted due to channel mode change. •...
Page 219: Ascii Read Characters (Ard)
ASCII Instructions 10-15 Use the ARD instruction to read characters from the buffer and store them in ASCII Read Characters a string. To repeat the operation, the rung must go from false-to-true. (ARD) Entering Parameters ASCII Read Channel Enter the following parameters when programming this instruction. Dest ST10:7 Control...
Page 220: Timing Diagram For A Successful Ard, Arl, Awa, And Awt Instructions
10-16 ASCII Instructions The Error bit (ER) is set during the execution of the instruction if: • the instruction is aborted - serial port is not in User mode. • the modem is disconnected (control line selection is other than NO HANDSHAKING).
Page 221: Ascii Read Line (Arl)
ASCII Instructions 10-17 Use the ARL instruction to read characters from the buffer, up to and ASCII Read Line (ARL) including the end-of-line (termination) characters, and store them in a string. The end-of-line characters are specified via the ASCII Configuration screen. Entering Parameters ASCII Read Line Channel...
Page 222: String Search (Asc)
10-18 ASCII Instructions When the program scans the instruction and finds the Done bit (DN) set, the processor then sets the Synchronous bit (EM). The EM bit acts as a secondary done bit corresponding to the program scan. The Error bit (ER) is set during the execution of the instruction if: •...
Page 223: Ascii String Compare (Asr)
ASCII Instructions 10-19 Example The following conditions cause the processor to set the ASCII Error bit (S:5/15). • Invalid string length or string length of zero • Index value outside of range • Index value greater than the length of the source string The destination is not changed in any of the above conditions.
Page 224: Ascii Write With Append (Awa)
10-20 ASCII Instructions Use the AWA instruction to write characters from a source string to an ASCII Write with Append external device. This instruction adds the one or two appended characters that (AWA) you configure on the ASCII Configuration screen. The default is a carriage return and line feed appended to the end of the string.
Page 225: Using Inline Indirection
ASCII Instructions 10-21 When the program scans the instruction and finds the Done bit (DN) set, the processor then sets the Synchronous Done bit (EM) to act as a secondary done bit corresponding to the program scan. The Error bit (ER) is set during execution of the instruction if: •...
Page 226: Ascii Write (Awt)
10-22 ASCII Instructions Examples For the following examples: N7:0 = 250 N7:1 = -37 F8:0 = 2.015000 F8:1 = 0.873000 Valid in-line direction: Input: Flow rate is currently [N7:0] GPH and contains [F8:0] PPM contaminants. Output: Flow rate is currently 250 GPH and contains 2.015000 PPM contaminants. Input: Current position is [N7:1] at a speed of [F8:1] RPM.
Page 227 ASCII Instructions 10-23 • Characters Sent (POS) is the number of characters that the processor sent to the display area (0 to 82). Only after the entire string is sent is this field updated (no running total for each character is stored). This field is display only.
Page 228: Ascii Instruction Error Codes
10-24 ASCII Instructions The following error codes indicate why the Error bit (ER) is set in the control ASCII Instruction Error data file (R6). Codes Table 10.8 ASCII Error Codes Error Conditions Resulting in the Recommended Action Code Setting of the ER Bit (HEX) No error.
Page 229: Ascii Conversion Table
ASCII Instructions 10-25 The table below lists the decimal, hexadecimal, and ASCII conversions. ASCII Conversion Table Table 10.9 ASCII Conversion Table ASCII Decimal Enter as Displayed as ^A or ^a or \01 ^B or ^b or \02 ^C or ^c or \03 ^D or ^d or \04 ^E or ^e or \05 ^F or ^f or \06...
Page 230 10-26 ASCII Instructions Table 10.9 ASCII Conversion Table (Continued) ASCII Decimal Enter as Displayed as ! or \21 ““““ “““ or \22” ““““ # or \23 $ or \24 % or \25 & & or \26 & ‘ ‘ or \27 ‘...
Page 231 ASCII Instructions 10-27 Table 10.9 ASCII Conversion Table (Continued) ASCII Decimal Enter as Displayed as E or \45 F or \46 G or \47 H or \48 I or \49 J or \4A or \4a K or \4B or \4b L or \4C or \4c M or \4D or \4d N or \4E or \4e...
Page 232 10-28 ASCII Instructions Table 10.9 ASCII Conversion Table (Continued) ASCII Decimal Enter as Displayed as I or \69 j or \6A or \6a k or \6B or \6b l or \6C or \6c m or \6D or \6d n or \6E or \6e o or \6F or \6f p or \70 q or \71...
Page 233 Chapter Understanding Interrupt Routines This chapter contains general information about interrupt routines and explains how they function in your logic program. Each interrupt routine includes: • an overview. • programming procedure. • operational description. • associated bit description. In addition, each interrupt routine contains an application example that shows the interrupt routine in use.
Page 234: Understanding Interrupt Routines
11-2 Understanding Interrupt Routines The user fault routine gives you the option of preventing a processor User Fault Routine shutdown when a specific user fault occurs. The file is executed when any Overview recoverable or non-recoverable user fault occurs. The file is not executed for non-user faults.
Page 235: Status File Data Saved
Understanding Interrupt Routines 11-3 Status File Data Saved Data in the following words is saved on entry to the user fault subroutine and re-written upon exiting the subroutine. • S:0 Arithmetic flags • S:13 and S:14 Math register • S:24 Index register Creating a User Fault Subroutine To use the user fault subroutine: 1.
Page 236: User Interrupt Routine Application Example
11-4 Understanding Interrupt Routines User Interrupt Routine Application Example Suppose you have a program in which you want to control major errors 0020h (MINOR ERROR AT END OF SCAN) and 0034h (NEGATIVE VALUE IN TIMER PRE OR ACC) under the following conditions. •...
Page 237 Understanding Interrupt Routines 11-5 Fault Routine - Subroutine File 3 Word S:6 is the fault code (in decimal). EQUAL JUMP TO SUBROUTINE Source SBR file number 4 Fault Code 0020 (Enter &H20. Decimal Source equivalent 32 appears.) EQUAL JUMP TO SUBROUTINE Source SBR file number 5 Fault Code 0034...
Page 238 11-6 Understanding Interrupt Routines Subroutine File 4 - Executed for Error 0020h C5:0 SUBROUTINE COUNT UP (CU) Counter S5:0 Preset (DN) Accum EQUAL RETURN Source C5:0.ACC Source RETURN If the overflow trap bit, S:5/0 is set, counter C5:0 increments. If the count of C5:0 is 4 or less, the overflow trap, S:5/0 is cleared, the major error halted bit S:1/13 is cleared, and the processor remains in the REM Run mode.
Page 239 Understanding Interrupt Routines 11-7 Subroutine File 5 - Executed for Error 0034h The following rung toggles an output every time an error code of 0034h has occurred in the processor assuming the reason for the error was a negative value in timer T4:0. Major Error Halted...
Page 240: Selectable Timed Interrupt Overview
11-8 Understanding Interrupt Routines This function allows you to interrupt the scan of the processor automatically, Selectable Timed Interrupt on a periodic basis, to scan a specified subroutine file. Afterward, the Overview processor resumes executing from the point where it was interrupted. This section describes: •...
Page 241: Operation
Understanding Interrupt Routines 11-9 After you download your program and enter the REM Run mode, the STI Operation begins operation as follows. 1. The STI timer begins timing. 2. When the STI interval expires, the STI timer is reset, the processor scan is interrupted and the STI subroutine file is scanned.
Page 242 11-10 Understanding Interrupt Routines SLC 5/02 STI SLC 5/03 and Higher SLC 5/03 and Higher STI with Bit S:33/8 set STI with Bit S:33/9 cleared Input Scan Between slot updates Between word updates Between slot updates Program Scan Between instruction Between word updates Between rung updates updates...
Page 243: Interrupt Priorities
Understanding Interrupt Routines 11-11 Interrupt Priorities Table 11.3 Interrupt Priorities SLC 5/02 Processor SLC 5/03 and Higher Processors 1. User Fault Routine 1. User Fault Routine 2. Selectable Timed Interrupt 2. Discrete Input Interrupt (DII) Subroutine 3. Interrupt Subroutine (ISR) 3.
Page 244: Sti Parameters
11-12 Understanding Interrupt Routines The following parameters are associated with the STI function. These STI Parameters parameters have status file addresses that are described here. • STI file number (Word S:31) - This can be any number from 3 to 255. A value of zero disables the STI function.
Page 245 Understanding Interrupt Routines 11-13 SLC 5/03 and higher processors: If this bit is set or reset by the user program or communications, it takes effect upon the STI timer expiration or next end of scan (whichever occurs first). • STI Executing Bit (S:2/2) - This bit is set when the STI file is being scanned and cleared when the scan is completed.
Page 246 11-14 Understanding Interrupt Routines STI Example The following program will demonstrate a STI. The follwoing values need to be loaded into S:30 (1), S:31 (4) and S:2/10 (0) in STI setup. This will guarantee that subroutine (4) will be executed every 10 ms. The subroutine program will calculate the time difference from its last execution.
Page 247 Understanding Interrupt Routines 11-15 The following rung will measure the time difference between consecutive interrupt subroutine executions. Integer N10.2 contains the number of microsecond "ticks" that have occured. Indicate Valid Measurement B3:0 0000 Subtract Source A S:43 0< Source B N10:1 0<...
Page 248: Std And Ste Instructions
11-16 Understanding Interrupt Routines The STD and STE instructions are used to create zones in which STI ladder STD and STE Instructions execution cannot occur. The STI timer continues to operate at the rate present in word S:30. Selectable Timed Disable - STD When true, this instruction resets the STI enable bit and prevents the STI Fixed SLC 5/01...
Page 249: Selectable Timed Start (Sts)
Understanding Interrupt Routines 11-17 Program File 3 STI Example The following program will demonstrate a STE and a STD. First Pass 0000 Selectable Timed Enable Any Bit Any Bit B3:0 B3:2 0001 Any Bit Any Bit B3:0 B3:2 0002 0003 Selectable Timed Disable Any Bit...
Page 250: Discrete Input Interrupt Overview
11-18 Understanding Interrupt Routines Use the Discrete Input Interrupt (DII) for high-speed processing applications Discrete Input Interrupt or any application that needs to respond to an event quickly. This instruction Overview allows the processor to execute a ladder subroutine when the input bit pattern of a discrete I/O card matches a compare value that you programmed.
Page 251: Operation
Understanding Interrupt Routines 11-19 PLC users: The main difference between the DII and the PLC 5/40 PII is that the DII requires all stated transitions to occur prior to generating a count, while the PII requires that only one of the stated transitions occur. Also, the PLC term “count”...
Page 252: Event Mode
11-20 Understanding Interrupt Routines Event Mode This mode is active when the preset value (S:50) contains a 0 or 1. 1. The DII reads the first byte of input data of a selected discrete input card at least once every 100µs. Note that this “polling”...
Page 253: Interrupt Latency And Interrupt Occurrences
Understanding Interrupt Routines 11-21 Interrupt Latency and Interrupt Occurrences Interrupt latency is the interval between DII detection and the start of the interrupt subroutine. DII interrupts can occur at any point in your program, but not necessarily at the same point on successive interrupts. Interrupts can occur between instructions in your program, inside the I/O scan (between slots), or between the servicing of communications packets.
Page 254: Interrupt Priorities
11-22 Understanding Interrupt Routines Interrupt Priorities Interrupt priorities for the SLC 5/03 and higher processors are: 1. User fault routine. 2. Discrete Input Interrupt (DII). 3. STI Subroutine. 4. I/O Interrupt Subroutine. An executing interrupt subroutine can only be interrupted by the fault routine. Under certain conditions, though, it is possible for a lower priority task to run during the DII execution.
Page 255: Dii Parameters
Understanding Interrupt Routines 11-23 If you want to vary the number of items that are packaged together, simply change the number in the DII preset parameter using a MOV instruction. The following parameters are associated with the DII function. These DII Parameters parameters have status file addresses that are described here.
Page 256 11-24 Understanding Interrupt Routines • Bit Mask (Word S:48) - You enter the bit-mapped value that corresponds to the bits you wish to monitor on the discrete I/O module (0 to 255). Only bits 0 to 7 are used in the DII function. Setting a bit indicates that you wish to include the bit in the comparison of the discrete I/O card’s bit pattern to the DII compare value (S:49).
Page 257: Discrete Input Interrupt Application Example
Understanding Interrupt Routines 11-25 For applications that measure the rate of incoming DII pulses while using a STI (Selectable Timed Interrupt), SLC 5/03 OS301 and above updates the DII accumulator prior to executing the first rung of the STI subroutine. Discrete Input Interrupt Application Example The following example shows how to use the Discrete Input Interrupt to control a high-speed application.
Page 258 11-26 Understanding Interrupt Routines Ladder Diagram for the Bottling Application DII Example The following program will demonstrate a DII. The following values need to be loaded into S:33/8 (1), S:46 (3), S:47 (1), S:49 (1) and S:50 (1) in the DII setup. This will guarantee that subroutine (3) will be executed every time that I:1.0/0 is true.
Page 259: I/O Interrupt Overview (Isr)
Understanding Interrupt Routines 11-27 This function allows a specialty I/O module to interrupt the normal processor I/O Interrupt Overview (ISR) operating cycle in order to scan a specified subroutine file. Interrupt operation for a specific module is described in the user’s manual for the module. Not all specialty I/O modules are capable of generating I/O interrupts.
Page 260: Interrupt Subroutine (Isr) Content
11-28 Understanding Interrupt Routines Interrupt Subroutine (ISR) Content The Interrupt Subroutine (INT) instruction should be the first instruction in your ISR. This identifies the subroutine file as an I/O interrupt subroutine. The ISR contains the rungs of your application logic. You can program any instruction inside an ISR except a TND, REF, or SVC instruction.
Page 261: Interrupt Priorities
Understanding Interrupt Routines 11-29 Latency periods are: • SLC 5/02 interrupts are serviced within 2.4ms maximum. • SLC 5/03 and higher processors: If an interrupt occurs while the processor is performing a multi-word slot update and your interrupt subroutine accesses that same slot, the multi-word transfer finishes to completion prior to performing the interrupt subroutine slot access.
Page 262: Status File Data Saved
11-30 Understanding Interrupt Routines SLC 5/02 specific: It is important to understand that the I/O pending bit associated with the interrupting slot remains clear during the time that the processor is waiting for the fault routine or STI subroutine to finish. SLC 5/03 and higher processors: The I/O pending bit is always set when the interrupt occurs.
Page 263 Understanding Interrupt Routines 11-31 • ISR Number - Specifies the subroutine file number that will be executed when an I/O interrupt is generated by an I/O module. The ISR Numbers are not part of the status file, but they are part of the I/O configuration for each slot in the SLC system.
Page 264: I/O Interrupt Disable (Iid) And I/O Interrupt Enable (Iie)
11-32 Understanding Interrupt Routines • I/O Interrupt Executing (Word S:32) - This word contains the slot number of the specialty I/O module that generated the currently executing ISR. This value is cleared upon completion of the ISR, run mode entry, or upon power up. You can interrogate this word inside of your DII or STI subroutine or fault routine if you wish to know if these higher priority interrupts have interrupted an executing ISR.
Page 265: Iie Operation
Understanding Interrupt Routines 11-33 IIE Operation When true, this instruction sets the I/O interrupt enable bits (S:27/1 through S:28/14) corresponding to the slots parameter of the instruction. Interrupt subroutines of the affected slots regain the ability to execute when an interrupt request is made.
Page 266: Reset Pending Interrupt (Rpi)
11-34 Understanding Interrupt Routines This instruction resets the pending status of the specified slots and informs the Reset Pending Interrupt corresponding I/O modules that you have aborted their interrupt requests. (RPI) This instruction is not required to configure a basic I/O interrupt application. When true, this instruction clears the I/O pending bits (S:25/1 through S:26/14) corresponding to the slots parameter of the instruction.
Page 267: Slc Communication Instructions
Chapter SLC Communication Instructions This chapter contains general information about the SLC communication instructions. Each of the instructions includes information on: • what the instruction symbol looks like. • how to use the instruction. Table 12.1 Communication Instructions Instruction Mnemonic Instruction Name Purpose Page...
Page 268: About The Communication Instructions
12-2 SLC Communication Instructions Use the SVC instruction to enhance communication performance of your About the Communication processor. Use the various message instructions to send and receive data from Instructions other processors and devices. In this chapter you will find a general overview preceding each type of instruction.
Page 269: Service Communications (Svc)
SLC Communication Instructions 12-3 Service Communications Use an SLC 5/02 Processor (SVC) The SVC instruction is an output instruction that has no programming parameters. When it is evaluated as true, the program scan is interrupted to execute the service communications part of the operating cycle. The scan then SERVICE COMMUNICATIONS Channel...
Page 270: Channel Servicing
12-4 SLC Communication Instructions The following status bits let you customize or monitor communications servicing. Table 12.2 Status Bits for Customizing Communication Servicing Channel 1 Channel 0 S:2/5 Incoming Command Pending Bit S:33/0 Incoming Command Pending Bit S:2/6 Message Reply Pending Bit S:33/1 Message Reply Pending Bit S:2/7...
Page 271: Message Instruction Overview
SLC Communication Instructions 12-5 The message instruction is an output instruction that lets you read or write Message Instruction data from one processor to another processor via the communication Overview channel(s). The SLC 5/02 processor can service one message instruction at any given time.
Page 272 12-6 SLC Communication Instructions Figure 12.1 SLC 5/02 Messaging Example with MSG Timeout MSG_TRIGGER SLC_502_MSG B3:0 0000 Read/Write Message Read/Write Read Target Device 500CPU Control Block N9:0 Control Block Length Setup Screen MSG_ST_BIT MSG_TIMEOUT N9:0 0001 Timer On Delay Timer T4:0 Time Base Preset...
Page 273 SLC Communication Instructions 12-7 Figure 12.2 SLC 5/02 Repeating Messaging Example with MSG Timeout SLC_502_MSG 0000 Read/Write Message Read/Write Read Target Device 500CPU Control Block N9:0 Control Block Length Setup Screen MSG_ST_BIT MSG_TIMEOUT N9:0 0001 Timer On Delay Timer T4:0 Time Base Preset 5<...
Page 274 12-8 SLC Communication Instructions If you consistently enable more MSG instructions than the buffers and queues can accommodate, the order in which MSG instructions enter the queue is determined by the order in which they are scanned. This means MSG instructions closest to the beginning of the program enter the queue regularly and MSG instructions later in the program may not ever enter the queue.
Page 275 SLC Communication Instructions 12-9 Figure 12.4 SLC 5/03, SLC 5/04, and SLC 5/05 Repeating Messaging Example SLC_503_504_505_MSG SLC_503_504_505_MSG 0000 0000 Read/Write Message Read/Write Message Type Type Peer-To-Peer Peer-To-Peer Read/Write Read/Write Read Read Target Device Target Device 500CPU 500CPU ER ER Local/Remote Local/Remote Local...
Page 276 12-10 SLC Communication Instructions Table 12.3 Dedicated Connections Dedicated to: Number of Connections peer messages (outgoing) client messages (incoming) either peer or client messages , 16 , 24 , 40 , 56 Connections established by an INTERCHANGE client, RSLinx client, and peers are all included when counting the number of connections All series A/B 16 K (1747-L551) processors and series A/B 32 K (1747-L552) and 64 K (1747-L553) processors with OS 501, series C, FRN 4 and lower firmware.
Page 277: Msg Instruction Configuration Options
SLC Communication Instructions 12-11 MSG Instruction Configuration Options The following configuration options are available on all SLC 5/02 and higher processors. • Peer-to-peer Read/Write on a local network to another SLC 500 processor • Peer-to-peer Read/Write on a local network to a 485CIF device (PLC-2 emulation) In addition, the following configuration options are available on all SLC 5/03 and higher processors.
Page 278 12-12 SLC Communication Instructions • Local or Remote identifies if the message is sent to a device on a local network, or to a remote device on another network through a bridge. Valid options are: – Local, if the target device is on the local network –...
Page 279: Msg Instruction Setup Screen Parameters
SLC Communication Instructions 12-13 MSG Instruction Setup Screen Parameters Parameters for This Controller • Data Table Address – For a Read, this is the starting address which receives the data that is read from the target device. – For a Write, this is the starting address of the data which is written to the target device.
Page 280 12-14 SLC Communication Instructions Table 12.6 MSG Instruction Maximum Number of Elements for Modbus RTU Master File Types Channel 0 on SLC 5/03, SLC 5/04, SLC 5/05 1856 bits 116 words 58 registers (32-bit) • Channel Specifies the communication channel that is used to transmit the message request.
Page 281 SLC Communication Instructions 12-15 Message Timeout for any SLC 5/05 channel 1 MSG cannot be modified in the Ethernet Message Setup dialog box. It is assigned by the processor and is determined by adding the Channel 1 MSG Connection Timeout to the MSG Reply Timeout, then adding five seconds. This value can be modified by changing one or both of the timeout values in the channel 1 channel configuration screen.
Page 282 12-16 SLC Communication Instructions Specifies the node number of the target device that is receiving the message. Table 12.7 Valid Range of Local Node Address, Local Bridge Address, and Remote Station Address Parameters Protocol Decimal Octal DH-485 0-31 0-37 0-63 0-77 0-254 0-376...
Page 283 SLC Communication Instructions 12-17 (1) (2) • Local Bridge Addr (dec)/(oct) Specifies the node number of the bridge device on the local network. Refer to page 12-16 for the valid range of addresses. • Remote Bridge Addr (dec) Specifies the node number of the bridge device on the bridging network, when the bridge is configured for gateway mode.
Page 284 12-18 SLC Communication Instructions • Data Table Address This variable defines the starting address in the local controller. Valid file types for the Data Table Address are shown below: Table 12.8 Valid File Types for Data Table Address Message Read Message Write Bit (B) Bit (B)
Page 285 SLC Communication Instructions 12-19 Message Type File Type Element Size Maximum Number of Elements per Message Modbus B, N (command 5) 1-bit Commands B, N, F (command 6) 1-word or 32-bit register (float file type) B, N (commands 1, 2, 1-bit 1856 Modbus bit elements and 15)
Page 286 12-20 SLC Communication Instructions Here are two examples of Read Register commands. Example 1: A 32-bit Read Request for an Integer (N) command RSLogix 500 Data View (dec) SLC Processor MLX Processor RSLogix 500 Data View (dec) (hex) (hex) Read no swap 8192 18417 2000 47F1...
Page 287 SLC Communication Instructions 12-21 Example 4: A 32-bit Write Request for a Float (F) command RSLogix 500 Data View (dec) SLC Processor MLX Processor RSLogix 500 Data View (dec) (hex) (hex) Write no swap error 123456 47F1 2000 1.086583e-19 47F1 2000 123456 2000 47F1 Similar to the Read Register command,...
Page 288 12-22 SLC Communication Instructions If the message timeout is set to zero, the message instruction will never timeout. Set the Time Out bit (TO = 1) to flush a message instruction from its buffer if the destination device does not respond to the communications request.
Page 289 SLC Communication Instructions 12-23 The default Slave Node Address is 1. The range is 0 to 247. Zero is the Modbus broadcast address and is only valid for Modbus write commands (5, 6, 15 and 16). To initiate a broadcast message on a Modbus network, set the slave node address to 0.
Page 290 12-24 SLC Communication Instructions Figure 12.2 “This Controller” Parameters Modbus Command Modbus command is configured at rung setup. If a Channel configured for Modbus Master is selected in the Channel field of the Message Setup Screen, the following Modbus Command options will become available. The controller supports eight Modbus commands.
Page 291 SLC Communication Instructions 12-25 capable of exchanging data with the device. Supported Modbus commands include: Modbus Command Types Modbus Command Used For 01 Read Coil Status reading bits 02 Read Input Status reading bits 03 Read Holding Registers reading words 04 Read Input Registers reading words 05 Write Single Coil...
Page 292 12-26 SLC Communication Instructions Configure MultiHop Tab To message to an Ethernet Network Interface (ENI) or MicroLogix 1100, enter the target device’s IP address in the first row ‘To Address’ field. To message to a CompactLogix, ControlLogix, or FlexLogix controller, enter the controller’s Ethernet interface IP address in the first row ‘To Address’...
Page 293: Msg Instruction Setup Screen Status Bits
SLC Communication Instructions 12-27 MSG Instruction Setup Screen Status Bits The column in the table below lists the various status bits associated with the SLC 500 MSG instruction as displayed in the RSLogix 500 MSG instruction setup screen. Table 12.9 MSG Instruction Setup Screen Status Bits Bit Definition Bit Mnemonic Bit Address...
Page 294 12-28 SLC Communication Instructions With an SLC 5/02 MSG instruction, the ladder logic must reset the Timeout Bit before triggering the MSG instruction. When programming timeout control in SLC 5/03 and higher processors, omit the Timeout Bit manual reset rung. •...
Page 295 SLC Communication Instructions 12-29 • Start Bit ST (bit 14) is set when the processor receives acknowledgment (ACK) from the target device. The ST bit is reset when the DN, ER, or TO bit is set. Do not set or reset this bit. It is informational only. For SLC 5/05 Ethernet (channel 1) communications, the ST bit indicates internally that the Ethernet daughterboard has received a command and it is acceptable for a transmission attempt.
Page 296: Msg Instruction Control Block
12-30 SLC Communication Instructions MSG Instruction Control Block Limitations for Manipulating the Control Block Bits Do not manipulate the MSG instruction control block values except as noted below. For example, do not clear the first word of the control block, do not unlatch the time-out control bit (except in an SLC 5/02 MSG instruction), and so on.
Page 297 SLC Communication Instructions 12-31 Control Block Layouts The control block layout is shown below for 500CPU or PLC-5 controller as the target device. Table 12.11 Read or Write, Local or Remote to a 500 CPU or PLC-5 (Without Logical ASCII/Symbolic Addressing) Word 0 Error Code Word 1...
Page 298 12-32 SLC Communication Instructions The control block layout is shown below for 485CIF as the target device. Table 12.12 Read or Write, Local or Remote to a 485 CIF Word 0 Error Code Word 1 Not Used Target Node Address (Local)/Remote Station Address (Remote) Word 2 Number of Words...
Page 299 SLC Communication Instructions 12-33 (1) (2) (3) Table 12.13 Read or Write, Local or Remote to a PLC-5 (with Logical ASCII/Symbolic Addressing) Word 0 Error Code Word 1 Not Used Target Node Address (Local)/Remote Station Address (Remote) Word 2 Number of Elements Word 3 Not Used Word 4...
Page 300 12-34 SLC Communication Instructions Table 12.14 SLC 5/05 Channel 1 Read or Write, Local or Remote to an SLC 500 CPU or PLC-5 (without Logical ASCII/Symbolic Addressing) Word 0 Error Codes Word 1 Reserved Remote Station Address (Remote only) Word 2 Number of Elements Word 3 File Number...
Page 301 SLC Communication Instructions 12-35 Table 12.15 Modbus RTU Master Control Block Word 0 Error Codes Word 1 Not Used - Always 0 Target Node Word 2 Number of Elements Word 3 Target Data Address (decrement user input by 1) Word 4 Reserved (unused, default to 0) Start-Bit/Coil/Input at Physical Address...
Page 302 12-36 SLC Communication Instructions Table 12.16 SLC 5/05 Channel 1 Read or Write, Local or Remote to a PLC-5 (with Logical ASCII/Symbolic Addressing) Word 0 Error Code Word 1 Reserved Remote Station Address (Remote only) Word 2 Number of Elements Word 3 Not Used Word 4...
Page 303: Status Bit Sequencing For Slc 5/03, Slc 5/04, And Slc 5/05 Msg Instruction
SLC Communication Instructions 12-37 The following section describes the status bit sequencing for an SLC 5/03, Status Bit Sequencing for SLC 5/04, or SLC 5/05 MSG instruction. SLC 5/03, SLC 5/04, and SLC 5/05 MSG Instruction 1.Rung goes True. 2.Target node 3.Acknowledge sent 4.Not shown.
Page 304 12-38 SLC Communication Instructions Once the EN bit is set, it remains set until the entire MSG process is complete and either the DN, ER, or TO bit is set. The MSG Timeout period begins timing when the EN bit is set. If the timeout period expires before the MSG instruction completes it function, the ER bit is set and an error code (37H) is placed in the MSG block to inform you of the timeout error.
Page 305: Next End Of Scan
SLC Communication Instructions 12-39 Next End of Scan At the next end of scan or SVC, the SLC processor determines if it should examine the MSG queue for “something to do.” The processor bases its decision on the state of bits S:2/15, S:33/7, S:33/5, S:33/6, network communication requests from other nodes, and if previous MSG instructions are already in progress.
Page 306: An Ack Is Not Received
12-40 SLC Communication Instructions Step 4 is not shown in the timing diagram. An ACK is Not Received If you do not receive an ACK, step 3 does not occur. Instead, either no response or a NAK (no acknowledge) is received. When this happens, the ST bit remains clear.
Page 307: Msg Instruction Error Codes
SLC Communication Instructions 12-41 For SLC 5/03 (OS301 and higher), SLC 5/04, and SLC 5/05 processors, there are four MSG buffers per channel. Each channel has its own 10-position MSG queue. The SLC processor unloads the two MSG queues into the MSG buffers evenly at end of scan or SVC.
Page 308 12-42 SLC Communication Instructions Table 12.17 MSG Instruction Error Codes (Continued) Error Code Description of Error Condition Improperly formatted Logical ASCII Address string. String not properly terminated with a NULL character or the string length does not match the value in the length parameter. Target Node responded with: Host has a problem and will not communicate.
Page 309 SLC Communication Instructions 12-43 Table 12.17 MSG Instruction Error Codes (Continued) Error Code Description of Error Condition Connection timed out by the network Connection refused by destination host Connection was broken Reply not received before user-specified timeout No network buffer space available Multi-hop messaging CIP message format error MSG has no IP address configured for network Target Node responded with: Illegal Address Format, a field has an illegal value.
Page 310: Explicit Message Instruction Overview
EtherNet/IP devices that don’t understand standard MSG commands, as well as providing access to data in Allen-Bradley EtherNet/IP devices that isn’t accessible via standard MSG instruction commands. The EEM instruction can be used with any SLC 5/05 processor at OS firmware level Series C, FRN 10 or higher.
Page 311: Controlnet Explicit Message (Cem)
SLC Communication Instructions 12-45 All three instructions use an integer control block for storing the instruction parameters and a configuration setup screen, similar to the MSG instruction. The CIP commands consist of a Service Code; the object Class, Instance, and Attribute;...
Page 312: Cem Instruction Setup Screen Parameters
12-46 SLC Communication Instructions CEM Instruction Setup Screen Parameters The following sections provide parameters for the CEM instruction setup screens. Parameters for This Controller on the General Tab • 1747-SCNR Slot This drop-down field lists all of the local slots that contain ControlNet scanner (1747-SCNR) modules within the IO Configuration.
Page 313 SLC Communication Instructions 12-47 Parameters for Target Device on the General Tab • Message Timeout(x1 ms) The amount of time in milliseconds that the scanner will wait for a reply to the explicit message command. Range is 2 to 32767. •...
Page 314 12-48 SLC Communication Instructions • Class (hex)/(dec) Possible Classes are 0 to FF (hex). See Volume 1 of the CIP Common Specification for the list of defined Classes. You may either enter in a hexadecimal Class value in the (hex) field or a decimal Class value in the (dec) field.
Page 315 SLC Communication Instructions 12-49 • Error bit ER (word 0, bit 12) is set when the message has failed to complete successfully. This bit is reset the next time the message rung goes from false to true. Do not set or reset this bit. It is informational only.
Page 316 12-50 SLC Communication Instructions A scanner code of 0x207 results in an error code of 1. All other scanner codes listed result in an Error Code of 2. Table 12.20 list all valid CEM instruction Error Codes. Table 12.20 Valid CEM Instruction Error Codes Error Code Description of Error Condition No error.
Page 317 SLC Communication Instructions 12-51 Control Block Layout The control block layout is shown below. Table 12.21 SLC 5/0x ControlNet Explicit Message (CEM) Control Block Structure Word 0 Reserved by 1747-SCNR Word 1 Target MAC ID Word 2 Message Timeout Preset (x1 ms) Word 3 Complex I0I Size Word 4...
Page 318: Devicenet Explicit Message (Dem)
12-52 SLC Communication Instructions This is an output instruction that lets you initiate unconnected CIP Generic DeviceNet Explicit messages via a 1747-SDN DeviceNet scanner module installed in the local Message (DEM) chassis. These messages can be initiated to any node on the same DeviceNet network as the 1747-SDN, as long as the node is in the scanner’s scan list.
Page 319 SLC Communication Instructions 12-53 Parameters for Target Device on the General Tab • Message Timeout(x1 sec) The amount of time in seconds that the processor will wait for a reply from the scanner to the explicit message command. Range is 0, 2 to 255. Like the Message Timeout in a standard MSG instruction, a value of 0 disables the Message Timeout and a value of 1 second gets bumped to 2 seconds upon instruction execution.
Page 320 12-54 SLC Communication Instructions • Class (hex)/(dec) Possible Classes are 0 to FF (hex). See Volume 1 of the CIP Common Specification for the list of defined Classes. You may either enter in a hexadecimal Class value in the (hex) field or a decimal Class value in the (dec) field.
Page 321 SLC Communication Instructions 12-55 • Done bit DN (word 0, bit 13) is set when the message has completed successfully. This bit is reset the next time the message rung goes from false to true. Do not set or reset this bit. It is informational only. •...
Page 322 12-56 SLC Communication Instructions All error codes listed above result in an error code of 2. Table 12.24 Complete List of Valid DEM Error Codes Error Code Description of Error Condition No error. Timeout error. DeviceNet explicit message timed out by processor. Scanner error.
Page 323 SLC Communication Instructions 12-57 Control Block Layout The control block layout is shown below. Table 12.25 SLC 5/0x DeviceNet Explicit Message (DEM) Control Block Structure Word 0 Error Code Word 1 Message Timeout Preset Word 2 Message Timeout Accumulator Word 3 Message Timer Scaled Zero Word 4 Unused...
Page 324: Ethernet/Ip Explicit Message (Eem)
12-58 SLC Communication Instructions This output instruction lets you initiate connected CIP Generic messages via EtherNet/IP Explicit channel 1 on a SLC 5/05 processor. These messages can be initiated to Message (EEM) EtherNet/IP nodes on the same Ethernet network as the SLC 5/05 or can be bridged through a ControlLogix gateway to nodes on remote ControlNet or Ethernet networks.
Page 325 SLC Communication Instructions 12-59 • Data Table Address (Send Data) If Size in Words (Send Data) is non-zero, then this field requires a starting integer (N) file address for storing the Send Data. • Data Table Address (Receive Data) If Size in Words (Receive Data) is non-zero, then this field requires a starting integer (N) file address for storing the Receive Data.
Page 326 12-60 SLC Communication Instructions • Service Code (hex) This field is read-only unless the Custom Service is selected. Possible Service Codes are 1 to 7F (hex). See Volume 1 of the CIP Common Specification, Appendix A, for the list of valid explicit messaging Service Codes.
Page 327 SLC Communication Instructions 12-61 Definitions for Message Status Bits on the General Tab The table below lists the various status bits associated with the EEM instruction as displayed in the EEM instruction setup screen. Table 12.26 EEM Instruction Setup Screen Status Bits Bit Definition Bit Mnemonic Bit Address...
Page 328 12-62 SLC Communication Instructions • Enabled bit EN (word 0, bit 15) is set after the message rung goes from false to true and there is space available in either the channel 1 message buffers or message queue. It remains set until message transmission is completed and the rung goes false.
Page 329 SLC Communication Instructions 12-63 Send Data Tab The Send Data Tab provides a convenient way of viewing and entering in data to be sent along with the explicit message command. The data is shown in byte format with a selectable radix of either Decimal or Hex/BCD. The display only shows the number of words that are defined in the Size in Words (Send Data) field, starting with the low byte of the first word as defined in the Data Table Address (Send Data) field.
Page 330 12-64 SLC Communication Instructions Control Block Layout Table 12.28 SLC 5/05 EtherNet/IP Explicit Message (EEM) Control Block Structure Word 0 Error Code Word 1 Extended STS Size (in words) General STS Word 2 Extended Status Debug Word 1 Word 3 Extended Status Debug Word 2 Word 4 Total Response Size (in bytes)
Page 331 Chapter SLC Communication Channels Use the information in this chapter to understand how to configure and monitor the SLC 500 communication channels including passthru. The following communication drivers are supported. Table 13.1 Supported Communication Drivers Communication Drivers SLC 500 SLC 5/01 SLC 5/02 SLC 5/03 SLC 5/04...
Page 332: Communication Driver Overview
13-2 SLC Communication Channels DH-485 - The SLC 500 Fixed, SLC 5/01, SLC 5/02 and SLC 5/03 have a Communication Driver dedicated channel for DH-485. SLC 5/03, SLC 5/04 and SLC 5/05 RS-232 Overview channel 0 can be reconfigured for DH-485. This network is a multi-master, token-passing network protocol capable of supporting up to 32 devices (nodes).
Page 333 This protocol allows: • transmission of information across full-duplex modems (dial-up, leased line, radio, or direct cable connections). • communication to occur between Allen-Bradley products and third-party products. DF1 Half-duplex (Master and Slave) - DF1 Half-duplex protocol provides a multi-drop single master/multiple slave network capable of supporting up to 255 devices (nodes).
Page 334: Dh-485 Communications
13-4 SLC Communication Channels The DH-485 network offers: DH-485 Communications • interconnection of 32 devices. • multi-master capability. • token passing access control. • the ability to add or remove nodes without disrupting the network. • maximum network length of 1219 m (4,000 ft). DH-485 Network Protocol The following section describes the protocol used to control message transfers on the DH-485 network.
Page 335: Dh-485 Network Considerations
SLC Communication Channels 13-5 DH-485 Network Initialization Network initialization begins when a period of inactivity exceeds the time of a link dead timeout. When the time for the link dead timeout is exceeded, usually the initiator with the lowest address claims the token. Building a network begins when the initiator that claimed the token tries to pass the token to the successor node.
Page 336 13-6 SLC Communication Channels Setting Node Addresses The best network performance occurs when node addresses start at 0 and are assigned in sequential order. SLC 500 processors default to node address 1. The node address is stored in the processor status file (S:15L). Processors cannot be node 0.
Page 337 SLC Communication Channels 13-7 Configuring a Channel for DH-485 To configure an SLC processor channel for DH-485, do the following using your programming software: To bring up the Channel Configuration interface, double-click on the Channel Configuration icon. For an SLC 500 Fixed, SLC 5/01 and SLC 5/02 processor, enter in the Baud Rate and Node Address parameters.
Page 338 13-8 SLC Communication Channels 1. On the Channel 1 or 0 tab, choose DH-485 for your Driver. 2. Configure the communication driver characteristics according to Table 13.2. Table 13.2 Define these communication parameters when configuring an SLC 5/03 or higher processor for DH-485 communications.
Page 339 SLC Communication Channels 13-9 DH-485 Channel Status For SLC 5/03 (OS302, Series C and higher), SLC 5/04 (OS401, Series C and higher) and SLC 5/05, channel status data is stored in the diagnostic file defined on the Channel Configuration screen. Table 13.3 on page 13-9 explains information regarding the diagnostic counter data displayed.
Page 340: Data Highway Plus Communications
13-10 SLC Communication Channels Table 13.3 SLC 5/03 Channel 1 and SLC 5/03 and Higher Channel 0 DH-485 Channel Status (Continued) Status field Bytes Displays the Total Bad Packets Number of incorrect data packets the processor has received. Received Packets with bad type Number of messages that the processor could not receive because they were of an illegal type byte that contained a bad control byte.
Page 341 SLC Communication Channels 13-11 The DH+ network uses factory set time-outs to restart token-passing communication if the token is lost because of a defective or powered down node. Example The example below shows the connectivity of an SLC 5/04 processor to a PLC-5 processor using the DH+ protocol.
Page 342: Configuring Channel 1 For Dh
13-12 SLC Communication Channels Configuring Channel 1 for DH+ To configure an SLC 5/04 processor channel for DH+, do the following using your programming software. To bring up the Channel Configuration interface, double-click on the Channel Configuration icon. Define the location of the diagnostic file used for Channel Status here.
Page 343: Dh+ Channel Status
SLC Communication Channels 13-13 1. On the Channel 1 tab, choose DH+ for your Driver. 2. Configure the communication driver characteristics according to Table 13.4. Table 13.4 Define these communication parameters when configuring an SLC 5/04 for DH+ communications. Parameter Default Selections General...
Page 344 13-14 SLC Communication Channels Double-click on the Channel Status Icon Located beneath the Configuration icon to bring up the Channel Status screen. See Table 13.5 for details concerning the DH+ Channel Status Screens for Messages, General, Data Sent with Acknowledgement, and Data Sent without Acknowledgement.
Page 345 SLC Communication Channels 13-15 Table 13.5 SLC 5/04 Channel 1 DH+ Channel Status Status field Word Displays the Messages Received Number of error-free messages the station has received. This number is the sum of the SDA and SDN received counters. Sent Total number of messages sent by the station.
Page 346 13-16 SLC Communication Channels Table 13.5 SLC 5/04 Channel 1 DH+ Channel Status (Continued) Status field Word Displays the General Network dead Number of times the station detects no traffic on the network. This usually occurs when the station with the token is powered down or is removed from the network. The other stations are waiting for the token to be passed to them.
Page 347 SLC Communication Channels 13-17 Table 13.5 SLC 5/04 Channel 1 DH+ Channel Status (Continued) Status field Word Displays the General Solicit rotations Number of times a complete solicit successor of all stations not on the link is completed. A solicit successor occurs during a token pass around the link. Here a station that is currently not on the link is solicited to see if it has been added to the link.
Page 348: Global Status Word Overview
13-18 SLC Communication Channels Table 13.5 SLC 5/04 Channel 1 DH+ Channel Status (Continued) Status field Word Displays the Data Sent Transmit failed Number of SDA messages sent by the station that were determined to be in error. This with counter is the sum of the SDA transmit not ACKed and SDA transmit time-out counter.
Page 349 SLC Communication Channels 13-19 This word is located in memory at S:99. If, S:34/3 is set, data in this memory location is transmitted every time the processor passes the DH+ token. Note that all other DH+ nodes see this data. •...
Page 350 13-20 SLC Communication Channels • The word in the Global Status File corresponding to the SLC 5/04 processor’s DH+ address will be set to 0x0000 if any thing is done to inhibit the transmission of the Global Status Word from S:99. This includes: –...
Page 351 SLC Communication Channels 13-21 Note that all 164 words are updated during each end-of-scan. The following table describes possible states of the DH+ node address and the value written to the Global Status Word (S:99). Table 13.6 DH+ Node Address State State of the DH+ Node Address Value written into S:99 by the SLC 5/04 processor...
Page 352: Ethernet Communications
13-22 SLC Communication Channels This section: Ethernet Communications • describes SLC 5/05 performance considerations. • describes Ethernet network connections and media. • explains how the SLC 5/05 establishes node connections. • lists Ethernet configuration parameters and procedures. • describes configuration for subnet masks and gateways. The SLC 5/05 supports Ethernet communication via the Ethernet communication channel 1.
Page 353: Slc 5/05 And Pc Connections To The Ethernet Network
SLC Communication Channels 13-23 Optimal Performance: PC to SLC 5/05 Processor (2-node Ethernet network) Table 13.7 Optimal Performance: RSLinx to SLC 5/05 Processor (2-node Ethernet network) Operation Words MSG per Second Words per Second Single Typed Read Single Typed Read 1980 Single Typed Read 8600...
Page 354: Configuring Channel 1 For Ethernet
13-24 SLC Communication Channels The SLC 5/05 processor contains an RJ45 Ethernet IMPORTANT connector which connects to standard Ethernet switches via 8-wire twisted pair straight-through cable. To access other Ethernet mediums, use RJ45 media converters or Ethernet switches that can be connected together via fiber, thin-wire, or thick-wire coaxial cables, or any other physical media commercially available with Ethernet switches.
Page 355 SLC Communication Channels 13-25 Define the location of the diagnostic file used for Channel Status here. See Table 13.10 on page 13-30 for diagnostic file details. Configure the communication driver characteristics according to Table 13.8. Publication 1747-RM001G-EN-P - November 2008...
Page 356 13-26 SLC Communication Channels Table 13.8 Define these communication parameters when configuring an SLC 5/05 processor for Ethernet communications. Parameter Default Selections General Diagnostic File Select an unused file to store channel status information. You must define a diagnostic file in order to be able to view channel 1 status.
Page 357 SLC Communication Channels 13-27 Table 13.8 Define these communication parameters when configuring an SLC 5/05 processor for Ethernet communications. (Continued) Parameter Default Selections Inactivity 30 minutes The amount of time (in minutes) that a MSG connection may remain inactive before it is terminated.
Page 358: Ethernet Channel Status
13-28 SLC Communication Channels Table 13.9 Configuration Setting Setting 100 Mbps 100 Mbps 10 Mbps 10 Mbps Full-duplex Half-duplex Full-duplex Half-duplex 10/100 Mbps Full-duplex/Half-duplex 100 Mbps Full-duplex or 100 Mbps Half-duplex 100 Mbps Full-duplex or 10 Mbps Half-duplex 100 Mbps Half-duplex or 10 Mbps Full-duplex 100 Mbps Full-duplex 100 Mbps Half-duplex 10 Mbps Full-duplex...
Page 359 SLC Communication Channels 13-29 See Table 13.10 for details concerning the Ethernet Channel Status Screen. Publication 1747-RM001G-EN-P - November 2008...
Page 360 13-30 SLC Communication Channels Table 13.10 SLC 5/05 Channel 1 Ethernet Channel Status Status field Words Displays the number of Commands Sent Commands sent by the channel. Received Commands received by the channel. Replies Sent Replies sent by the channel. Sent with error Replies containing errors sent by the channel.
Page 361: Configuration Via Bootp
SLC Communication Channels 13-31 Table 13.10 SLC 5/05 Channel 1 Ethernet Channel Status (Continued) Status field Words Displays the number of Connections Total Message Total existing Ethernet message connections. Connections Incoming Message Existing incoming Ethernet message connections. Connections Outgoing Message Existing outgoing Ethernet message connections.
Page 362 13-32 SLC Communication Channels The host system’s BOOTP configuration file must be updated to service requests from SLC 5/05 processors. The following parameters must be configured. Table 13.11 BOOTP Configuration Parameters Parameter Description IP Address A unique IP Address for the SLC 5/05 processor. Subnet Mask Specifies the net and local subnet mask as per the standard on subnetting RFC 950, Internet Standard Subnetting Procedure.
Page 363: Using The Rockwell Bootp Utility
SLC Communication Channels 13-33 Using the Rockwell BOOTP Utility The Rockwell BOOTP utility is a standalone program that incorporates the functionality of standard BOOTP software with a user-friendly graphical interface. It is located in the Utils directory on the RSLogix 5000 installation CD. It can also be downloaded from www.ab.com/networks/bootp/index.html web page.
Page 364 13-34 SLC Communication Channels Publication 1747-RM001G-EN-P - November 2008...
Page 365: Slc 5/05 Embedded Web Server Capability
SLC Communication Channels 13-35 SLC 5/05 processors with OS501, Series C, FRN 6 (or higher) include an SLC 5/05 Embedded Web enhanced embedded web server (introduced in Series C, FRN 5) which allows Server Capability viewing of not only module information, TCP/IP configuration, and diagnostic information, but also includes the data table memory map, data table monitor screen, and user-provided web pages via Ethernet using a standard web browser.
Page 366: Tcp/Ip Configuration
13-36 SLC Communication Channels Figure 13.2 SLC 5/05 Module Information Page TCP/IP Configuration This page displays a table with information about the current TCP/IP configuration parameters. Included are the module’s IP address, the subnet mask, gateway address, the Ethernet hardware address and whether BOOTP is enabled.
Page 367: Diagnostic Information
Application Level Statistics. The Network Stack Statistics detail information about the TCP/IP stack, while the Application Level Statistics are related to the Allen-Bradley Client Server Protocol (CSP) and Common Industrial Protocol (CIP) diagnostics. The individual diagnostic screens automatically refresh using a time which is configurable by the user and defaults to 15 seconds.
Page 368: Data Table Memory Map
13-38 SLC Communication Channels Data Table Memory Map The Data Table Memory Map page displays a list of the data table files, their type, and size in elements for a connected SLC 5/05, as shown in the following example. Figure 13.5 Data Table Memory Map Page Publication 1747-RM001G-EN-P - November 2008...
Page 369 SLC Communication Channels 13-39 Each file contains a hyperlink that takes you to the specific Data Table Monitor page for that file. When you click on a particular file, the Data Table Monitor page appears, displaying the contents of the data table file you selected.
Page 370: Data Table Monitor
13-40 SLC Communication Channels Data Table Monitor You may also go directly to the Data Table Monitor screen by selecting it on the home page or by clicking on D/T Monitor on the bottom row of the other pages. In this case, since a particular data file has not been chosen, a default screen is displayed.
Page 371: User Provided Pages
SLC Communication Channels 13-41 User Provided Pages You can use a text editor to generate up to 16 user-provided web pages. Each page is stored in four consecutive ASCII files of the SLC 5/05 processor. The channel configuration feature of RSLogix 500 (version 6.0 or later) allows you to select the starting file number and the number of user pages to be stored, as shown in the following example.
Page 372 13-42 SLC Communication Channels HTML Pages Referencing Other Pages/Servers - following are some basic considerations when referencing other pages or servers. • Reference User Specified Pages in the SLC 5/05 by using the names user1.html through user16.html • To reference a page on the same processor, specify a URL such as /user2.html •...
Page 373 SLC Communication Channels 13-43 When defining your custom tag, consider the following: Table 13.12 Custom Tags: Tag Item Description #elements If not specified, this defaults to one. If it is less than one, it also defaults to one. Each element is output using the same format (whether specified with %format or defaulted).
Page 374 13-44 SLC Communication Channels Generating Custom Data Table Monitor Pages You can generate Custom Data Table Monitor pages with your text editor then download them to the SLC 5/05 processor using RSLogix 500 version 6.0 or later. The first element of the file must contain a special tag as follows: <!ABCDM-xx>...
Page 375 SLC Communication Channels 13-45 Tag Item Description %format Legal values are %b for binary, %d for decimal, %0 for octal and %x for hexadecimal. The following file types allow the format to be specified. • Input • Status • Output •...
Page 376 13-46 SLC Communication Channels Figure 13.9 User Provided Pages Menu Click on the User Provided Page #X to display that specific page. Figure 13.10 User Provided Page #5 Displayed You can change the radix display of I, O, S, and N file addresses, which appear with an underline.
Page 377 SLC Communication Channels 13-47 2. In the Address column, click on an underlined address to display the radix selection page. 3. Click on a radio button to select the desired radix type. To see the Sample Extended Format page: 1. Go back to the User-Provided Custom Data Table Monitor page. 2.
Page 378 13-48 SLC Communication Channels Exporting User Provided Page Files from the SLC 5/05 Processor To export user provided pages to HTML files: 1. In the Project folder (under the Data Files folder), right click on the first block of four consecutive ASCII files you want to export. 2.
Page 379: Df1 Full-Duplex Communications
SLC Communication Channels 13-49 DF1 Full-duplex protocol (also referred to as DF1 point-to-point protocol) is DF1 Full-duplex provided for applications where RS-232 point-to-point communication is Communications required. This type of protocol supports simultaneous transmissions between two devices in both directions. You can use channel 0 as a programming port, or as a peer-to-peer port using the MSG instruction.
Page 380 13-50 SLC Communication Channels Define the location of the diagnostic file used for Channel Status here. For channel status details, refer to 13-53. 1. On the Channel 0 tab, choose DF1 Full-Duplex for your Driver. 2. Configure the communication driver characteristics according to table 13.15.
Page 381 SLC Communication Channels 13-51 Table 13.15 Define these communication parameters when configuring a SLC 5/03, 5/04, or 5/05 processor for DF1 full-duplex communication. Parameter Default Selections General Diagnostic File SLC 5/03 (OS 302, Series C or higher), SLC 5/04 (OS 401, Series C or higher) and SLC 5/05 only.
Page 382 To use embedded responses, choose Enabled. If you want the processor to use embedded responses only when it detects embedded responses from another device, choose Auto-detect. If you are communicating with another Allen-Bradley device, choose Enabled. Embedded responses increase network traffic efficiency. Duplicate Packet...
Page 383: Df1 Full-Duplex Channel Status
SLC Communication Channels 13-53 DF1 Full-duplex Channel Status Channel Status data is stored in the diagnostic file defined on the Channel 0 Configuration screen. See Table 13.25 for information regarding the diagnostic counter data displayed. Double-click on the Channel Status Icon Located beneath the Configuration icon to bring up the Channel Status screen.
Page 384 13-54 SLC Communication Channels Table 13.16 SLC 5/03 and Higher Channel 0 DF1 Full-duplex Channel Status Status Field Diagnostic File Location Definition DCD Recover word 11 The number of times the processor detects the DCD handshaking line has gone low to high Messages Sent word 1 The total number of DF1 messages sent by the processor (including...
Page 385: Df1 Half-Duplex Communications
The master then transmits the data packets for that slave. Many Allen-Bradley products support half-duplex master protocol. They include the enhanced PLC-5 processors, SLC 5/03 (OS301 and higher), SLC 5/04, and SLC 5/05 processors.
Page 386: Configuring Channel 0 For Standard Polling Mode Df1 Half-Duplex Master
13-56 SLC Communication Channels master received the packet without error. When the DF1 half-duplex master re-broadcasts the broadcast write command, the initiating DF1 half-duplex slave receives and executes the command along with all of the other slave nodes receiving the broadcast packet. No acknowledgement or reply is returned.
Page 387 SLC Communication Channels 13-57 Define the location of the diagnostic file used for Channel Status here. For Channel Status details, see page 13-68. 1. On the Channel 0 tab, choose DF1 Half-Duplex for your Driver. 2. Choose a Standard Polling Mode.
Page 388 13-58 SLC Communication Channels Table 13.17 Define these parameters when configuring a SLC 5/03, 5/04, or 5/05 processor as a master station using standard polling mode to communicate with slave stations Parameter Default Selections General Diagnostic File SLC 5/03 (OS 302, Series C or higher), SLC 5/04 (OS 401, Series C or higher) and SLC 5/05 only.
Page 389 SLC Communication Channels 13-59 Table 13.17 Define these parameters when configuring a SLC 5/03, 5/04, or 5/05 processor as a master station using standard polling mode to communicate with slave stations (Continued) Parameter Default Selections Polling Mode Message Based If you want to receive: •...
Page 390 13-60 SLC Communication Channels Table 13.17 Define these parameters when configuring a SLC 5/03, 5/04, or 5/05 processor as a master station using standard polling mode to communicate with slave stations (Continued) Parameter Default Selections Normal Polling Range Select the last slave station address to normal poll. –...
Page 391: Minimum Df1 Half-Duplex Master Channel 0 Ack Timeout
SLC Communication Channels 13-61 Minimum DF1 Half-duplex Master Channel 0 ACK Timeout The governing timeout parameter to configure for a DF1 Half-duplex Master is the channel 0 ACK Timeout. The ACK Timeout is the amount of time you want the processor to wait for an acknowledgment of its message transmissions.
Page 392: Determining Minimum Master Ack Timeout
13-62 SLC Communication Channels Determining Minimum Master ACK Timeout To determine the minimum ACK Timeout, you must first calculate the transmission time by multiplying the maximum sized data packet for your processor by the modem rate in ms/byte. For an example we will assume an SLC 5/03 processor (103 data words or 224 bytes total packet size including overhead) and a 9600 bps modem, which transmits at approximately 1 ms/byte.
Page 393: Monitor Active Stations
SLC Communication Channels 13-63 Table 13.19 Sum of the Transmission Rates Parameter Example Values (in ms) modem turnaround time calculated ACK Timeout round up to nearest 20 ms Monitor Active Stations To see what stations are active, view the channel 0 active node table in the SLC 5/03, SLC 5/04, or SLC 5/05 processor status file (S:67/0-S:82/15).
Page 394 13-64 SLC Communication Channels Message-based communication should also be used in redundant SLC master station systems implemented with the 1746-BSN backup communication module. With message-based mode, you do not have an active node file that you can use to monitor station status. Also, you cannot implement slave station-to-slave station messaging.
Page 395 SLC Communication Channels 13-65 1. On the Channel 0 tab, choose DF1 Half-Duplex Master for your Driver. 2. Choose a Message-based Polling Mode. 3. Configure the communication driver characteristics according to Table 13.20. Publication 1747-RM001G-EN-P - November 2008...
Page 396 13-66 SLC Communication Channels Table 13.20 Define these parameters when configuring a SLC 5/03, 5/04, or 5/05 processor as a master station using message-based polling mode to communicate with slave stations. Parameter Default Selections General Diagnostic File 0 SLC 5/03 (OS 302, Series C or higher), SLC 5/04 (OS 401, Series C or higher) and SLC 5/05 only.
Page 397 SLC Communication Channels 13-67 Table 13.20 Define these parameters when configuring a SLC 5/03, 5/04, or 5/05 processor as a master station using message-based polling mode to communicate with slave stations. (Continued) Parameter Default Selections Channel 0 Polling Mode Message If you want to accept unsolicited messages from slave stations, choose MESSAGE BASED System Based...
Page 398: Df1 Half-Duplex Master Channel Status
13-68 SLC Communication Channels DF1 Half-duplex Master Channel Status Channel Status data is stored in the diagnostic file defined on the Channel 0 Configuration screen. See Table 13.21 on page 13-68 for information regarding the diagnostic counter data displayed. Double-click on the Channel Status Icon Located beneath the Configuration icon to bring up the Channel Status screen.
Page 399: Configuring Channel 0 For Df1 Half-Duplex Slave
SLC Communication Channels 13-69 Table 13.21 SLC 5/03 and Higher Channel 0 DF1 Half-duplex Master Channel Status (Continued) Status Field Diagnostic File Location Definition Message Retry word 4 The number of message retries sent by the processor Undelivered Messages word 3 The number of messages that were sent by the processor but not acknowledged by the destination device Duplicate Messages...
Page 400 13-70 SLC Communication Channels Define the location of the diagnostic file used for Channel Status here. For Channel Status details, see page 13-74. 1. On the Channel 0 tab, choose DF1 Half-Duplex Slave for your Driver. 2. Configure the communication driver characteristics according to Table 13.22.
Page 401 SLC Communication Channels 13-71 Table 13.22 Define these parameters when configuring a SLC 5/03, 5/04, or 5/05 processor as a slave station. Parameter Default Selections General Diagnostic SLC 5/03 (OS 302, Series C or higher), SLC 5/04 (OS 401, Series C or higher) and SLC 5/05 only. File Select an unused file (9 to 255) to store channel status information.
Page 402 13-72 SLC Communication Channels Table 13.22 Define these parameters when configuring a SLC 5/03, 5/04, or 5/05 processor as a slave station. (Continued) Parameter Default Selections Error With this selection, you choose the how the processor checks the accuracy of each DF1 packet Detection transmission.
Page 403: Configuring Channel 0 Poll Timeout
SLC Communication Channels 13-73 Table 13.22 Define these parameters when configuring a SLC 5/03, 5/04, or 5/05 processor as a slave station. (Continued) Parameter Default Selections Message Defines the number of times a slave station resends its message to the master station before Retries the slave station declares the message undeliverable.
Page 404: Df1 Half-Duplex Slave Channel Status
13-74 SLC Communication Channels DF1 Half-duplex Slave Channel Status Channel Status data is stored in the diagnostic file defined on the Channel 0 Configuration screen. See Table 13.23 for information regarding the diagnostic counter data displayed. Double-click on the Channel Status Icon Located beneath the Configuration icon to bring up the Channel Status screen.
Page 405 SLC Communication Channels 13-75 Table 13.23 SLC 5/03 and Higher Channel 0 DF1 Half-duplex Slave Channel Status (Continued) Status Field Diagnostic File Location Definition Messages Retry word 4 The number of message retries sent by the processor Undelivered Messages word 3 The number of messages that were sent by the processor but not acknowledged by the destination device Duplicate Messages...
Page 406: Df1 Radio Modem Communications
13-76 SLC Communication Channels Processors running OS Series C FRN 6 and higher firmware include a new DF1 Radio Modem channel 0 system mode driver called DF1 Radio Modem. This driver Communications implements a protocol, optimized for use with radio modem networks, that is a hybrid between DF1 Full-duplex protocol and DF1 Half-duplex protocol, and therefore is not compatible with either of these protocols.
Page 407: Df1 Radio Modem System Limitations
SLC Communication Channels 13-77 For modern serial radio modems that support full-duplex data port buffering and radio transmission collision avoidance, the DF1 Radio Modem driver can be used to set up a masterless peer-to-peer radio network, where any node can initiate communications to any other node at any time, as long as all of the nodes are within radio range so that they receive each other’s transmissions.
Page 408: Configuring Channel 0 For Df1 Radio Modem
13-78 SLC Communication Channels • Can I take advantage of the SLC 5/03, 5/04, and 5/05 channel-to-channel passthru to remotely program the other SLC nodes using RSLinx and RSLogix 500 running on a PC connected to a local SLC processor via DH-485, DH+ or Ethernet? Yes, with certain limitations imposed based on the radio modem network.
Page 409 SLC Communication Channels 13-79 1. On the Channel 0 tab, choose DF1 Radio Modem for your Driver. 2. Configure the communication driver characteristics according to Table 13.24. Table 13.24 Define these communication parameters when configuring a SLC 5/03, 5/04, or 5/05 processor for DF1 Radio Modem communication.
Page 410 13-80 SLC Communication Channels Table 13.24 Define these communication parameters when configuring a SLC 5/03, 5/04, or 5/05 processor for DF1 Radio Modem communication. (Continued) Parameter Default Selections Chan. 0 System Control Line No Handshaking This parameter defines the mode in which the driver operates. Choose a method appropriate for your system’s configuration.
Page 411: Df1 Radio Modem Channel Status
SLC Communication Channels 13-81 DF1 Radio Modem Channel Status Channel Status data is stored in the diagnostic file defined on the Channel 0 Configuration screen. See Table 13.25 for information regarding the diagnostic counter data displayed. Double-click on the Channel Status Icon Located beneath the Configuration icon to bring up the Channel Status screen.
Page 412: Configuring The Store & Forward Table
13-82 SLC Communication Channels Table 13.25 SLC 5/03 and Higher Channel 0 DF1 Radio Modem Channel Status Status Field Diagnostic File Location Definition Messages Sent word 1 The total number of DF1 messages sent by the processor Messages Received word 2 The number of messages received with no errors Lack of Memory/Packet word 8...
Page 413 SLC Communication Channels 13-83 Figure 13.13 Applying DF1 Radio Modem Protocol (2nd Rebroadcast) Note 4 REPLY 1 (1st Rebroadcast) Note 3 REPLY 1 Node 1 Node 2 Node 3 Node 4 REPLY 1 CMD 1 (DST = 1, SRC = 4) (DST = 4, SRC = 1) No Bits 1, 3, 4...
Page 414: Using Modems That Support Df1 Communication Protocols
13-84 SLC Communication Channels The types of modems that you can use with SLC processors include dial-up Using Modems that Support phone modems, leased-line modems, radio modems and line drivers. For DF1 Communication point-to-point full-duplex modem connections, use DF1 Full-duplex protocol. Protocols For radio modem connections, use DF1 Radio Modem.
Page 415: Radio Modems
Line drivers, also called short-haul modems, do not actually modulate the serial data, but rather condition the electrical signals to operate reliably over long transmission distances (up to several miles). Allen-Bradley’s AIC+ Advanced Interface Converter is a half-duplex line driver that converts an RS-232 electrical signal into an RS-485 electrical signal, increasing the signal transmission distance from 50 to 4000 feet.
Page 416: Modem Control Line Operation In Slc 5/03, Slc 5/04 And
13-86 SLC Communication Channels The following sections explain the operation of the SLC 5/03, SLC 5/04, and Modem Control Line SLC 5/05 modem control when you configure the RS232 channel for a Operation in SLC 5/03, SLC particular modem handshaking method. 5/04 and SLC 5/05 Processors DF1 Full-duplex...
Page 417: Df1 Half-Duplex Master
SLC Communication Channels 13-87 Transmission requires all three inputs (CTS, DCD, and DSR) to be active. Whenever DSR and DCD are both active, the modem lost bit is reset. Half-duplex Modem without Continuous Carrier Selected - This is exactly the same as Half-duplex Modem with Continuous Carrier except monitoring of DCD is not performed.
Page 418: Df1 Radio Modem
13-88 SLC Communication Channels DF1 Radio Modem When you configure the SLC 5/03, SLC 5/04, and SLC 5/05 processors for DF1 Radio Modem, the following control line operation takes effect: No Handshaking Selected - DTR is always active and RTS is always inactive.
Page 419: Rts Send Delay And Rts Off Delay Parameters
SLC Communication Channels 13-89 Full Duplex Modem - DTR and RTS are always active except at the following times. If DSR goes inactive, modem lost bit (S:5/14) is turned on immediately. While DSR is inactive, neither reception nor transmission is performed.
Page 420: Modbus Rtu Protocol
13-90 SLC Communication Channels This section shows the configuration parameters for Modbus RTU (Remote Modbus RTU Protocol Terminal Unit transmission mode) protocol. For more information about the Modbus RTU protocol, see the Modbus Protocol Specification (available from http://www.modbus.org). SLC 5/03, SLC 5/04, and SLC 5/05 support Modbus RTU Master from Series C FRN11 onwards.
Page 421: Configuring A Channel For Modbus Rtu Master
SLC Communication Channels 13-91 Modbus protocol may not be consistently implemented in IMPORTANT the field. The Modbus specification calls for the addressing range to start at 1; however, some devices start addressing at 0. The Modbus Data Address in the Message Setup Screen may need to be incremented by one to properly access a Modbus slave’s memory, depending on that slave’s implementation of memory addressing.
Page 422 13-92 SLC Communication Channels Define the location of the diagnostic file used for Channel Status here. For Channel Status details, see page 13-94. Select the Modbus RTU Master from the Channel Configuration menu as shown below. Publication 1747-RM001G-EN-P - November 2008...
Page 423 SLC Communication Channels 13-93 The Baud defaults to 19200. The Control Line can be configured as: • No Handshaking • Full-Duplex Modem • Half Duplex without Continuous Carrier The Protocol Control defaults are: • No Handshaking • InterChar. Timeout = 0 •...
Page 424: Modbus Rtu Master Channel Status
13-94 SLC Communication Channels Modbus RTU Master Channel Status Channel Status data is stored in the diagnostic file defined on the Channel 0 Configuration screen. Double-click on the Channel Status Icon Located beneath the Configuration icon to bring up the Channel Status screen.
Page 425 SLC Communication Channels 13-95 Table 13.27 SLC 5/03 and Higher Channel 0 Modbus RTU Master Channel Status Data Link Layer Diagnostic Counters (Modbus Master RTU) Status Field Diagnostic File Location Definition Word 0; Bit 4 DTR (Data Terminal Ready) Word 0; Bit 3 DCD (Data Carrier Detect) Word 0;...
Page 426: Modbus Commands
13-96 SLC Communication Channels Table 13.28 SLC 5/03 and Higher Channel 0 Modbus RTU Master Channel Status PL Diagnostic Counters (Modbus Master RTU) Status Field/Description Diagnostic File Location Last Device Reporting Error Code 3 Word 12 Error Code 4 Counter Word 13 Error Code 5 Counter Word 14...
Page 427: Modbus Error Codes
SLC Communication Channels 13-97 Modbus Error Codes Upon receiving a Modbus command that is not supported or improperly formatted, the controller configured for Modbus RTU Master will respond with one of the exception codes listed in the following table: Table 13.30 Modbus Error Codes in Modbus RTU Master MSG Instruction Error Error Description...
Page 428: Ascii Communications
13-98 SLC Communication Channels The SLC 5/03 (OS301 and higher), SLC 5/04, and SLC 5/05 processors ASCII Communications support user-defined ASCII protocol by configuring channel 0 for User mode. In User mode, all received data is placed in a buffer. To access the data, use the ASCII instructions in your ladder program.
Page 429 SLC Communication Channels 13-99 Select User Mode 1. On the Channel 0 user tab, choose ASCII for your Driver. 2. Configure the communication driver characteristics according to Table 13.31. Publication 1747-RM001G-EN-P - November 2008...
Page 430 13-100 SLC Communication Channels Table 13.31 Define these communication parameters when configuring an SLC 5/03, SLC 5/04, or SLC 5/05 processor for ASCII communication. Parameter Default Selections Channel 0 User Baud Rate 19200 Toggles between the communication rate of 110, 300, 600, 1.2K, 2.4K, 4.8K, 9.6K and 19.2K (additional rate of 38.4K for SLC 5/04 and SLC 5/05 only).
Page 431: Slc Passthru Communications
Chapter SLC Passthru Communications There are three types of communications passthru (or bridging) supported by SLC 5/03, SLC 5/04 and SLC 5/05 processors. • Remote I/O passthru via the 1747-SN and 1747-BSN remote I/O scanner modules • DeviceNet passthru via the 1747-SDN DeviceNet scanner module •...
Page 432: Devicenet Passthru
14-2 SLC Passthru Communications Remote I/O passthru uses buffer number 32 in the IMPORTANT M0 and M1 files of the remote I/O scanner module. Avoid using these buffers for block transfer read/write instructions if you intend to use the remote I/O passthru capability. DeviceNet passthru allows the SLC processor system to act as a bridge DeviceNet Passthru between the channel 0 or channel 1 network, and the DeviceNet network...
Page 433 SLC Passthru Communications 14-3 processor communications during end-of-scan. In program mode, the processor continuously services communications including passthru. Channel-to-channel passthru only works for single hop bridging. One end node must be connected to the channel 0 network and the other end node must be connected to the channel 1 network.
Page 434: Additional Slc 5/03 Passthru Status Bits
14-4 SLC Passthru Communications destination equal to 128 plus the processor’s channel 1 network address are kept and executed by the passthru processor. DF1 Half-duplex Master packets received with a destination address outside of the valid channel 1 address range are rebroadcast as slave-to-slave messages.
Page 435: Using Rslinx Classic, Version 2.50 And Higher, With Slc 5/03
SLC Passthru Communications 14-5 The SLC 500 Fixed, SLC 5/01, SLC 502, ControlLogix, FlexLogix, and CompactLogix controllers can only respond to local DH-485 packets. Set S34/6=1 when using SLC 5/03 channel-to-channel passthru to communicate with the SLC 500 Fixed, SLC 5/01, SLC 502, ControlLogix, FlexLogix, and CompactLogix controllers via DH-485 on channel 1.
Page 436 14-6 SLC Passthru Communications When channel 0 is configured for DF1 Full-duplex and S:34/5=1, the SLC 5/03 passthru processor can be used by RSLinx to go online through channel 0 to the channel 1 DH-485 network. The RSLinx RS-232 DF1 driver is used, with Device configured for 1770-KF3/1747-KE.
Page 437: Slc 5/03 Passthru Error Codes
SLC Passthru Communications 14-7 DH-485 with S:34/0=0 or for DF1 Full-duplex with S:34/5=1, then a ‘+’ sign will appear to the left of the SLC 5/03 icon. Clicking on the ‘+’ sign will expose a DH-485 or DF1 network underneath the SLC 5/03 icon. Clicking on the ‘+’...
Page 438: Using Rslinx Classic, Version 2.50 And Higher, With Slc 5/04
14-8 SLC Passthru Communications Using RSLinx Classic, version 2.50 and higher, with SLC 5/04 Passthru RSLinx Classic, version 2.42 and below, only supports DF1 Full-duplex to DH+, DF1 Half-duplex Master to DH+, DH-485 to DH+, DH+ to DF1 Full-duplex, and DH+ to DH-485 passthru. RSLinx Classic, version 2.43 supports all modes of channel-to-channel passthru described below, except when channel 0 control line handshaking is enabled.
Page 439: Creating And Filling Out The Passthru Routing Table File
SLC Passthru Communications 14-9 1784-KT, -KTX(D), -PKTX(D), or –PCMK card. When RSWho is browsing the SLC 5/04 on DH+, and channel 0 is either configured for DH-485 with S:34/0=0 or for DF1 with S:34/5=1, then a ‘+’ sign will appear to the left of the SLC 5/04 icon.
Page 440 14-10 SLC Passthru Communications Access to the passthru routing table is located under the channel configuration selection in RSLogix 500 Programming Software. If a Passthru Routing Table File number was entered in the General Tab in the Channel Configuration dialog box, click on the + in front of Channel Configuration to reveal the routing table selection.
Page 441: Using Rslinx Classic, Version 2.50 And Higher, With Slc 5/05
SLC Passthru Communications 14-11 Only Ethernet devices that support Client Server IMPORTANT Protocol (CSP), such as SLC 5/05 processors, PLC-5 processors, PLC-5 Ethernet sidecars (1785-ENET), and RSLinx software, can use SLC 5/05 passthru. Passthru does not work with Ethernet devices supporting only EtherNet/IP protocol.
Page 442 14-12 SLC Passthru Communications exceed the number of available outgoing connections. The passthru processor will show up on the RSWho browse at node 128. When channel 0 is configured for DH-485 and S:34/0=0, the SLC 5/05 passthru processor can be used by RSLinx to go online through channel 0 to the channel 1 Ethernet network, as long as the PC running RSLinx is directly connected to the DH-485 network through a 1784-KTX(D), -PKTX(D), or –...
Page 443: Slc 5/05 Passthru Error Codes
SLC Passthru Communications 14-13 SLC 5/05 Passthru Error Codes A SLC 5/05 passthru processor may respond to a MSG instruction or RSLinx with an error code of 20H under the following conditions. • The routing table integer file number is out of range (9 to 255). •...
Page 444 14-14 SLC Passthru Communications 4. When you run RSWho on that passthru processor network, the SLC 5/03, 5/04, or 5/05 passthru processor should appear with a ‘+’ sign to the left of its icon as shown below: Figure 14.1 SLC 5/04 Passthru Processor on RSWho 5.
Page 445 SLC Passthru Communications 14-15 6. Check Browse only the specified addresses: and specify the low and high addresses of the range to be browsed: Figure 14.3 Configuring RSWho Browse Addresses 7. Click on the Advanced Browse Settings tab, check the Use custom browse settings box and enter 1 for the Maximum concurrent packets to this network: Figure 14.4 Advanced RSWho Browse Settings...
Page 446 14-16 SLC Passthru Communications If channel 0 is configured for DF1 Half-duplex Master, then the RSWho Poll Timeout should be set to: Channel 0 ACK Timeout * [1+ (2 * channel 0 message retries)] If channel 0 of an SLC 5/05 is configured for DF1 Radio Modem, then the RSWho Poll Timeout should be set the same as the Ethernet channel 1 MSG Reply Timeout.
Page 447: Messaging Examples
Chapter Messaging Examples The purpose of this chapter is to illustrate some of the more common but elaborate messaging examples using the SLC 500 processors. Not all examples will appear with a full detailed step by step procedure necessary. Step by Step procedures are available for all of the examples in KnowledgeBase Documents at the following website: http://support.rockwellautomation.com/knowledgebase Search for the associated Knowledge Base Document Number referenced...
Page 448: Remote Terminology
15-2 Messaging Examples In a multi-network environment, each network must IMPORTANT have a unique Link ID (Pass Thru Link ID) for help in obtaining acceptable results. Remote Terminology Remote Bridge Address Remote Bridge Address is the remote node address of the bridge device used to connect two networks together.
Page 449: Slc 5/03 Passthru Examples
Messaging Examples 15-3 Link ID’s are modified in each processors Channel Configuration properties. The default Passthru Link ID for the SLC 5/03, 5/04 and 5/05 processors channel 0 port is 1. The default Passthru Link ID for the SLC 5/03, 5/04 and 5/05 processors channel 1 port is 2.
Page 450 15-4 Messaging Examples The DF1 Remote/Local Pass-Thru bit (S2:34/6) is cleared in order to send messages to the channel 1 DH-485 network as remote DH-485 packets. This is the default setting for this bit. The DF1 Remote/Local Pass-Thru bit (S2:34/6) is needed when non-remote capable devices exist on the channel 1 DH-485 network, such as SLC 500 Fixed, SLC 5/01, SLC 5/02, ControlLogix, FlexLogix, and CompactLogix controllers.
Page 451 Messaging Examples 15-5 The following is the ladder logic necessary for the SLC 5/04 processor. The following is the MSG setup for the SLC 5/04 processor. The type of MSG instruction is Local. The local node address is the node number of the destination DH-485 address.
Page 452: Passthru Example: Dh-485 To Df1
15-6 Messaging Examples Passthru Example: DH-485 to DF1 The following illustrates a SLC 5/03 processor as a passthru processor that receives remote messages targeting the SLC 5/04 on the DF1 network. The SLC 5/03 processor will forward remote messages received on the DH-485 network (channel 1) to the DF1 network (channel 0) as local messages.
Page 453 Messaging Examples 15-7 No programming logic is necessary in the passthru processor. The following is the ladder logic necessary for the SLC 5/03 processor (node The following is the MSG Setup for the SLC 5/03 processor (node 2). Publication 1747-RM001G-EN-P - November 2008...
Page 454 15-8 Messaging Examples The type of MSG instruction is Remote. Local Bridge Address is the node number of the passthru DH-485 processor. Remote Bridge Address is not required. Remote Station Address is the node number of the target processor. A DF1 Full-duplex target device does not require a Remote Station Address.
Page 455 Messaging Examples 15-9 Passthru Example: DH-485 to DH-485 The following illustrates a SLC 5/03 processor as a passthru processor when both channel’s networks are configured for DH-485. The SLC 5/03 processor will forward remote messages received on the DH-485 network (channel 1) to the DH-485 network (channel 0) as remote messages.
Page 456 15-10 Messaging Examples No programming logic is necessary in the passthru processor. The following is the ladder logic necessary for the SLC 5/03 processor (node The following is the MSG Setup for the SLC 5/03 processor (node 2). The type of MSG instruction is Remote. Publication 1747-RM001G-EN-P - November 2008...
Page 457 Messaging Examples 15-11 Local Bridge Address is the node number of the passthru DH-485 processor. Remote Bridge Address is not required if the target device is remote capable. Remote Station Address is the node number of the target processor. Remote Bridge Link ID is the Link ID number of the destination network. The SLC 5/04 processor (node 15) is also capable of messaging to the SLC 5/03 (node 2).
Page 458: Slc 5/04 Passthru Examples
15-12 Messaging Examples SLC 5/04 Passthru Passthru Example: DF1 to DH+ Examples The following illustrates a SLC5/03 sending a local message via DF1 (CH0) to a SLC5/04 processor. The SLC5/04 processor that receives the initial message will send the message out DH+ to the SLC5/04 processor whose address matches the Local Bridge Address on the DH+ network as long as DF1 Passthru is enabled.
Page 459 Messaging Examples 15-13 The following is the ladder logic necessary for the SLC5/03 processor. MSG Instruction The following rung triggers the MSG instruction with a true-to-false transition upon entering into the run mode. Each time the MSG instruction either reaches Error or Done, rung 2:1 unlatches the enable bit, giving the instruction a false-to-true transition the next scan.
Page 460 15-14 Messaging Examples The following is the Channel Configuration MSG Setup for the SLC5/03 processor. Channel 0 Mode is set for System. Chan. 0 - System driver is set for DF1 Full Duplex. For the step by step procedure for this example, refer to Knowledgebase Document Number: G20023.
Page 461: Passthru Example: Dh+ To Df1
Messaging Examples 15-15 Passthru Example: DH+ to DF1 For the Step by Step procedure for this example refer to Knowledgebase Document Number: G20024. Publication 1747-RM001G-EN-P - November 2008...
Page 462: Passthru Example: Dh-485 To Dh
15-16 Messaging Examples Passthru Example: DH-485 to DH+ For the Step by Step procedure for this example refer to Knowledgebase Document Number: G20025. Publication 1747-RM001G-EN-P - November 2008...
Page 463 Messaging Examples 15-17 Passthru Example: DH+ to DH-485 For the Step by Step procedure for this example refer to Knowledgebase Document Number: G20026. Publication 1747-RM001G-EN-P - November 2008...
Page 464: Slc 5/05 Passthru Examples
15-18 Messaging Examples SLC 5/05 Passthru Passthru Example: DF1 to Ethernet Examples The IP Addresses used in the following illustration are for example purposes only. Contact your system administrator for IP addresses unique to your network. In the following diagram, a SLC 5/03 will send a local message via DF1 to the SLC 5/05 (IP Address 100.100.115.9).
Page 465 Messaging Examples 15-19 The following is the logic necessary for the SLC5/03 processor. MSG Instruction The following rung triggers the MSG instruction with a true-to-false transition upon entering into the run mode. Each time the MSG instruction either reaches Error or Done, rung 2:1 unlatches the enable bit, giving the instruction a false-to-true transition the next scan.
Page 466: Slc 5/05 (Ip Address 100.100.115.9) Bridge
15-20 Messaging Examples Local node address is the station address in the SLC 5/05 (IP Address 100.100.115.9) routing table where the target IP address for SLC 5/05 (IP Address 100.100.115.1) is stored. SLC 5/05 (IP Address 100.100.115.9) Bridge Ladder logic is not required for the SLC 5/05 which acts as the bridge from DF1-to-Ethernet.
Page 467: Passthru Routing Table
Messaging Examples 15-21 The Passthru Routing Table File is the integer file used by the processor to store routing table IP addresses and link them to unique node addresses. Channel 0 Source ID must be set to 0 when SLC 5/05 IMPORTANT (IP Address 100.100.115.9) is used as the bridge between DF1 full-duplex and Ethernet.
Page 468: Passthru Example: Ethernet To Df1
15-22 Messaging Examples Passthru Example: Ethernet to DF1 For the Step by Step procedure for this example refer to Knowledgebase Document Number: G20028. Publication 1747-RM001G-EN-P - November 2008...
Page 469: Passthru Example: Dh-485 To Ethernet
Messaging Examples 15-23 Passthru Example: DH-485 to Ethernet For the Step by Step procedure for this example refer to Knowledgebase Document Number: G20029. Publication 1747-RM001G-EN-P - November 2008...
Page 470: Passthru Example: Ethernet To Dh-485
15-24 Messaging Examples Passthru Example: Ethernet to DH-485 For the Step by Step procedure for this example refer to Knowledgebase Document Number: G20030. Publication 1747-RM001G-EN-P - November 2008...
Page 471: Remote Examples
Messaging Examples 15-25 All of the following remote examples were constructed for the following Remote Examples network. Remote Example: Network Overview Publication 1747-RM001G-EN-P - November 2008...
Page 472: Network Message Example: Slc 5/04 To Slc 5/02 Via Dhrio And Ka5
15-26 Messaging Examples Network Message Example: SLC 5/04 to SLC 5/02 via DHRIO and For the Step by Step procedure for this example refer to Knowledgebase Document Number: G20031. Publication 1747-RM001G-EN-P - November 2008...
Page 473: Network Message Example: Slc 5/04 To Slc 5/03 Via Dhrio And Ka5
Messaging Examples 15-27 Network Message Example: SLC 5/04 to SLC 5/03 via DHRIO and For the Step by Step procedure for this example refer to Knowledgebase Document Number: G20032. Publication 1747-RM001G-EN-P - November 2008...
Page 474 15-28 Messaging Examples Network Message Example: SLC 5/04 to SLC 5/04 via DHRIO For the Step by Step procedure for this example refer to Knowledgebase Document Number: G20033. Publication 1747-RM001G-EN-P - November 2008...
Page 475: Network Message Example: Slc 5/04 To Slc
Messaging Examples 15-29 Network Message Example: SLC 5/04 to SLC 5/02 via KA5 For the Step by Step procedure for this example refer to Knowledgebase Document Number: G20034. Publication 1747-RM001G-EN-P - November 2008...
Page 476: Network Message Example: Slc 5/04 To Slc
15-30 Messaging Examples Network Message Example: SLC 5/04 to SLC 5/03 via KA5 For the Step by Step procedure for this example refer to Knowledgebase Document Number: G20035. Publication 1747-RM001G-EN-P - November 2008...
Page 477: Network Message Example: Slc 5/04 To Slc 5/05 Via Dhrio And Enet
Messaging Examples 15-31 Network Message Example: SLC 5/04 to SLC 5/05 via DHRIO and ENET For the Step by Step procedure for this example refer to Knowledgebase Document Number: G20036. Publication 1747-RM001G-EN-P - November 2008...
Page 478: Network Message Example: Slc 5/05 To Slc 5/04 Via Enet And Dhrio
15-32 Messaging Examples Network Message Example: SLC 5/05 to SLC 5/04 via ENET and DHRIO For the Step by Step procedure for this example refer to Knowledgebase Document Number: G20037. Publication 1747-RM001G-EN-P - November 2008...
Page 479: Network Message Example: Slc 5/05 To Slc 5/03 Via Enet, Cnb And Kfc
Messaging Examples 15-33 Network Message Example: SLC 5/05 to SLC 5/03 via ENET, CNB and KFC For the Step by Step procedure for this example refer to Knowledgebase Document Number: G20038. Publication 1747-RM001G-EN-P - November 2008...
Page 480: Network Message Example: Slc 5/05 To Slc 5/03 Via Enet, Dhrio And Ka5
15-34 Messaging Examples Network Message Example: SLC 5/05 to SLC 5/03 via ENET, DHRIO and KA5 For the Step by Step procedure for this example refer to Knowledgebase Document Number: G20039. Publication 1747-RM001G-EN-P - November 2008...
Page 481 Messaging Examples 15-35 Network Message Example: PLC 5/20E to SLC 500 CH0 via ENI For the Step by Step procedure for this example refer to Knowledgebase Document Number: G20040. Publication 1747-RM001G-EN-P - November 2008...
Page 482 15-36 Messaging Examples Notes: Publication 1747-RM001G-EN-P - November 2008...
Page 483: Troubleshooting Faults
Chapter Troubleshooting Faults This chapter lists the major error fault codes, indicates the probable causes of faults, and recommends corrective action. This chapter also explains the operating system download faults for the SLC 5/03 (and higher) processors. The following section describes the different ways to automatically clear a fault Automatically Clear Faults using your programming software.
Page 484: Manually Clear Faults
16-2 Troubleshooting Faults The following section describes the different ways to manually clear a fault Manually Clear Faults when using an SLC processor. • Manually clear the major fault bit S:1/13, and the minor and major error bits S:5/0-7 in the status file, using a programming device or a Data Table Access Module.
Page 485: Slc Processor Faults
Troubleshooting Faults 16-3 The processor faults are divided into the following types. SLC Processor Faults • Powerup errors • Going-to-run errors • Run errors • User program instruction errors Powerup Errors Table 16.1 Powerup Errors Error Code Description Probable Cause Recommended Action (Hex) •...
Page 486: Going-To-Run Errors
16-4 Troubleshooting Faults Table 16.1 Powerup Errors Error Code Description Probable Cause Recommended Action (Hex) 0008 Internal software error. An unexpected software error Correct the problem, reload the occurred due to: program, and run. You can use the autoload feature with a memory •...
Page 487 Troubleshooting Faults 16-5 Table 16.2 Going-to-Run Errors (Continued) Error Code Description Probable Cause Recommended Action (Hex) • Either noise, 0012 The ladder program has a memory Correct the problem, reload the error. program, and run. If the error persists, • lightning, be sure to use current RSI •...
Page 488: Run Errors
16-6 Troubleshooting Faults Table 16.2 Going-to-Run Errors (Continued) Error Code Description Probable Cause Recommended Action (Hex) 0018 Incompatible user program. The user program is too advanced to Contact your your local Rockwell Operating system type mismatch. be executed in the current operating Automation representative to This error can also occur during system.
Page 489 Troubleshooting Faults 16-7 Table 16.3 Run Errors (Continued) Error Code Description Probable Cause Recommended Action (Hex) 0021 A remote power failure of an Fixed in FRN 1 to 4 SLC 5/01 Fixed and FRN 1 to 4 SLC 5/01 expansion I/O chassis has occurred. processors: Power was removed or processors: Cycle power on the local the power dipped below specification...
Page 490 16-8 Troubleshooting Faults Table 16.3 Run Errors (Continued) Error Code Description Probable Cause Recommended Action (Hex) 0025 Excessive stack depth/JSR calls for A JSR instruction is calling for a file Correct the user program to meet the the STI routine. number assigned to an STI routine.
Page 491: User Program Instruction Errors
Troubleshooting Faults 16-9 Table 16.3 Run Errors (Continued) Error Code Description Probable Cause Recommended Action (Hex) 002D An invalid referenced indirect Either a subelement is referenced Correct the references and try again. address subelement exists. incorrectly or an indirect reference has been made to an M-file.
Page 492 16-10 Troubleshooting Faults Table 16.4 User Program Instruction Errors (Continued) Error Code Description Probable Cause Recommended Action (Hex) 0034 A negative value for a timer The accumulated or preset value of a If the user program is moving values accumulator or preset value was timer in the user program was to the accumulated or preset word of detected.
Page 493: I/O Errors
Troubleshooting Faults 16-11 I/O Errors ERROR CODES: The characters xx in the following codes represent the slot number, in hexadecimal. If the exact slot cannot be determined, the characters xx become 03 for fixed controllers and 1F for modular controllers. Refer to the table below.
Page 494 16-12 Troubleshooting Faults Table 16.6 I/O Errors Error Code Description Probable Cause Recommended Action (Hex) • Either noise, xx50 A chassis data error is detected. Correct the problem, clear the fault, and re-enter Run mode. • lightning, • improper grounding, •...
Page 495 Troubleshooting Faults 16-13 Table 16.6 I/O Errors (Continued) Error Code Description Probable Cause Recommended Action (Hex) xx56 The chassis configuration specified The chassis configuration specified by Correct the chassis configuration, in the user program is detected as the user does not match the hardware. reload the program and run.
Page 496 16-14 Troubleshooting Faults Table 16.6 I/O Errors (Continued) Error Code Description Probable Cause Recommended Action (Hex) xx90 Interrupt problem on a disabled A specialty I/O module requested Refer to the user manual for the slot. service while a slot was disabled. specialty I/O module.
Page 497: Troubleshoot Slc 5/03 And Higher Processors
Troubleshooting Faults 16-15 Between the time you apply power to the processor, and it has a chance to Troubleshoot SLC 5/03 and establish communication with a connected programming device, the only form Higher Processors of communication between you and the processor is through the LED display. Powerup LED Display When power is applied, all the LEDs flash on momentarily and then off.
Page 498 16-16 Troubleshooting Faults The following table describes the possible LED combinations that are displayed every other time the LEDs flash on. Table 16.7 LED Combinations ON LED Display Description FAULT, FORCE, DH-485, DH+ , or Ethernet Fatal hardware error exists. FAULT, FORCE, RS232, DH-485 or DH+ A hardware watchdog timeout exists.
Page 499: Os300, Series A, Frn 1
Appendix SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History OS300, Series A, FRN 1 Original Release released: June 1993 OS300, Series A, FRN 2 Enhancements released: July 1993 None OS300, Series A, FRN 3 Enhancements released: March 1994 •...
Page 500: Released: August 1994
SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History OS301, Series A, FRN 5 Enhancements released: August 1994 • ASCII Instructions The ASCII instructions ABL, ACB, ACI, ACL, ACN, AEX, AHL, AIC, ARD, ARL, ASC, ASR, AWA, and AWT are supported in this release. The STRING and ASCII data types are also supported.
Page 501 SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History OS400, Series A, FRN 1 Original Release released: August 1994 OS301, Series A, FRN 6 Enhancements OS400, Series A, FRN 2 None released: November 1994 OS301, Series A, FRN 7 Enhancements 0S400, Series A, FRN 3 •...
Page 502 SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History OS301, Series A, FRN 8 Enhancements OS400, Series A, FRN 4 None released: April 1995 OS302, Series A, FRN 9 Enhancements OS401, Series A, FRN 5 • Indirect Addressing released: December 1995 Allows for simplified programming.
Page 503 SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History • Remote I/O (RIO) Passthru via a 1747-SN Scanner Module (OS401 only) Allows an SLC 5/04 processor to act as a bridge between DH+ and RIO. Remote I/O passthru also supports uploads/downloads of applications to RIO devices.
Page 504: Os302, Series C, Frn
SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History OS500, Series A, FRN 1 Original Release released: October 1997 OS302, Series B, FRN 11 Enhancements OS401, Series B, FRN 8 19200 DF1 FD Default Baud Rate (OS302 and OS401 only) OS500, Series A, FRN 2 released: November 1997 The default baud rate of channel 0 has been modified from 1200 to...
Page 505: Os501, Series C, Frn 3
September 2000 With block-transfer instructions, you can transfer up to 64 words to or from a remote device over an Allen-Bradley RIO link. A Block Transfer Read (BTR) is used when a remote device transfers data to the SLC. A Block Transfer Write (BTW) is used when an SLC processor writes data to a remote device.
Page 506 SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History instruction moves the current value of the 10uS free running clock into the destination address. If it is an integer address, it only moves the least 16 bits into the address. If it is a float address, it converts the long integer value into a float and moves it to the relative address.
Page 507 SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History permissible for the control block to take up User Ladder Program space as well as use additional user memory for storing runtime ramp information that is not user accessible. •...
Page 508 A-10 SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History • Message Error Code (OS501 only) After a Unix Server has defined the unsolicited “Client” IP address in SLC 5/05, the Server is removed from the network. The SLC 5/05 “Client”...
Page 509: Os302, Series C, Frn 4
SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History A-11 (BSD) that has been in use since the development of the PLC-5 Ethernet over eight years ago. This stack was also ported over to the legacy Ethernet products to let us take advantage of any bug fixes we did not pickup over the years, enhanced UDP message support and the ability to do super-netting.
Page 510 A-12 SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History OS302, Series C, FRN 5 Enhancements OS401, Series C, FRN 5 • Additional Ethernet connections for 32k and 64k processors (OS501 OS501, Series C, FRN 5 only) released: October 2001 The total number of available Ethernet connections has increased by eight from 16 to 24 in the 32k (L552) and 64k (L553) SLC 5/05...
Page 511 SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History A-13 OS302, Series C, FRN 6 Enhancements OS401, Series C, FRN 6 • Response support for additional PLC-5 style commands OS501, Series C, FRN 6 released: November 2002 SLC 5/03, 5/04 and 5/05 processors now can receive and respond to the following additional PLC-5 style commands received through channel 0 or channel 1.
Page 512 A-14 SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History coordinate a timed sequence of events among multiple processors on the network. • DF1 radio modem channel 0 driver This driver implements a protocol, optimized for use with radio modem networks, that is a hybrid between DF1 Full-duplex protocol and DF1 Half-duplex protocol, and therefore is not compatible with either of these protocols.
Page 513 SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History A-15 OS302, Series C, FRN 7 Enhancements OS401, Series C, FRN 7 • SLC 5/03 channel-to-channel passthru including the following OS501, Series C, FRN 7 operations: released: November 2003 –...
Page 514 A-16 SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History OS302, Series C, FRN 8 Enhancements OS401, Series C, FRN 8 None OS501, Series C, FRN 8 released: May 2004 OS501, Series C, FRN 9 Enhancements released: November 2004 Only SLC 5/05 Series C processor hardware can support IMPORTANT 100 Mbps Ethernet and increased Ethernet connections.
Page 515 SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History A-17 Using RSLogix 500 V6.30 and higher, you can disable the SLC 5/05 SNMP functionality from within the Channel 1 Configuration by unchecking the SNMP Server Enable check box shown in Figure A.1. The default (checked SNMP Server Enable box shown in Figure A.1) allows you to connect to the SLC 5/05 using an SNMP client.
Page 516 A-18 SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History network as the SLC 5/05 using the RSLinx Ethernet/IP driver (AB_ETHIP-x), the RSLinx CIP Options need to be configured for Messaging as shown in Figure A.3. Figure A.3 RSLinx CIP Options Configuration In addition to reducing the number of RSLinx Messaging Connections per PLC to one, it is also recommended that the Messaging Connection Retry Interval be increased from the default of 1.25 seconds to 8...
Page 517 SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History A-19 OS302, Series C, FRN 10 Enhancements OS401, Series C, FRN 10 • Three new explicit message instructions: OS501, Series C, FRN 10 – CEM (ControlNet Explicit Message) released: January 2006 –...
Page 518 A-20 SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History DHCP is another option for dynamically configuring the IP address of the SLC 5/05 processor channel 1 Ethernet port (in addition to BOOTP). When the SLC 5/05 is configured for DHCP, it will broadcast a DHCP request at every power-up requesting that an IP address be assigned to it.
Page 519 SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History A-21 OS302, Series C, FRN 11 Enhancements OS401, Series C, FRN 11 • Modbus RTU Master capability on RS232 Channel 0 OS501, Series C, FRN 11 released: June 2008 Modbus RTU Master capability is added to RS232 Channel 0 communication.
Page 520 A-22 SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History Notes: Publication 1747-RM001G-EN-P - November 2008...
Page 521: Status File Overview
Appendix SLC Status File This appendix lists the: • SLC processor status file overview • status file detailed word/bit descriptions This appendix discusses the status file functions of the Fixed, SLC 500, SLC 5/01, SLC 5/02, SLC 5/03, SLC 5/04 and SLC 5/05 processors. The processors function similarly, but the higher numbered processors utilize more features.
Page 522 SLC Status File The status file contains the following words: Table B.1 Status File Location Word Function Applies To Page Arithmetic and Scan Status Flags processors Processor Mode Status/Control Processor Alternate Mode Status/Control B-13 S:3L Current Scan Time B-19 S:3H Watchdog Scan Time B-20 Free Running Clock...
Page 523 SLC Status File Table B.1 Status File Location (Continued) Word Function Applies To Page S:16, S:17 Word Single Step Rung/File SLC 5/02 and B-40 higher S:18, S:19 Single Step Breakpoint Rung/File B-40 S:20, S:21 Word Fault Powerdown Rung/File B-41 S:22 Maximum Observed Scan Time B-42 S:23...
Page 524: Status File Details
SLC Status File Table B.1 Status File Location (Continued) Word Function Applies To Page S:54 Last Major Error Fault Code SLC 5/03 and B-57 higher S:55 Last DII ISR Scan Time B-57 S:56 Maximum DII ISR Scan Time B-57 S:57 Operating System Catalog Number B-57 S:58...
Page 525 SLC Status File Table B.2 Status File Functions Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 Arithmetic and Scan Status Bits • • • • • The arithmetic flags are assessed by the processor following the execution of any math, logical, or move instruction. The state of these bits remains in effect until the next math, logical, or move instruction in the program is executed.
Page 526 SLC Status File Table B.2 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:0/3 Status Sign Bit • • • • • This bit is set by the processor when the result of a math, logical, or move instruction is negative.
Page 527 SLC Status File Table B.2 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:1/6 Status Forces Installed Bit • • • • • This bit is set by the processor if you have installed forces in a ladder program.
Page 528 SLC Status File Table B.2 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:1/10 Static Config Load Memory Module on Memory Error Bit • • • • • (See table on You can use this bit to transfer a memory module program to page B-60 for all the processor in the event that a processor memory error is setting...
Page 529 SLC Status File Table B.2 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:1/11 Static Config Load Memory Always Bit • • • • (See table on When this bit is set, you can overwrite a processor program page B-60 for all with a memory module program by cycling processor power.
Page 530 B-10 SLC Status File Table B.2 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:1/12 Static Config Load Memory Module and Run Bit • • • • (See table on With this bit, you can overwrite a processor program with a page B-60 for all memory module program by cycling processor power.
Page 531 SLC Status File B-11 Table B.2 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:1/12 All modes in the fixed, SLC 5/01, and SLC 5/02 processors are • • • • considered to be remote because they do not have a continued keyswitch.
Page 532 B-12 SLC Status File Table B.2 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:1/13 Dynamic Major Error Halted Bit • • • • • Config This bit is set by the processor any time a major error is encountered.
Page 533 SLC Status File B-13 Table B.2 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:1/14 Status Access Denied Bit (OEM Lock) • • • • • You can allow or deny future access to a processor file. Set this bit to deny access.
Page 534 B-14 SLC Status File Table B.2 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:2/1 Static Config STI (Selectable Timed Interrupt) Enabled Bit • • • • This bit is set in its default condition, or when set by the STE or STS instruction.
Page 535 Byte address mode - in effect when the bit is set (1): This mode is used when the processor is receiving a message from a device on the network, possibly through a bridge or gateway. This setting is compatible with Allen-Bradley PLC inter-processor communication. Publication 1747-RM001G-EN-P - November 2008...
Page 536 B-16 SLC Status File Table B.2 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:2/9 Static Config Memory Module Program Compare • • • When this bit is set inside a valid program that is contained in a memory module, no modification of the NVRAM user program files is allowed.
Page 537 SLC Status File B-17 Table B.2 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:2/14 Dynamic Math Overflow Selection Bit • • • • Config Set this bit when you intend to use 32-bit addition and subtraction.
Page 538 B-18 SLC Status File Table B.2 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:2/15 Dynamic Communications Servicing Selection Bit • • • • Config (Ethernet Channel 1 for SLC 5/05) (DH+ Channel 1 for SLC 5/04) (DH-485 Channel 1 for SLC 5/03) When set, only one communication request/command can be serviced per END, TND, REF, or SVC.
Page 539 SLC Status File B-19 Table B.2 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:3L Status Current/Last 10 ms Scan Time • • The value of this byte tells you how much time elapses in a program cycle.
Page 540 B-20 SLC Status File Table B.2 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:3L Application example: Your application requires that each continued and every program scan execute in the same length of time. You measure the maximum and minimum scan times and find them to be 40 ms and 20 ms.
Page 541 SLC Status File B-21 Table B.2 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 Status Free Running Clock • Only the first 8 bits (byte value) of this word are assessed by the processor. This value is zeroed at powerup in the REM Run mode.
Page 542 B-22 SLC Status File Table B.2 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:5/0 Dynamic Overflow Trap Bit • • • • • Config When this bit is set by the processor, it indicates that a mathematical overflow has occurred in the ladder program.
Page 543 SLC Status File B-23 Table B.2 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:5/4 Dynamic M0-M1 Referenced on Disabled Slot Bit • • • • Config This bit is set whenever any instruction references an M0 or M1 module file element for a slot that is disabled (via its I/O slot enable bit).
Page 544 B-24 SLC Status File Table B.2 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:5/11 Status Battery Low Bit • • • • This bit is set whenever the Battery Low LED is on. The bit is cleared when the Battery Low LED is off.
Page 545 SLC Status File B-25 Table B.2 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:5/15 Status ASCII String Manipulation Error • • • This bit applies to SLC 5/03 (OS301 and higher), SLC 5/04, and SLC 5/05 processors.
Page 546 B-26 SLC Status File Table B.2 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 Status Major Error Fault Code • • • • • A hexadecimal code is entered in this word by the processor when a major error is declared.
Page 547 SLC Status File B-27 Table B.3 S:6 Error Codes Address Error Errors Fault Classification Processor Code Non- User Fixed 5/02 5/03 5/04 5/05 (Hex) User 5/01 Non- Recov Recov 0001 NVRAM error. • • • • • continued 0002 Unexpected hardware watchdog •...
Page 548 B-28 SLC Status File Table B.3 S:6 Error Codes (Continued) Address Error Errors Fault Classification Processor Code Non- User Fixed 5/02 5/03 5/04 5/05 (Hex) User 5/01 Non- Recov Recov 0020 A minor error bit is set at the end of the •...
Page 549 SLC Status File B-29 Table B.3 S:6 Error Codes (Continued) Address Error Errors Fault Classification Processor Code Non- User Fixed 5/02 5/03 5/04 5/05 (Hex) User 5/01 Non- Recov Recov 002B Either the file number exists, but it is • •...
Page 550 B-30 SLC Status File Slot Slot Slot Slot This value indicates that the slot was not found (500 fixed controller). Slot Numbers (xx) in hexadecimal This value indicates that the slot was not found (SLC 5/01, SLC 5/02, SLC 5/03, SLC 5/04, and SLC 5/05 processors). Publication 1747-RM001G-EN-P - November 2008...
Page 551 SLC Status File B-31 Table B.3 S:6 Error Codes Address Error User Program Instruction Fault Classification Processor Code Errors Non- User Fixed 5/02 5/03 5/04 5/05 (Hex) User 5/01 Non- Recov Recov 0030 Attempt was made to jump to • •...
Page 552 B-32 SLC Status File Table B.3 S:6 Error Codes (Continued) Address Error User Program Instruction Fault Classification Processor Code Errors Non- User Fixed 5/02 5/03 5/04 5/05 (Hex) User 5/01 Non- Recov Recov xx51 A “stuck” runtime error is • •...
Page 553 SLC Status File B-33 Table B.3 S:6 Error Codes (Continued) Address Error User Program Instruction Fault Classification Processor Code Errors Non- User Fixed 5/02 5/03 5/04 5/05 (Hex) User 5/01 Non- Recov Recov xx5A Hardware interrupt problem. • • • •...
Page 554 B-34 SLC Status File Table B.3 S:6 Error Codes (Continued) Address Error User Program Instruction Fault Classification Processor Code Errors Non- User Fixed 5/02 5/03 5/04 5/05 (Hex) User 5/01 Non- Recov Recov xx80 Identifies a specialty I/O module • •...
Page 555 SLC Status File B-35 Table B.4 Status File Functions Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 Status Suspend Code/Suspend File • • • • • When a non-zero value appears in S:7, it indicates that the SUS instruction identified by this value has been evaluated as true, and the Suspend Idle mode is in effect.
Page 556 B-36 SLC Status File Table B.4 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:11 Dynamic Config I/O Slot Enables • • • • • S:12 These two words are bit mapped to represent the 30 possible I/O slots in an SLC 500 system.
Page 557 SLC Status File B-37 Table B.4 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:13 Status and Math Register • • • • • Dynamic Config S:14 Use this double register to produce 32-bit signed divide and multiply operations, precision divide or double divide operations, and 5-digit BCD conversions.
Page 558 B-38 SLC Status File Table B.4 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:15L Static Config Node Address • • • • This byte value contains the node address of your processor on the DH-485 or DH+ link. Each device on the DH-485 link must have a unique address between the decimal values 0 and 31.
Page 559 SLC Status File B-39 Table B.4 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:15H Static Config When a configure channel command is received for channel • • 1, the node address is overwritten with the value contained in your channel configuration.
Page 560 B-40 SLC Status File Table B.4 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:16 Status Test Single Step - Start Step On - Rung/File • • • • S:17 These registers indicate the executable rung (word S:16) and file (word S:17) number that the processor executes next when operating in the Test Single Step mode.
Page 561 SLC Status File B-41 Table B.4 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:20 Status Test - Fault/Powerdown - Rung/File • • • • S:21 These registers indicate the executable rung (word S:20) and file (word S:21) number that the processor last executed before a major error or powerdown occurred.
Page 562 B-42 SLC Status File Table B.4 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:22 Status Maximum Observed Scan Time • • • • This word indicates the maximum observed interval between consecutive scans. Consecutive scans are defined as intervals between file 2/rung 0 and the END, TND, or the REF instruction.
Page 563 SLC Status File B-43 Table B.4 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:24 Dynamic Config Index Register • • • • This word indicates the element offset used in indexed addressing. When an STI, I/O Slot, or Fault Routine interrupts normal execution of your program, the original value of this register is restored when execution resumes.
Page 564 B-44 SLC Status File Table B.4 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:27 Status I/O Interrupt Enabled • • • • S:28 These two words are bit-mapped to the 30 I/O slots. Bits S:27/1 through S:28/14 refer to slots 1 through 30.
Page 565 SLC Status File B-45 Table B.4 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:30 Dynamic Config Selectable Timed Interrupt - Setpoint • • • • You enter the timebase, in tens of milliseconds, to be used in the selectable timed interrupt.
Page 566 B-46 SLC Status File Table B.4 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:32 Status I/O Interrupt Executing • • • • This word indicates the slot number of the specialty I/O module that generated the currently executing ISR. This value is cleared upon completion of the ISR, REM Run mode entry, or upon power-up.
Page 567 SLC Status File B-47 Table B.4 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:33/3 Status Selection Status (Channel 0) • • • When set, this bit indicates that the channel 0 communication port is in the System mode (DF1 mode). When reset, this bit indicates that channel 0 is in the User mode (ASCII mode).
Page 568 B-48 SLC Status File Table B.4 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:33/7 Dynamic Config Message Servicing Selection (Channel 1) • • • This bit is only valid when the channel 1 Comms Servicing Selection bit (S:2/15) is clear (which selects service all commands).
Page 569 SLC Status File B-49 Table B.4 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:33/10 Dynamic Config Discrete Input Interrupt Reconfiguration Bit • • • Set this bit with your user program or programming terminal to cause the DII function to reconfigure itself at the next interrupt occurrence or end of each scan (END, TND, or REF).
Page 570 B-50 SLC Status File Table B.4 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:33/13 Static Config Scan Time Timebase Selection • • • This bit determines the timebase used to average the Scan time (S:23) and the maximum Scan Time (S:22). When clear, the value contained in the average and maximum scan times represent the number of 10 ms increments that have occurred.
Page 571 SLC Status File B-51 Table B.4 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:34/0 Dynamic Config DH-485 Passthru Disabled Bit • • • When channel 0 is configured for DH-485 protocol, this bit provides the capability to pass received packets between channels.
Page 572 B-52 SLC Status File Table B.4 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:34/5 Dynamic Config DF1 Passthru Enabled Bit • • • If channel 0 is enabled with a DF1 protocol and this bit is SET, then the passthru operation is enabled between Channel 0 and Channel 1.
Page 573 SLC Status File B-53 Table B.4 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:36/8 Status DII Lost • • • This bit is set anytime a DII interrupt occurs while the DII Pending bit (S:2/11) is also set. When set, you are notified that a DII interrupt has been lost.
Page 574 B-54 SLC Status File Table B.4 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:39 Dynamic Config Clock/Calendar Day • • • This value contains the day value of the clock/calendar. Valid range is 1 to 31. To disable the clock/calendar, write zeros to all clock or calendar words (S:37 to S:42).
Page 575 SLC Status File B-55 Table B.4 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:46 Dynamic Config Discrete Input Interrupt - File Number • • • You enter a program file number (3-255) to be used as the discrete input interrupt subroutine.
Page 576 B-56 SLC Status File Table B.4 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:49 Dynamic Config Discrete Input Interrupt - Compare Value • • • You enter a bit mapped value that corresponds to the bit transitions that must occur in the discrete I/O card for a count or interrupt to occur.
Page 577 SLC Status File B-57 Table B.4 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:53L Dynamic Config Day-of-Week • • • This value contains the day-of-week value of the clock/calendar. Valid range is 0 to 6 (Sunday=0). To disable the clock/calendar, write zeros to all clock and calendar words (S:37 to S:42).
Page 578 B-58 SLC Status File Table B.4 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:61 Status Processor Series Indicates the processor series. For example, the value of 0 indicates series A and the value of 1 indicates series B. S:62 Status Processor Revision...
Page 579 SLC Status File B-59 Table B.4 Status File Functions (Continued) Address Classification Description Fixed 5/02 5/03 5/04 5/05 5/01 S:67 to S:82 Dynamic Config DF1 Radio Modem Store and Forward Table • • • In DF1 Radio Modem with Store and Forward enabled in the channel configuration, these 16 words are bit mapped to represent the 255 possible nodes and the broadcast address.
Page 580 B-60 SLC Status File The following table lists all combination settings for S:1/10, S:1/11 and S:1/12. Table B.5 Combination Settings for S:1/10, S:1/11, and S:1/12 S:1/10 S:1/11 S:1/12 Memory Memory Mode Before/After Powerdown Major Fault Module Memory Module Before/After Present? Error? Transfer? Powerdown...
Page 581 Appendix Memory Usage This appendix provides: • instruction words for the Fixed, SLC 5/01, SLC 5/02, SLC 5/03, SLC 5/04, and SLC 5/05 processor. • examples on how to estimate the total memory usage of your system. If you want to use a See page Fixed or SLC 5/01 processor SLC 5/02 processor...
Page 582 Memory Usage The number of words used by an instruction is indicated in the following table. Fixed and SLC 5/01 Since the program is compiled by the programmer, it is only possible to Processors establish estimates for the instruction words used by individual instructions. The calculated memory usage will normally be greater than the actual memory usage, due to compiler optimization.
Page 583 Memory Usage Table C.2 SLC 500 Fixed and SLC 5/01 List of Instructions (Continued) Mnemonic Memory Usage Name Instruction Type Page (user words) 1.50 Negate Data Handling 5-24 1.50 Not Equal Comparison 1.00 Data Handling 5-23 1.50 Data Handling 5-21 1.00 One-shot Rising Basic...
Page 584 Memory Usage Estimating Total Memory Usage of Your System Using a Fixed or SLC 5/01 Processor __________ 1. Calculate the total instruction words used by the instructions in your program and enter the result. Refer to the table on page C-2. __________ 2.
Page 585 Memory Usage Fixed Controller Memory Usage Example L20B Fixed I/O Controller XIC and XIO 42 x 1.00 42.00 OTE instructions 10 x 0.75 7.50 TON instructions 10 x 1.00 10.00 CTU instruction 1 x 1.00 1.00 RES instruction 1 x 1.00 1.00 Instruction Usage 61.50...
Page 586 Memory Usage SLC 5/01 Processor Memory Usage Example 1747-L514 processor, 30-slot configuration, (15) 1746-IA16, (10) 1746-OA8, (1) 1747-DCM full configuration, (1) 1746-NI4, (1) 1746-NIO4I 50 XIC and XIO 50 x 1.00 = 50.00 15 OTE instructions 15 x 0.75 = 11.25 TON instructions 5 x 1.00 = 5.00...
Page 587 Memory Usage The number of instruction words used by an instruction is indicated in the SLC 5/02 Processor following table. Since the program is compiled by the programmer, it is only possible to establish estimates for the instruction words used by individual instructions.
Page 588 Memory Usage Table C.3 SLC 5/02 List of Instructions (Continued) Mnemonic Memory Usage Name Instruction Type Page (user words) 1.50 Limit Test Comparison 1.50 LIFO Load Data Handling 5-28 1.50 LIFO Unload Data Handling 5-28 0.50 Master Control Reset Program Flow Control 1.50 Masked Comparison for Equal Comparison...
Page 589 Memory Usage Table C.3 SLC 5/02 List of Instructions (Continued) Mnemonic Memory Usage Name Instruction Type Page (user words) 0.50 Temporary End Program Flow Control 1.00 Convert to BCD Data Handling 1.00 Timer Off-delay Basic 2-10 1.00 Timer On-delay Basic 1.00 Examine If Closed Basic...
Page 590 C-10 Memory Usage Estimating Total Memory Usage of Your System Using a SLC 5/02 Processor __________ 1. Calculate the total instruction words used by the instructions in your program and enter the result. Refer to the table on page -7. __________ 2.
Page 591 Memory Usage C-11 SLC 5/02 Memory Usage Example 1747-L524 series C processor, 30-slot configuration, (15) 1746-IA16, (10) 1746-OA8, (1) 1747-DCM full configuration, (1) 1746-NI4, (1) 1746-NIO4I XIC and XIO 50 x 1.00 = 50.00 OTE instructions 15 x 0.75 = 11.25 TON instructions 5 x 1.00 = 5.00...
Page 592 C-12 Memory Usage The SLC 5/03 (and higher) processors and the SLC 5/02 processor User Word Comparison accumulate user words differently during the creation of a user program. The Between SLC 5/03 (and SLC 5/02 processor is generally more efficient in its word usage than the SLC higher) Processors and the 5/03 (and higher) processors.
Page 593 Memory Usage C-13 Data Words Files 0 and 1 In the SLC 5/02 processor, each I/O data word consumes 0.75 words of memory. In the SLC 5/03 processor, each I/O data word consumes 3 words of data. File 2 The status file word usage is contained in the overhead values for both the SLC 5/02 and SLC 5/03 processors.
Page 594 C-14 Memory Usage Table C.5 SLC 5/03, SLC 5/04 and SLC 5/05 List of Instructions (Continued) Mnemonic Applies to SLC Memory Usage Name Instruction Type Page (user words) FP = floating point • • • • 2.00 ASCII Clear Receive and/or Send ASCII 10-9 Buffer...
Page 595 Memory Usage C-15 Table C.5 SLC 5/03, SLC 5/04 and SLC 5/05 List of Instructions (Continued) Mnemonic Applies to SLC Memory Usage Name Instruction Type Page (user words) FP = floating point • • • • • 2.00 Decode 4 to 1 of 16 Data Handling 5-10 •...
Page 596 C-16 Memory Usage Table C.5 SLC 5/03, SLC 5/04 and SLC 5/05 List of Instructions (Continued) Mnemonic Applies to SLC Memory Usage Name Instruction Type Page (user words) FP = floating point • • • • 3.00 Less Than or Equal Comparison •...
Page 597 Memory Usage C-17 Table C.5 SLC 5/03, SLC 5/04 and SLC 5/05 List of Instructions (Continued) Mnemonic Applies to SLC Memory Usage Name Instruction Type Page (user words) FP = floating point • • • • • 1.00 Reset Basic 2-20 •...
Page 598 C-18 Memory Usage Table C.5 SLC 5/03, SLC 5/04 and SLC 5/05 List of Instructions (Continued) Mnemonic Applies to SLC Memory Usage Name Instruction Type Page (user words) FP = floating point • • • • • 1.00 Timer Off-delay Basic 2-10 •...
Page 599 Memory Usage C-19 Estimating Total Memory Usage of Your System Using an SLC 5/03, SLC 5/04, or SLC 5/05 Processor __________ 1. Add the total number of data file words used (excluding the status file and I/O data words) and enter the result.
Page 600 C-20 Memory Usage SLC 5/03, SLC 5/04, or SLC 5/05 Memory Usage Example 1747-L532 processor, 30-slot configuration, (15) 1746-IA16, (10) 1746-OA8, (1) 1747-DCM full configuration, (1) 1746-NI4, (1) 1746-NIO4I 100 data words 100 x 1.00 = 100.00 I/O data words 49 x 3.00 = 147.00 slot...
Page 601 Appendix Programming Instruction References This appendix lists all of the available programming instructions along with their parameters, valid addressing modes, and file types. The following addressing modes are available. Valid Addressing Modes and File Types Table D.1 Available Addressing Modes Addressing Mode Example Direct...
Page 602 Programming Instruction References Understanding the Different Addressing Modes The following descriptions will help you understand how to structure a specific type of address. Direct Addressing The data stored in the specified address is used in the instruction. For example: N7:0 ST20:5 T4:8.ACC Indexed Addressing...
Page 603 Programming Instruction References #N7:[N10:3] where N10:3 = 20 and S:24 = 15 The actual address used by the instruction is N7:35. Table D.3 Available Addressing Modes Instruction Description Instruction Valid Addressing Valid File Types Immediate Parameter Mode(s) Values ASCII Test Buffer for Line channel control direct none...
Page 604 Programming Instruction References Table D.3 Available Addressing Modes (Continued) Instruction Description Instruction Valid Addressing Valid File Types Immediate Parameter Mode(s) Values ASCII Set/Reset channel Handshake Lines AND mask direct, indexed direct O, I, S, B, T, C, R, N, 0 to FFFF indirect, indexed indirect A, ST, M OR mask...
Page 605 Programming Instruction References Table D.3 Available Addressing Modes (Continued) Instruction Description Instruction Valid Addressing Valid File Types Immediate Parameter Mode(s) Values Arc Tangent source direct, indexed direct O, I, S, B, T, C, R, N, -32,768 to 32,767 indirect, indexed indirect F, A, ST, M f-min to f-max destination...
Page 606 Programming Instruction References Table D.3 Available Addressing Modes (Continued) Instruction Description Instruction Valid Addressing Valid File Types Immediate Parameter Mode(s) Values ControlNet Explicit control block direct none Message control block length 1747-SCNR slot 1 to 30 size in words 0 to 248 (receive data) size in words 0 to 248...
Page 607 Programming Instruction References Table D.3 Available Addressing Modes (Continued) Instruction Description Instruction Valid Addressing Valid File Types Immediate Parameter Mode(s) Values Count Down counter direct none preset -32,768 to 32,767 accum -32,768 to 32,767 Count Up counter direct none preset -32,768 to 32,767 accum -32,768 to 32,767...
Page 608 Programming Instruction References Table D.3 Available Addressing Modes (Continued) Instruction Description Instruction Valid Addressing Valid File Types Immediate Parameter Mode(s) Values Divide source A direct, indexed direct O, I, S, B, T, C, R, N, -32,768 to 32,767 indirect, indexed indirect F, A, ST, M f-min to f-max source B...
Page 609 Programming Instruction References Table D.3 Available Addressing Modes (Continued) Instruction Description Instruction Valid Addressing Valid File Types Immediate Parameter Mode(s) Values FIFO Load source direct, indexed direct O, I, S, B, T, C, R, N, -32,768 to 32,767 indirect, indexed indirect A, ST, M FIFO array indexed direct...
Page 610 D-10 Programming Instruction References Table D.3 Available Addressing Modes (Continued) Instruction Description Instruction Valid Addressing Valid File Types Immediate Parameter Mode(s) Values High-speed Counter (SLC counter none 5/01) preset 1 to 32,767 counter direct none preset -32,768 to 32,767 accum -32,768 to 32,767 source direct...
Page 611 Programming Instruction References D-11 Table D.3 Available Addressing Modes (Continued) Instruction Description Instruction Valid Addressing Valid File Types Immediate Parameter Mode(s) Values LIFO Load source direct, indexed direct O, I, S, B, T, C, R, N, -32,768 to 32,767 indirect, indexed indirect A, ST, M LIFO array indexed direct...
Page 612 D-12 Programming Instruction References Table D.3 Available Addressing Modes (Continued) Instruction Description Instruction Valid Addressing Valid File Types Immediate Parameter Mode(s) Values Message read/write 0=read,1=write (5/02 only) target device 2=500CPU, 4=485CIF control block direct none control block length local address direct O, I, S, B, T, C, R, N, none...
Page 613 Programming Instruction References D-13 Table D.3 Available Addressing Modes (Continued) Instruction Description Instruction Valid Addressing Valid File Types Immediate Parameter Mode(s) Values Message type 64=peer-to-peer (5/03, 5/04, and read/write 0=read, 1=write 5/05 target device 2=500CPU, 4=485CIF, 8=PLC5 local/remote 16=local, 32=remote control block direct none...
Page 614 D-14 Programming Instruction References Table D.3 Available Addressing Modes (Continued) Instruction Description Instruction Valid Addressing Valid File Types Immediate Parameter Mode(s) Values Message type 64=peer-to-peer (5/05 Ethernet) read/write 0=read, 1=write target device 2=500CPU, 4=485CIF, 8=PLC5 local 16=local control block direct none control block length...
Page 615 Programming Instruction References D-15 Table D.4 Available Addressing Modes Instruction Description Instruction Valid Addressing Valid File Types Immediate Parameter Mode(s) Values Multiply source A direct, indexed direct O, I, S, B, T, C, R, N, -32,768 to 32,767 indirect, indexed indirect F, A, ST, M f-min to f-max source B...
Page 616 D-16 Programming Instruction References Table D.4 Available Addressing Modes (Continued) Instruction Description Instruction Valid Addressing Valid File Types Immediate Parameter Mode(s) Values Degrees to Radians source direct, indexed direct O, I, S, B, T, C, R, N, -32,768 to 32,767 indirect, indexed indirect F, A, ST, M f-min to f-max...
Page 617 Programming Instruction References D-17 Table D.4 Available Addressing Modes (Continued) Instruction Description Instruction Valid Addressing Valid File Types Immediate Parameter Mode(s) Values Scale with Parameters input direct, indexed direct O, I, S, B, T, C, R, N, none indirect, indexed indirect F, A, ST, M input min.
Page 618 D-18 Programming Instruction References Table D.4 Available Addressing Modes (Continued) Instruction Description Instruction Valid Addressing Valid File Types Immediate Parameter Mode(s) Values Sequencer Output file indexed direct O, I, S, B, N, A, ST none indexed indirect mask O, I, S, B, T, C, R, N, -32,768 to 32,767 direct, indexed direct A, ST, M...
Page 619 Programming Instruction References D-19 Table D.4 Available Addressing Modes (Continued) Instruction Description Instruction Valid Addressing Valid File Types Immediate Parameter Mode(s) Values Tangent source direct, indexed direct O, I, S, B, T, C, R, N, -32,768 to 32,767 indirect, indexed indirect F, A, ST, M f-min to f-max destination...
Page 620 D-20 Programming Instruction References Table D.4 Available Addressing Modes (Continued) Instruction Description Instruction Valid Addressing Valid File Types Immediate Parameter Mode(s) Values X to the Power of Y source A direct, indexed direct O, I, S, B, T, C, R, N, -32,768 to 32,767 indirect, indexed indirect F, A, ST, M...
Page 621 Programming Instruction References D-21 Message lengths for SLC 5/05 processors are shown in the next table. Message lengths are based on Ethernet buffer size of 2108 bytes (includes command header and system addressing in addition to actual file data). The local file is the destination file for reads and the source files for writes.
Page 622 D-22 Programming Instruction References Notes: Publication 1747-RM001G-EN-P - November 2008...
Page 623 Appendix Data File Organization and Addressing This chapter discusses the following topics. • Data file organization and addressing • Specifying indexed addressing • Specifying indirect addressing (SLC 5/03 OS302, SLC 5/04 OS401, and SLC 5/05 processors) • Specifying indirect indexed addressing (SLC 5/03 OS302, SLC 5/04 OS401, and SLC 5/05 processors) •...
Page 624 Data File Organization and Addressing hard to disk, replacing the original disk version with the edited version. The hard disk is the recommended location for a processor file. PROGRAMMING DEVICE Hard Disk Workspace Uniquely named processor files Processor files are created in the offline mode using the programming device. These files are then restored (downloaded), to the processor for online operation.
Page 625 Data File Organization and Addressing • Status (file 2) - This file stores controller operation information. This file is useful for troubleshooting controller and program operation. • Bit (file 3) - This file is used for internal relay logic storage. •...
Page 626 Data File Organization and Addressing Table E.1 Data file types, identifiers, and numbers (data files in processor memory) File Type Identifier File Number Output Input Status Timer Counter Control Integer Float User-Defined Files File Type Identifier File Number 9 to 255 Timer Counter Control...
Page 627 Data File Organization and Addressing Specifying Logical Addresses You assign logical addresses to instructions from the highest level (element) to the lowest level (bit). Addressing examples are shown in the table below. To specify the address Use these parameters of a Word within an integer N 7 : file...
Page 628 Data File Organization and Addressing To specify the address Use these parameters of a Bit within a bit file B 3 / File Type File Number Bit Delimiter Bit Number Bit within an integer file R 6 : File Type File Number File Delimiter Structure Number...
Page 629 Data File Organization and Addressing Slot Inputs Outputs None Table E.2 Data File 0 - Output Image Slot 0 Outputs (0 to Slot 1 Outputs (0 to INVALID Slot 2 Outputs (0 to Table E.3 Data File 1 - Input Image Slot 0 Inputs (0 to Slot 0 Inputs (16 to INVALID...
Page 630 Data File Organization and Addressing Assign I/O addresses to fixed I/O controllers Table E.4 Addressing Format Format Explanation Output Input Element delimiter Slot number Fixed I/O controller: 0 (decimal) Left slot of expansion chassis: 1 O:e.s/b Right slot of expansion chassis: 2 Word delimiter.
Page 631 Data File Organization and Addressing Slots 1 through 10 contain I/O modules. The remaining slots are saved for future I/O expansion. The figure indicates the number of inputs and outputs in each slot and also shows how these inputs and outputs are arranged in the data files. For these files, the element size is always 1 word.
Page 632 E-10 Data File Organization and Addressing Specifying Indexed Addresses The indexed address symbol is the # character. Place the # character immediately before the file-type identifier in a logical address. You can use more than one indexed address in your ladder program. Enter the offset value in word 24 of the status file (S:24).
Page 633 Data File Organization and Addressing E-11 In this example, the processor uses the following addresses: Table E.5 Addresses used for Indexing Value: Base Address: Offset Value in Offset Address: S:24 Source N7:10 N7:20 Destination N7:50 N7:60 SLC 5/03 (OS301 and higher), SLC 5/04, and SLC 5/05 processors: If the indexed address is a floating point (F8:) data file, then the index offset value in S:24 is the offset in elements.
Page 634 E-12 Data File Organization and Addressing SLC 5/03 (OS301 and higher) SLC 5/04, and SLC 5/05 processors: When an indexed string data file is specified, indexed addressing is not allowed to cross a string element boundary. A run-time error will occur if you use an offset value that results in crossing a string element boundary.
Page 635 Data File Organization and Addressing E-13 Monitoring Indexed Addresses The offset address value is not displayed when you monitor an indexed address. For example, the value at N7:2 appears when you monitor indexed address #N7:2. Example If your application requires you to monitor indexed data, we recommend that you use a MOV instruction to store the value.
Page 636 E-14 Data File Organization and Addressing Effects of Program Interrupts on Index Register S:24 When normal program operation is interrupted by the user error handler, an STI, or an I/O interrupt, the content of index register S:24 is saved; then, when normal program operation is resumed, the content of index register S:24 is restored.
Page 637 Data File Organization and Addressing E-15 Examples Table E.6 Valid Addresses Valid Address Variable Explanation N7:[C5:7.ACC] Word number The word number is the accumulated value of counter 7 in file 5. B3/[I:0.17] Bit number The bit number is stored in input word 17. N[N7:0]:[N9:1] File and word The file number is stored in integer address N7:0 and the word number in integer address N9:1.
Page 638 E-16 Data File Organization and Addressing If you are using file instructions and also indexed ATTENTION addressing, make sure that you monitor and/or load the correct offset value prior to using an indexed address. Otherwise, unpredictable operation could occur, resulting in possible personal injury and/or damage to equipment.
Page 639 Data File Organization and Addressing E-17 Sequencer Instructions The following figure shows a user-defined file within bit data file 3. For this particular user-defined file, you would enter the following parameters when programming the instruction. Bit Data File 3 #B3:4 Address of the user-defined file is #B3:4.
Page 640 E-18 Data File Organization and Addressing The following figure shows a user-defined file within Data File 0- Output Image. We used this particular data file configuration in regard to I/O addressing on page B-12. Here, we are defining a file 5 elements long. Note that for the output file (and the input file as well), an element is always one word, referenced as the slot and word taken together.
Page 641 Data File Organization and Addressing E-19 When entering values into an instruction or data table element, you can specify the radix of your entry using the appropriate suffix. The radixes that can be used to enter data into an instruction or data table element are: •...
Page 642 E-20 Data File Organization and Addressing Addressing M0-M1 Files The addressing format for M0 and M1 files is below: Mf:e.s/b Where M = module f = file type (0 or 1) e = slot (1 to 30) s = word (0 to max. supplied by module) b = bit (0 to 15) Restrictions on Using M0 and M1 Data File Addresses M0 and M1 data file addresses can be used in all instructions except the OSR...
Page 643 Data File Organization and Addressing E-21 Mf:e.s Mf:e.s Mf:e.s Mf:e.s Mf:e.s f = file (0 or 1) When you are monitoring the ladder program in the run or test mode, the programming terminal does not show these instructions as being true when the processor evaluates them as true. SLC 5/03 and Higher Processors The SLC 5/03 and higher processors allow you to monitor the actual state of each addressed M0/M1 address (or data table).
Page 644 E-22 Data File Organization and Addressing First scan bit. It makes this rung true only for the first scan after entering the Run mode. The COP instruction that follows copies data form an M1 data file to an integer file. This technique is used to monitor the contents of an M0 or M1 data file indirectly, in a processor data file.
Page 645 Data File Organization and Addressing E-23 In the equivalent rungs of the following figure, XIC instruction M0:2.1/1 is used only in rung 1, reducing the scan time by approximately 1 ms. These rungs provide equivalent operation to those of figure A by substituting XIC instruction B3/10 for XIC instruction M0:2.1/1 in rung 2.
Page 646 E-24 Data File Organization and Addressing Capturing M0-M1 File Data The first two ladder diagrams in the last section illustrate a technique allowing you to capture and use M0 or M1 data as it exists at a particular time. In the first figure, bit M0:2.1/1 could change state between rungs 1 and 2.
Page 647 Data File Organization and Addressing E-25 This rung is true for the first scan after powerup to unlatch M0:2.1/1. Some specialty I/O modules use G (confiGuration) files (indicated in the G Data Files - Specialty I/O specific specialty I/O module user’s manual). These files can be thought of as Modules the software equivalent of DIP switches.
Page 648 E-26 Data File Organization and Addressing Notes: Publication 1747-RM001G-EN-P - November 2008...
Page 649 Appendix Number Systems This appendix: • covers binary and hexadecimal numbers. • explains the use of a hex mask to filter data in certain programming instructions. The processor memory stores 16-bit binary numbers. As indicated in the Binary Numbers following figure, each position in the number has a decimal value, beginning at the right with 2 and ending at the left with 2 Each position can be 0 or 1 in the processor memory.
Page 650 Number Systems = 16384 = 8192 = 4096 = 2048 = 1024 = 512 = 256 = 128 = 64 = 32 = 16 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 32767 = 0 This position is always zero for positive numbers.
Page 651 Number Systems = 16384 = 8192 = 4096 = 2048 = 1024 = 512 = 256 = 128 = 64 = 32 = 16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 32767 = 32768 This position is always 1 for negative numbers.
Page 652 Number Systems 2x16 = 8192 1x16 = 256 8x16 = 128 10x16 = 10 2 1 8 A 8586 Hexadecimal and binary numbers have the following equivalence. Hexadecimal 2 1 8 A = 8586 Binary 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 = 8586...
Page 653 Number Systems This is a 4-character code, entered as a parameter in SQO, SQC, and other Hex Mask instructions to exclude selected bits of a word from being operated on by the instruction. The hexadecimal values are used in their binary equivalent form, as indicated in the figure below.
Page 654 Number Systems The SLC 5/03, OS301 and higher, SLC 5/04, and SLC 5/05 processors Binary Floating-point support the use of floating-point. Use floating-point when you want to Arithmetic manipulate numbers outside of the range − 32768 to + 32767 or for a resolution finer than one unit.
Page 655 Appendix Application Example Programs This appendix is designed to illustrate various instructions described previously in this manual. Application example programs include: • paper drilling machine using most of the instructions. • time driven sequencer using TON and SQO instructions. • event driven sequencer using SQC and SQO instructions. •...
Page 656 Application Example Programs OPERATOR PANEL Start I:1/6 Stop I:1/7 Change Drill Soon Change Drill Now O:3/4 O:3/6 Thumbwheel for Thickness in 1/4 in. Drill Change Reset 5 Hole 3 Hole 7 Hole (Keyswitch) I:1/11-I:1/14 I:1/9-I:1/10 I:1/8 Drill Home Drill On/Off O:3/1 I:1/5 Drill Retract O:3/2 Drill Forward O:3/3...
Page 657 Application Example Programs Undrilled books are placed onto a conveyor taking them to a single spindle Paper Drilling Machine drill. Each book moves down the conveyor until it reaches the first drilling Operation Overview position. The conveyor stops moving and the drill lowers and drills the first hole.
Page 658 Application Example Programs The following rung will call the drill sequence subroutine. The subroutine manages the operation of the drilling sequence and will restars the conveyor upon completion of the drilling sequence. 0003 Jump T o Subroutine SBR File Number The following rung will call the subroutine that is used to track the amount of wear on the current drill bit.
Page 659 Application Example Programs Drill Mechanism Operation When the operator presses the start button, the drill motor turns on. After the book is in the first drilling position, the conveyor subroutine sets a drill sequence start bit, and the drill moves toward the book. When the drill has drilled through the book, the drill body hits a limit switch and causes the drill to retract up out of the book.
Page 660 Application Example Programs Conveyor Operation When the start button is pressed, the conveyor moves the books forward. As the first book moves close to the drill, the book trips a photo-eye sensor. This tells the machine where the leading edge of the book is. Based on the position of the selector switch, the conveyor moves the book until it reaches the first drilling position.
Page 661 Application Example Programs The following rung will keep track of the hole number that is being drilled and loads the next correct DII preset based on the hole count. This rung is only active when the "HOLE SELECTOR" switch is in the "3-HOLE" position.
Page 662 Application Example Programs The following rung is identical to the previous two rungs except that it is only active when the "HOLE SELECTOR" switch is in the "7-HOLE" position. 0004 Sequencer Output File #N10:12 1746-IA16 1746-IA16 Mask 0FFFFh Dest S:50 Control R6:6 Length...
Page 663 Application Example Programs The following rung stops the conveyor and signals the main program (file 2) to initialize a drilling sequence. The DRILL SEQUENCE subroutine (program file 6) resets the drill sequence start bit and sets the conveyor drive bit (O:3/0) upon completion of the drilling sequence.
Page 664 G-10 Application Example Programs Drill Calculation and Warning The program tracks the number of holes drilled and the number of inches of material that have been drilled through using a thumbwheel. The thumbwheel is set to the thickness of the book per 1/4 inch. (If the book is 1 1/2 inches thick, the operator would set the thumbwheel to 6.) When 25,000 inches have been drilled, the Change Drill Soon pilot light turns on.
Page 665 Application Example Programs G-11 The following rung will reset the number o f 1/4" increments and the 1/4" thousands when the "DRILL CHANGE RESET" keyswitch is energized. Drill Change Reset Keyswitch 0001 Clear Dest N7:11 1746-IA16 0< Clear Dest N7:10 0<...
Page 666 G-12 Application Example Programs The following rung will convert the BCD thumbwheel value from BCD to integer. This is done because processor operates upon integer values. This rung also "debounces" the thumbwheel to ensure that conversion only occurs on valid BCD values. Note that invalid BCD values can occur while the operator is changing the BCD thumbwheel.
Page 667 Application Example Programs G-13 The following rung will keep a running total of how many inches of paper have been drilled with the current drill bit. Every time a hole is drilled, add the thickness (in ¼"s) to the running total (kept in ¼"s). The same OSR is necessary because the ADD will execute every scan that the rung is true, and the drill body would actuate...
Page 668 G-14 Application Example Programs The following application example illustrates the use of the TON and SQO Time Driven Sequencer instructions in a traffic signal at an intersection. The timing requirements are: Application Example • Red light - 30 seconds. • Yellow light - 15 seconds. •...
Page 669 Application Example Programs G-15 The following application example illustrates how the FD (found) bit on an Event Driven Sequencer SQC instruction can be used to advance as SQO to the next step (position). Application Example This application program is used when a specific order of events is required to occur repeatedly.
Page 670 G-16 Application Example Programs Table G.1 SQC Compare Data Addresses Data (Radix = Decimal) N7:0 N7:10 If the high-speed counter reached its high preset of 350 (indicates that the holding area reached maximum capacity), it would energize O:0/0, shutting down the filling operation. Before re-starting the filler, allow the packer to empty the holding area until it is about 1/3 full. HSC Interr due to High Preset...
Page 671 Dummy Bit Go to rest of program 0003 0004 The purpose of this section is to illustrate how to interface Allen-Bradley Interfacing with Enhanced Enhanced Bar Code Decoders to SLC 5/03 and higher processors via the Bar Code Decoders Over DH-485 network.
Page 672 G-18 Application Example Programs The only devices capable of polling a slave device on DH-485 are the SLC 5/03 and higher processors. For the SLC 5/03 processors (1747-OS302, FRN10 or later), polling can be done via channels 0 and 1. For the SLC 5/04 processors (1747-OS401, FRN7 or later), channel 0 supports this capability.
Page 673 2 seconds. Refer to the DS/DD Series Enhanced Bar Code Decoders (Bulletin 2755) User’s Manual, publication 2755-833, for details concerning the configuration of your Allen-Bradley Enhanced Bar Code Decoder. Operating Sequence With the bar code decoder configured as previously described, the following series of event take place when a product with a good bar code label breaks the photo switch and this input to the SLC goes from false-to-true.
Page 674 G-20 Application Example Programs Sequence of Events The photo switch input to the SLC goes from false-to-true The SLC processors send a “trigger” command to the decoder via a “MSG Write” command. The decoder immediately replies to the SLC that it has properly received the command.
Page 675 Application Example Programs G-21 Optimizing MSG Time-out If the time delay between sending a command to an Enhanced Bar Code Decoder and polling for the reply is not long enough, the MSG instruction will time-out (MSG TO bit = 1) each time it is enabled from that point forward. To re-synchronize the SLC processor and the decoder, you need to cycle power on the decoder to clear its buffer.
Page 676 G-22 Application Example Programs Example Scanner and Decoder Configuration Table G.4 Scanner and Decoder Configuration Scanner Configuration Parameters 2755-DS/DD Series B Enhanced Bar Code Decoder Configuration Parameters Scanner Control Page Host Configurations Page Discrete I/O: Read Package 25 ms Baud Rate: 19200 No-Read Package 25 Laser Light:...
Page 677 Application Example Programs G-23 Example Ladder Program This rung detects the Photo Switch input going from false-to-true, and latches internal storage bit B3/1. This rung moves the decimal value for the bar code decoder “trigger” command into the MSG instructions “Offset” parameter. The programming software does not allow values greater than 255 decimal to be entered into a MSG control block “Offset”...
Page 678 G-24 Application Example Programs The internal storage bit, B3/1, holds the MSG instruction true until DN and DA are both set, indicating completion of the command sent and reply received sequence. When DN is set and DA is reset, unlatching the MSG EN bit effectively toggles the MSG instruction the same as if the MSG rung were toggled, i.e.
Page 679 Application Example Programs G-25 This rung moves the decimal value for the bar code decoder “Read” command into the MSG instruction’s “Offset” parameter. The programming software does not allow values greater than 255 decimal to be entered into a MSG control block “Offset” value. The internal storage bit, B3/2, gives the MSG instruction a false-to-true transition to send the initial command.
Page 680 G-26 Application Example Programs When the SLC processor sets both DN and DA for a MSG instruction, the MSG sequence to an Enhanced BAr Code Decoder is complete. In this case, the decoder has received the “Read” command and has formulated a reply to this command. Therefore, unlatch B3/2 at this time to be ready for the next “REad”...
Page 681 Appendix Supported Read/Write Commands This appendix provides the read and write commands that are supported by Supported Read/Write the SLC 500 Fixed, SLC 5/01, SLC 5/02, SLC 5/03, SLC 5/04, and SLC 5/05 Commands processors. Refer to the DF1 Protocol and Command Set Reference Manual, publication 1770-6.5.16, for additional command details.
Page 682 Supported Read/Write Commands Notes: Publication 1747-RM001G-EN-P - November 2008...
Page 683 Index 10-15 Numerics ASCII Read Characters (ARD) 10-17 ASCII Read Line (ARL) 5/03 processors 10-19 ASCII String Compare (ASR) 15-3 passthru examples 10-22 ASCII Write (AWT) 5/04 processors 10-20 ASCII Write with Append (AWA) 15-12 passthru examples 10-14 Integer to String (AIC) 5/05 processors 10-11 String Concatenate (ACN)
Page 684 Index 13-31–13-34 12-5 configuring SLC 5/05 message instruction (5/02 only) 13-33 using the Rockwell Utility message instruction (SLC 5/03 and SLC 13-6 Broadcast write command 5/04) 12-11 configuration options 12-30 control block layout 12-11 entering parameters E-24 12-37 capturing M0-M1 file data timing diagram 12-3 carry bit...
Page 685 Index 2-13 how counters work Data Highway Plus communication 13-52, 13-58, 13-66, 13-72, 13-80 13-10 protocol 13-18 creating data for indexed addresses global status word overview E-11 13-19 transmit enable bit 13-20 E-11, E-15 transmit receive bit crossing file boundaries 13-22 B-19 using the SLC 5/04 processors...
Page 686 Index B-55 13-22 Slot Number processor performance 11-20 12-3 subroutine content SVC instruction Discrete Input Interrupt Status File EtherNet/IP Explicit Message (EEM) B-56 12-58 Accumulator B-55 Bit mask Examine if Closed (XIC) B-56 Compare Value basic instruction B-56 Down Coun Examine if Open (XIO) E-18 displaying values...
Page 687 Index A-19, A-21 FRN 10 update instruction execution times - SLC A-13 FRN 6 update processors A-15 FRN 7 update fixed and SLC 5/01 processors A-16 SLC 5/02 processor FRN 9 update 13-51, 13-80 SLC 5/03, 5/04, and 5/05 processors full-duplex station C-13 instruction set...
Page 688 Index B-12 major error halted bit message 12-5 manuals, related instruction (SLC 5/02 processor) 12-41 instruction error codes Masked Move (MVM) B-46 5-18 reply pending (channel 0) updates to arithmetic status bits B-47 servicing selection (channel 0) math instructions B-48 servicing selection (channel 1) 32-Bit addition and subtraction 15-1...
Page 689 Index E-18 B-57 radices used processor catalog number E-18 numeric constants processor files B-58 NVRAM size organization overview data files program files B-58 One-Shot Rising (OSR) processor revision E-18 entering parameters program constants 16-15 operating system program file B-57 catalog number memory structure 16-15 downloading...
Page 690 Index 15-2 remote station address effects on index register B-6, B-22, B-23, B-53, B-59 7-12 reserved Sequencer Load (SQL) 2-20 Sequencer Output (SQO) Reset (RES) operation Retentive Timer (RTO) 7-12 Sequencer Load (SQL) 2-12 using status bits 7-12 application specific instruction retries 12-3 Service Communications (SVC)
Page 691 Index clearing faults 16-1 automatically 4-32 Tangent (TAN) 16-2 manually 4-32 math instruction 16-4 going-to-run errors test single step 16-15 processor LEDs B-40 breakpoint 16-6 runtime errors B-40 start step on 16-9 user program instruction errors B-41 test-fault/powerdown timer accumulator value (.ACC) timer accuracy timer and counter instructions understanding file organization...
Page 692 Publication 1747-RM001G-EN-P - November 2008...
Page 693 SLC 500 Alphabetical List of Instructions Instruction Page Instruction Page Instruction Page ABL - Test Line for Buffer 10-6 ENC - Encode 1 of 16 to 4 5-11 PID - Proportional/Intergral/Differential ABS - Absolute 4-24 EQU - Equal RAD - Degrees to Radians ACB - Number of Characters In Buffer 10-7 FBC - File Bit Comparison...
Page 694 States return procedure. PLC-2, PLC-3, PLC-5, SLC, SLC 500, DH+, DAta Highway Plus, RSLogix 500, RSLinx, RSLinx Classic, Allen-Bradley, and Rockwell Automation are trademarks of Rockwell Automation, Inc. Trademarks not belonging to Rockwell Automation are property of their respective companies.

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