Allen-Bradley SLC 500 Series Reference Manual page 557

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Table B.4 Status File Functions (Continued)

Classification

Dynamic Config

Math Register

Use this double register to produce 32-bit signed divide and

multiply operations, precision divide or double divide

operations, and 5-digit BCD conversions.

These two words are used in conjunction with the MUL, DIV,

DDV, FRD, and TOD math instructions. The math register

value is assessed upon execution of the instruction and

remains valid until the next MUL, DIV, DDV, FRD, or TOD

instruction is executed in the user program.

An explanation of how the math register operates is

included with the instruction definitions.

If you store 32-bit signed data values, you must manage this

data type without the aid of an assigned 32-bit data type.

For example, combine B10:0 and B10:1 to create a 32-bit

signed data value. We recommend that you keep all 32-bit

signed data in a unique data file and that you start all 32-bit

values on an even or odd word boundary for ease of

application and viewing. Also, we recommend that you

design, document, and view the contents of 32-bit signed

data in either the hexadecimal or binary radix.

When an STI, I/O Slot, or Fault Routine interrupts normal

execution of your program, the original value of the math

S:13 and S:14 are not used when the source or destination

is defined as floating point data.

When a DII interrupts normal execution of your program, the

original value of the math register is restored when

execution resumes.

SLC Status File

Publication 1747-RM001G-EN-P - November 2008

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