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● DPV1 functionality
● CiR functionality (DP slave / DP slot, configurable extension)
Note
ET 200M devices that were assigned to SYNC/FREEZE groups with STEP 7, must not
have modules of the type FM or CP inserted.
Table 1- 1
Use with the current CPU types
CPU
Order number of
the CPU:
6ES7...
CPU412
.. 412-1XF04-
0AB0
CPU412-2
..412-2XG04-0AB0 as of V4.0
CPU414-2
..414-2XG04-0AB0 as of V4.0
CPU414-3
..414-3XJ04-0AB0
CPU414-4H
..414-4HJ04-0AB0 as of V4.0
CPU416-2
..416-2XK04-0AB0 as of V4.0
CPU416-3
..416-3XL04-0AB0 as of V4.0
CPU416F-2
..416-2FK04-0AB0 as of V4.0
CPU417-4
..417-4XL04-0AB0 as of V4.0
CPU417-4H
..417-4HL04-0AB0 as of V4.0
Legend:
+ => The characteristic is supported / the listed mode is possible
- => The characteristic is not supported / the listed mode is not possible
All CPUs are capable of CiR (the H-CPUs HCiR).
1)
CP 443-5 Extended
Manual, 11/2018, C79000-G8976-C162-09
Firmware
Number of
version
AG_SEND or
AG_RECV calls at
same time
as of V4.0
24 /24
as of V4.1
24 /24
24 /24
as of V4.1
24 /24
24 /24
as of V4.1
24 /24
as of V4.0
24 /24
as of V4.1
24 /24
24 /24
as of V4.0.5
24 /24
64 / 64
as of V4.1
64 / 64
64 / 64
as of V4.1
64 / 64
64 / 64
as of V4.1
64 / 64
64 / 64
as of V4.1
64 / 64
64 / 64
as of V4.0.5
64 / 64
Application and functions
1.3 Requirements for use
a = SYNC/FREEZE functionality
b = DP-V1 functionality
c = CiR / HCiR functionality
d = enable / disable DP slaves
e = identify bus topology
a
b
c
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
+
+
-
+
+
1)
d
e
+
-
+
+
+
-
+
+
+
-
+
+
+
-
+
+
+
-
-
+
+
-
+
+
+
-
+
+
+
-
+
+
+
-
+
+
-
-
-
+
13
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