NEC 78K0S/KU1+ User Manual page 74

(a) The internal reset signal is generated by the power-on clear function on power application, the option byte is
referenced after reset, and the system clock is selected.
(b) The option byte is referenced and the system clock is selected. Then the high-speed internal oscillation
clock operates as the system clock.
Figure 5-9. Status Transition of Default Start by High-Speed internal oscillation
Remark PCC: Processor clock control register
PPCC: Preprocessor clock control register
74
CHAPTER 5 CLOCK GENERATORS
Power
application
V
Reset by
power-on clear
High-speed internal
oscillator selected
by option byte
Start with PCC = 02H,
PPCC = 02H
Clock division ratio
variable during
CPU operation
Interrupt
HALT
instruction
instruction
HALT
User's Manual U18172EJ2V0UD
> 2.1 V ±0.1 V
DD
Reset signal
Interrupt
STOP
STOP