Cpld Registers - Spectrum Digital TMS320VC5509A EVM PLUS Technical Reference

2.1.2 CPLD Registers

There are 11 DSP CPLD registers mapped into the DSP's lower CE1 address space
starting at address 0x3F0000. Since the CPLD decoder only uses part of the address
for decoding, the registers will be mirrored within the space.
The table below shows the bit definitions for the 11 registers in CPLD.
Addr
LSB Name
A4-A1
0000 USER_REG
0001 DC_REG
0010 Reserved
0011 Reserved
0100 VERSION
0101 Reserved
0110 MISC VCORE_CTL
0111 INT REG
1000 LCD0
Address0
1001 LCD1
Address0
1010 5502EVM LCD BUSY
Misc
Table 1: CPLD Register Definitions
Bit 7 Bit 6
USR_SW3 USR_SW2 USR_SW1
R R
DC_DET 0 DC_STAT1
R
CPLD_VER[3.0]
R
VCORE_CTL Reserved
1 0
Reserved Reserved Reserved
SHIFT SHIFT SHIFT
DATA7 DATA6 DATA5
SHIFT SHIFT SHIFT
DATA7 DATA6 DATA5
LCD_RESET Reserved
R R/W
1 BUSY 0
Bit 5 Bit 4 Bit 3
USR_SW0 USR_LED3
R R R/W
0(Off)
DC_STAT0 DC_RST
R R R
0(No reset)
0
VCORE_SEL Reserved
CPLD
REGISTERS
0 GPIO
1 BIT 6 & 7
THIS REG
Reserved WAKEUP
INT3
SHIFT SHIFT
DATA4 DATA3
SHIFT SHIFT
DATA4 DATA3
Reserved Reserved
R R R
Spectrum Digital, Inc
Bit 2 Bit 1 Bit 0
USR_LED2 USR_LED1 USR_LED0
R/W R/W R/W
0(Off) 0(Off) 0(Off)
0 DC_CNTL1 DC_CNTL0
R/W R/W
0(Low) 0(Low)
BOARD VERSION[2.0]
R
TIN0 McBSP2 McBSP0
IN/OUT ON/OFF SROM/
R/W Board AIC23
(0 INPUT) R/W Board
0 R/W
(Onboard) 0
(SROM)
Reserved WAKUP WAKEUP
INT1 INT0
SHIFT SHIFT SHIFT
DATA2 DATA1 DATA0
SHIFT SHIFT SHIFT
DATA2 DATA1 DATA0
Reserved Reserved Reserved
R R R
2-3