Power-On Sequence And System Reset; Power-On Sequence - Espressif Systems ESP32 Hardware Design Manuallines

2. SCHEMATIC CHECKLIST AND PCB LAYOUT DESIGN
cause a power rail collapse. Therefore, it is highly recommended to add another 10 µF capacitor to the power
trace, which can work in conjunction with the 0.1 µF capacitor. LC filter circuit needs to be added to near the
power pin so as to suppress high-frequency harmonics. The inductor's rated current is preferably 500 mA and
above.
VDD33
VDD33
VDD33
ANT1
PCB ANT
Notice:
• The recommended voltage of the power supply for ESP32 is 3.3V, and its recommended output current
is 500 mA or more.
• It is suggested that users add an ESD tube at the power entrance.

2.1.2 Power-on Sequence and System Reset

2.1.2.1 Power-on Sequence

ESP32 uses a 3.3V system power supply. The chip should be activated after the power rails have stabilized. This is
achieved by delaying the activation of CHIP_PU (Pin9) by time T after the 3.3V rails have been brought up. The rec-
ommended delay time (T) is given by the parameter of the RC(R = 10 kΩ, C = 0.1 µF) circuit. For reference design,
please refer to Figure ESP-WROOM-32 Peripheral Schematics in the
Notice:
If CHIP_PU is driven by a power management chip, then the power management chip controls the
ESP32 power state. When the power management chip turns on/off Wi-Fi through the high/low level
on GPIO, a pulse current may be generated. To avoid level instability on CHIP_PU, an RC delay (R = 10
kΩ, C = 0.1 µF) circuit is required.
Espressif Systems
L5
C13 C12 C11
C10
10uF NC
1uF 0.1uF
GND GND GND GND
1 L4 2.7nH±0.1nH
2
C15 C14
C16
270pF(NC)
Figure 3: ESP32 Analog Power Supply Pins
C20
C3 GND
100pF
1uF
C5
GND
GND
10nF
C9
GND
0.1uF
GND
2.0nH
C21
NC
GND
1
VDDA
2
LNA_IN
3
VDD3P3
4
VDD3P3
SENSOR_VP
5
SENSOR_VP
6
ESP-WROOM-32
9 ESP32 Hardware Design Guidelines V2.1
20K
R1
C6 3.3nF
Datasheet.