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SDC-SSD30AG
H
I
G
ARDWARE
NTEGRATION
UIDE
V
3.3
ERSION
Americas: +1-800-492-2320 Option 2
Europe: +44-1628-858-940
Hong Kong: +852-2268-6567 x026
www.lairdtech.com/wireless

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Summary of Contents for Laird SDC-SSD30AG

  • Page 1 SDC-SSD30AG ARDWARE NTEGRATION UIDE ERSION Americas: +1-800-492-2320 Option 2 Europe: +44-1628-858-940 Hong Kong: +852-2268-6567 x026 www.lairdtech.com/wireless...
  • Page 2: Revision History

    SDC-SSD30AG Hardware Integration Guide, version 3.3 EVISION ISTORY Version Revision Date Change Description 11/19/09 Transitioned Application Notes documentation to Hardware Integration Guide format. 1.01 11/23/09 Updated Specifications table. 1.02 12/15/09 Updated Power Consumption values in the Specifications table. 1.03 01/10/10 Revised Operational Description.
  • Page 3: Table Of Contents

    SDC-SSD30AG Hardware Integration Guide, version 3.3 ONTENTS Revision History ............................2 Contents ..............................3 Scope ................................4 Operational Description ..........................4 Block Diagram .............................. 5 Specifications ............................... 5 DC Electrical Characteristics ........................10 SDIO Interface Timing ..........................11 Pin Definitions ............................12 SSD30AG and SSD40NBT Pin Comparison Table ..................
  • Page 4: Scope

    The SDC-SSD30AG is a System in Package (SiP) Quad Flat pack, No leads (QFN) module and interfaces to host devices via 58 pads on the perimeter of the package. The device is based on the Atheros AR6002 chip which is an integrated device providing a Media Access Controller (MAC), a Physical Layer Controller (PHY or baseband processor), and 2.4 GHz and 5 GHz transceivers.
  • Page 5: Block Diagram

    SDC-SSD30AG Hardware Integration Guide, version 3.3 LOCK IAGRAM The block diagram for the SDC-SSD30 with Atheros AR6002 is as follows: PECIFICATIONS Feature Description System Interface 1-bit or 4-bit Secure Digital I/O Physical Interface 0.4 mm pitch QFN (Quad Flat No leads)
  • Page 6 SDC-SSD30AG Hardware Integration Guide, version 3.3 Feature Description Wi-Fi Media Access Protocol Carrier sense multiple access with collision avoidance (CSMA/CA) Network Architecture Types Infrastructure and ad hoc Network Standards IEEE 802.11a, 802.11b, 802.11d, 802.11e, 802.11g, 802.11h, 802.11i Wi-Fi Data Rates Supported 802.11a (OFDM) 6, 9, 12, 18, 24, 36, 48, 54 Mbps...
  • Page 7 0.25 dB for 2.4 GHz 54 Mbps -67 dBm (PER <= 10%) operation and 0.5 dB for 5 GHz 802.11b: operation when mounting the SDC-SSD30AG on an 1 Mbps -95 dBm appropriate PCB. 2 Mbps -94 dBm 5.5 Mbps...
  • Page 8 SDC-SSD30AG Hardware Integration Guide, version 3.3 Feature Description Wi-Fi Delay Spread 600 ns @ 1 Mbps 500 ns @ 2 Mbps 400 ns @ 5.5 Mbps 400 ns @ 6 Mbps 400 ns @ 9 Mbps 200 ns @ 11 Mbps...
  • Page 9 SDC-SSD30AG Hardware Integration Guide, version 3.3 Feature Description Compliance ETSI Regulatory Domain EN 300 328 EN 301 489 EN 301 893 EN 60950-1 EU 2002/95/EC (RoHS) FCC Regulatory Domain Part 15.247 Subpart C Grant Test Report Part 15.407 Subpart E...
  • Page 10: Dc Electrical Characteristics

    SDC-SSD30AG Hardware Integration Guide, version 3.3 DC E LECTRICAL HARACTERISTICS Note: VDDIO is the reference voltage for all chip IO and applies to the following pins: SDIO_DATA_0, SDIO_DATA_1, SDIO_DATA_2, SDIO_DATA_3, SDIO_CLK, SDIO_CMD, CHIP_PWD_L, SYS_RST_L, WL_LED_ACT, EX_GPIO, WLAN_ACTIVE, BT_ACTIVE, BT_PRIORITY, BT_FREQ,...
  • Page 11: Sdio Interface Timing

    SDC-SSD30AG Hardware Integration Guide, version 3.3 SDIO Interface Timing SDIO Timing Definitions Parameter Description Unit SDIO CLK (All values are referred to minimum VIH and maximum VIL Clock frequency data transfer mode Clock low time Clock high time Clock rise time...
  • Page 12: Pin Definitions

    SDC-SSD30AG Hardware Integration Guide, version 3.3 EFINITIONS Power Description Number Name Supply Ground Ground Ground Ground Antenna 2 (Auxiliary) ANT_2 50 ohm coplanar wave guide to antenna or antenna connector Ground Ground Ground Ground Antenna 1 (Main) ANT_1 50 ohm coplanar wave guide...
  • Page 13 SDC-SSD30AG Hardware Integration Guide, version 3.3 Power Description Number Name Supply RSVD Reserved – No Connect RSVD Reserved – No Connect 3.3/1.8V I/O Power VDDIO This is the reference pin for all I/O signaling pins. It accepts 1.8VDC to 3.3VDC WLAN LED activity indicator = 2mA max (VDDIO = 1.8V)
  • Page 14 SDC-SSD30AG Hardware Integration Guide, version 3.3 Power Description Number Name Supply Input from BT device. When high, indicates that Bluetooth is transmitting or BT_PRIORITY VDDIO receiving high priority packets, e.g. SCO and LMP. When not in use, leave open (float).
  • Page 15: Ssd30Ag And Ssd40Nbt Pin Comparison Table

    SDC-SSD30AG Hardware Integration Guide, version 3.3 SSD30AG and SSD40NBT Pin Comparison Table SSD30AG SSD40NBT SSD30AG SSD40NBT Pin Name Pin Name Pin Name Pin Name RSVD BT_PCM_SYNC RSVD BT_PCM_IN RSVD BT_PCM_CLK VDDIO VDDIO ANT_2 ANT_2 WL_LED_ACT WL_LED_ACT WL_GPIO_1 WL_GPIO_1 SYS_RST_L SYS_RST_L...
  • Page 16: Mechanical Specifications

    SDC-SSD30AG Hardware Integration Guide, version 3.3 your reference only to aid you in integrating the SSD30AG into your device. ECHANICAL PECIFICATIONS Note: DWG files are available from the Summit website. Please contact Summit for additional information or to request a different file type.
  • Page 17 SDC-SSD30AG Hardware Integration Guide, version 3.3 Note: The ground pad beneath the SiP (radio) should be the ground plane of your circuit board. The exposed portion of the ground pad beneath the SiP is controlled by the Solder Mask layer.
  • Page 18 SDC-SSD30AG Hardware Integration Guide, version 3.3 Americas: +1-800-492-2320 Option 2 Laird Technologies Europe: +44-1628-858-940 Hong Kong: +852-2268-6567 x026 www.lairdtech.com/wireless...
  • Page 19: Mounting

    Hardware Integration Guide, version 3.3 Mounting The SDC-SSD30AG is a Quad Flat pack with No Leads (QFN) System in Package (SiP). Summit has mounted this device to a PCB with a host and antenna connectors and markets that radio module as the SDC- MSD30AG.
  • Page 20: Rf Layout Design Guidelines

    Summit does not have specific regulatory approvals for the SDC-SSD30AG. Summit has regulatory approvals for the SDC-MSD30AG which is a PCB module that is based on the SDC-SSD30AG. As such, the ETSI, FCC, and Industry Canada final test reports for the SDC-MSD30AG may be leveraged when pursuing approvals for host devices that incorporate the SDC-SSD30AG.
  • Page 21: Documentation Requirements

    When integrating the SDC-SSD30AG into a host device, the integrator must include specific information in the user’s guide for the device into which the SDC-SSD30AG is integrated. The integrator must not provide information to the end user regarding how to install or remove this RF module in the user’s manual of the device into which the SDC-SSD30AG is integrated.
  • Page 22: Industry Canada

    When integrating the SDC-SSD30AG into a host device, the integrator must include specific information in the user’s guide for the device into which the SDC-SSD30AG is integrated. The integrator must not provide information to the end user regarding how to install or remove this RF module in the user’s manual of the device into which the SDC-SSD30AG is integrated.
  • Page 23: European Union

    R&TTE statements must be added in their entirety and without modification into a prominent place in the user’s guide for the device into which the SDC-SSD30AG is integrated: This device complies with the essential requirements of the R&TTE Directive 1999/5/EC. The following test methods have been applied in order to prove presumption of conformity with the essential requirements of the R&TTE Directive 1999/5/EC:...
  • Page 24 SDC-SSD30AG Hardware Integration Guide, version 3.3 [Jméno výrobce] tímto prohlašuje, že tento [typ za ízení] je ve shodě se základními ř Česky [Czech] požadavky a dalšími příslušnými ustanoveními směrnice 1999/5/ES. [fabrikantens navn] [udstyrets Undertegnede erklærer herved, at følgende udstyr Dansk [Danish] typebetegnelse] overholder de væsentlige krav og øvrige relevante krav i direktiv...
  • Page 25 SDC-SSD30AG Hardware Integration Guide, version 3.3 [Nome do fabricante] [tipo de equipamento] declara que este está conforme com os Português requisitos essenciais e outras disposições da Directiva 1999/5/CE. [Portuguese] [Ime proizvajalca] [tip opreme] izjavlja, da je ta v skladu z bistvenimi zahtevami in Slovensko ostalimi relevantnimi določili direktive 1999/5/ES.
  • Page 26: Appendix A: Schematic

    SDC-SSD30AG Hardware Integration Guide, version 3.3 PPENDIX CHEMATIC Because the SDC-MSD30AG is a PCB module that is based on the SDC-SSD30AG, the following SDC- MSD30AG schematic may be used as a reference. Figure 2: MSD30AG Schematic Americas: +1-800-492-2320 Option 2...

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