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®
Intel
IQ80315 I/O Processor Evaluation Platform
Table 5
defines the product code register bits.
Table 5.
PROD_CODE Register Definition
Bit
3–0
7–4
Table 6
defines the board stepping register bits.
Table 6.
BOARD_STEPPING Register Definition
Bit
3–0
7–4
Table 7
defines the CPLD firmware revision register bits.
Table 7.
CPLD_FW Register Definition
Bit
7–0
2.7.2
Flash
Eight MB of flash memory is implemented in the IQ80315 CRB using an Intel StrataFlash
device. The flash chip is packaged in a 64-ball easy BGA package. The IQ80315 CRB makes the
following signal connections to the flash chip:
•
The Intel
flash chip enable input CE# to enable flash access after reset.
•
The flash reset input is tied to the power supervisor reset output to prevent spurious flash
writes during power-up.
•
The program enable (VPEN) signal is tied high to enable flash programming under software
control.
•
The BYTE# signal is tied low to keep the flash in 8-bit interface mode.
18
Name
Identifies variants within a family of related products. This is a
resistor strapping input to the CPLD.
Product SKU
The IQ80315 product SKU definition is TBD.
Identifies the product. This value is hard-coded in the CPLD
firmware.
Product code
0x1 = IQ80315 CRB
Name
Board rework level
Board stepping
Name
CPLD code revision
®
80314 I/O processor companion chip PCE0# chip-enable output is connected to the
®
Intel
IQ80315 I/O Processor Evaluation Platform Board Manual
Definition
Definition
Identifies rework completed on the board. This is a resistor
strapping input to the CPLD.
Identifies the board stepping. This value is a resistor strapping
input to the CPLD firmware.
Definition
Identifies the CPLD code revision level. This value is coded into
the CPLD code.
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