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®
Intel
IQ80315 I/O Processor Evaluation Platform
2.8
UART
The IQ80315 CRB has two 9-pin D-shell serial port connectors mounted on the back panel. These
are driven by a Max3232E* 3.3 V dual serial port transceiver. The Intel
companion chip TX, RX, CTS#, and RTS# signals for each UART are connected to the serial port
transceiver. The DSR#, DTR#, DCD#, and RI# signals are muxed with 80314 GPIO signals and
are used as GPIO signals on the IQ80315 CRB.
2.9
Electronic Serial Number
The IQ80315 CRB has two DS2401 electronic serial number components (ESN) connected to a
GPIO pin on the CPLD. These components are accessed via the Maxim* Integrated Products
1-wire bus protocol. The bus protocol is implemented by "bit-banging" the CPLD GPIO pin with
the appropriate timing and listening for the returned serial-number bits. The ESN GPIO pin is set
high by writing 0x01 to any address within the ESN address space and is cleared by writing 0x00 to
any ESN address. Reading any address within the ESN address space returns the current value of
the ESN GPIO pin on data bit[0]. Data bits[7:1] are undefined during ESN read cycles. It requires
about 8 mS to read both ESN devices. See
The software routine that reads the ESN devices can store the serial numbers in flash memory to
simplify future serial-number accesses. Following this method, the ESN devices only need to be
read after the flash memory has been erased.
2
2.10
I
C
The IQ80315 CRB has two independent I
•
Main I
2
•
I
C bus dedicated to SDRAM presence detect and configuration
20
2
C bus
®
Intel
IQ80315 I/O Processor Evaluation Platform Board Manual
Table 16 on page 40
for the ESN address range.
2
C serial busses:
®
80314 I/O processor
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