Fixed Reset Configuration Inputs; Cpld Reset Configuration Outputs - Intel IQ80315 Board Manual

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Intel IQ80315 I/O Processor Evaluation Platform
Table 13
selectable.
Table 13.

Fixed Reset Configuration Inputs

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Intel 80314 I/O Processor Companion Chip (80314)
PWRUP_TRANS
PWRUP_P1_BYP
PWRUP_P2_BYP
TEST_ON
BIDIR_CTL
P1_RSTDIR
P2_RSTDIR
CPU
PLLCFG
LOWVCC
LOWVPP
Serial ATA
32BITPCI#
Table 14.

CPLD Reset Configuration Outputs

XS_C_IRQ[0] / PWRUP_FADJ
XS_C_IRQ[1] /
PWRUP_XS_BYP
XS_C_FIQ[1] /
PWRUP_SD_BYP
36
shows the 80314 reset configuration options that are fixed on the CRB and are not user-
Signal Pu / Pd
Signal
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Intel IQ80315 I/O Processor Evaluation Platform Board Manual
Pd 80314 PCI interfaces are set to embedded mode
Pd Enable PCI 1 PLL
Pd Enable PCI 2 PLL
Pd Disable 80314 internal test mode
Pd Test data direction. pull low for normal operation.
Pu PCI 1 reset is an output from the 80314
Pu PCI 2 reset is an output from the 80314
Pu Selects 6× CPU core clock
Pu CPU Core voltage is greater than 1.0 V.
Pu CPU I/O voltage is greater than 2.5 V.
Pu Sets the 31244 to 64-bit PCI/X bus
Reset
0 100 MHz CPU bus clock
0 Don't bypass Intel XScale
0 Don't bypass SDRAM PLL
Option Selected
Option Selected
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PLL