Yamaha CL3 Service Manual page 75

PIN
OUTER
NAME I/O
NO.
NO.
159 L1 MA15 O
L2 O
160 MA16
161 L3 MA17 O
162 L4 MA18 O
163 L5 VDD -
164 L9 VSS -
165 L10 VSS -
166 L11 VSS -
167 L12 VSS -
168 L16 VDD -
169 L17 D11 I/O
L18 I/O
170 D12
171 L19 D13 I/O
172 L20 D14 I/O
173 M1 MA19 O
174 M2 MA20 O
175 M3 MA21 O
176 M4 MA22 O
177 M5 VSS -
178 M9 VSS -
179 M10 VSS -
M11 -
180 VSS
181 M12 VSS -
182 M16 VSS -
183 M17 D7 I/O
184 M18 D8 I/O
185 M19 D9 I/O
186 M20 D10 I/O
187 N1 MA23/PG4 O
188 N2 MA24/PG5 O
189 N3 MA25/PG6 O
N4 O
190 MA26/PG7
191 N5 VCCQ -
192 N16 VCCQ -
193 N17 D3 I/O
194 N18 D4 I/O
195 N19 D5 I/O
196 N20 D6 I/O
197 P1 MCS3N/PG3 O
198 P2 MCS2N/PG2 O
199 P3 MCS1N/PG1 O
O
200 P4 MWRN/PG0
201 P5 VSS -
202 P16 VSS -
203 P17 RD/WRN O
204 P18 D0 I/O
205 P19 D1 I/O
206 P20 D2 I/O
207 R1 MCS0N O
208 R2 MRDN O
209 R3 BTCHG I
I/O
210 R4 PA0
211 R5 VDD -
212 R16 VDD -
213 R17 WE3N/DQMUU/PH3 O
214 R18 RASLN O
215 R19 CASLN O
216 R20 RDN O
217 T1 PA1 I/O
218 T2 PA2 I/O
219 T3 PA3 I/O
I/O
220 T4 PA4
221 T5 VDD -
222 T6 VDD -
223 T7 VSS -
224 T8 VCCQ -
225 T9 VSS -
226 T10 VCCQ -
227 T11 VCCQ -
228 T12 VSS -
229 T13 VCCQ -
-
230 T14 VSS
231 T15 VDD -
232 T16 VDD -
233 T17 A0/PH4 O
234 T18 WE0N/DQMLL/PH0 O
235 T19 WE1N/DQMLU/PH1 O
236 T20 WE2N/DQMUL/PH2 O
237 U1 PA5 I/O
FUNCTION
Wave memory address bus 15
Wave memory address bus 16
Wave memory address bus 17
Wave memory address bus 18
Power supply +1.2 V
Ground
Power supply +1.2 V
SH2A-CPU data bus 11
SH2A-CPU data bus 12
SH2A-CPU data bus 13
SH2A-CPU data bus 14
Wave memory address bus 19
Wave memory address bus 20
Wave memory address bus 21
Wave memory address bus 22
Ground
SH2A-CPU data bus 7
SH2A-CPU data bus 8
SH2A-CPU data bus 9
SH2A-CPU data bus 10
Wave memory address bus 23
Wave memory address bus 24
Wave memory address bus 25
Wave memory address bus 26
Power supply +3.3 V
SH2A-CPU data bus 3
SH2A-CPU data bus 4
SH2A-CPU data bus 5
SH2A-CPU data bus 6
Wave memory chip select 3
Wave memory chip select 2
Wave memory chip select 1
Wave memory write enable
Ground
SH2A-CPU read/write enable
SH2A-CPU data bus 0
SH2A-CPU data bus 1
SH2A-CPU data bus 2
Wave memory chip select 0
Wave memory read enable
BOOT ROM switching control
Parallel port A0
Power supply +1.2 V
Writing byte of D31 - D24/Selecting D31 - D24 in case of SDRAM
RAS output for SDRAM
CAS output for SDRAM
SH2A-CPU read enable
Parallel port A1
Parallel port A2
Parallel port A3
Parallel port A4
Power supply +1.2 V
Ground
Power supply +3.3 V
Ground
Power supply +3.3 V
Ground
Power supply +3.3 V
Ground
Power supply +1.2 V
SH2A-CPU address bus 0
Writing byte of D7 - D0/Selecting D7 - D0 in case of SDRAM
Writing byte of D15 - D8/Selecting D15 - D8 in case of SDRAM
Writing byte of D23 - D16/Selecting D23 - D16 in case of SDRAM
Parallel port A5
PIN
OUTER
NAME I/O
NO.
NO.
238 U2 PA6 I/O
PA7 I/O
239 U3
240 U4 VCCQ -
241 U5 ED1/PC1 I/O
242 U6 ED5/PC5 I/O
243 U7 ED9/PD1 I/O
244 U8 ED13/PD5 I/O
245 U9 EA2/PK1 I
246 U10 ECSN I
247 U11 BCLK O
248 U12 IRQ0 I
A25 O
249 U13
250 U14 A21 O
251 U15 A17 O
252 U16 A13 O
253 U17 VCCQ -
254 U18 A3 O
255 U19 A2 O
256 U20 A1 O
257 V1 PB0 I/O
258 V2 PB1 I/O
VCCQ -
259 V3
260 V4 PB6 I/O
261 V5 ED2/PC2 I/O
262 V6 ED6/PC6 I/O
263 V7 ED10/PD2 I/O
264 V8 ED14/PD6 I/O
265 V9 EA3/PK2 I
266 V10 SDI0/PK5 I
267 V11 WCLK2/SDO2 O
268 V12 IRQ1 I
I
269 V13 BW_MD0
270 V14 A22/PH5 O
271 V15 A18 O
272 V16 A14 O
273 V17 A10 O
274 V18 VCCQ -
275 V19 A5 O
276 V20 A4 O
277 W1 PB2 I/O
278 W2 VCCQ -
279 W3 PB4 I/O
280 W4 PB7 I/O
281 W5 ED3/PC3 I/O
282 W6 ED7/PC7 I/O
283 W7 ED11/PD3 I/O
284 W8 ED15/PD7 I/O
285 W9 ERDN/PK3 I
286 W10 SDI1/PK6 I
287 W11 WCLK O
288 W12 SYSCLK2 O
289 W13 WAITN/PK7 I
290 W14 A23/PH6 O
291 W15 A19 O
292 W16 A15 O
293 W17 A11 O
294 W18 A8 O
295 W19 VCCQ -
296 W20 A6 O
297 Y1 VCCQ -
298 Y2 PB3 I/O
299 Y3 PB5 I/O
300 Y4 ED0/PC0 I/O
301 Y5 ED4/PC4 I/O
302 Y6 ED8/PD0 I/O
303 Y7 ED12/PD4 I/O
304 Y8 EA1/PK0 I
305 Y9 EWRN/PK4 I
306 Y10 SDO0 O
307 Y11 SDO1 O
308 Y12 SYSCLK O
309 Y13 SYI I
310 Y14 A24/PH7 O
311 Y15 A20 O
312 Y16 A16 O
313 Y17 A12 O
314 Y18 A9 O
315 Y19 A7 O
316 Y20 VCCQ -
CL3/CL1
FUNCTION
Parallel port A6
Parallel port A7
Power supply +3.3 V
External CPU data bus 1
External CPU data bus 5
External CPU data bus 9
External CPU data bus 13
External CPU address bus 2
External CPU chip select
Bit clock output
Interrupt input 0
SH2A-CPU address bus 25
SH2A-CPU address bus 21
SH2A-CPU address bus 17
SH2A-CPU address bus 13
Power supply +3.3 V
SH2A-CPU address bus 3
SH2A-CPU address bus 2
SH2A-CPU address bus 1
Parallel port B0
Parallel port B1
Power supply +3.3 V
Parallel port B6
External CPU data bus 2
External CPU data bus 6
External CPU data bus 10
External CPU data bus 14
External CPU address bus 3
Serial audio input 0
Word clock output 2/Serial audio output 2
Interrupt input 1
SH2A-CPU data bus width configuration
SH2A-CPU address bus 22
SH2A-CPU address bus 18
SH2A-CPU address bus 14
SH2A-CPU address bus 10
Power supply +3.3 V
SH2A-CPU address bus 5
SH2A-CPU address bus 4
Parallel port B2
Power supply +3.3 V
Parallel port B4
Parallel port B7
External CPU data bus 3
External CPU data bus 7
External CPU data bus 11
External CPU data bus 15
External CPU read enable
Serial audio input 1
Word clock output
Clock output 2
External wait input
SH2A-CPU address bus 23
SH2A-CPU address bus 19
SH2A-CPU address bus 15
SH2A-CPU address bus 11
SH2A-CPU address bus 8
Power supply +3.3 V
SH2A-CPU address bus 6
Power supply +3.3 V
Parallel port B3
Parallel port B5
External CPU data bus 0
External CPU data bus 4
External CPU data bus 8
External CPU data bus 12
External CPU address bus 1
External CPU write enable
Serial audio output 0
Serial audio output 1
Clock output
Sync. input from external device
SH2A-CPU address bus 24
SH2A-CPU address bus 20
SH2A-CPU address bus 16
SH2A-CPU address bus 12
SH2A-CPU address bus 9
SH2A-CPU address bus 7
Power supply +3.3 V
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