Yamaha CL3 Service Manual page 302

H G
■ BLOCK DIAGRAM 002 (CL3/CL1)
1 DSP
CN103 (5P)
USB
CN201
(5P)
See page 5
CN102 (6P)
LCDC
CN101
(6P)
See page 5
CN706 (8P)
Power OFF
PNM
CN007
(8P)
See page 6
I2C
2 I2C
PNMB
CN301
See page 7
(10P)
CN705 (4P)
FD8
CN901 CN702-704 (7P)
See page 6
(7P) E-bus
E-bus
E-bus
CL3: FD8 x 3
CL1: FD8 x 2
CN941
(7P)
3 W401
DCMS
LAMP CNT
(7P)
See page 10, 11
CPU
CN601 CN101
(180P) (180P)
See page 5
4
DNTU
Dante IN
8ch/line
CN503 (40P)
CN504 (40P)
Dante OUT
8ch/line
See page 8
5
DANTE CLOCK
CN552 (40P)
CN553 (40P)
6
28CA1-2001089459-2
1
4
F
USB
IC102, 103
(20P)
SCI
Master Clock
IC703 (16P)
I2C
hub
IC701 (20P)
I2C
hub
SCI
IC702 (16P)
IC941 (8P)
IC942 (14P)
CAUTIONS SPI
60MHz
1/4
2TR OUT
IC116-119 (20P), IC120, IC121 (24P)
2ch/line
CPU bus
CPU IN/OUT
2ch/line
DSP block
Master Clock
See page 12
IC654 (100P)
CPLD
Clock
IC653 (30P)
SRC
MP3 DSP7 *11
IC652
(144P)
DSP
DSP6 *4
SHARC *1
24.576MHz
IC552 (144P) Dante IN
4ch/line 60MHz
8 16
/ /
FPGA FX
/ /
Dante OUT
4ch/line
8 16
X152 X151
49.152 45.1584
MHz MHz
IC152 (144P)
CPLD
PLL
IC153
(14P)
E D
CN851
(40P)
OPT
IC751-761 (20P)
SLOT1 SLOT2 SLOT3
CN751-753
(38P)
IC851 (20P)
Master Clock
IC871 (20P)
ADIN
2ch/line
4
/
DAOUT
2ch/line
4
/
PHONE OUT
2ch/line
IC921 (20P)
TB IN
2ch/line
IC922 (20P)
IC901 (20P)
SLOT WCIN
3
/
BNC IN
Master Clock
C B
JK
27
IC101(28P) JK101
26
DIGITAL OUT
DIT
25
AES/EBU
CS8406
IC601, 602
(20P)
IC202 (20P)
CN201
Reg. GPI
CN601
(40P) IC201 (20P)
IC301 (16P)
JK301
13 14
IN
WORD CLOCK
IC302 (16P)
OUT
10 9
JK302
IC402 (6P)
5 1, 3
PC IN
JK401 MIDI
OUT
IC401 (14P)
CN851
(40P)
HAAD
Master Clock
(OMNI IN 1-8)
Tx_CPU
ADIN 1-8
CN901 (23P)
/RESET_ADA,/RESET_CPU
SID2-0
See page 9
CN871 (23P)
DA
Master Clock
(OMNI OUT 1-8)
/RESET_ADA
CN901 (11P)
DAOUT 1-8
CN903 (8P)
CN921 (11P), CN922 (8P) See page 9
TBPHN
Master Clock
PHONES L-R (PHONES OUT,
TALK BACK TALKBACK IN)
TB_48V,/RESET_ADA
CN901 (16P)
See page 9
CN901 (16P)
■ BLOCK DIAGRAM 002 (CL3/CL1)
A
CL3/CL1
DSP, FX, JK, OPT