Figure 4-2 P2020 Processor Block Diagram - SMART Embedded Computing COMX-P2020 Installation And Use Manual

Functional Description
 64 bit DDR2/DDR3 controller with ECC supports data rate of up to 800Mbps per
pin
 31x31 mm 689-pin wirebond power-BGA
 45 nm SOI process technology
Each e500 core complex contains a separate 32KB, eight-way set associative level 1 (L1)
instruction and data caches to provide the execution units and registers rapid access to
instructions and data. The 32KB cache is divided into eight ways and 128 sets, so there is
a total of 1024 blocks. The size of each block is eight words (32 bytes).
The integrated L2 Cache/SRAM can be configured as Cache or SRAM. For COMX-P2020,
it is configured as 512 KB L2 cache that is organized as 2048 eight way sets of 32 byte
cache lines based on 36 bit physical addresses.

Figure 4-2 P2020 Processor Block Diagram

70 COMX-P2020 Module Installation and Use (6806800K97F)
Functional Description