SMART Embedded Computing COMX-P2020 Installation And Use Manual page 52

Controls, LEDs, and Connectors
Signal name
Function
Select Option
Default value
Supported configuration
52
SRIO2 (1x) on SerDes lane 0 (2.5Gbps)
SRIO1 (1x) on SerDes lane 1 (2.5Gbps)
1100
SGMII eTSEC2 (x1) on SerDes lane 2
SGMII eTSEC3(x1) on SerDes lane 3
PCI Express 1 (x1) on SerDes lane 0
SRIO1 (1x) on SerDes lane 1
1101
SGMII eTSEC2 (x1) on SerDes lane 2
SGMII eTSEC3(x1) on SerDes lane 3
PCI Express 1 (x1) on SerDes lane 0;
PCI Express 2 (x1) on SerDes lane 1;
1110
SGMII eTSEC2 (x1) on SerDes lane 2;
SGMII eTSEC3 (x1) on SerDes lane 3.
PCI Express 1 (x2) on SerDes lanes 0-1;
1111 SGMII eTSEC2 (x1) on SerDes lane 2;
SGMII eTSEC3 (x1) on SerDes lane 3.
LA27, LA16
CPU Boot Configuration
(cfg_cpu0_boot, cfg_cpu1_boot)
PU / PD Resistors
11
CPU boot holdoff mode for both cores. The cores are
00 prevented from booting until configured by an
external master.
Core 1 is allowed to boot without waiting for
configuration by an external master, while core 0 is
01
prevented from booting until configured by an
external master or the other core.
Core 0 is allowed to boot without waiting for
configuration by an external master, while core 1 is
10
prevented from booting until configured by an
external master or the other core.
Both cores are allowed to boot without waiting for
11
configuration by an external master.
COMX-P2020 Module Installation and Use (6806800K97F)
Controls, LEDs, and Connectors