Aaeon AEV-6356 User Manual
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Aaeon AEV-6356 User Manual

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AEV-6356
Railway Embedded Box PC
nd
User's Manual 2
Ed
Last Updated: November 4, 2015

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Summary of Contents for Aaeon AEV-6356

  • Page 1 AEV-6356 Railway Embedded Box PC User’s Manual 2 Last Updated: November 4, 2015...
  • Page 2 AAEON assumes no liabilities resulting from errors or omissions in this document, or from the use of the information contained herein. AAEON reserves the right to make changes in the product design without notice to its users.
  • Page 3 Acknowledgement All other products’ name or trademarks are properties of their respective owners. ® Microsoft Windows is a registered trademark of Microsoft Corp.  ITE is a trademark of Integrated Technology Express, Inc.  IBM, PC/AT, PS/2, and VGA are trademarks of International Business Machines ...
  • Page 4 Packing List Before setting up your product, please make sure the following items have been shipped: Item Quantity AEV-6356  Wallmount brackets  M12 power DC jack kit  M12 USB Y cable  M12 COM cable  M12 LAN cable ...
  • Page 5 (if any), its specifications, dimensions, jumper/connector settings/definitions, and driver installation instructions (if any), to facilitate users in setting up their product. Users may refer to the AAEON.com for the latest version of this document. Preface...
  • Page 6 Safety Precautions Please read the following safety instructions carefully. It is advised that you keep this manual for future references All cautions and warnings on the device should be noted. Make sure the power source matches the power rating of the device. Position the power cord so that people cannot step on it.
  • Page 7 If any of the following situations arises, please the contact our service personnel: Damaged power cord or plug Liquid intrusion to the device iii. Exposure to moisture Device is not working as expected or in a manner as described in this manual The device is dropped or damaged Any obvious signs of damage displayed on the device...
  • Page 8 FCC Statement This device complies with Part 15 FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interference that may cause undesired operation. Caution: There is a danger of explosion if the battery is incorrectly replaced.
  • Page 9 China RoHS Requirements (CN) 产品中有毒有害物质或元素名称及含量 AAEON Embedded Box PC/ Industrial System 有毒有害物质或元素 部件名称 铅 汞 镉 六价铬 多溴联苯 多溴二苯醚 (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) 印刷电路板 × ○ ○ ○ ○ ○ 及其电子组件 外部信号 × ○ ○ ○ ○ ○...
  • Page 10 China RoHS Requirement (EN) Poisonous or Hazardous Substances or Elements in Products AAEON Embedded Box PC/ Industrial System Poisonous or Hazardous Substances or Elements Hexavalent Polybrominated Polybrominated Component Lead Mercury Cadmium Chromium Biphenyls Diphenyl Ethers (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) PCB &...

  • Page 11: Table Of Contents

    Table of Contents Chapter 1 - Product Specifications ..................1 Specifications ......................2 Chapter 2 – Hardware Information ..................4 Dimensions ....................... 5 Jumpers and Connectors ..................6 List of Jumpers ......................8 2.3.1 COM4 RS232/422/485 (JP1) .............. 9 2.3.2 Clear CMOS (JP4) .................
  • Page 12 3.4.4 Advanced: Intel TXT (LT) Configuration ......... 26 3.4.5 Advanced: PCH-FW Configuration ..........27 3.4.6 Advanced: Firmware Update Configuration ......... 28 3.4.7 Advanced: Super IO Configuration ..........29 3.4.7.1 Super IO Configuration: Serial Port 1 Configuration ..30 3.4.7.2 Super IO Configuration: Serial Port 2 Configuration ..31 3.4.7.3 Super IO Configuration: Serial Port 3 Configuration ..
  • Page 13 Setting AHCI ......................71 Appendix D – Electrical Specifications for I/O Ports............77 DI/O Programming ....................78 DI/O Register ......................79 Digital I/O Sample Program................80 Preface XIII...

  • Page 14: Chapter 1 - Product Specifications

    Chapter 1 Chapter 1 - Product Specifications...

  • Page 15: Specifications

    Specifications System ® Intel Core™ i7-3517UE up to 2.8GHz Processor  ® ® Intel Celeron 827E ,1.4 GHz DDR3 SODIMM x 1, up to 8 GB System Memory  ® Intel QM77 Chipset   Display DB-15 x 1 for VGA Interface DVI-I x 1 Storage...
  • Page 16 75V-compliant) (M12) Expansion PCIe Full-size Mini PCIe x 1  Half-size Mini PCIe x 1 (WiFi/ 3G/ GPS) (Optional) Indicator Front System LED x 1 (powerbutton)  Power Requirement 12 V DC-in with lockable connector  ATX mode (optional AT by jumper/ BIOS setting) System Cooling Passive cooling...

  • Page 17: Chapter 2 - Hardware Information

    Chapter 2 Chapter 2 – Hardware Information...

  • Page 18: Dimensions

    Dimensions Chapter 2 – Hardware Information...

  • Page 19: Jumpers And Connectors

    Jumpers and Connectors Component side Chapter 2 – Hardware Information...
  • Page 20 Solder Side Chapter 2 – Hardware Information...

  • Page 21: List Of Jumpers

    List of Jumpers Please refer to the table below for all of the system’s jumpers that you can configure for your application Label Function COM4 RS232/422/485 Clear CMOS COM3 12V/5V/RI COM2 12V/5V/RI COM1 RS232/422/485 Chapter 2 – Hardware Information...

  • Page 22: Com4 Rs232/422/485 (Jp1)

    2.3.1 COM4 RS232/422/485 (JP1) RS-232 RS-422 RS-485 2.3.2 Clear CMOS (JP4) Clear CMOS 2.3.3 COM3 12V/5V/RI (JP5) +5 V +12 V Chapter 2 – Hardware Information...

  • Page 23: Com2 12V/5V/Ri (Jp6)

    2.3.4 COM2 12V/5V/RI (JP6) +5 V +12 V 2.3.5 COM1 RS232/422/485 (JP7) RS-232 RS-422 RS-485 Chapter 2 – Hardware Information...

  • Page 24: List Of Connectors

    List of Connectors Please refer to the table below for all of the board’s connectors that you can configure for your application Label Function CN12 Isolated DI/O CN13 USB3.0 CN15 COM3 CN16 COM2 CN17 COM1 CN18 CFast CN21 Audio SIM1 SIM Card PWR1 SATA Power...

  • Page 25: Rs-232/422/485 Serial Port Connector

    RS-232/422/485 Serial Port Connector COM1 Signal Signal DCD (422TXD-/485DATA-) RXD (422RXD+) TXD (422TXD+/485DATA+) DTR (422RXD-) COM2 and COM3 Signal +12 V +5 V (default) COM4 (RS-422/RS-485) MX+2 USB+ USB- MX-2 USB- USB+ MX+3 MX+0 Green-100Mbps MX-3 Orange-1000Mbps YELLOW COM4/RS422/RS485 Chapter 2 – Hardware Information...

  • Page 26: Usb Connector (M12)

    Signal DCD (422TXD-/485DATA-) RXD (422RXD+) TXD (422TXD+/485DATA+) DTR (422RXD-) USB Connector (M12) MX+2 USB+ USB- MX-2 MX-1 USB- USB+ MX+3 MX+1 MX+0 MX-0 Green-100Mbps Green-100Mbps MX-3 Orange-1000Mbps Orange-1000Mbps YELLOW YELLOW COM4/RS422/RS485 LAN Connector (M12) MX+2 MX+2 MX-2 MX-1 MX-2 MX-1 MX+3 MX+1 MX+3...

  • Page 27: Isolated Di/O

    Isolated DI/O Isolated Digital Input Max. frequency of IDI tPHL : TYP . 48 ns, (Logic High to Low response time) tPLH : TYP . 50 ns (Logic Low to High response time) Max. voltage input: Logic level 0: +2.5 V max. Logic level 1: +5 V to +30 V (Source to DI) Max.
  • Page 28 Isolated Digital Output Max. frequency of IDO Rise time : 18us(Max) Fall time : 18us(Max) Max. voltage output: +5 V max. Max. current output: 50mA Isolated 5V Output (with short protection) Max. voltage output: +5 V max. Max. current output: 200mA Chapter 2 –...

  • Page 29: Chapter 3 - Ami Bios Setup

    Chapter 3 Chapter 3 - AMI BIOS Setup...

  • Page 30: System Test And Initialization

    System Test and Initialization The system uses certain routines to perform testing and initialization. If an error, fatal or non-fatal, is encountered, a few short beeps or an error message will be outputted. The board can usually continue the boot up sequence with non-fatal errors. The system configuration verification routines check the current system configuration against the values stored in the CMOS memory.

  • Page 31: Ami Bios Setup

    AMI BIOS Setup The AMI BIOS ROM has a pre-installed Setup program that allows users to modify basic system configurations, which is stored in the battery-backed CMOS RAM and BIOS NVRAM so that the information is retained when the power is turned off. To enter BIOS Setup, press <Del>...

  • Page 32: Setup Submenu: Main

    Setup Submenu: Main Chapter 3 – AMI BIOS Setup...

  • Page 33: Setup Submenu: Advanced

    Setup Submenu: Advanced Chapter 3 – AMI BIOS Setup...

  • Page 34: Advanced: Acpi Settings

    3.4.1 Advanced: ACPI Settings Options summary: Suspend mode S1 only (CPU Stop Clock) S3 only (Suspend to RAM) Optimal Default, Failsafe Default Select the ACPI state used for System Suspend Chapter 3 – AMI BIOS Setup...

  • Page 35: Advanced: Cpu Configuration

    3.4.2 Advanced: CPU Configuration Options summary: Intel Virtualization Disabled Optimal Default, Failsafe Default Technology Enabled When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology Chapter 3 – AMI BIOS Setup...

  • Page 36: Advanced: Ide Configuration (Ide)

    3.4.3 Advanced: IDE Configuration (IDE) Chapter 3 – AMI BIOS Setup...

  • Page 37: Advanced: Ide Configuration (Ahci)

    3.4.3.1 Advanced: IDE Configuration (AHCI) Chapter 3 – AMI BIOS Setup...

  • Page 38: Advanced: Ide Configuration (Raid)

    3.4.3.2 Advanced: IDE Configuration (RAID) Options summary: SATA Controllers Disabled Enabled Default En/Disable SATA Controller. SATA Mode Default AHCI RAID IDE: Configure SATA controllers as legacy IDEAHCI: Configure SATA controllers to operate in AHCI mode Port x Disabled Enabled Optimal Default, Failsafe Default En/Disable SATA Port.

  • Page 39: Advanced: Intel Txt (Lt) Configuration

    3.4.4 Advanced: Intel TXT (LT) Configuration Chapter 3 – AMI BIOS Setup...

  • Page 40: Advanced: Pch-Fw Configuration

    3.4.5 Advanced: PCH-FW Configuration Options summary: MDES BIOS Status Code Disabled Optimal Default, Failsafe Default Enabled Enable/Disable MDES BIOS Status Code. Chapter 3 – AMI BIOS Setup...

  • Page 41: Advanced: Firmware Update Configuration

    3.4.6 Advanced: Firmware Update Configuration Options summary: Me FW Image Re-Flash Disabled Optimal Default, Failsafe Default Enabled Enable/Disable Me FW Image Re-Flash function. Chapter 3 – AMI BIOS Setup...

  • Page 42: Advanced: Super Io Configuration

    3.4.7 Advanced: Super IO Configuration Options summary: Power Failure Keep last state Always on Always off Default Power Saving Function Disabled Default Enabled Enable to reduce power consumption in system off state. When Enabled, only power button can power-up system. Chapter 3 –...

  • Page 43: Super Io Configuration: Serial Port 1 Configuration

    3.4.7.1 Super IO Configuration: Serial Port 1 Configuration Options summary: Serial Port Disabled Enabled Default Allows BIOS to En/Disable correspond serial port. Change Settings Auto Default IO=3F8h; IRQ=4; IO=3F8h; IRQ=3,4; IO=2F8h; IRQ=3,4; IO=3E8h; IRQ=3.4 IO=2E8h; IRQ=3,4; Allows BIOS to Select Serial Port resource. Chapter 3 –...

  • Page 44: Super Io Configuration: Serial Port 2 Configuration

    3.4.7.2 Super IO Configuration: Serial Port 2 Configuration Options summary: Serial Port Disabled Enabled Default Allows BIOS to En/Disable correspond serial port. Change Settings Auto Default IO=2F8h; IRQ=3; IO=3F8h; IRQ=3,4; IO=2F8h; IRQ=3,4; IO=3E8h; IRQ=3,4; IO=2E8h; IRQ=3,4; Allows BIOS to Select Serial Port resource. Chapter 3 –...

  • Page 45: Super Io Configuration: Serial Port 3 Configuration

    3.4.7.3 Super IO Configuration: Serial Port 3 Configuration Options summary: Serial Port Disabled Enabled Default Allows BIOS to En/Disable correspond serial port. Change Settings Auto Default IO=3E8h; IRQ=10; IO=3E8h; IRQ=10,11;; IO=2E8h; IRQ=10,11; IO=2D0h; IRQ=10,11; IO=2D8h; IRQ=10,11; Allows BIOS to Select Serial Port resource. Chapter 3 –...

  • Page 46: Super Io Configuration: Serial Port 4 Configuration

    3.4.7.4 Super IO Configuration: Serial Port 4 Configuration Options summary: Serial Port Disabled Enabled Default Allows BIOS to En/Disable correspond serial port. Change Settings Auto Default IO=2E8h; IRQ=10; IO=3E8h; IRQ=10,11;; IO=2E8h; IRQ=10,11; IO=2D0h; IRQ=10,11; IO=2D8h; IRQ=10,11; Allows BIOS to Select Serial Port resource. Chapter 3 –...

  • Page 47: Advanced: F81866 H/W Monitor

    3.4.8 Advanced: F81866 H/W Monitor Chapter 3 – AMI BIOS Setup...

  • Page 48: Advanced: Digital I/O

    3.4.9 Advanced: Digital I/O Options summary: DIO_P#1~6 Input Default Output Allows BIOS to select input/output function to corresponding DIO ping. DIO_P#7~8 Input Output Default Allows BIOS to select input/output function to corresponding DIO ping. DIO_P#7~8 Direction Default Allows BIOS to select high/low voltage level to output to corresponding DIO ping. Chapter 3 –...

  • Page 49: Setup Submenu: Chipset

    Setup submenu: Chipset Chapter 3 – AMI BIOS Setup...

  • Page 50: Chipset: Pch-Io Configuration

    3.5.1 Chipset: PCH-IO Configuration Options summary: Power Mode ATX Type Default AT Type Select Power Supply Mode. PCH LAN Controller Enabled Default Disabled Enable or disable onboard NIC. Wake on LAN Enabled Default Disabled Enable or disable integrated LAN to wake the system.(The Wake On LAN cannot be disabled if ME is on at Sx state.) Deep S5 Disabled...
  • Page 51 Gen2 Default Select Mini PCI Express port speed. Chapter 3 – AMI BIOS Setup...

  • Page 52: Setup Submenu: Boot

    Setup submenu: Boot Options summary: Quiet Boot Disabled Enabled Default En/Disable showing boot logo. Launch I82579LM PXE Disabled Default OpROM Enabled En/Disable Legacy Boot Option for I82579LM. Launch I82574L PXE Disabled Default OpROM Enabled En/Disable Legacy Boot Option for I82583V. Chapter 3 –...

  • Page 53: Boot: Bbs Priorities

    3.6.1 Boot: BBS Priorities Chapter 3 – AMI BIOS Setup...

  • Page 54: Setup Submenu: Security

    Setup submenu: Security Change User/Administrator Password You can set a User Password once an Administrator Password is set. The password will be required during boot up, or when the user enters the Setup utility. Please Note that a User Password does not provide access to many of the features in the Setup utility. Select the password you wish to set, press Enter to open a dialog box to enter your password (you can enter no more than six letters or numbers).

  • Page 55: Setup Submenu: Exit

    Setup submenu: Exit Chapter 3 – AMI BIOS Setup...

  • Page 56: Chapter 4 - Drivers Installation

    Chapter 4 Chapter 4 – Drivers Installation...

  • Page 57: Product Cd/Dvd

    Product CD/DVD The AEV-6356 comes with a product DVD that contains all the drivers and utilities you need to setup your product. Insert the DVD and follow the steps in the autorun program to install the drivers. In case the program does not start, follow the sequence below to install the drivers.
  • Page 58 Step 4 – Install Audio Driver (Windows 8.1/10 only) Open the Step 4 – Audio folder and select your OS Open the.exe file in the folder Follow the instructions Drivers will be installed automatically Step 5 – Install USB 3.0 Drivers Open the Step 5 –...

  • Page 59: Appendix A - Watchdog Timer Programming

    Appendix A Appendix A - Watchdog Timer Programming...

  • Page 60: Watchdog Timer Initial Program

    A.1 Watchdog Timer Initial Program Table 1 : SuperIO relative register table Default Value Note SIO MB PnP Mode Index Register Index 0x2E(Note1) 0x2E or 0x4E SIO MB PnP Mode Data Register Data 0x2F(Note2) 0x2F or 0x4F Table 2 : Watchdog relative register table Register BitNum Value...

  • Page 61: Watchdog Sample Program

    A.2 Watchdog Sample Program ************************************************************************************ // SuperIO relative definition (Please reference to Table 1) #define byte SIOIndex //This parameter is represented from Note1 #define byte SIOData //This parameter is represented from Note2 #define void IOWriteByte(byte IOPort, byte Value); #define byte IOReadByte(byte IOPort); // Watch Dog relative definition (Please reference to Table 2) #define byte TimerLDN //This parameter is represented from Note3 #define byte TimerReg //This parameter is represented from Note4...
  • Page 62 ************************************************************************************ VOID Main(){ // Procedure : AaeonWDTConfig // (byte)Timer : Time of WDT timer.(0x00~0xFF) // (boolean)Unit : Select time unit(0: second, 1: minute). AaeonWDTConfig(); // Procedure : AaeonWDTEnable // This procudure will enable the WDT counting. AaeonWDTEnable(); ************************************************************************************ Appendix A – Watchdog Timer Programming...
  • Page 63 ************************************************************************************ // Procedure : AaeonWDTEnable VOID AaeonWDTEnable (){ WDTEnableDisable(EnableLDN, EnableReg, EnableBit, 1); // Procedure : AaeonWDTConfig VOID AaeonWDTConfig (){ // Disable WDT counting WDTEnableDisable(EnableLDN, EnableReg, EnableBit, 0); // Clear Watchdog Timeout Status WDTClearTimeoutStatus(); // WDT relative parameter setting WDTParameterSetting(); VOID WDTEnableDisable(byte LDN, byte Register, byte BitNum, byte Value){ SIOBitSet(LDN, Register, BitNum, Value);...
  • Page 64 ************************************************************************************ VOID SIOEnterMBPnPMode(){ IOWriteByte(SIOIndex, 0x87); IOWriteByte(SIOIndex, 0x87); VOID SIOExitMBPnPMode(){ IOWriteByte(SIOIndex, 0xAA); VOID SIOSelectLDN(byte LDN){ IOWriteByte(SIOIndex, 0x07); // SIO LDN Register Offset = 0x07 IOWriteByte(SIOData, LDN); VOID SIOBitSet(byte LDN, byte Register, byte BitNum, byte Value){ Byte TmpValue; SIOEnterMBPnPMode(); SIOSelectLDN(byte LDN); IOWriteByte(SIOIndex, Register); TmpValue = IOReadByte(SIOData);...

  • Page 65: Appendix B - I/O Information

    Appendix B Appendix B - I/O Information...

  • Page 66: I/O Address Map

    I/O Address Map Appendix B – I/O Information...
  • Page 67 Appendix B – I/O Information...

  • Page 68: Memory Address Map

    Memory Address Map Appendix B – I/O Information...

  • Page 69: Irq Mapping Chart

    IRQ Mapping Chart Appendix B – I/O Information...
  • Page 70 Appendix B – I/O Information...
  • Page 71 Appendix B – I/O Information...

  • Page 72: Dma Channel Assignment

    DMA Channel Assignment Appendix B – I/O Information...

  • Page 73: Appendix C - Raid & Ahci Settings

    Appendix C Appendix C – RAID & AHCI Settings...

  • Page 74: Setting Raid

    Setting RAID OS installation to setup RAID Mode Driver CD -> Step6 - RAID&AHCI\F6 Floppy - x86 Step 1: Copy the files below from “ ” to Disk Step 2: Connect the USB Floppy (disk with RAID files) to the board Appendix C –...
  • Page 75 Step 3: The setting procedures “ In BIOS Setup Menu” A: Advanced -> SATA Configuration -> SATA Mode -> RAID Mode Step 4: The setting procedures “In BIOS Setup Menu” B: Advanced -> Launch Storage OpROM -> Enabled Appendix C – RAID & AHCI Settings...
  • Page 76 Step 5: The setting procedures “In BIOS Setup Menu” C: Boot -> Boot Option #1 -> DVD-ROM Type Step 6: The setting procedures “In BIOS Setup Menu” D: Save & Exit -> Save Changes and Exit Appendix C – RAID & AHCI Settings...
  • Page 77 Step 7: Press Ctrl-I to enter MAIN MENU Step 8: Choose “1.Create RAID Volume” Appendix C – RAID & AHCI Settings...
  • Page 78 Step 9: RAID Level -> RAID0(Stripe) Step 10: Choose “Create Volume” Appendix C – RAID & AHCI Settings...
  • Page 79 Step 11: Choose “Y” Step 12: Choose “5. Exit” Appendix C – RAID & AHCI Settings...
  • Page 80 Step 13: Choose “Y” Step 14: Setup OS Appendix C – RAID & AHCI Settings...
  • Page 81 Step 15: Press “F6” Step 16: Choose “S” Appendix C – RAID & AHCI Settings...
  • Page 82 Step 17: Choose “Intel(R) ICH8M-E/ICH9M-E/5 Series SATA RAID Controller” Step 18: It will show the model number you select and then press “ENTER” Appendix C – RAID & AHCI Settings...
  • Page 83 Step 19: Setup is starting Windows Appendix C – RAID & AHCI Settings...

  • Page 84: Setting Ahci

    Setting AHCI OS installation to setup AHCI Mode Driver CD -> Step 6 - RAID&AHCI\F6 Floppy - x86 Step 1: Copy the files below from “ ” to Disk Step 2: Connect the USB Floppy (disk with RAID files) to the board Appendix C –...
  • Page 85 Step 3: The setting procedures “ In BIOS Setup Menu” A: Advanced -> SATA Configuration -> SATA Configuration -> SATA Mode -> AHCI Mode Step 4: The setting procedures “In BIOS Setup Menu” B: Boot -> Boot Option #1 -> DVD-ROM Type Appendix C –...
  • Page 86 Step 5: The setting procedures “In BIOS Setup Menu” C: Save & Exit -> Save Changes and Exit Step 6: Setup OS Appendix C – RAID & AHCI Settings...
  • Page 87 Step 7: Press “F6” Step 8: Choose “S” Appendix C – RAID & AHCI Settings...
  • Page 88 Step 9: Choose “Intel(R) 5 Series 6 Port SATA AHCI Controller” Step 10: It will show the model number you select and then press “ENTER” Appendix C – RAID & AHCI Settings...
  • Page 89 Step 11: Setup is loading files Appendix C – RAID & AHCI Settings...

  • Page 90: Appendix D - Electrical Specifications For I/O Ports

    Appendix D Appendix D – Electrical Specifications for I/O Ports...

  • Page 91: Di/O Programming

    DI/O Programming AEV-6356 utilizes FINTEK 81866 chipset as its Digital I/O controller. Below are the procedures to complete its configuration and the AAEON initial watchdog timer program is also attached based on which you can develop customized program to fit your application.

  • Page 92: Di/O Register

    DI/O Register Table 1 : SuperIO relative register table Default Value Note SIO MB PnP Mode Index Register Index 0x2E(Note1) 0x2E or 0x4E SIO MB PnP Mode Data Register Data 0x2F(Note2) 0x2F or 0x4F Table 2 : Digital Input relative register table Register BitNum Value...

  • Page 93: Digital I/O Sample Program

    Digital I/O Sample Program ************************************************************************************ // SuperIO relative definition (Please reference to Table 1) #define byte SIOIndex //This parameter is represented from Note1 #define byte SIOData //This parameter is represented from Note2 #define void IOWriteByte(byte IOPort, byte Value); #define byte IOReadByte(byte IOPort); // Digital Input Status relative definition (Please reference to Table 2) #define byte DInput1LDN // This parameter is represented from Note3 #define byte DInput1Reg // This parameter is represented from Note4...
  • Page 94 ************************************************************************************ // Digital Output control relative definition (Please reference to Table 3) #define byte DOutput1LDN // This parameter is represented from Note27 #define byte DOutput1Reg // This parameter is represented from Note28 #define byte DOutput1Bit // This parameter is represented from Note29 #define byte DOutput1Val // This parameter is represented from Note30 #define byte DOutput2LDN // This parameter is represented from Note31 #define byte DOutput2Reg // This parameter is represented from Note32...
  • Page 95 ************************************************************************************ VOID Main(){ Boolean PinStatus ; // Procedure : AaeonReadPinStatus // Input : Example, Read Digital I/O Pin 3 status // Output : InputStatus : 0: Digital I/O Pin level is low 1: Digital I/O Pin level is High PinStatus = AaeonReadPinStatus(DInput3LDN, DInput3Reg, DInput3Bit); // Procedure : AaeonSetOutputLevel // Input : Example, Set Digital I/O Pin 6 level...
  • Page 96 ************************************************************************************ Boolean AaeonReadPinStatus(byte LDN, byte Register, byte BitNum){ Boolean PinStatus ; PinStatus = SIOBitRead(LDN, Register, BitNum); Return PinStatus ; VOID AaeonSetOutputLevel(byte LDN, byte Register, byte BitNum, byte Value){ ConfigToOutputMode(LDN, Register, BitNum); SIOBitSet(LDN, Register, BitNum, Value); ************************************************************************************ Appendix D – RAID & AHCI Settings...
  • Page 97 ************************************************************************************ VOID SIOEnterMBPnPMode(){ IOWriteByte(SIOIndex, 0x87); IOWriteByte(SIOIndex, 0x87); VOID SIOExitMBPnPMode(){ IOWriteByte(SIOIndex, 0xAA); VOID SIOSelectLDN(byte LDN){ IOWriteByte(SIOIndex, 0x07); // SIO LDN Register Offset = 0x07 IOWriteByte(SIOData, LDN); VOID SIOBitSet(byte LDN, byte Register, byte BitNum, byte Value){ Byte TmpValue; SIOEnterMBPnPMode(); SIOSelectLDN(byte LDN); IOWriteByte(SIOIndex, Register); TmpValue = IOReadByte(SIOData);...
  • Page 98 ************************************************************************************ Boolean SIOBitRead(byte LDN, byte Register, byte BitNum){ Byte TmpValue; SIOEnterMBPnPMode(); SIOSelectLDN(LDN); IOWriteByte(SIOIndex, Register); TmpValue = IOReadByte(SIOData); TmpValue &= (1 << BitNum); SIOExitMBPnPMode(); If(TmpValue == 0) Return 0; Return 1; VOID ConfigToOutputMode(byte LDN, byte Register, byte BitNum){ Byte TmpValue, OutputEnableReg; OutputEnableReg = Register-1;...

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