Texas Instruments TMS320C6457 User Manual page 4

1 HPI Position in the Host-DSP System
2 Example of Host-DSP Signal Connections When Using the HAS Signal in the 32-Bit Multiplexed Mode
3 Example of Host-DSP Signal Connections When the HAS Signal is Tied High in the 32-Bit Multiplexed
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Mode
4 Example of Host-DSP Signal Connections When Using the HAS Signal in the 16-Bit Multiplexed Mode
5 Example of Host-DSP Signal Connections When the HAS Signal is Tied High in the 16-Bit Multiplexed
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Mode
6 HPI Strobe and Select Logic
7 16-Bit Multiplexed Mode Host Read Cycle Using HAS
8 16-Bit Multiplexed Mode Host Write Cycle Using HAS
9 16-Bit Multiplexed Mode Host Read Cycle With HAS Tied High
10 16-Bit Multiplexed Mode Host Write Cycle With HAS Tied High
11 16-Bit Multiplexed Mode Single-Halfword HPIC Cycle with HAS Tied High
12 HRDY Behavior During an HPIC or HPIA Read Cycle in the 16-Bit Multiplexed Mode
13 HRDY Behavior During a Data Read Operation in the 16-Bit Multiplexed Mode (Case 1: HPIA Write
Cycle Followed by Nonautoincrement HPID Read Cycle)
14 HRDY Behavior During a Data Read Operation in the 16-Bit Multiplexed Mode (Case 2: HPIA Write
Cycle Followed by Autoincrement HPID Read Cycles)
15 HRDY Behavior During an HPIC Write Cycle in the 16-Bit Multiplexed Mode
16 HRDY Behavior During a Data Write Operation in the 16-Bit Multiplexed Mode (Case 1: No
Autoincrementing)
17 HRDY Behavior During a Data Write Operation in the 16-Bit Multiplexed Mode(Case 2: Autoincrementing
Selected, FIFO Empty Before Write)
18 HRDY Behavior During a Data Write Operation in the 16-Bit Multiplexed Mode(Case 3: Autoincrementing
Selected, FIFO Not Empty Before Write)
19 HRDY Behavior During an HPIC or HPIA Read Cycle in the 32-Bit Multiplexed Mode
20 HRDY Behavior During a Data Read Operation in the 16-Bit Multiplexed Mode (Case 1: HPIA Write
Cycle Followed by Nonautoincrement HPID Read Cycle)
21 HRDY Behavior During a Data Read Operation in the 32-Bit Multiplexed Mode (Case 2: HPIA Write
Cycle Followed by Autoincrement HPID Read Cycles)
22 HRDY Behavior During an HPIC Write Cycle in the 32-Bit Multiplexed Mode
23 HRDY Behavior During a Data Write Operation in the 32-Bit Multiplexed Mode (Case 1: No
Autoincrementing)
24 HRDY Behavior During a Data Write Operation in the 32-Bit Multiplexed Mode (Case 2:
Autoincrementing Selected, FIFO Empty Before Write)
25 HRDY Behavior During a Data Write Operation in the 32-Bit Multiplexed Mode (Case 3:
Autoincrementing Selected, FIFO Not Empty Before Write)
26 Host-to-CPU Interrupt State Diagram
27 CPU-to-Host Interrupt State Diagram
28 FIFOs in the HPI
29 Power and Emulation Management Register (PWREMU_MGMT)
30 Host Access Permissions
31 CPU Access Permissions
32 Format of an Address Register (HPIAW or HPIAR) - Host Access Permissions
33 Format of an Address Register (HPIAW or HPIAR) - CPU Access Permissions
34 Data Register (HPID) (Host access permissions, CPU cannot access HPID)
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List of Figures
List of Figures
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Copyright © 2009-2010, Texas Instruments Incorporated
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SPRUGK7A - March 2009 - Revised July 2010
www.ti.com
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