Dual 32-Bit Timers Chained Mode Example; Dual 32-Bit Timers Unchained Mode Block Diagram - Texas Instruments TMS320C6472 User Manual

Timer Modes
32-bit prescaler settings: count = CNTHI = 200; period = PRDHI = 202
32-bit timer settings: count = CNTLO = 3; period = PRDLO= 4
Prescale counter
(CNTHI)
T imer counter
(CNTLO)
2.2.2 Unchained Mode
In the unchained mode, shown in
32-bit timer (TIMHI) can be configured as a 32-bit timer being clocked by a 4-bit prescaler. The other
(TIMLO) can be used as a 32-bit timer.
Figure 6. Dual 32-Bit Timers Unchained Mode Block Diagram
32-bit timer with 4-bit prescaler
Internal
clock
Input clock
4-bit prescale counter
TDDRHI
Equality comparator
32-bit timer counter
CNTHI
Equality comparator
Pulse generator
10
C6472/TCI648x 64-Bit Timer
Figure 5. Dual 32-Bit Timers Chained Mode Example
200 201
3
Figure 6, the timer can operate as two independent 32-bit timers. One
(TIMHI)
Internal
Prescale period
PSCHI
Timer period
PRDHI
CP_LO
PWID_LO
(CP_LO = 0)
TSTAT bit in TCR
Timer interrupt
(TINTHI) to CPU
Timer event (TEVTHI)
to EDMA controller
Copyright © 2005–2010, Texas Instruments Incorporated
202 0
Prescale counter reset
Timer counter incremented
Gated internal clock
External clock
via TINPL
clock
CLKSRC
Input clock
32-bit timer counter
CNTLO
Equality comparator
Pulse generator
Output via TOUTL
SPRU818B – December 2005 – Revised September 2010
1 2
4
32-bit timer
(TIMLO)
Timer period
PRDLO
CP_HI
PWID_HI (CP_HI = 0)
Timer interrupt (TINTLO) to CPU
Timer event (TEVTLO) to EDMA controller
TSTAT bit in TCR
INVOUTP_LO
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