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Texas Instruments TMS320TCI6486 User Manual

Texas Instruments TMS320TCI6486 User Manual

Dsp ethernet media access controller (emac)/ management data input/output (mdio) module
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TMS320C6472/TMS320TCI6486 DSP
Ethernet Media Access Controller (EMAC)/
Management Data Input/Output (MDIO) Module
User's Guide
Literature Number: SPRUEF8F
March 2006 – Revised November 2010

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Summary of Contents for Texas Instruments TMS320TCI6486

  • Page 1 TMS320C6472/TMS320TCI6486 DSP Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO) Module User's Guide Literature Number: SPRUEF8F March 2006 – Revised November 2010...
  • Page 2 SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated...

  • Page 3: Table Of Contents

    MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) 4.10 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated Table of Contents...
  • Page 4 Back Off Test Register (BOFFTEST) 5.40 Transmit Pacing Algorithm Test Register (TPACETEST) 5.41 Receive Pause Timer Register (RXPAUSE) 5.42 Transmit Pause Timer Register (TXPAUSE) Contents SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...
  • Page 5 Transmit Channel 0-7 Completion Pointer Register (TXnCP) 5.49 Receive Channel 0-7 Completion Pointer Register (RXnCP) 5.50 Network Statistics Registers Appendix A Glossary Appendix B Revision History SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated Contents...
  • Page 6 Transmit Control Register (TXCONTROL) Transmit Teardown Register (TXTEARDOWN) Receive Identification and Version Register (RXIDVER) Receive Control Register (RXCONTROL) List of Figures List of Figures Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback...
  • Page 7 Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) Transmit Channel n Completion Pointer Register (TXnCP) Receive Channel n Completion Pointer Register (RXnCP) Statistics Register SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated List of Figures...
  • Page 8 Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions List of Tables List of Tables SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...
  • Page 9 Transmit Channel n Completion Pointer Register (TXnCP) Field Descriptions Receive Channel n Completion Pointer Register (RXnCP) Field Descriptions Statistics Register Field Descriptions EMAC/MDIO Revision History SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated List of Tables...

  • Page 10: Preface

    Physical layer (PHY) device Management Data Input/Output (MDIO) module integrated with TMS320TCI6486/TMS320C6472 devices. Included are the features of the EMAC and MDIO modules, a discussion of their architecture and operation, how these modules connect to the outside world, and the registers descriptions for each module.

  • Page 11: Introduction

    These two modules are considered integral to the EMAC/MDIO peripheral. Purpose of the Peripheral The EMAC module is used on TMS320TCI6486/TMS320C6472 devices to move data between the device and another host connected to the same network, in compliance with the Ethernet protocol. Features Two EMAC modules are integrated with the TCI6486/C6472 device.

  • Page 12: Functional Block Diagram

    CPPI RAM0 CPPI buffer manager + CPPI RAM1 EMIC1 EMAC Control 1 Module To GEMs SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com MII0/GMII0 S3MII0 EMAC0 RMII0 RGMII0 MDIO To PHYs S3MII1 EMAC1...

  • Page 13: Serial Management Interface Pins

    MII/GMII/RMII/S3MII management data. Available on 3.3-V LVCMOS buffers. RGMII management clock. Available on 1.8-V HSTL buffers. RGMII management data. Available on 1.8-V HSTL buffers. Table 2. EMAC1_EN Pin Description Copyright © 2006–2010, Texas Instruments Incorporated Introduction Table 1 shows the two...

  • Page 14: Industry Standard(S) Compliance Statement

    EMAC intentionally generates an incorrect check sum by inverting the frame CRC so that the network detects the transmitted frame as an error. C6472/TCI6486 EMAC/MDIO SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...

  • Page 15: Emac Functional Architecture

    125 MHz used for GMII /100 5 MHz Used for RGMII0 only 250 MHz Used for RGMII1 only 50 MHz Used for RGMII1 (default) /100 5 MHz Used for RGMII1 only Copyright © 2006–2010, Texas Instruments Incorporated EMAC Functional Architecture C6472/TCI6486 EMAC/MDIO...

  • Page 16: Memory Map

    However, the EMAC throughput is better when the descriptors are put in the local EMAC RAM. C6472/TCI6486 EMAC/MDIO SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...

  • Page 17: System-Level Connections

    GMII RGMII Not used S3MII Not used Not used Interface Not used S3MII RGMII RMII MACSEL11 MACSEL10 Copyright © 2006–2010, Texas Instruments Incorporated EMAC Functional Architecture Table 4) and EMAC1 EMAC_EN EMAC0 EMAC1 None None RGMII GMII None GMII None...

  • Page 18: Ethernet Configuration With Mii Interface

    MTXEN MCOL MCRS Physical layer MRCLK device MRXD[3−0] (PHY) MRXDV MRXER MDCLK MDIO SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com EMAC_EN EMAC0 EMAC1 None RMII S3MII None S3MII S3MII S3MII RGMII S3MII...

  • Page 19: Emac And Mdio Signals For Mii Interface

    (RMII1, S3MII1). due to this multiplexing, when the MII0 interface is selected on EMAC0, except for RGMII1, no Ethernet interface is available on EMAC1. SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated EMAC Functional Architecture C6472/TCI6486 EMAC/MDIO...

  • Page 20: Ethernet Configuration With Rmii Interface

    C6472/TCI6486 EMAC/MDIO 50-MHz zero-delay clock buffer RMREFCLK RMREFCLK RMTXD[1−0] RMTXEN RMCRSDV RMRXD[1−0] RMRXER MDCLK MDIO SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Physical layer device (PHY) Table 8 summarizes the Submit Documentation Feedback...

  • Page 21: Ethernet Configuration With Gmii Interface

    SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback MTCLK GMTCLK MTXD[7−0] MTXEN MCOL MCRS Physical layer MRCLK device MRXD[7−0] (PHY) MRXDV MRXER MDCLK MDIO Copyright © 2006–2010, Texas Instruments Incorporated EMAC Functional Architecture 2.5 MHz, 25 MHz, or 125 MHz Transformer RJ−45 C6472/TCI6486 EMAC/MDIO...

  • Page 22: Emac And Mdio Signals For Gmii Interface

    TCI6486/C6472 device with integrated EMAC and MDIO interfaced to the PHY via an RGMII connection. This interface is available in 10 Mbps, 100 Mbps, and 1000 Mbps modes. C6472/TCI6486 EMAC/MDIO SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...

  • Page 23: Ethernet Configuration With Rgmii Interface

    SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback RGTXC RGTXD[3−0] RGTXCTL RGREFCLK Physical layer RGRXC device RGRXD[3−0] (PHY) RGRXCTL RGMDCLK RGMDIO Copyright © 2006–2010, Texas Instruments Incorporated EMAC Functional Architecture 2.5 MHz 25 MHz, or 125 MHz Transformer RJ−45 C6472/TCI6486 EMAC/MDIO...
  • Page 24 (RGMII pins are 1.5-V/1.8-V HSTL I/O, whereas other interfaces are 3.3-V LVCMOS I/O). The unused pins of the RGMII PHY should be pulled down to avoid floating inputs. C6472/TCI6486 EMAC/MDIO SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...

  • Page 25: Ethernet Configuration With S3Mii Interface

    System core SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback 125-MHz 125-MHz zero-delay clock buffer MHZ_125_CLK TX_CLK TX_SYNC RX_CLK RX_SYNC MDCLK MDIO Copyright © 2006–2010, Texas Instruments Incorporated EMAC Functional Architecture Physical layer device (PHY) C6472/TCI6486 EMAC/MDIO...

  • Page 26: Emac And Mdio Signals For S3Mii Interface

    TCI6486/C6472 devices can be different. configuration for S3MII. C6472/TCI6486 EMAC/MDIO Figure 7 demonstrates the example mutli-PHY SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...

  • Page 27: S3Mii Multi-Phy Configuration

    SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback External logic element Low-skew buffer Zero-delay clock buffer Copyright © 2006–2010, Texas Instruments Incorporated EMAC Functional Architecture S3MII multi-PHY TX_CLK TX_SYNC P0_TXD P0_RXD P1_TXD P1_RXD Pn_TXD...

  • Page 28: S3Mii Switch Configuration

    Figure 8 Figure 8. S3MII Switch Configuration External logic element Low-skew buffer Zero-delay clock buffer SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com demonstrates the example S3MII switch TX_CLK TX_SYNC P0_TXD P0_RXD P1_TXD...

  • Page 29: Ethernet Protocol Overview

    CRC value for the FCS field. The frame check sequence covers the 60 to (RXMAXLEN - 4) bytes of the packet data. Note that the 4-byte FCS field may not be included as part of the packet data, depending on the EMAC configuration. Copyright © 2006–2010, Texas Instruments Incorporated EMAC Functional Architecture Figure...
  • Page 30 The port then waits an amount of time which is multiple of this random value, and returns to Step 1. C6472/TCI6486 EMAC/MDIO SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...

  • Page 31: Programming Interface

    Figure 10. Basic Descriptor Format Bit Fields 16 15 Next Descriptor Pointer Buffer Pointer Flags Table 13. Basic Descriptors Section 2.5.4 Section 2.5.5 Copyright © 2006–2010, Texas Instruments Incorporated EMAC Functional Architecture Table Buffer Length Packet Length describe the flags. C6472/TCI6486 EMAC/MDIO...

  • Page 32: Typical Descriptor Linked List

    500 bytes −−− pNext (NULL) pBuffer 1514 1514 bytes 1514 (Section SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Packet A 60 bytes Packet B 512 bytes Packet B Packet B Packet C 2.5.1).
  • Page 33 SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback (Section 2.5.1), using the linked list queue Copyright © 2006–2010, Texas Instruments Incorporated EMAC Functional Architecture C6472/TCI6486 EMAC/MDIO...

  • Page 34: Transmit Descriptor Format

    Figure 12. Transmit Descriptor Format Next Descriptor Pointer Buffer Pointer PASS Packet Length 0x80000000u 0x40000000u 0x20000000u 0x10000000u 0x08000000u 0x04000000u SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Buffer Length Reserved Submit Documentation Feedback...
  • Page 35 EOP flag. This bit is set by the software application and is not altered by the EMAC. SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated EMAC Functional Architecture C6472/TCI6486 EMAC/MDIO...
  • Page 36 CRC bytes, as they are part of the valid packet data. Note that this flag is valid on SOP descriptors only. C6472/TCI6486 EMAC/MDIO SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...

  • Page 37: Receive Descriptor Format

    TDOWNCMPLT OVERRUN CODEERROR Packet Length 0x80000000u 0x40000000u 0x20000000u 0x10000000u 0x08000000u 0x04000000u 0x02000000u 0x01000000u 0x00800000u 0x00400000u 0x00200000u 0x00100000u 0x00080000u 0x00040000u 0x00020000u 0x00010000u Copyright © 2006–2010, Texas Instruments Incorporated EMAC Functional Architecture Buffer Length PASSCRC JABBER OVERSIZE ALIGNERROR CRCERROR NOMATCH C6472/TCI6486 EMAC/MDIO...
  • Page 38 EOP flag set. The software application initially clears this flag before adding the descriptor to the receive queue. The EMAC sets this bit on SOP descriptors. C6472/TCI6486 EMAC/MDIO SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...
  • Page 39 The EMAC sets this flag in the SOP buffer descriptor if the received packet is undersized and was not discarded because the RXCSFEN bit was set in the RXMBPENABLE register. SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated EMAC Functional Architecture C6472/TCI6486 EMAC/MDIO...

  • Page 40: Communications Port Programming Interface (Cppi)

    Receive Pacer and Interrupt Combiner (RPIC) which consists of: – Pacer block per TX event C6472/TCI6486 EMAC/MDIO Figure 14. The following components, as shown in SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...

  • Page 41: Emic Block Diagram

    RX pacer and interrupt combiner Common interrupt combiner TX pacer and interrupt combiner RX pacer and interrupt combiner Common interrupt combiner Registers PS_TICK Prescaler Copyright © 2006–2010, Texas Instruments Incorporated EMAC Functional Architecture MACTXINT0 MACRXINT0 To GEM0 MACINT0 MACTXINT1 MACRXINT1...

  • Page 42: Pacing Block

    The prescaler block forwards this signal to all the pacing blocks. Pacing block PS_TICK EVT_IN C6472/TCI6486 EMAC/MDIO Figure 15. Pacing Block EVT_TIMED Timed- delay SM Divide SM EVT_DIV SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com EVT_OUT Submit Documentation Feedback...

  • Page 43: Tdsm State Transition Diagram

    Delay PS_TICK=1 && TIME < TIME_CFG Time=0 && DIV_NEXT=0 Output EVT_PULSE=0 (or) EVT_PULSE=1 && TIME >= TIME_CFG Copyright © 2006–2010, Texas Instruments Incorporated EMAC Functional Architecture Section 3) is set to 0 on reset Time=0 Increment time Time=0 C6472/TCI6486 EMAC/MDIO...

  • Page 44: Dsm State Transition Diagram

    Count CNT=1 CNT >= CNT_CFG && EVT_PULSE=1 NEXT_ DIV=1 NEXT_ DIV=1 SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Section 3) is set to 0 on reset and CNT=1 Output Submit Documentation Feedback...

  • Page 45: Transmit Pacer And Interrupt Combiner

    Pacing block PS_TICK SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Transmit pacer and interrupt combiner EW_INTCTL[8] EW_INTCTL[9] EW_INTCTL[10] EW_INTCTL[11] EW_INTCTL[12] EW_INTCTL[13] EW_INTCTL[14] EW_INTCTL[15] EW_INTCTL[15:8] Copyright © 2006–2010, Texas Instruments Incorporated EMAC Functional Architecture MACTXINT C6472/TCI6486 EMAC/MDIO...

  • Page 46: Receive Pacer And Interrupt Combiner

    Pacing block RXEVT[7] Pacing block PS_TICK C6472/TCI6486 EMAC/MDIO Receive pacer and interrupt combiner EW_INTCTL[16] EW_INTCTL[17] EW_INTCTL[18] EW_INTCTL[19] EW_INTCTL[20] EW_INTCTL[21] EW_INTCTL[22] EW_INTCTL[23] EW_INTCTL[23:16] SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com MACRXINT Submit Documentation Feedback...

  • Page 47: Management Data Input/Output (Mdio) Module

    Submit Documentation Feedback Figure 20. Common Interrupt Combiner Common interrupt combiner block EW_INTCTL[1] EW_INTCTL[2] EW_INTCTL[3] EW_INTCTL[4] EW_INTCTL[4:1] Figure 21) interfaces to PHY components through two MDIO pins (MDCLK Copyright © 2006–2010, Texas Instruments Incorporated EMAC Functional Architecture MACINT C6472/TCI6486 EMAC/MDIO...

  • Page 48: Mdio Module Block Diagram

    The requests are processed sequentially. C6472/TCI6486 EMAC/MDIO Figure 21. MDIO Module Block Diagram MDIO clock generator monitoring Control registers and logic Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com MDCLK MDIO interface MDIO polling SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback...
  • Page 49 USERACCESSn registers to trigger a completion interrupt. The other register is not set up. SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated EMAC Functional Architecture C6472/TCI6486 EMAC/MDIO...
  • Page 50 Starts the process of writing a PHY register Synchronizes operation (makes sure read/write is idle) Waits for read to complete and returns data read SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...
  • Page 51 (CSL_FEXT(MDIO_REGS->USERACCESS0,MDIO_USERACCESS0_GO) ); results = CSL_FEXT(MDIO_REGS->USERACCESS0, MDIO_USERACCESS0_DATA); } SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Section 2.8.2.3. As the ALIVE register initially selects a PHY, it is Copyright © 2006–2010, Texas Instruments Incorporated EMAC Functional Architecture C6472/TCI6486 EMAC/MDIO...

  • Page 52: Emac Module

    22, the number associated with each MII interface Receive address Receive FIFO receiver Transmit FIFO transmitter State Statistics SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com MII0/GMII0 RMII0, RMII1 SYNC RGMII0, RGMII1 S3MII0, S3MII1 Submit Documentation Feedback...
  • Page 53 16-byte descriptor per fragment. In typical operation, there is only one descriptor per receive buffer, but transmit packets may be fragmented, depending on the software architecture. SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated EMAC Functional Architecture C6472/TCI6486 EMAC/MDIO...

  • Page 54: 2.10 Media Independent Interfaces

    Receive buffer flow control issues flow control collisions in half-duplex mode and IEEE 802.3X pause frames for full-duplex mode. C6472/TCI6486 EMAC/MDIO SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...
  • Page 55 The 16-bit pause time value of FF.FFh. A pause-quantum is 512 bit-times. Pause frames sent to cancel a pause request have a pause time value of 00.00h. SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated EMAC Functional Architecture C6472/TCI6486 EMAC/MDIO...
  • Page 56 MCRS is not de-asserted until more than approximately 48 bit times after MTXEN is de-asserted, then 96 bit times (approximately, but not less) is measured from MCRS. C6472/TCI6486 EMAC/MDIO SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...
  • Page 57 64 bytes to be discarded or interpreted as valid pause frames. The EMAC recognizes any pause frame between 64 bytes and RXMAXLEN bytes in length. SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated EMAC Functional Architecture C6472/TCI6486 EMAC/MDIO...

  • Page 58: 2.11 Packet Receive Operation

    RAM locations should be initialized, including locations to be unused. The system software is responsible for adding and removing addresses from the RAM. C6472/TCI6486 EMAC/MDIO SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...
  • Page 59 535 free buffers available. The RXnFREEBUFFER registers only need to be updated by the host if receive QOS or flow control is used. SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated EMAC Functional Architecture C6472/TCI6486 EMAC/MDIO...
  • Page 60 If the frame length is 1522, there are 1518 bytes transferred to memory. The last byte is the last data byte. C6472/TCI6486 EMAC/MDIO SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...

  • Page 61: Receive Frame Treatment Summary

    Proper/oversize/jabber/code/align/CRC data frames transferred to address match channel. No control or undersized frames are transferred. Proper/oversize/jabber/fragment/undersized/code/align/CRC data frames transferred to address match channel. No control frames are transferred. Copyright © 2006–2010, Texas Instruments Incorporated EMAC Functional Architecture C6472/TCI6486 EMAC/MDIO...

  • Page 62: 2.12 Packet Transmit Operation

    OVERRUN flag is set in the SOP buffer descriptor. Note that the RXMAXLEN number of bytes cannot be reached for an overrun to occur (it would be truncated). Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com shows how the overrun condition SPRUEF8F –...

  • Page 63: 2.13 Receive And Transmit Latency

    TXCELLTHRESH number of internal 64-byte FIFO cells. SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated EMAC Functional Architecture C6472/TCI6486 EMAC/MDIO...

  • Page 64: 2.15 Reset Considerations

    2.15 Reset Considerations 2.15.1 Software Reset Considerations For information on the chip level reset capabilities of various peripherals, see the TMS320TCI6486 Communications Infrastructure Digital Signal Processor data manual (SPRS300) or the TMS320C6472 Fixed-Point Digital Signal Processor data manual (SPRS612). Within the peripheral itself, the EMAC component of the Ethernet MAC peripheral can be placed in a reset state by writing to the SOFTRESET register located in EMAC memory map.

  • Page 65: 2.16 Initialization

    EMAC/MDIO is enabled through the chip level module state control register 0 (MDCTL0) and module status register 0 (MDSTAT0). For detailed information on the programming sequence, see the TMS320TCI6486 Communications Infrastructure Digital Signal Processor data manual (SPRS300) or the TMS320C6472 Fixed-Point Digital Signal Processor data manual (SPRS612). This sequence enables the EMAC peripheral, and the register values are reset to default.
  • Page 66 MACCONTROL register. 19. When using RMII, release the interface logic from reset by clearing the RMII_RST field of the EMAC C6472/TCI6486 EMAC/MDIO SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...

  • Page 67: 2.17 Interrupt Support

    RAM block. The write generates the interrupt when enabled by the interrupt mask, regardless of the value written. SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated EMAC Functional Architecture C6472/TCI6486 EMAC/MDIO...
  • Page 68 LINKINT: Serial interface link change interrupt. Indicates a change in the state of the PHY link. • USERINT: Serial interface user command event complete interrupt. C6472/TCI6486 EMAC/MDIO SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...

  • Page 69: 2.18 Power Management

    71 through the use of the enhanced interrupt selector within the C64x+ core. For more details, see the Interrupt Controller chapter in the TMS320C64x+ Megamodule Peripherals Reference Guide and the TMS320TCI6486 Communications Infrastructure Digital Signal Processor data manual (SPRS300) or the TMS320C6472 Fixed-Point Digital Signal Processor data manual (SPRS612).

  • Page 70: Emulation Control

    SOFT and FREE bits affect the operation of the emulation suspend. SOFT C6472/TCI6486 EMAC/MDIO Table 16. Emulation Control FREE Description Normal operation Emulation suspend Normal operation SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...

  • Page 71: Emic Module Registers

    SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Figure 23. EW_INTCTL Register Reserved 0000 0000 R/W-0 R/W-0 R/W-0 R/W-0 MDIO_USER MDIO_LINT R/W-0 R/W-0 Copyright © 2006–2010, Texas Instruments Incorporated EMIC Module Registers Figure R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STAT HOST Reserved R/W-0...

  • Page 72: Rpcfg Register

    Resets the divide by N count C6472/TCI6486 EMAC/MDIO Figure 24. RPCFG Register TIME_CFG R/W-0000 0000 Reserved 0000 Table 17. RPCFG Register Field Descriptions Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com R/W-0 R/W-0 R/W-0 SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback R/W-0...

  • Page 73: Rpstat Register

    SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Figure 25. RPSTAT Register TIME R-0000 0000 Reserved 0000 Table 18. RPSTAT Register Field Descriptions Copyright © 2006–2010, Texas Instruments Incorporated EMIC Module Registers Figure 25 TIM_SM DIV_SM R-00 R-00 C6472/TCI6486 EMAC/MDIO...

  • Page 74: Tpic Registers

    C6472/TCI6486 EMAC/MDIO Figure 26. TPCFG Register TIME_CFG R/W-0000 0000 Reserved 0000 Table 19. TPCFG Register Field Descriptions Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Figure 26 R/W-0 R/W-0 R/W-0 SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback...

  • Page 75: Prescalar Configuration Register (Pscfg)

    Submit Documentation Feedback Figure 27. TPSTAT Register TIME R-0000 0000 Reserved 0000 Table 20. TPSTAT Register Field Descriptions Figure Reserved 0000 0000 PRESCALE_CFG R/W-0000 0000 Copyright © 2006–2010, Texas Instruments Incorporated EMIC Module Registers Figure 27 TIM_SM DIV_SM R-00 R-00 C6472/TCI6486 EMAC/MDIO...

  • Page 76: Mdio Registers

    Table 21 lists the memory-mapped registers for the Management Data Input/Output (MDIO). For the memory address of these registers, see the TMS320TCI6486 Communications Infrastructure Digital Signal Processor data manual (SPRS300) or the TMS320C6472 Fixed-Point Digital Signal Processor data manual (SPRS612).

  • Page 77: Mdio Version Register (Version)

    Management Interface Module minor revision value SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Figure 29 and described in Figure 29. MDIO Version Register (VERSION) MODID Copyright © 2006–2010, Texas Instruments Incorporated MDIO Registers Table REVMIN C6472/TCI6486 EMAC/MDIO...

  • Page 78: Mdio Control Register (Control)

    Clock Divider bits. This field specifies the division ratio between peripheral bus peripheral clock and the frequency of MDCLK. MDCLK is disabled when CLKDIV is set to 0. MDCLK frequency = peripheral clock frequency/(CLKDIV + 1). Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Table...

  • Page 79: Phy Acknowledge Status Register (Alive)

    The most recent access to the PHY with an address corresponding to the register bit number was acknowledged by the PHY. SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Figure 31 ALIVE R/WC-0 ALIVE R/WC-0 Copyright © 2006–2010, Texas Instruments Incorporated MDIO Registers and described in Table C6472/TCI6486 EMAC/MDIO...

  • Page 80: Phy Link Status Register (Link)

    The PHY with the corresponding address has a link and the PHY acknowledges the read transaction C6472/TCI6486 EMAC/MDIO Figure 32 and described in Figure 32. PHY Link Status Register (LINK) LINK LINK SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Table Submit Documentation Feedback...

  • Page 81: Mdio Link Status Change Interrupt (Unmasked) Register (Linkintraw)

    USERPHYSEL1, respectively. Writing a 1 will clear the event and writing 0 has no effect. SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Reserved Reserved Descriptions Copyright © 2006–2010, Texas Instruments Incorporated MDIO Registers Figure 33 LINKINTRAW R/WC-0 C6472/TCI6486 EMAC/MDIO...

  • Page 82: Mdio Link Status Change Interrupt (Masked) Register (Linkintmasked)

    LINKINTRAW[1] correspond to USERPHYSEL0 and USERPHYSEL1, respectively. Writing a 1 will clear the event and writing 0 has no effect. C6472/TCI6486 EMAC/MDIO Reserved Reserved Descriptions SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Figure 34 LINKINT MASKED R/WC-0 Submit Documentation Feedback...

  • Page 83: Mdio User Command Complete Interrupt (Unmasked) Register (Userintraw)

    Writing a 1 will clear the event and writing 0 has no effect. SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Reserved Reserved Descriptions Copyright © 2006–2010, Texas Instruments Incorporated MDIO Registers Figure 35 USERINTRAW R/WC-0 C6472/TCI6486 EMAC/MDIO...

  • Page 84: Mdio User Command Complete Interrupt (Masked) Register (Userintmasked)

    USERINTMASKSET bit is set to 1. Writing a 1 will clear the interrupt and writing 0 has no effect. SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com USERINT...

  • Page 85: Mdio User Command Complete Interrupt Mask Set Register (Userintmaskset)

    MDIO user command complete interrupts for that particular USERACCESS register. MDIO user interrupt for a particular USERACCESS register is disabled if the corresponding bit is 0. Writing a 0 to this register has no effect. Copyright © 2006–2010, Texas Instruments Incorporated MDIO Registers USERINT...

  • Page 86: Mdio User Command Complete Interrupt Mask Clear Register (Userintmaskclear)

    MDIO user command complete interrupt mask clear for USERINTMASKED[1:0] respectively. Setting a bit to 1 will disable further user command complete interrupts for that particular USERACCESS register. Writing a 0 to this register has no effect. Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com USERINT...

  • Page 87: Mdio User Access Register 0 (Useraccess0)

    User data bits. These bits specify the data value read from or to be written to the specified PHY register. SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Figure 39 REGADR R/W-0 DATA R/W-0 Copyright © 2006–2010, Texas Instruments Incorporated MDIO Registers and described in Table PHYADR R/W-0 C6472/TCI6486 EMAC/MDIO...

  • Page 88: Mdio User Phy Select Register 0 (Userphysel0)

    PHY address whose link status is to be monitored. C6472/TCI6486 EMAC/MDIO Reserved LINKSEL LINKINTENB R/W-0 R/W-0 SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Figure 40 and described in Table Reserved PHYADRMON R/W-0...

  • Page 89: Mdio User Access Register 1 (Useraccess1)

    User data bits. These bits specify the data value read from or to be written to the specified PHY register. SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Figure 41 REGADR R/W-0 DATA R/W-0 Copyright © 2006–2010, Texas Instruments Incorporated MDIO Registers and described in Table PHYADR R/W-0 C6472/TCI6486 EMAC/MDIO...

  • Page 90: Mdio User Phy Select Register 1 (Userphysel1)

    PHY address whose link status is to be monitored. C6472/TCI6486 EMAC/MDIO Reserved LINKSEL LINKINTENB R/W-0 R/W-0 SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Figure 42 and described in Table Reserved PHYADRMON R/W-0...

  • Page 91: Emac Port Registers

    Table 36 lists the memory-mapped registers for the Ethernet Media Access Controller (EMAC). For the memory address of these registers, see the TMS320TCI6486 Communications Infrastructure Digital Signal Processor data manual (SPRS300) or the TMS320C6472 Fixed-Point Digital Signal Processor data manual (SPRS612).
  • Page 92 Acknowledge) Register Transmit Channel 5 Completion Pointer (Interrupt Acknowledge) Register Transmit Channel 6 Completion Pointer (Interrupt Acknowledge) Register SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Section 5.28 Section 5.29 Section 5.30 Section 5.31 Section 5.32...
  • Page 93 Transmit and Receive 128 to 255 Octet Frames Register Transmit and Receive 256 to 511 Octet Frames Register Transmit and Receive 512 to 1023 Octet Frames Register Copyright © 2006–2010, Texas Instruments Incorporated EMAC Port Registers Section 5.48 Section 5.49 Section 5.49...
  • Page 94 Receive FIFO or DMA Start-of-Frame Overruns Register Receive FIFO or DMA Middle-of-Frame Overruns Register Receive DMA Start-of-Frame and Middle-of-Frame Overruns Register SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Section 5.50.32 Section 5.50.33 Section 5.50.34 Section 5.50.35...

  • Page 95: Transmit Identification And Version Register (Txidver)

    Transmit major version value TXMINORVER Transmit minor version value SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback TXIDENT 0x000C TXMAJORVER 0x02 Copyright © 2006–2010, Texas Instruments Incorporated EMAC Port Registers Figure 43 and described in TXMINORVER 0x08 C6472/TCI6486 EMAC/MDIO...

  • Page 96: Transmit Control Register (Txcontrol)

    Reserved TXEN Transmit enable Transmit is disabled Transmit is enabled C6472/TCI6486 EMAC/MDIO Figure 44 Reserved Reserved SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com and described in Table TXEN R/W-0 Submit Documentation Feedback...

  • Page 97: Transmit Teardown Register (Txteardown)

    Teardown transmit channel 6 Teardown transmit channel 7 SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Figure 45 Reserved Reserved Copyright © 2006–2010, Texas Instruments Incorporated EMAC Port Registers and described in Table TXTDNCH R/W-0 C6472/TCI6486 EMAC/MDIO...

  • Page 98: Receive Identification And Version Register (Rxidver)

    Receive major version value RXMINORVER Receive minor version value C6472/TCI6486 EMAC/MDIO RXIDENT 0x000C RXMAJORVER 0x02 SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Figure 46 and described in RXMINORVER 0x08 Submit Documentation Feedback...

  • Page 99: Receive Control Register (Rxcontrol)

    Receive DMA enable Receive is disabled Receive is enabled SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Figure 47 Reserved Reserved Copyright © 2006–2010, Texas Instruments Incorporated EMAC Port Registers and described in Table RXEN R/W-0 C6472/TCI6486 EMAC/MDIO...

  • Page 100: Receive Teardown Register (Rxteardown)

    Teardown receive channel 5 Teardown receive channel 6 Teardown receive channel 7 C6472/TCI6486 EMAC/MDIO Figure 48 Reserved Reserved SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com and described in Table RXTDNCH R/W-0 Submit Documentation Feedback...

  • Page 101: Transmit Interrupt Status (Unmasked) Register (Txintstatraw)

    TX0PEND TX0PEND raw interrupt read (before mask) SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Reserved PEND PEND PEND Copyright © 2006–2010, Texas Instruments Incorporated EMAC Port Registers Figure 49 and described PEND PEND PEND PEND PEND...

  • Page 102: Transmit Interrupt Status (Masked) Register (Txintstatmasked)

    TX1PEND masked interrupt read TX0PEND TX0PEND masked interrupt read C6472/TCI6486 EMAC/MDIO Reserved PEND PEND PEND SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Figure 50 PEND PEND PEND PEND PEND Submit Documentation Feedback...

  • Page 103: Transmit Interrupt Mask Set Register (Txintmaskset)

    SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Reserved TX4PULSE TX3PULSE MASK MASK Reserved TX4PEND TX3PEND MASK MASK Copyright © 2006–2010, Texas Instruments Incorporated EMAC Port Registers Figure 51 and described in TX2PULSE TX1PULSE TX0PULSE MASK MASK MASK TX2PEND TX1PEND...

  • Page 104: Transmit Interrupt Mask Clear Register (Txintmaskclear)

    C6472/TCI6486 EMAC/MDIO Reserved TX4PULSE TX3PULSE MASK MASK Reserved TX4PEND TX3PEND MASK MASK SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Figure 52 and described in TX2PULSE TX1PULSE TX0PULSE MASK MASK MASK TX2PEND TX1PEND...

  • Page 105: Mac Input Vector Register (Macinvector)

    Transmit channels 0-7 interrupt (TXnPEND) pending status bit. Bit 0 is transmit channel 0. SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Figure 53 Reserved Copyright © 2006–2010, Texas Instruments Incorporated EMAC Port Registers and described in Table HOST...

  • Page 106: Mac End-Of-Interrupt Vector Register (Maceoivector)

    The EOI_WR signal is asserted for a single clock cycle after a latency of two peripheral bus clock cycles when a write is performed to this location. SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Figure 54...

  • Page 107: Receive Interrupt Status (Unmasked) Register (Rxintstatraw)

    RX0PEND RX0PEND raw interrupt read (before mask) SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Reserved PEND PEND PEND Copyright © 2006–2010, Texas Instruments Incorporated EMAC Port Registers Figure 55 and described PEND PEND PEND PEND PEND...

  • Page 108: Receive Interrupt Status (Masked) Register (Rxintstatmasked)

    RX1PEND masked interrupt read RX0PEND RX0PEND masked interrupt read C6472/TCI6486 EMAC/MDIO Reserved PEND PEND PEND SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Figure 56 PEND PEND PEND PEND PEND Submit Documentation Feedback...

  • Page 109: Receive Interrupt Mask Set Register (Rxintmaskset)

    SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Reserved RX4PULSE RX3PULSE MASK MASK Reserved RX4PEND RX3PEND MASK MASK Copyright © 2006–2010, Texas Instruments Incorporated EMAC Port Registers Figure 57 and described in RX2PULSE RX1PULSE RX0PULSE MASK MASK MASK RX2PEND RX1PEND...

  • Page 110: Receive Interrupt Mask Clear Register (Rxintmaskclear)

    C6472/TCI6486 EMAC/MDIO Reserved RX4PULSE RX3PULSE MASK MASK Reserved RX4PEND RX3PEND MASK MASK SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Figure 58 and described in RX2PULSE RX1PULSE RX0PULSE MASK MASK MASK RX2PEND RX1PEND...

  • Page 111: Mac Interrupt Status (Unmasked) Register (Macintstatraw)

    Host pending interrupt (HOSTPEND); raw interrupt read (before mask) STATPEND Statistics pending interrupt (STATPEND); raw interrupt read (before mask) SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Reserved Reserved Copyright © 2006–2010, Texas Instruments Incorporated EMAC Port Registers Figure 59 and described HOST STAT PEND...

  • Page 112: Mac Interrupt Status (Masked) Register (Macintstatmasked)

    Host pending interrupt (HOSTPEND); masked interrupt read STATPEND Statistics pending interrupt (STATPEND); masked interrupt read C6472/TCI6486 EMAC/MDIO Reserved Reserved SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Figure 60 and described HOST STAT PEND...

  • Page 113: Mac Interrupt Mask Set Register (Macintmaskset)

    Statistics interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Reserved Reserved Copyright © 2006–2010, Texas Instruments Incorporated EMAC Port Registers Figure 61 and described in HOST...

  • Page 114: Mac Interrupt Mask Clear Register (Macintmaskclear)

    Statistics interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. C6472/TCI6486 EMAC/MDIO Reserved Reserved SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Figure 62 and described in HOST...

  • Page 115: Receive Multicast/Broadcast/Promiscuous Channel Enable Register (Rxmbpenable)

    Short frames are transferred to memory SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback RXNOCHAIN R/W-0 Reserved Reserved Reserved Field Descriptions Copyright © 2006–2010, Texas Instruments Incorporated EMAC Port Registers Reserved RXCMFEN R/W-0 RXPROMCH R/W-0 RXBROADCH R/W-0...

  • Page 116: Descriptions

    RXMULTCH bits. Multicast frames are filtered Multicast frames are copied to the channel selected by RXMULTCH bits Reserved Reserved C6472/TCI6486 EMAC/MDIO Descriptions (continued) SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...
  • Page 117 Select channel 5 to receive multicast frames Select channel 6 to receive multicast frames Select channel 7 to receive multicast frames SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Descriptions (continued) Copyright © 2006–2010, Texas Instruments Incorporated EMAC Port Registers C6472/TCI6486 EMAC/MDIO...

  • Page 118: Receive Unicast Enable Set Register (Rxunicastset)

    C6472/TCI6486 EMAC/MDIO Reserved RXCH6EN RXCH5EN RXCH4EN RXCH3EN R/WS-0 R/WS-0 R/WS-0 SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Figure 64 and described in RXCH2EN RXCH1EN RXCH0EN R/WS-0 R/WS-0 R/WS-0 R/WS-0 Submit Documentation Feedback...

  • Page 119: Receive Unicast Clear Register (Rxunicastclear)

    SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Reserved RXCH6EN RXCH5EN RXCH4EN RXCH3EN R/WC-0 R/WC-0 R/WC-0 Copyright © 2006–2010, Texas Instruments Incorporated EMAC Port Registers Figure 65 and described in Table RXCH2EN RXCH1EN RXCH0EN R/WC-0 R/WC-0 R/WC-0...

  • Page 120: Receive Maximum Length Register (Rxmaxlen)

    Long frames with no errors are oversized frames. Long frames with CRC, code, or alignment errors are jabber frames. C6472/TCI6486 EMAC/MDIO Figure 66 Reserved RXMAXLEN R/W-1518 SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com and described in Table Submit Documentation Feedback...

  • Page 121: Receive Buffer Offset Register (Rxbufferoffset)

    15 bytes of the buffer are to be ignored by the EMAC and that valid buffer data starts on byte 16 of the buffer. This value is used for all channels. Copyright © 2006–2010, Texas Instruments Incorporated EMAC Port Registers...

  • Page 122: Receive Filter Low Priority Frame Threshold Register (Rxfilterlowthresh)

    Receive filter low threshold. These bits contain the free buffer count threshold value for filtering low priority incoming frames. This field should remain 0 if no filtering is desired. SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Figure 68...

  • Page 123: Receive Channel 0-7 Flow Control Threshold Register (Rxnflowthresh)

    Reserved Descriptions Description Reserved Receive flow threshold. These bits contain the threshold value for issuing flow control on incoming frames for channel n (when enabled). Copyright © 2006–2010, Texas Instruments Incorporated EMAC Port Registers Figure 69 RXnFLOWTHRESH R/W-0 C6472/TCI6486 EMAC/MDIO...

  • Page 124: Receive Channel 0-7 Free Buffer Count Register (Rxnfreebuffer)

    The host must write this field with the number of buffers that have been freed due to host processing. C6472/TCI6486 EMAC/MDIO Reserved RXnFREEBUF WI-0 SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Figure 70 Submit Documentation Feedback...

  • Page 125: Mac Control Register (Maccontrol)

    Copyright © 2006–2010, Texas Instruments Incorporated EMAC Port Registers and described in...
  • Page 126 Full duplex mode. The gigabit mode forces full duplex mode regardless of whether the FULLDUPLEX bit is set or not. Half-duplex mode is enabled Full-duplex mode is enabled SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...

  • Page 127: Mac Status Register (Macstatus)

    The host error occurred on transmit channel 4. The host error occurred on transmit channel 5. The host error occurred on transmit channel 6. The host error occurred on transmit channel 7. Copyright © 2006–2010, Texas Instruments Incorporated EMAC Port Registers Table TXERRCH...
  • Page 128 Any transmission in progress when this bit is asserted will complete. Transmit flow control is inactive Transmit flow control is active SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...

  • Page 129: Emulation Control Register (Emcontrol)

    Emulation soft bit FREE Emulation free bit SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Figure 73 Reserved Reserved Copyright © 2006–2010, Texas Instruments Incorporated EMAC Port Registers and described in Table SOFT FREE R/W-0 R/W-0 C6472/TCI6486 EMAC/MDIO...

  • Page 130: Fifo Control Register (Fifocontrol)

    FIFO before the packet transfer is initiated. Packets with fewer cells are initiated when the complete packet is contained in the FIFO. This value must be greater then or equal to 2 and less than or equal to 24. Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com and described in...

  • Page 131: Mac Configuration Register (Macconfig)

    Receive cell depth. These bits indicate the number of cells in the receive FIFO. 15-8 ADDRESSTYPE Address type MACCFIG MAC configuration value SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Figure 75 Copyright © 2006–2010, Texas Instruments Incorporated EMAC Port Registers and described in Table RXCELLDEPTH R-68 MACCFIG C6472/TCI6486 EMAC/MDIO...

  • Page 132: Soft Reset Register (Softreset)

    A software reset has occurred C6472/TCI6486 EMAC/MDIO Figure 76 and described in Figure 76. Soft Reset Register (SOFTRESET) Reserved Reserved Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Table SOFTRESET R/W-0 SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback...

  • Page 133: Mac Source Address Low Bytes Register (Macsrcaddrlo)

    MAC source address lower 8 bits (byte 0) MACSRCADDR1 MAC source address bits 15-8 (byte 1) SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Reserved Copyright © 2006–2010, Texas Instruments Incorporated EMAC Port Registers Figure 77 and described in MACSRCADDR1 R/W-0...

  • Page 134: Mac Source Address High Bytes Register (Macsrcaddrhi)

    MACSRCADDR4 MAC source address bits 39-32 (byte 4) MACSRCADDR5 MAC source address bits 47-40 (byte 5) C6472/TCI6486 EMAC/MDIO SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Figure 78 and described in MACSRCADDR3 R/W-0...

  • Page 135: Mac Hash Address Register 1 (Machash1)

    XOR DA(14) XOR DA(20) XOR DA(26) XOR DA(32) XOR DA(38) XOR DA(44); XOR DA(15) XOR DA(21) XOR DA(27) XOR DA(33) XOR DA(39) XOR DA(45); Figure 79 MACHASH1 R/W-0 MACHASH1 R/W-0 Copyright © 2006–2010, Texas Instruments Incorporated EMAC Port Registers and described in Table C6472/TCI6486 EMAC/MDIO...

  • Page 136: Mac Hash Address Register 2 (Machash2)

    C6472/TCI6486 EMAC/MDIO Figure 80 MACHASH2 R/W-0 MACHASH2 R/W-0 SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com and described in Table Submit Documentation Feedback...

  • Page 137: Back Off Test Register (Bofftest)

    This field is loaded automatically according to the back off algorithm, and is decremented by one for each slot time after the collision. SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Figure 81 and described in Copyright © 2006–2010, Texas Instruments Incorporated EMAC Port Registers Table RNDNUM TXBACKOFF C6472/TCI6486 EMAC/MDIO...

  • Page 138: Transmit Pacing Algorithm Test Register (Tpacetest)

    Transmit pacing helps reduce capture effects, which improves overall network bandwidth. C6472/TCI6486 EMAC/MDIO Reserved SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Figure 82 and described in PACEVAL Submit Documentation Feedback...

  • Page 139: Receive Pause Timer Register (Rxpause)

    0, then another outgoing pause frame is sent and the load/decrement process is repeated. SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Figure 83 Reserved PAUSETIMER Copyright © 2006–2010, Texas Instruments Incorporated EMAC Port Registers and described in Table C6472/TCI6486 EMAC/MDIO...

  • Page 140: Transmit Pause Timer Register (Txpause)

    0 at which time EMAC transmit frames are again enabled. C6472/TCI6486 EMAC/MDIO Figure 84 Reserved PAUSETIMER SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com and described in Table Submit Documentation Feedback...

  • Page 141: Mac Address Low Bytes Register (Macaddrlo)

    MAC address lower 8 bits (byte 0) MACADDR1 MAC address bits 15-8 (byte 1) SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated EMAC Port Registers Figure 85 and described in Table...

  • Page 142: Mac Address High Bytes Register (Macaddrhi)

    MACADDR4 MAC source address bits 39-32 (byte 4) MACADDR5 MAC source address bits 47-40 (byte 5) C6472/TCI6486 EMAC/MDIO SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Figure 86 and described in Table MACADDR3...

  • Page 143: Mac Index Register (Macindex)

    SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Figure 87 and described in Figure 87. MAC Index Register (MACINDEX) Reserved Copyright © 2006–2010, Texas Instruments Incorporated EMAC Port Registers Table MACINDEX R/W-0 C6472/TCI6486 EMAC/MDIO...

  • Page 144: Transmit Channel 0-7 Dma Head Descriptor Pointer Register (Txnhdp)

    Writing to these locations when they are nonzero is an error (except at reset). Host software must initialize these locations to zero on reset. C6472/TCI6486 EMAC/MDIO TXnHDP R/W-x TXnHDP R/W-x SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Figure 88 Submit Documentation Feedback...

  • Page 145: Receive Channel 0-7 Dma Head Descriptor Pointer Register (Rxnhdp)

    Writing to these locations when they are nonzero is an error (except at reset). Host software must initialize these locations to zero on reset. SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback RXnHDP R/W-x RXnHDP R/W-x Copyright © 2006–2010, Texas Instruments Incorporated EMAC Port Registers Figure 89 C6472/TCI6486 EMAC/MDIO...

  • Page 146: Transmit Channel 0-7 Completion Pointer Register (Txncp)

    The EMAC uses the value written to determine if the interrupt should be de-asserted. C6472/TCI6486 EMAC/MDIO TXnCP R/W-x TXnCP R/W-x SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Figure 90 and described in Submit Documentation Feedback...

  • Page 147: Receive Channel 0-7 Completion Pointer Register (Rxncp)

    SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback RXnCP R/W-x RXnCP R/W-x Copyright © 2006–2010, Texas Instruments Incorporated EMAC Port Registers Figure 91 and described in C6472/TCI6486 EMAC/MDIO...

  • Page 148: 5.50 Network Statistics Registers

    CRC errors. Overruns have no effect on this statistic. C6472/TCI6486 EMAC/MDIO Figure 92 and described in Figure 92. Statistics Register COUNT R/W-0 COUNT R/W-0 SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Table Submit Documentation Feedback...
  • Page 149 CRC alignment or code errors can be calculated by summing receive alignment errors, receive code errors, and receive CRC errors. SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated EMAC Port Registers Section 2.5.5 C6472/TCI6486 EMAC/MDIO...
  • Page 150 Was not the result of a collision caused by half duplex, collision based flow control Section 2.5.5 for definitions of alignment, code, and CRC errors. Overruns have no effect on this statistic. C6472/TCI6486 EMAC/MDIO SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...
  • Page 151 Any data or MAC control frame that was destined for any unicast, broadcast, or multicast address • Was any length • Had no late or excessive collisions, no carrier loss, and no underrun SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated EMAC Port Registers C6472/TCI6486 EMAC/MDIO...
  • Page 152 • Was any data or MAC control frame destined for any unicast, broadcast, or multicast address C6472/TCI6486 EMAC/MDIO SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...
  • Page 153 The number of frames sent by the EMAC that experienced FIFO underrun. Late collisions, CRC errors, carrier loss, and underrun have no effect on this statistic. SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated EMAC Port Registers C6472/TCI6486 EMAC/MDIO...
  • Page 154 Was 128-bytes to 255-bytes long CRC errors, alignment/code errors, underruns, and overruns do not affect the recording of frames in this statistic. C6472/TCI6486 EMAC/MDIO SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...
  • Page 155 The objective of this statistic is to give a reasonable indication of Ethernet utilization. SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated EMAC Port Registers C6472/TCI6486 EMAC/MDIO...
  • Page 156 (zero head descriptor pointer at the start or during the middle of the frame reception). CRC errors, alignment errors, and code errors have no effect on this statistic. C6472/TCI6486 EMAC/MDIO SPRUEF8F – March 2006 – Revised November 2010 Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...

  • Page 157: Appendix A Glossary

    Descriptors are used by the EMAC and application to describe the memory buffers that hold Ethernet data. Device — In this document, device refers to the TMS320TCI6486/TMS320C6472 digital signal processor. Ethernet MAC Address (MAC Address)— A unique 6-byte address that identifies an Ethernet device on the network.
  • Page 158 Category 5 balanced copper cabling. A cable element that consists of two insulated conductors twisted together in a regular fashion to form a balanced transmission line. Copyright © 2006–2010, Texas Instruments Incorporated www.ti.com SPRUEF8F – March 2006 – Revised November 2010...

  • Page 159: Appendix B Revision History

    Modified RXINTMASKSET register table Figure 58 Modified RXINTMASKCLEAR register figure Table 52 Modified RXINTMASKCLEAR register table SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Table 87. EMAC/MDIO Revision History Copyright © 2006–2010, Texas Instruments Incorporated Revision History...

  • Page 160: Important Notice

    Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

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