Texas Instruments TMS320DM643X DMP User Manual
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Texas Instruments TMS320DM643X DMP User Manual

Texas Instruments TMS320DM643X DMP User Manual

Dmp universal asynchronous receiver/transmitter (uart)
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TMS320DM643x DMP
Universal Asynchronous Receiver/Transmitter
(UART)
User's Guide
Literature Number: SPRU997C
December 2009

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Summary of Contents for Texas Instruments TMS320DM643X DMP

  • Page 1 TMS320DM643x DMP Universal Asynchronous Receiver/Transmitter (UART) User's Guide Literature Number: SPRU997C December 2009...
  • Page 2 SPRU997C – December 2009 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated...

  • Page 3: Table Of Contents

    Line Status Register (LSR) Divisor Latches (DLL and DLH) 3.10 Peripheral Identification Registers (PID1 and PID2) 3.11 Power and Emulation Management Register (PWREMU_MGMT) Appendix A Revision History SPRU997C – December 2009 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Table of Contents...
  • Page 4 Divisor MSB Latch (DLH) Peripheral Identification Register 1 (PID1) Peripheral Identification Register 2 (PID2) Power and Emulation Management Register (PWREMU_MGMT) List of Figures List of Figures Copyright © 2009, Texas Instruments Incorporated www.ti.com SPRU997C – December 2009 Submit Documentation Feedback...
  • Page 5 Peripheral Identification Register 1 (PID1) Field Descriptions Peripheral Identification Register 2 (PID2) Field Descriptions Power and Emulation Management Register (PWREMU_MGMT) Field Descriptions Document Revision History SPRU997C – December 2009 Submit Documentation Feedback List of Tables Copyright © 2009, Texas Instruments Incorporated List of Tables...

  • Page 6: Preface

    The current documentation that describes the DM643x DMP, related peripherals, and other technical collateral, is available in the C6000 DSP product folder at: www.ti.com/c6000. SPRU978 — TMS320DM643x DMP DSP Subsystem Reference Guide. Describes the digital signal processor (DSP) subsystem in the TMS320DM643x Digital Media Processor (DMP). SPRU983 —...

  • Page 7: Universal Asynchronous Receiver/Transmitter (Uart)

    Modem control functions using CTS and RTS signals (not supported on all UARTs. See the device-specific data manual for supported features.) SPRU997C – December 2009 Submit Documentation Feedback Universal Asynchronous Receiver/Transmitter (UART) Copyright © 2009, Texas Instruments Incorporated User's Guide SPRU997C – December 2009...

  • Page 8: Functional Block Diagram

    TL16C450. Any deviations in supported functions are indicated in Table The information in this document assumes the reader is familiar with these standards. Universal Asynchronous Receiver/Transmitter (UART) Figure Copyright © 2009, Texas Instruments Incorporated www.ti.com Support Supported Supported Supported...

  • Page 9: Uart Block Diagram

    Register Interrupt Interrupt/ Enable Event Register Control Logic Interrupt Identification Register FIFO Control Register Universal Asynchronous Receiver/Transmitter (UART) Copyright © 2009, Texas Instruments Incorporated Introduction Receiver Shift Register Receiver Timing and Control Transmitter Timing and Control Transmitter Shift Register Control...

  • Page 10: Peripheral Architecture

    - 1) to produce a baud clock (BCLK). The frequency of BCLK is sixteen 3. These divisor latches must be loaded during initialization of the UART UART DLH:DLL UART input clock Clock Baud generator Other logic Copyright © 2009, Texas Instruments Incorporated www.ti.com Table Receiver timing and control BCLK Transmitter timing and control SPRU997C –...

  • Page 11: Relationships Between Data Bit, Bclk, And Uart Input Clock

    Submit Documentation Feedback Each bit lasts 16 BCLK cycles. Actual Baud Rate 2400.427 4794.034 9588.068 19176.14 38352.27 56250 129807.7 Universal Asynchronous Receiver/Transmitter (UART) Copyright © 2009, Texas Instruments Incorporated Peripheral Architecture PARITY STOP1 STOP2 Error (%) 0.018 -0.124 -0.124 -0.124 -0.124 0.446...

  • Page 12: Signal Descriptions

    3. Note that the number of UARTs and their supported features Table 3. UART Signal Descriptions Function Serial data transmit Serial data receive Clear-to-Send handshaking signal Request-to-Send handshaking signal Copyright © 2009, Texas Instruments Incorporated www.ti.com SPRU997C – December 2009 Submit Documentation Feedback...

  • Page 13: Endianness Considerations

    DM643x DMP, there are no endianness considerations when using the DM643x UART peripheral. SPRU997C – December 2009 Submit Documentation Feedback Figure 4 Figure 4. UART Protocol Formats PARITY Universal Asynchronous Receiver/Transmitter (UART) Copyright © 2009, Texas Instruments Incorporated Peripheral Architecture STOP1 PARITY STOP1 PARITY STOP1...

  • Page 14: Operation

    RBR. In the FIFO mode, the interrupt is generated when the FIFO is filled to the trigger level selected in the FIFO control register (FCR), and it is cleared when the FIFO contents drop below the trigger level. Universal Asynchronous Receiver/Transmitter (UART) Copyright © 2009, Texas Instruments Incorporated www.ti.com SPRU997C – December 2009 Submit Documentation Feedback...

  • Page 15: Character Time For Word Lengths

    Time for 8 bits Time for 9 bits Time for 10 bits Time for 11 bits Universal Asynchronous Receiver/Transmitter (UART) Copyright © 2009, Texas Instruments Incorporated Peripheral Architecture Four Character Times Time for 32 bits Time for 36 bits Time for 40 bits...

  • Page 16: Uart Interface Using Autoflow Diagram

    Serial to Parallel to Parallel Serial Flow Flow Control Control Parallel to Serial to Serial Parallel Flow Flow Control Control Off-chip Copyright © 2009, Texas Instruments Incorporated www.ti.com Transmitter FIFO D[7:0] Receiver FIFO SPRU997C – December 2009 Submit Documentation Feedback...

  • Page 17: Autoflow Functional Timing Waveforms For Rts

    6), RTS is deasserted. The sending UART may send Stop Stop Start Bits N Bits N+1 Figure Bits0−7 Stop Start Bits 0−7 Universal Asynchronous Receiver/Transmitter (UART) Copyright © 2009, Texas Instruments Incorporated Peripheral Architecture Stop Start 7). When flow control is enabled, CTS Stop Start Bits 0−7 Stop...

  • Page 18: Reset Considerations

    The UARTs have dedicated interrupt signals to the DSP CPU and the interrupts are not multiplexed with any other interrupt source. Universal Asynchronous Receiver/Transmitter (UART) Table 5. All requests are multiplexed through an Figure Copyright © 2009, Texas Instruments Incorporated www.ti.com Section 8. Each of the interrupt requests SPRU997C – December 2009 Submit Documentation Feedback...

  • Page 19: Uart Interrupt Request Enable Paths

    (OE), parity error indicator (PE), framing error indicator (FE), and break indicator (BI). Enable bits UART interrupt requests THREINT IER(ETBEI) RDRINT IER(ERBI) RTOINT RLSINT IER(ELSI) Universal Asynchronous Receiver/Transmitter (UART) Copyright © 2009, Texas Instruments Incorporated Peripheral Architecture Arbiter UART interrupt request to CPU...

  • Page 20: 2.10 Dma Event Support

    Controller (PSC). The PSC acts as a master controller for power management for all of the peripherals on the device. For detailed information on power management procedures using the PSC, see the TMS320DM643x DMP DSP Subsystem Reference Guide (SPRU978). 2.12 Emulation Considerations The FREE bit in the power and emulation management register (PWREMU_MGMT) determines how the UART responds to an emulation suspend event such as an emulator halt or breakpoint.

  • Page 21: 2.13 Exception Processing

    Line Status Register Divisor LSB Latch Divisor MSB Latch Peripheral Identification Register 1 Peripheral Identification Register 2 Power and Emulation Management Register Universal Asynchronous Receiver/Transmitter (UART) Copyright © 2009, Texas Instruments Incorporated Registers Section Section 3.1 Section 3.2 Section 3.3 Section 3.4 Section 3.5...

  • Page 22: Receiver Buffer Register (Rbr)

    Description 31-8 Reserved Reserved DATA 0-FFh Received data Universal Asynchronous Receiver/Transmitter (UART) Figure 9 and described in Figure 9. Receiver Buffer Register (RBR) Reserved Copyright © 2009, Texas Instruments Incorporated www.ti.com Table DATA SPRU997C – December 2009 Submit Documentation Feedback...

  • Page 23: Transmitter Holding Register (Thr)

    31-8 Reserved Reserved DATA 0-FFh Data to transmit SPRU997C – December 2009 Submit Documentation Feedback Figure 10 and described in Figure 10. Transmitter Holding Register (THR) Reserved Universal Asynchronous Receiver/Transmitter (UART) Copyright © 2009, Texas Instruments Incorporated Registers Table DATA...

  • Page 24: Interrupt Enable Register (Ier)

    Receiver data available interrupt and character timeout indication interrupt is enabled. Universal Asynchronous Receiver/Transmitter (UART) and described in Table Figure 11. Interrupt Enable Register (IER) Reserved Reserved Copyright © 2009, Texas Instruments Incorporated www.ti.com Rsvd ELSI ETBEI ERBI R/W-0 R/W-0...

  • Page 25: Interrupt Identification Register (Iir)

    IPEND is never forced to 0. Interrupts pending. No interrupts pending. SPRU997C – December 2009 Submit Documentation Feedback Figure 12 and described in Reserved FIFOEN Reserved Table Universal Asynchronous Receiver/Transmitter (UART) Copyright © 2009, Texas Instruments Incorporated Registers Figure INTID IPEND...

  • Page 26: Fifo Control Register (Fcr)

    (THR) is empty. FIFO mode: Transmitter FIFO is empty. Figure 13 and described in CAUTION Copyright © 2009, Texas Instruments Incorporated www.ti.com Event That Clears Interrupt None For an overrun error, reading the line status register (LSR) clears the interrupt.

  • Page 27: Fifo Control Register (Fcr)

    FIFO mode. The transmitter and receiver FIFOs are enabled. SPRU997C – December 2009 Submit Documentation Feedback Figure 13. FIFO Control Register (FCR) Reserved Reserved Reserved DMAMODE1 Universal Asynchronous Receiver/Transmitter (UART) Copyright © 2009, Texas Instruments Incorporated Registers TXCLR RXCLR FIFOEN W1C-0 W1C-0...

  • Page 28: Line Control Register (Lcr)

    Universal Asynchronous Receiver/Transmitter (UART) Figure 14 and described in Figure 14. Line Control Register (LCR) Reserved DLAB R/W-0 R/W-0 R/W-0 Table Table Table Copyright © 2009, Texas Instruments Incorporated www.ti.com Table R/W-0 R/W-0 R/W-0 R/W-0 SPRU997C – December 2009 Submit Documentation Feedback...

  • Page 29: Relationship Between St, Eps, And Pen Bits In Lcr

    Table 15. Number of STOP Bits Generated Word Length Selected Number of STOP Bits with WLS Bits Any word length 5 bits 6 bits 7 bits 8 bits Universal Asynchronous Receiver/Transmitter (UART) Copyright © 2009, Texas Instruments Incorporated Registers Baud Clock (BCLK) Generated Cycles...

  • Page 30: Modem Control Register (Mcr)

    RTS and CTS are enabled. Reserved Reserved Universal Asynchronous Receiver/Transmitter (UART) Figure 15 and described in Figure 15. Modem Control Register (MCR) Reserved R/W-0 Copyright © 2009, Texas Instruments Incorporated www.ti.com Table 16. The modem control LOOP Reserved Rsvd R/W-0 R/W-0 SPRU997C –...

  • Page 31: Line Status Register (Lsr)

    (TSR). SPRU997C – December 2009 Submit Documentation Feedback Figure 16 and described in Figure 16. Line Status Register (LSR) Reserved RXFIFOE TEMT THRE Universal Asynchronous Receiver/Transmitter (UART) Copyright © 2009, Texas Instruments Incorporated Registers Table 17. LSR provides information...
  • Page 32 An overrun error is indicated to the CPU as soon as it happens. The new character overwrites the character in the shift register, but it is not transferred to the FIFO. Universal Asynchronous Receiver/Transmitter (UART) Copyright © 2009, Texas Instruments Incorporated www.ti.com SPRU997C – December 2009...

  • Page 33: Divisor Latches (Dll And Dlh)

    The divisor LSB latch (DLL) is shown in is shown in Figure 18 and described in SPRU997C – December 2009 Submit Documentation Feedback Figure 17 and described in Table Universal Asynchronous Receiver/Transmitter (UART) Copyright © 2009, Texas Instruments Incorporated Registers Table 18. The divisor MSB latch (DLH)

  • Page 34: Divisor Lsb Latch (Dll)

    Maximum baud rate is 128 kbps. Universal Asynchronous Receiver/Transmitter (UART) Figure 17. Divisor LSB Latch (DLL) Reserved Figure 18. Divisor MSB Latch (DLH) Reserved Copyright © 2009, Texas Instruments Incorporated www.ti.com R/W-0 R/W-0 SPRU997C – December 2009 Submit Documentation Feedback...

  • Page 35: Peripheral Identification Registers (Pid1 And Pid2)

    Identifies type of peripheral. UART SPRU997C – December 2009 Submit Documentation Feedback Figure 19 and described in Table 20. PID2 is shown in Reserved Reserved Universal Asynchronous Receiver/Transmitter (UART) Copyright © 2009, Texas Instruments Incorporated Registers Figure 20 R-1h R-04h...

  • Page 36: Power And Emulation Management Register (Pwremu_Mgmt)

    If a transmission is not in progress, the UART halts immediately. If a transmission is in progress, the UART halts after completion of the one-word transmission. Free-running mode is enabled; UART continues to run normally. Universal Asynchronous Receiver/Transmitter (UART) Reserved Reserved Copyright © 2009, Texas Instruments Incorporated www.ti.com Figure 21 and described FREE R/W-0 SPRU997C –...

  • Page 37: Appendix A Revision History

    Table 23 lists the changes made since the previous version of this document. Reference Additions/Modifications/Deletions Section 2.1 Changed first paragraph. SPRU997C – December 2009 Submit Documentation Feedback Table 23. Document Revision History Copyright © 2009, Texas Instruments Incorporated Revision History...

  • Page 38: Important Notice

    Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

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