Direct Interconnect (Xc4000X Only); I/O Routing; Octal I/O Routing (Xc4000X Only) - Xilinx XC4000E Series Manual

vents undefined floating levels. However, it is overridden by
any driver, even a pull-up resistor.
Each XC4000E longline has a programmable splitter
switch at its center, as does each XC4000X longline driven
by TBUFs. This switch can separate the line into two inde-
pendent routing channels, each running half the width or
height of the array.
Each XC4000X longline not driven by TBUFs has a buff-
ered programmable splitter switch at the 1/4, 1/2, and 3/4
points of the array. Due to the buffering, XC4000X longline
performance does not deteriorate with the larger array
sizes. If the longline is split, the resulting partial longlines
are independent.
Routing connectivity of the longlines is shown in
on page 4-31.

Direct Interconnect (XC4000X only)

The XC4000X offers two direct, efficient and fast connec-
tions between adjacent CLBs. These nets facilitate a data
flow from the left to the right side of the device, or from the
top to the bottom, as shown in
the direct interconnect exhibit minimum interconnect prop-
agation delay and use no general routing resources.
The direct interconnect is also present between CLBs and
adjacent IOBs. Each IOB on the left and top device edges
has a direct path to the nearest CLB. Each CLB on the right
and bottom edges of the array has a direct path to the near-
est two IOBs, since there are two IOBs for each row or col-
umn of CLBs.
The place and route software uses direct interconnect
whenever possible, to maximize routing resources and
minimize interconnect delays.
IOB
CLB
IOB
IOB
CLB
IOB
Figure 31: XC4000X Direct Interconnect
March 30, 1998 (Version 1.5)
Figure 28
Figure 31. Signals routed on
IOB
CLB CLB
IOB
IOB
CLB
CLB
IOB
X6603

I/O Routing

XC4000 Series devices have additional routing around the
IOB ring. This routing is called a VersaRing. The VersaRing
facilitates pin-swapping and redesign without affecting
board layout. Included are eight double-length lines span-
ning two CLBs (four IOBs), and four longlines. Global lines
and Wide Edge Decoder lines are provided. XC4000X
devices also include eight octal lines.
A high-level diagram of the VersaRing is shown in
Figure 32. The shaded arrows represent routing present
only in XC4000X devices.
Figure 34 on page 4-35
XC4000E and XC4000X VersaRing. The area shown
includes two IOBs. There are two IOBs per CLB row or col-
umn, therefore this diagram corresponds to the CLB rout-
ing diagram shown in Figure 28 on page
areas represent routing and routing connections present
only in XC4000X devices.

Octal I/O Routing (XC4000X only)

Between the XC4000X CLB array and the pad ring, eight
interconnect tracks provide for versatility in pin assignment
and fixed pinout flexibility. (See
These routing tracks are called octals, because they can be
broken every eight CLBs (sixteen IOBs) by a programma-
ble buffer that also functions as a splitter switch. The buff-
ers are staggered, so each line goes through a buffer at
every eighth CLB location around the device edge.
The octal lines bend around the corners of the device. The
lines cross at the corners in such a way that the segment
most recently buffered before the turn has the farthest dis-
tance to travel before the next buffer, as shown in
Figure 33.
is a detailed diagram of the
4-31. The shaded
Figure 33 on page 4-34.)
4-33