Description; Taking Advantage Of Reconfiguration - Xilinx XC4000E Series Manual

XC4000E and XC4000X Series Field Programmable Gate Arrays
Note: All functionality in low-voltage families is the same as
in the corresponding 5-Volt family, except where numerical
references are made to timing or power.
Table 2: XC4000E and XC4000X Series Field Programmable Gate Arrays
Logic
Device Cells
XC4002XL 152
XC4003E 238
XC4005E/XL 466
XC4006E 608
XC4008E 770
XC4010E/XL 950
XC4013E/XL 1368
XC4020E/XL 1862
XC4025E 2432
XC4028EX/XL 2432
XC4036EX/XL 3078
XC4044XL 3800
XC4052XL 4598
XC4062XL 5472
XC4085XL 7448
* Max values of Typical Gate Range include 20-30% of CLBs used as RAM.

Description

XC4000 Series devices are implemented with a regular,
flexible, programmable architecture of Configurable Logic
Blocks (CLBs), interconnected by a powerful hierarchy of
versatile routing resources, and surrounded by a perimeter
of programmable Input/Output Blocks (IOBs). They have
generous routing resources to accommodate the most
complex interconnect patterns.
The devices are customized by loading configuration data
into internal memory cells. The FPGA can either actively
read its configuration data from an external serial or byte-
parallel PROM (master modes), or the configuration data
can be written into the FPGA from an external device (slave
and peripheral modes).
XC4000 Series FPGAs are supported by powerful and
sophisticated software, covering every aspect of design
from schematic or behavioral entry, floorplanning, simula-
tion, automatic block placement and routing of intercon-
nects, to the creation, downloading, and readback of the
configuration bit stream.
Because Xilinx FPGAs can be reprogrammed an unlimited
number of times, they can be used in innovative designs
where hardware is changed dynamically, or where hard-
ware must be adapted to different user applications.
4-6
Max Logic Max. RAM
Gates Bits
(No RAM) (No Logic)
1,600 2,048
3,000 3,200
5,000 6,272
6,000 8,192
8,000 10,368
10,000 12,800
13,000 18,432
20,000 25,088
25,000 32,768
28,000 32,768
36,000 41,472
44,000 51,200
52,000 61,952
62,000 73,728
85,000 100,352
Typical
Gate Range CLB
(Logic and RAM)* Matrix
1,000 - 3,000 8 x 8
2,000 - 5,000 10 x 10
3,000 - 9,000 14 x 14
4,000 - 12,000 16 x 16
6,000 - 15,000 18 x 18
7,000 - 20,000 20 x 20
10,000 - 30,000 24 x 24
13,000 - 40,000 28 x 28
15,000 - 45,000 32 x 32
18,000 - 50,000 32 x 32
22,000 - 65,000 36 x 36
27,000 - 80,000 40 x 40
33,000 - 100,000 44 x 44
40,000 - 130,000 48 x 48
55,000 - 180,000 56 x 56
FPGAs are ideal for shortening design and development
cycles, and also offer a cost-effective solution for produc-
tion rates well beyond 5,000 systems per month. For lowest
high-volume unit cost, a design can first be implemented in
the XC4000E or XC4000X, then migrated to one of Xilinx'
compatible HardWire mask-programmed devices.
Taking Advantage of Reconfiguration
FPGA devices can be reconfigured to change logic function
while resident in the system. This capability gives the sys-
tem designer a new degree of freedom not available with
any other type of logic.
Hardware can be changed as easily as software. Design
updates or modifications are easy, and can be made to
products already in the field. An FPGA can even be recon-
figured dynamically to perform different functions at differ-
ent times.
Reconfigurable logic can be used to implement system
self-diagnostics, create systems capable of being reconfig-
ured for different environments or operations, or implement
multi-purpose hardware for a given application. As an
added benefit, using reconfigurable FPGA devices simpli-
fies hardware design and debugging and shortens product
time-to-market.
Number
Total of Max.
CLBs Flip-Flops User I/O
64 256
100 360
196 616 112
256 768 128
324 936 144
400 1,120 160
576 1,536 192
784 2,016 224
1,024 2,560 256
1,024 2,560 256
1,296 3,168 288
1,600 3,840 320
1,936 4,576 352
2,304 5,376 384
3,136 7,168 448
March 30, 1998 (Version 1.5)
64
80