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XC4000E and XC4000X Series Field Programmable Gate Arrays
Additional Input Latch for Fast Capture (XC4000X only)
The XC4000X IOB has an additional optional latch on the
input. This latch, as shown in
output clock — the clock used for the output flip-flop —
rather than the input clock. Therefore, two different clocks
can be used to clock the two input storage elements. This
additional latch allows the very fast capture of input data,
which is then synchronized to the internal clock by the IOB
flip-flop or latch.
To use this Fast Capture technique, drive the output clock
pin (the Fast Capture latching signal) from the output of one
of the Global Early buffers supplied in the XC4000X. The
second storage element should be clocked by a Global
Low-Skew buffer, to synchronize the incoming data to the
internal logic. (See
Figure
described in
"Global Nets and Buffers (XC4000X only)" on
page
4-38.
The Fast Capture latch (FCL) is designed primarily for use
with a Global Early buffer. For Fast Capture, a single clock
signal is routed through both a Global Early buffer and a
Global Low-Skew buffer. (The two buffers share an input
pad.) The Fast Capture latch is clocked by the Global Early
buffer, and the standard IOB flip-flop or latch is clocked by
the Global Low-Skew buffer. This mode is the safest way to
use the Fast Capture latch, because the clock buffers on
both storage elements are driven by the same pad. There
is no external skew between clock pads to create potential
problems.
To place the Fast Capture latch in a design, use one of the
special library symbols, ILFFX or ILFLX. ILFFX is a trans-
parent-Low Fast Capture latch followed by an active-High
input flip-flop. ILFLX is a transparent-Low Fast Capture
latch followed by a transparent-High input latch. Any of the
clock inputs can be inverted before driving the library ele-
ment, and the inverter is absorbed into the IOB. If a single
BUFG output is used to drive both clock inputs, the soft-
ware automatically runs the clock through both a Global
Low-Skew buffer and a Global Early buffer, and clocks the
Fast Capture latch appropriately.
Figure 17 on page 4-22
also shows a two-tap delay on the
input. By default, if the Fast Capture latch is used, the Xilinx
software assumes a Global Early buffer is driving the clock,
and selects MEDDELAY to ensure a zero hold time. Select
IPAD
D
GF
BUFGE
CE
C
IPAD
BUFGLS
Figure 18: Examples Using XC4000X FCL
4-24
Figure
17, is clocked by the
18.) These special buffers are
ILFFX
to internal
Q
logic
X9013
the desired delay based on the discussion in the previous
subsection.
IOB Output Signals
Output signals can be optionally inverted within the IOB,
and can pass directly to the pad or be stored in an edge-
triggered flip-flop. The functionality of this flip-flop is shown
in
Table
12.
An active-High 3-state signal can be used to place the out-
put buffer in a high-impedance state, implementing 3-state
outputs or bidirectional I/O. Under configuration control, the
output (OUT) and output 3-state (T) signals can be
inverted. The polarity of these signals is independently con-
figured for each IOB.
The 4-mA maximum output current specification of many
FPGAs often forces the user to add external buffers, which
are especially cumbersome on bidirectional I/O lines. The
XC4000E and XC4000EX/XL devices solve many of these
problems by providing a guaranteed output sink current of
12 mA. Two adjacent outputs can be interconnected exter-
nally to sink up to 24 mA. The XC4000E and XC4000EX/XL
FPGAs can thus directly drive buses on a printed circuit
board.
By default, the output pull-up structure is configured as a
TTL-like totem-pole. The High driver is an n-channel pull-
up transistor, pulling to a voltage one transistor threshold
below Vcc. Alternatively, the outputs can be globally config-
ured as CMOS drivers, with p-channel pull-up transistors
pulling to Vcc. This option, applied using the bitstream gen-
eration software, applies to all outputs on the device. It is
not individually programmable. In the XC4000XL, all out-
puts are pulled to the positive supply rail.
Table 12: Output Flip-Flop Functionality (active rising
edge is shown)
Mode
Clock
Power-Up
X
or GSR
X
__/
Flip-Flop
X
0
Legend:
X
Don't care
__/
Rising edge
SR
Set or Reset value. Reset is default.
0*
Input is Low or unconnected (default value)
1*
Input is High or unconnected (default value)
Z
3-state
Clock
Enable
T
D
X
0*
X
0
0*
X
1*
0*
D
X
1
X
X
0*
X
March 30, 1998 (Version 1.5)
Q
SR
Q
D
Z
Q
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