Power Distribution - Xilinx XC4000E Series Manual

XC4000E and XC4000X Series Field Programmable Gate Arrays
The top and bottom Global Early buffers are about 1 ns
slower clock to out than the left and right Global Early buff-
ers.
The Global Early buffers can be driven by either semi-ded-
icated pads or internal logic. They share pads with the Glo-
bal Low-Skew buffers, so a single net can drive both global
buffers, as described above.
To use a Global Early buffer, place a BUFGE element in a
schematic or in HDL code. If desired, attach a LOC
attribute or property to direct placement to the designated
location. For example, attach a LOC=T attribute or property
to direct that a BUFGE be placed in one of the two Global
Early buffers on the top edge of the device, or a LOC=TR to
indicate the Global Early buffer on the top edge of the
device, on the right.

Power Distribution

Power for the FPGA is distributed through a grid to achieve
high noise immunity and isolation between logic and I/O.
Inside the FPGA, a dedicated Vcc and Ground ring sur-
rounding the logic array provides power to the I/O drivers,
as shown in Figure 40. An independent matrix of Vcc and
Ground lines supplies the interior logic of the device.
This power distribution grid provides a stable supply and
ground for all internal logic, providing the external package
power pins are all connected and appropriately decoupled.
Typically, a 0.1 µF capacitor connected between each Vcc
pin and the board's Ground plane will provide adequate
decoupling.
Output buffers capable of driving/sinking the specified 12
mA loads under specified worst-case conditions may be
capable of driving/sinking up to 10 times as much current
under best case conditions.
Noise can be reduced by minimizing external load capaci-
tance and reducing simultaneous output transitions in the
same direction. It may also be beneficial to locate heavily
loaded output buffers near the Ground pads. The I/O Block
output buffers have a slew-rate limited mode (default)
which should be used where output rise and fall times are
not speed-critical.
4-40
GND
Vcc
GND
Figure 40: XC4000 Series Power Distribution
Pin Descriptions
There are three types of pins in the XC4000 Series
devices:
• Permanently dedicated pins
• User I/O pins that can have special functions
• Unrestricted user-programmable I/O pins.
Before and during configuration, all outputs not used for the
configuration process are 3-stated with a 50 kΩ - 100 kΩ
pull-up resistor.
After configuration, if an IOB is unused it is configured as
an input with a 50 kΩ - 100 kΩ pull-up resistor.
XC4000 Series devices have no dedicated Reset input.
Any user I/O can be configured to drive the Global Set/
Reset net, GSR. See "Global Set/Reset" on page 4-11
more information on GSR.
XC4000 Series devices have no Powerdown control input,
as the XC3000 and XC2000 families do. The XC3000/
XC2000 Powerdown control also 3-stated all of the device
I/O pins. For XC4000 Series devices, use the global 3-state
net, GTS, instead. This net 3-states all outputs, but does
not place the device in low-power mode. See
Signals" on page 4-24 for more information on GTS.
Device pins for XC4000 Series devices are described in
Table 17. Pin functions during configuration for each of the
seven configuration modes are summarized in
page 4-59, in the "Configuration Timing" section.
Ground and
Vcc Ring for
I/O Drivers
Vcc
Logic
Power Grid
X5422
"IOB Output
Table 23 on
March 30, 1998 (Version 1.5)
for