Flip-Flops; Latches (Xc4000X Only); Clock Input; Clock Enable - Xilinx XC4000E Series Manual

XC4000E and XC4000X Series Field Programmable Gate Arrays
4
C 1 • • • C 4
G 4
G 3
LOGIC
FUNCTION
OF
G 2
G1-G4
G 1
F 4
F 3 LOGIC
FUNCTION
OF
F 2
F1-F4
F 1
K
(CLOCK)
Figure 2: Simplified Block Diagram of XC4000 Series CLB (RAM and Carry Logic functions not shown)

Flip-Flops

The CLB can pass the combinatorial output(s) to the inter-
connect network, but can also store the combinatorial
results or other incoming data in one or two flip-flops, and
connect their outputs to the interconnect network as well.
The two edge-triggered D-type flip-flops have common
clock (K) and clock enable (EC) inputs. Either or both clock
inputs can also be permanently enabled. Storage element
functionality is described in

Latches (XC4000X only)

The CLB storage elements can also be configured as
latches. The two latches have common clock (K) and
clock enable (EC) inputs. Storage element functionality is
described in Table 3.

Clock Input

Each flip-flop can be triggered on either the rising or falling
clock edge. The clock pin is shared by both storage ele-
ments. However, the clock is individually invertible for each
storage element. Any inverter placed on the clock input is
automatically absorbed into the CLB.
4-10
H 1
G'
LOGIC
FUNCTION
OF
H'
F', G',
AND
H1
F'
Table 3.
D IN /H 2 EC
SR/H 0
CONTROL
DIN
F'
G'
H'
G'
H'
1
CONTROL
DIN
F'
G'
H'
1
H'
F'
Multiplexer Controlled
by Configuration Program

Clock Enable

The clock enable signal (EC) is active High. The EC pin is
shared by both storage elements. If left unconnected for
either, the clock enable for that storage element defaults to
the active state. EC is not invertible within the CLB.
Table 3: CLB Storage Element Functionality
(active rising edge is shown)
Mode K
Power-Up or
X
GSR
X
Flip-Flop __/
0
1
Latch
0
Both X
Legend:
X Don't care
__/ Rising edge
SR Set or Reset value. Reset is default.
0* Input is Low or unconnected (default value)
1* Input is High or unconnected (default value)
S/R Bypass
SD
D Q
EC
RD
Bypass
S/R
SD
D Q
EC
RD
EC SR
X X X
X 1 X
1* 0* D
X 0* X
1* 0* X
1* 0* D
0 0* X
March 30, 1998 (Version 1.5)
YQ
Y
XQ
X
X6692
D Q
SR
SR
D
Q
Q
D
Q