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Default - Aaeon SBC-410 Manual

Half-size 486 all-in-one cpu card with cache

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If CPU processing comes to a halt because of EMI or software
bug, the watchdog timer can either reset the CPU or signal an
interrupt on IRQ15.
Reset CPU*
IRQ15
1
2
3
1
2
3

* default

The watchdog timer must be programmed to write to I/O port
address 443 at an interval shorter than the timer's preset interval.
The timer's interval has a tolerance of ±5%, so you should
program an instruction that will refresh the timer before a time-
out occurs. The following steps illustrate how you might
program the watchdog timer.
Chapter 2 Installation
29
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