Toshiba TXZ Series Reference Manual page 66

3.0 2019-02-28
2019-02-28
-4.2.6. [TSPIxFMTR0]:
Modified to "This setup...of <FINT> occurs." in <FINT>.
Corrected to "Polarity of serial clock" to "Polarity of idle period of serial clock
(Note2)" in <CKPOL>.
Modified "Minimum idle time" to "Idle time" and to "CS deassertion...in master
mode." in <CSINT>.
Deleted "Valid...mode.", modified description in <CSSCKDL>/<SCLCSDL>.
-4.2.9. [TSPIxSR]:
Corrected "3. In the single..." to "3. In the continuously..." modified/ added
description in <TSPISUE>.
Modified description in <TXEND>, modified description in <RXEND>.
-4.2.10.[TSPIxERR]： Corrected "<VPERR>" to "<PERR>"
- 5.Example for use:
Corrected "Single" to "Burst", "Burst transfer" to "Burst transfer (Include single
transfer)".
-6.Precautions: Deleted "●When using ...to confirm which trigger can use.".
-Trademark
Modified description
- 1, Outline
Deleted "Data is sampled with 1st edge" from Data sampling timing in
Table1.2
Deleted "Trigger error interrupt" from Interruption in Table 1.2 and Table 1.4
Added "Output level of TSPIxTXD when underrun error occurred" in
Table1.4
Modified fsys to f of Final bit hold time of a TSPIxTXD pin in Table1.4.
clk
Added Note in Table1.4.
- 2. Configuration
Modified fsys to f (Note) and signal name of f
clk
Added reference manual of f
- 3.3.1 Transfer clock
Tile was modified from Transmission clock to Transfer clock
- 3.3.1.1 Master operation
Modified parameter of (1/x),
Modified the formula in case of [TSPIxCR2]<RXDLY>=0
Modified fsys to fclk of formula
Added Note2 in Table3.1 And modified Note to Note2
- 3.3.1.2 Slave operation
Added the formula of slave operation
- 3.3.2.1 SPI mode
Modified "Master device operation" to "Master operation"
- 3.3.2.2 SIO mode
Modified "Master device operation" to "Master operation", Added Note
- 3.3.5.3 Continuously transfer
Deleted Note1 and Note2
- 3.3.6 Data sampling timing
Added Table 3.3, Table 3.4
Deleted Data sampling timing of SPI mode(slave) 1st edge from Figure 3.17
Modified Data sampling timing of SIO mode(master) 2nd edge from Figure
3.18
Modified Data sampling timing of SIO mode(slave) 2nd edge from Figure
3.19
3.3.9.1 Transmit Completion Interrupt/Receive Completion Interrupt
Added explanation of slave device operation
4.2.3 [TSPIxCR2]
Deleted Note1) of function explanation in <TIDLE[1:0]>
Added Note1) of function explanation in <RXDLY>
Modified <INTERR> of function explanation
Deleted old Note1), Shifted old Note2) to Note1), Added new Note2)
4.2.5 [TSPIxBR] (TSPI Baud Rate Register)
Deleted Note
4.2.6 [TSPIxFMTR0]
Added (Master operation) in <CKPHA> function explanation field,
4.2.7 [TSPIxFMTR1]
Modified <EHOLD> of function explanation.
Added Note1, Shifted old Note1 to Note2.
4.2.9 [TSPIxSR] (TSPI Status Register)
Modified headline of Table 4.2
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Serial Peripheral Interface
in Table2.1
clk
and Note in Table2.1.
clk
TXZ Family
Rev. 3.0