Toshiba TXZ Series Reference Manual page 4

TXZ Family
Serial Peripheral Interface
List of Figures
Figure 2.1 Block diagram of TSPI ............................................................................................................ 14
Figure 3.1 Data format ............................................................................................................................. 17
Figure 3.2 MSB first (32-bit data without a parity bit)............................................................................... 18
Figure 3.3 MSB first (16-bit data without a parity bit)............................................................................... 19
Figure 3.4 LSB first (32-bit data without a parity bit)................................................................................ 20
Figure 3.5 LSB first (16-bit data without a parity bit)................................................................................ 21
Figure 3.6 MSB first (31-bit data with a parity) ........................................................................................ 22
Figure 3.7 MSB first (15-bit data with parity)............................................................................................ 23
Figure 3.8 LSB first (31-bit data with parity)............................................................................................. 24
Figure 3.9 LSB first (15-bit data with parity)............................................................................................. 25
Figure 3.10 Transfer clock generation circuit ........................................................................................... 26
Figure 3.11 Operation in 7 to 16-bit data length ...................................................................................... 30
Figure 3.12 Operation in 17 to 32-bit data length .................................................................................... 31
Figure 3.13 Operation example of full duplex communication ................................................................. 32
Figure 3.14 Operation example of transmit mode ................................................................................... 34
Figure 3.15 Operation example in receive mode ..................................................................................... 35
Figure 3.16 Data sampling timing of SPI mode (master) ......................................................................... 38
Figure 3.17 Data sampling timing of SPI mode (slave) ........................................................................... 39
Figure 3.18 Data sampling timing of SIO mode (master) ........................................................................ 39
Figure 3.19 Data sampling timing of SIO mode (slave) ........................................................................... 39
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Figure 3.20 Transfer format and timing adjustment(Example for 2 edge sampling) ............................ 40
Figure 3.21 Idle state in SPI mode and the transmit pin status ............................................................... 42
Figure 3.22 Idle state in SIO mode and the transmit pin status............................................................... 42
Figure 3.23 Circuit of interrupt request .................................................................................................... 44
Figure 3.24 Overrun error and underrun error ......................................................................................... 46
List of Tables
Table 1.1 Functional outline (SPI mode, master) .................................................................................... 10
Table 1.2 Functional outline (SPI mode, slave) ....................................................................................... 11
Table 1.3 Functional outline (SIO mode, master) .................................................................................... 12
Table 1.4 Functional outline (SIO mode, slave) ....................................................................................... 13
Table 2.1 List of Signals ........................................................................................................................... 15
Table 3.1 Example of f /ΦT0/ΦTx/ transfer clock and usability ............................................................. 27
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Table 3.2 Data format and settable fill level ............................................................................................. 29
Table 3.3 Usability of communication mode and data sampling timing................................................... 37
Table 3.4 Data capture timing .................................................................................................................. 37
Table 3.5 TSPIxTXD output during idle state .......................................................................................... 41
Table 3.6 Interrupt events and requests .................................................................................................. 44
Table 4.1 Initialized registers by software reset ....................................................................................... 49
Table 4.2 The timing of write "0" to <TRXE>, and state of <TSPISUE> ................................................. 60
Table 4.3 Current value of fill level depending on the range of <TLVL>/<RLVL> ................................... 60
Table 5.1 Transfer starting and stopping operation in each mode setting (Master) ................................ 62
Table 7.1 Revision History ....................................................................................................................... 65
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