Toshiba TXZ Series Reference Manual page 56

32-bit risc microcontroller, serial peripheral inteface tspi-b
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13:10
CSINT[3:0]
9:8
-
7:4
CSSCKDL[3:0]
3:0
SCKCSDL[3:0]
Note1: All data in the FIFO are discarded if <FL[5:0]> is changed remaining data in the FIFO even if
[TSPIxSR]<TSPISUE> is "0".
Note2: Please perform a <CKPOL> setup when transmission/reception is disabled ([TSPIxCR2]<TRXE>=0) at
the time of slave operation.
st
Note3: When use 1
"Setting value (Integer multiple of TSPIxSCK) + 0.5 × TSPIxSCK".
2019-02-28
0001
R/W
0
R
0000
R/W
0000
R/W
edge data sampling of master operation,
Idle time (Note3)
TSPIxCS0/1/2/3 invalidTSPIxCS0/1/2/3 valid time
0000: Prohibited
0001: 1 x TSPIxSCK cycle
0010: 2 x TSPIxSCK cycles
:
0111: 14 x TSPIxSCK cycles
1111: 15 x TSPIxSCK cycles
CS deassertion period until the start of next frame of
continuously transfer.
Even if selecting SIO mode, transfer waits <CSINT> setting
value time equivalent.
The setting is valid only in master mode.
Read as "0".
Serial clock delay
TSPIxCS0/1/2/3 validTSPIxSCK valid time
0000: 1 x TSPIxSCK 1000: 9 x TSPIxSCK
0001: 2 x TSPIxSCK 1001: 10 x TSPIxSCK
0010: 3 x TSPIxSCK 1010: 11 x TSPIxSCK
0011: 4 x TSPIxSCK 1011: 12 x TSPIxSCK
0100: 5 x TSPIxSCK 1100: 13 x TSPIxSCK
0101: 6 x TSPIxSCK 1101: 14 x TSPIxSCK
0110: 7 x TSPIxSCK 1110: 15 x TSPIxSCK
0111: 8 x TSPIxSCK 1111: 16 x TSPIxSCK
Set the time from the assertion of the TSPIxCS0/1/2/3 pin until
the TSPIxSCK pin changes in units of the serial clock cycle. The
setting is valid only in master mode.
TSPIxCS0/1/2/3 deassertion delay
Last data TSPIxCS0/1/2/3 invalid time
0000: 1 x TSPIxSCK 1000: 9 x TSPIxSCK
0001: 2 x TSPIxSCK 1001: 10 x TSPIxSCK
0010: 3 x TSPIxSCK 1010: 11 x TSPIxSCK
0011: 4 x TSPIxSCK 1011: 12 x TSPIxSCK
0100: 5 x TSPIxSCK 1100: 13 x TSPIxSCK
0101: 6 x TSPIxSCK 1101: 14 x TSPIxSCK
0110: 7 x TSPIxSCK 1110: 15 x TSPIxSCK
0111: 8 x TSPIxSCK 1111: 16 x TSPIxSCK
Set the time from the position of the last data until the
TSPIxCS0/1/2/3 pin is deasserted in units of the serial clock
cycle. The setting is valid only in master mode.
56 / 67
TXZ Family
Serial Peripheral Interface
Rev. 3.0

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