Toshiba TXZ Series Reference Manual page 63

Burst transfer
(Include single
transfer)
2019-02-28
A reception starts if receive buffer (receive FIFO or
receive shift register) is not full.
If the receive buffer is full, next frame cannot be
transferred. When reading the receive FIFO data, if
data in the shift register is automatically transferred to
the FIFO, the shift register is determined as not full
and a transfer is automatically restarted.
TSPIxCS0/1/2/3 stays asserted until a transfer starts
again. If a burst transfer is attempted again, set "1" to
<TRXE> after [TSPIxSR]<TSPISUE> bit was
returned to "0".
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TXZ Family
Serial Peripheral Interface
In reception, if <TRXE> is set to
stop, a transfer is stopped after a
frame in progress is complete.
Rev. 3.0