Toshiba TXZ Series Reference Manual page 59

20 TFEMP
19:16 TLVL[3:0]
15:8 -
7 RXRUN
6 RXEND
5 INTRXFF
4 RFFLL
3:0 RLVL[3:0]
2019-02-28
0: Don't care
1: Flag is cleared.
W
This bit is cleared by writing "1".
Transmit FIFO empty flag
0: Data exists in the FIFO.
1: Empty
0 R
When the transmit FIFO is empty, "1" is set.
If transmit data is written to the transmit FIFO, this bit is
automatically cleared to "0".
Transmit FIFO fill level status
Indicates the current value of the transmit FIFO fill level (number of
0000 R
data). Stages of the FIFO varies depending on the length of frame.
Table 4.3 shows the display range.
0 R Read as "0".
Receive operation flag
0: Stop
1: Operation
A status flag indicates the receive shift operation is ongoing.
Combination of <RXRUN> and <RFFLL> indicate the following
status.
0 R
<RXRUN>
Receive completion flag
0: -
1: Receiving is complete.
R
A flag that is set at the time when reception is complete.
This flag is set at the last frame (TSPIxCS0/1/2/3 is deasserted) in
the single transfer, burst transfer and continuously transfer after
0
one frame transfer.
This bit is cleared by writing "1".
0: Don't care
1: Flag is cleared.
W
When setting by reception completion and clearing by writing "1"
occur simultaneously, setting receives a higher priority.
Receive FIFO interrupt flag
0: No interrupt
1: Interrupt occurs
R
This bit is set when remaining data in the receive FIFO reaches an
0
RIL value from a fill level setting value (RIL)-1.
0: Don't care
1: Flag is cleared.
W
This bit is cleared by writing "1".
Receive FIFO full flag
0: A space exists in the FIFO
1: Full
0 R
Indicates that the receive FIFO is full.
This bit is automatically cleared if data is read from the receive
FIFO.
Receive FIFO fill level status
Indicates that the current value of the receive FIFO fill level
0000 R (number of data).
Stages of the FIFO varies depending on the length of frame. Table
4.3 shows the display range on <TLVL>.
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<RFFLL>
0 Stop or wait for next reception
0
The receive FIFO is FULL and
1
reception is complete.
1 - Receiving is ongoing.
TXZ Family
Serial Peripheral Interface
Conditions
Rev. 3.0