Chapter 4. System Theory Of Operation; Detailed Description; 8500C/C; Balancer/Analyzer Assembly - Honeywell Chadwick-Helmuth 8500C Maintenance Manual

Chapter 4 - System Theory of Operation
4.2

Detailed Description

4.2.1 8500C/C+

Balancer/Analyzer Assembly

4.2.1.1
The balancer/analyzer assembly contains four printed circuit boards, a digital board, an analog board, a
heater/EL control board, and a graphics module. The digital board contains memory, a microprocessor,
communications controllers, and a clock. The data acquisition (analog) board contains the analog
inputs, noise generator, input multiplexer, analog-to-digital converter (ADC), programmable gain
amplifier, anti-alias filters, and overload detector. The heater/EL control board provides backlighting
power for the display and heater power during low outside temperature conditions. The graphics
module contains an LCD and drivers for communicating with the user.
4.2.1.1.1 Analog Board (Figure 4-2)
The analog board receives analog input signals from the selected Velocimeter channel in the Signal
Selector 8520C or the onboard noise generator. The signals are then filtered, sampled, and converted to
digital form. The timing controller on the digital board provides programmable clock signals that
synchronize this process. The digitized output data are communicated over the system bus to the
microprocessor on the digital board. The data are then stored in memory for analysis and display as
directed by the user and firmware.
a. Noise Generator. The noise generator is a 12-bit, low drift, pseudorandom noise generator.
This precisely repeatable, broadband signal source provides a frequency, amplitude, and
phase reference for power-up characterization of the analog anti-alias filter. By injecting
this known signal into the input of the analog filter, the digital board firmware can
measure and record the unique frequency dependent characteristics of the analog filter
every time power is applied to the 8500C/C+. With this information, the firmware
compensates for filter component tolerances and drift that would otherwise degrade
system measurement accuracy. This feature also enables the system firmware to perform a
thorough front-to-back test of the analog board.
b. Multiplexer. The 2:1 multiplexer is controlled by the digital board timing controller. The
timing controller selects the signal from either the noise generator or the 8520C.
c. High-Pass Filter. The high-pass filter is a three-pole filter with a corner frequency of 2Hz.
The filter removes very low frequency signals and noise from the selected signal input.
Otherwise, high energy levels of these frequencies could affect the gain settings, reducing
the signal resolution.
d. Anti-Alias Filters. The anti-alias filters consist of an analog ten-pole Tchebyschev low-
pass filter which provides low passband ripple, short transition band, and high stopband
attenuation. The anti-alias filter consists of five two-pole sections. The initial two-pole
section has the lowest Q. The Q of each successive section is higher.
The first section is actually two side-by-side sections: a low-frequency section and a high-
frequency section. Only one of the two outputs is used at any given time. The appropriate
output is routed to the following section by a program-controlled 2:1 multiplexer. The
firmware automatically selects the low-frequency section for analysis of signals below
500 Hz. The high-frequency section is chosen for analysis above 500 Hz.
4-2 Chadwick-Helmuth A Business Unit of Honeywell International, Inc.