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In case of a wrong command or data frame, the interface is immediately locked and the device falls back to its
normal application mode. The read access to the device is triggered by clock pulses on the supply line as shown
in
Figure
3-4. The timing of read and write accesses is described in
internal buffer on
Figure 3-4 Frame Transmisson from the Sensor to the Programmer (Read Access)
3.3
Command Frame
The structure of a command frame is shown in
bits PE (bit 17) and PO (bit 18) have to be set in the follwing way (bit 0 is the LSB, bit 20 is the MSB):
bit0 XOR bit2 XOR bit4 XOR .... XOR bit20 = 0
bit1 XOR bit3 XOR bit5 XOR .... XOR bit19 = 0
MSB (bit 20)
P
P
1
1
O
E
Figure 3-5 Command Frame Structure
Table 3-2
List of Available Commands
Command
Bits (MSB...LSB)
0
000000
H
1
000001
H
3
000011
H
9
001001
H
B
001011
H
C
001100
H
D
001101
H
E
001110
H
F
001111
H
1) not to be followed by any data frame
2) followed by application of a programming pulse
3) followed by application of a margin voltage level before the last clock pulse falling edge
User's Manual
LSB
digital data readout, buffer in I/O mode
Figure
0
0
ADDR (6bit)
Function
Leave programming mode
Single data readout from given address without increment (sensor
response: one data frame)
Data readout from given address with increment (readout finishes
when address "xxx111
Single data write to given address without increment (followed by
one data frame)
Data write to given address with increment (followed by multiple data
frames; finishes at address "xxx111
command frame)
Enable EEPROM write mode (programs "1"-bits)
Enable EEPROM erase mode (programs "0"-bits)
Enable EEPROM margin check mode (programs level check)
EEPROM refresh (update EEPROM registers)
Chapter
VDD
Vout
MSB
3-5. Available commands are given in
1
0
1)
" is reached)
B
7
User's Manual
TLE4997 Programming
3.3.2.
tailing driver on
pulse
internal buffer on
Table
3-2. The parity
CMD (6bit)
" or by sending another
B
1)2)
1)2)
1)
v01_01, 2019-08
TLE4997
LSB (bit 0)
1
1)3)
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