Scope; Tle4997 Signal Processing - Infineon TLE4997 User Manual

1

Scope

This document is valid for all TLE4997 variants and derivates. It gives a detailed description of the configuration
and calibration procedure, which is recommended to configure the TLE4997 for optimum accuracy in a sensing
application.
2

TLE4997 Signal Processing

The TLE4997 uses a fully digital signal processing concept. Analog values from the Hall probe are directly
converted to raw digital signals by the Hall ADC and then compensated and processed in the digital signal
processing unit (DSP) using configuration parameters stored in the EEPROM and the temperature data acquired
by an integrated temperature sensor. A configurable second-order temperature polynomial is implemented to
compensate the thermal reduction of the remanent magnetic flux of a permanent magnet used in a position
sensing application. Additionally, an application-specific output characteristic can be set by configuring the
EEPROM parameters of Gain and Offset.
Hall
Sensor
Temperature
Sensor
TADC
A
Norm-
D
Figure 2-1 Signal Flow Diagram of the TLE4997
Figure 2-1 shows the signal flow diagram for temperature compensation and output characteristic in the DSP, and
the influence of the relevant configuration parameters stored in the EEPROM. The Hall signal is processed in the
following sequence of steps:
1. The analog Hall signal is converted by the Hall ADC, which operates at the configured magnetic range setting.
2. The digital value is filtered by a digital low-pass filter, which operates at a configurable filter frequency given
by the "LP filter"-setting. The output of the filter is stored in the HADC register.
3. The HADC value is multiplied by the temperature compensation polynomial and stored in the HCAL register.
The first order (TL) and second order (TQ) coefficients of the polynomial are configurable. The third order
coefficient (TT) is fixed.
4. The HCAL value is multiplied by the configured gain value.
5. The configured offset value is added to the HCAL value.
6. The digital Hall value is clamped according to the configured upper and lower clamping limits. The output value
of the clamping stage is converted from digital to analog.
7. An output voltage is transmitted on the OUT pin and is proportional to the supply voltage (ratiometric DAC).
User's Manual
Range LP
A
D
HADC
TL TQ
TCAL
T-Polynomial
alize
TT
Gain
Limiter
(Clamp)
x
+
X
HCAL
Offset
Stored in
EEPROM
Memory
4
TLE4997
User's Manual
VOUT
D
Out
A
VDAC
Clamping Low
Clamping High
v01_01, 2019-08
Scope