Data Memory - Spectrum Digital TMS320F240 Technical Reference

Spectrum Digital, Inc

2.2.2 Data Memory

The two data memory configurations are configured by jumper JP12. Configured in the
1-2 position the external RAM is enabled from 0x8000-0xffff. Loading the GREG
register will disable all or part the external memory, depending on the value, and allow
devices connected to the expansion bus to be accessed.
When JP12 is configured in the 2-3 position and jumper JP9 is also configured in the
2-3 position then the setting of the GREG register is used to remap the unused 32K of
RAM into the memory map. In this mode BR- is used to invert address A15. In other
words if BR- is inactive address 0x8000 would map to address 0x8000 in the RAM. If
BR- was active then address 0x8000 would be mapped to 0x0000 in the data RAM.
2-8
Data Space
Hex
0000 Memory-Mapped
Register and
005F Reserved
0060 On-Chip
007F DARAM B2
0080 Reserved
00FF
0100 On-Chip DARAM
B0 (CNF = 0)
01FF Reserved (CNF = 1)
0200 On-Chip DARAM
B0' (CNF = 0)
02FF Reserved (CNF = 1)
0300 On-Chip
03FF DARAM B1
On-Chip
0400
04FF DARAM B1'
Reserved
0500
07FF
0800 Illegal
6FFF
Peripheral Memory-
7000
Mapped Registers
(System, ADC, SCI,
73FF SPI, I/O, Interrupts)
Peripheral Memory-
7400
Mapped Registers
743F (Event Manager)
7440 Reserved
77FF
7800 Illegal
7FFF
8000 External RAM
FFFF
TMS320F240 Evaluation Module Technical Reference