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PTM0RPH Register
Bit 7
Name —
R/W —
POR —
Bit 7 ~ 2 Unimplemented, read as "0"
Bit 1 ~ 0 PTM0 CCRP High Byte Register bit 1 ~ bit 0
PTM0 10-bit CCRP bit 9 ~ bit 8
Periodic Type TM Operating Modes
The Periodic Type TM can operate in one of five operating modes, Compare Match Output Mode,
PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The
operating mode is selected using the PT0M1 and PT0M0 bits in the PTM0C1 register.
Compare Match Output Mode
To select this mode, bits PT0M1 and PT0M0 in the PTM0C1 register, should be set to 00
respectively. In this mode once the counter is enabled and running it can be cleared by three
methods. These are a counter overflow, a compare match from Comparator A and a compare match
from Comparator P. When the PT0CCLR bit is low, there are two ways in which the counter can be
cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all
zero which allows the counter to overflow. Here both PTMA0F and PTMP0F interrupt request flags
for Comparator A and Comparator P respectively, will both be generated.
If the PT0CCLR bit in the PTM0C1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the PTMA0F interrupt request flag will
be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore
when PT0CCLR is high no PTMP0F interrupt request flag will be generated. In the Compare Match
Output Mode, the CCRA can not be cleared to zero.
If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF
Hex, value, however here the PTMA0F interrupt request flag will not be generated.
As the name of the mode suggests, after a comparison is made, the PTM0 output pin, will change
state. The PTM0 output pin condition however only changes state when a PTMA0F interrupt request
flag is generated after a compare match occurs from Comparator A. The PTMP0F interrupt request
flag, generated from a compare match occurs from Comparator P, will have no effect on the PTM0
output pin. The way in which the PTM0 output pin changes state are determined by the condition of
the PT0IO1 and PT0IO0 bits in the PTM0C1 register. The PTM0 output pin can be selected using
the PT0IO1 and PT0IO0 bits to go high, to go low or to toggle from its present condition when a
compare match occurs from Comparator A. The initial condition of the PTM0 output pin, which is
setup after the PT0ON bit changes from low to high, is setup using the PT0OC bit. Note that if the
PT0IO1 and PT0IO0 bits are zero then no pin change will take place.
Rev. 1.20
BS82B12A-3/BS82C16A-3/BS82D20A-3
Touch Key 8-Bit Flash MCU with LED/LCD Driver
6 5 4
— — —
— — —
— — —
90
3 2 1
— — D9
— — R/W
— — 0
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0
D8
R/W
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