Table 10. Default Pin Configuration - Panasonic eUniStone Application Note Design Manual



If LPM wakeup output P0.0 is not used, it can be left open.

The GPIO pin P0.1 (pin E5) can be used to indicate the connection status. P0.1 is
configured as input pin by default. To use this feature the host must send the AT
command "AT+JGPC=FFFD,0000,0000,0000,FFFD" which configures P0.1 as an
output pin.
Above points are summarized in

Table 10. Default Pin Configuration

Interface Pin Name
UART F4 P0.14
UART E4 P0.0
UART E6 UARTRXD
UART F6 UARTCTS
A8 P1.5/CLK32
B9 P0.15/SLEEPX
E5 P0.1
B5 ONOFF
A3 RESET#
JTAG C3 JTAG#
JTAG B3 TMS / P1.0
JTAG D3 TCK / P1.1
JTAG F2 TDI / P1.2
JTAG B3 TDO / P1.3
JTAG B4 RTCK / P1.4
JTAG C4 TRST#
In case of using JTAG, the resistors shall be placed on the external JTAG connector.
Application Note
Design Guide
Table 10.
Note
If LPM is not used, this pin shall be pulled up to VDDUART.
If LPM is not used, this pin may be left open.
A 4.7 k pull up resistor can be needed to keep level in LPM.
A 4.7 k pull up resistor can be needed to keep level in LPM.
Internal LPO is used; this pin can be left open.
Not used. Leave open.
Indicating connection status, when configured as an output pin.
If not used, connect to VSUPPLY.
Shall be controlled by host I/O.
If JTAG interface is not used, this pin can be kept high; otherwise a 4.7 k pull down
resistor shall be used to enable JTAG.
If JTAG enabled: 4.7 k pull up; otherwise: leave open.
If JTAG enabled: 4.7 k pull up; otherwise: leave open.
If JTAG enabled: 4.7 k pull up; otherwise: leave open.
If JTAG enabled: 4.7 k pull up; otherwise: leave open.
If JTAG enabled: 4.7 k pull down; otherwise: leave open.
If JTAG enabled: 4.7 kpull down; otherwise: leave open.
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Revision 1.2, 2013-12-18
PAN1322