Reference Design Schematic - Panasonic eUniStone Application Note Design Manual

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6

Reference Design Schematic

The reference design schematic is shown in

VSUPPLY, VDDUART and VDD1 can be supplied by the same 3.3 V voltage.

C1 is only need to be placed in case noise is present from the power supply.
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All VSS pins must be connected to ground.
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All NC pins are internally not connected and can be left open.
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Since the internal LPO (low power oscillator) is used by the module then the
P1.5/CLK32 pin can be left open.
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Is strongly suggested having test point on P0.12/SDA0 and P0.13/SCL0. These can be
useful for debugging purpose.
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A test point on P0.1 or P0.8 is needed for crystal calibration in case the pre-stored
value is lost and for the HCI application for RF Testing.

The line UARTRXD and UARTCTS must remain high during low power mode. If the
host cannot drive them all the time, a pull-up might be needed.

For debugging, test points on the UART lines can be helpful. .

If JTAG interface is not used, JTAG# pin can be kept open (internal pull up). To
enable JTAG interface, a 4.7 k pull down resistor must be put on this pin.

RESET# pin shall be driven by the host. A pull-down of 4.7kOhm is strongly
recommended to reset the device when the power supply fails. See section
Power up

ONOFF pin shall be connected to VSUPPLY, if it is not used.

If LPM wakeup input P0.14 is not used, it shall be pulled up to VDDUART.
1
If only one voltage supply is used, then the ONOFF pin may not be used. The ONOFF
pin shall be connected to VSUPPLY.
2
No reference level or input signal shall be applied to the module while ONOFF is low.
Output signal levels are not defined while ONOFF is low.
Application Note
Design Guide
Figure 13.
Sequence.
41
PAN1322
1
3.1
2
Revision 1.2, 2013-12-18