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AN5010
Application note
SPC570Sx Getting Started
Introduction
®
The SPC570Sx devices family is built on Power Architecture
technology and is targeted for
ABS and airbag applications that require a high safety integrity level (ISO 26262 for ASIL-D
safety integrity).
In order to minimize additional software and module level features to reach this target, an
on-chip redundancy is offered for the critical components (see Functional Safety chapter of
RM) of the microcontroller by an e200z0Hn2p core, a DMA controller and an interrupt
controller in a delayed lockstep configuration, a crossbar bus system, a memory protection
unit, a fault collection and control unit (FCCU), Flash and SRAM with end-to-end error
correction coding (ECC) and End to end (E2E) protection on the data path and memory
ECC.
This family operates up to 80MHz and offers a high performance processing power specially
if compared with the previous family (SPC56) within a similar power envelope.
Some hardware in the new family also helps to prevent and control critical electronics
system faults and protects against harmful hacks.
This application note details the steps required to properly initialize the SPC570Sx devices
family from power-up to the code execution.
A development flow is described throughout the application note to explain the steps.
It is intended that this application note is read along with the SPC570Sx reference manual,
that can be obtained from the STMicroelectronics website at
http://www.st.com
(see
Section D.1: Reference
documents).
February 2017
DocID030311 Rev 1
1/44
www.st.com
1
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Table of Contents
Related Manuals for ST SPC570S Series
Summary of Contents for ST SPC570S Series
- Page 1 A development flow is described throughout the application note to explain the steps. It is intended that this application note is read along with the SPC570Sx reference manual, that can be obtained from the STMicroelectronics website at http://www.st.com (see Section D.1: Reference documents).
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Page 2: Table Of Contents
Contents AN5010 Contents Application example description ....... 6 Limitations ..........6 Family architecture . - Page 3 AN5010 Contents Appendix A Copy Initialized Data ........35 Appendix B Core registers initialization code .
- Page 4 List of tables AN5010 List of tables Table 1. Sub-Family features comparison ..........9 Table 2.
- Page 5 AN5010 List of figures List of figures Figure 1. SPC570Sx Block diagram ..........7 Figure 2.
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Page 6: Application Example Description
Application example description AN5010 Application example description This application note describes the necessary steps to configure the device in order to boot- up from the Flash and run independent codes out of internal Flash. This family (SPC57x) superseded the previous one (SPC56x): It is built on 55nm technology and indeed apart from the technological point of view (55nm versus the older 90nm) it has been designed to help the user to obtain an ISO26262 ASIL-D compliance for his applications (see... -
Page 7: Family Architecture
AN5010 Family architecture Family architecture Two identical e200z0Hn2p processors (see Figure 1: SPC570Sx Block diagram) are used: the main core, which executes the software application, and the safety core, linked to the main core in delayed lock-step mode for ASIL-D safety requirements. The e200z0h processor family is a CPU core that it implement cost-efficient versions of the Power Architecture®. -
Page 8: Figure 2. E200Z0H Block Diagram
Family architecture AN5010 Figure 2. e200z0h block diagram OnCE/Nexus Control Logic Control Logic Integer Nexus Execution Debug Unit Unit Multiply Instruction Unit Unit Instruction Buffer Control External Interface Data (MTSPR/MFSPR) Branch Unit Unit Load/ Store Unit Data Bus Interface Unit Address Data Control... -
Page 9: Differences Across Sub-Family
AN5010 Family architecture Differences across sub-family Table 1. Sub-Family features comparison SPC570S40x SPC570S50x Flash 256KB 512KB SRAM 32KB 48KB FlexCAN Other aligned to Superset 1. 128KB Block 0 and 128KB Block 1 excluded on SPC570S40x. 2. [0x4000_8000 - 0x4000_BFFF] out of complete [0x4000_0000 - 0x4000_BFFF] System RAM only available on SPC570S50. - Page 10 Family architecture AN5010 Table 2. Flash Memory Map (continued) Start Address End address Field RWW partition ID 0x00FC_8000 0x00FC_BFFF Flash 16 KB Code Block 2 0x00FC_C000 0x00FC_FFFF Flash 16 KB Code Block 3 0x00FD_0000 0x00FD_7FFF Flash 32KB Code Block 0 0x00FD_8000 0x00FD_FFFF Flash 32KB Code Block 1...
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Page 11: Reset And Boot
AN5010 Reset and boot Reset and boot The power-up reset sequence always begins with the application of the power and follows different sequences depending on enabled option settings in the DCF records. This allows the user to control several configuration parameters and customize the final behavior of the device (see Section D.1: Reference documents). -
Page 12: Boot From Internal Flash
Reset and boot AN5010 Figure 3. Modules involved in Reset and Boot process Since this document is focused on how to boot-up the device from the internal flash (with no use of security/safety functions) in the following sections will be detailed how the user has to configure the device (and its own code) to choose the proper behavior. -
Page 13: Table 3. Boot Record Structure
AN5010 Reset and boot The system configuration is set as application boot records and is programmed by the customer. It is used to set the customer application entry point after reset or after the BAF execution (if enabled). Figure 4 shows the various possible system boots. -
Page 14: Boot Header Format And Boot Search Locations
Reset and boot AN5010 3.1.1 Boot Header format and Boot search locations The boot header (see Table 3: Boot record structure) is used to supply a software entry point to the core: It is written by the user and loaded into specific locations in the flash memory (see Table 4: Boot record search locations). -
Page 15: Hw Boot Record Search (Sscm Search)
AN5010 Reset and boot the software will start from the BAF (see Section 3.1.3: SW boot record search (BAF search)). 3.1.2 HW boot record search (SSCM search) The SSCM module looks (see Figure 4: Processor Boot) for a valid software entry point called SSCM boot record (see Table 3: Boot record structure).... -
Page 16: Spc570Sx Initialization Example
SPC570Sx initialization example AN5010 SPC570Sx initialization example As soon the device ends reset phase, in order to run an application from the Flash memory, user code has to perform a series of basic initializations (see Section 4.1: Initialization steps) so to make the device able to run user application taking also into account safety related initializations (core registers, SRAM, software watchdog) so to avoid safety reactions as defined by the device’s safety architecture. -
Page 17: Initialization Steps
AN5010 SPC570Sx initialization example Initialization steps Below the list of initialization steps the user has to do to run the application from the flash for a proper execution: Valid boot header (see Section 4.2: A valid Boot Header) setting ... - Page 18 SPC570Sx initialization example AN5010 When enabled, the SWT requires periodic execution of a watchdog servicing operation. In order to prevent a system reset the watchdog must be serviced or disabled prior to the initial expiry of the timer. In a real application it is expected that the SWT would be serviced (before the timer expires) and reconfigured to match the application timing rather than being disabled.
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Page 19: Core Registers Initialization
AN5010 SPC570Sx initialization example Core registers initialization 4.4.1 EABI Register initialization The Power Architecture Enhanced Application Binary Interface (EABI) specifies certain general purpose registers as having special meaning for the C code execution. It defines the system interface for the compiled programs (see Table 5: Power Architecture EABI Registers). -
Page 20: Core Register Initialization
SPC570Sx initialization example AN5010 Below an example code to initialize these three pointers: e_lis r1, __SP_INIT@h ;# Initialize stack pointer r1 to e_or2i r1, __SP_INIT@l ;# value in linker command file. e_lis r13, _SDA_BASE_@h ;# Initialize r13 to sdata base e_or2i r13, _SDA_BASE_@l ;# (provided by linker). -
Page 21: Figure 6. E200Z0H Supervisor Mode Program Model Sprs
AN5010 SPC570Sx initialization example Figure 6. e200z0h SUPERVISOR mode program model SPRs SUPERVISOR mode program model SPRs General Registers Exception Handling/Control Registers SPR General Save and Restore Condition Register General-Purpose Registers SPRG0 SPR 272 SRR0 SPR 26 GPR0 SPRG1 SPR 273 SRR1 SPR 27 Count Register... -
Page 22: Enable Branch Target Buffer
SPC570Sx initialization example AN5010 Enable Branch Target Buffer The SPC570Sx Power Architecture core (e200zx) features a branch prediction optimization which can be enabled to improve the overall performance by storing the results of branches and using that to predict the direction of the future branches at the same location. To initialize it, the user needs to flush, invalidate the buffer and enable branch prediction: This can be also accomplished with a single write to the Branch Unit Control and Status Register (BUCSR) in the core. -
Page 23: Figure 7.Sram Ecc Initialization Flow
AN5010 SPC570Sx initialization example Figure 7.SRAM ECC Initialization flow DocID030311 Rev 1 23/44... -
Page 24: Environment Initializations
SPC570Sx initialization example AN5010 Below the code to initialize the SRAM ECC: ;#/*==================================================================*/ ;# macro to initialize sram_ecc ;# param size_value: ram size [bytes] ;# param addr_value: base address .macro sram_ecc_init size_value addr_value ;#********************** Initialise SRAM ECC ****************************/ ;# Store number of 128Byte (32GPRs) segments in Counter e_lis r5, size_value@h;#/* Initialize r5 to size of SRAM (Bytes) */ e_or2i r5, size_value@l;#/* */ e_srwi r5, r5, 0x7;#/* Divide SRAM size by 128 */... -
Page 25: Xbar Configuration
AN5010 SPC570Sx initialization example Figure 8.Booting flow using GHS startup libraries XBAR Configuration The crossbar switch connects bus masters and bus slaves using a hardware interconnect matrix. This structure allows all bus masters to access the different bus slaves simultaneously with no interference while providing arbitration among the bus masters when they access the same slave. -
Page 26: Xbar Registers Configuration
SPC570Sx initialization example AN5010 Figure 9.Crossbar switch integration It is suggested to configure XBAR in order to balance data workloads across the architecture and to improve application performances. For this purpose a control register is available (XBAR_CRSn) for each slave (see Section 4.8.1: XBAR Registers configuration). -
Page 27: Flash Memory Access
AN5010 SPC570Sx initialization example (* (uint32_t *)0xFC004110) = 0x00FF0000; /* S1 Slave: IBUS(M0) */ /* System RAM */ (* (uint32_t *)0xFC004210) = 0x00FF0001; /* S2 Slave: DBUS(M1) */ /* PBRIDGE_0 */ (* (uint32_t *)0xFC004310) = 0x00FF0001; /* S3 Slave: DBUS(M1) */ /* PBRIDGE_1 */ (* (uint32_t *)0xFC004410) = 0x00FF0001;... -
Page 28: Memory Controllers Configuration
SPC570Sx initialization example AN5010 Memory Controllers configuration 4.9.1 Flash Controller configuration The flash memory controller supports 2 32-bit AHB buses and a 128-bit read data interface to the flash memory array (see D.1: Reference documents for further details). Each AHB port contains a 4-entry, 2-way set-associative mini-cache (see Figure 10: 2-way, 4-entry mini-cache... -
Page 29: Sram Wait State
AN5010 SPC570Sx initialization example configured for desired target system clock frequency (see D.1: Reference documents). Note: When modifying characteristics for a memory, it is good practice not to execute code in the same memory that is having its characteristics modified. Hence the code to modify the flash performance parameters of the module’s configuration registers will be executed from the SRAM. - Page 30 SPC570Sx initialization example AN5010 Figure 11.Mode Entry Diagram In order to use all of the available modes, they must be enabled in the Mode Enable register. Below a scratch code that shows how to configure it: #define DRUN_MODE 0x3 MC_ME.ME.R = 0x000005E2; /* Enable all modes */ /* MC_ME.DRUN_MC.R not yet configured...IRC Osc by default */ /* Setting RUN Configuration Register ME_RUN_PC[0] */...
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Page 31: Clock And Pll Configuration
AN5010 SPC570Sx initialization example /* Wait for mode entry to complete */ while(MC_ME.GS.B.S_MTRANS == 1); /* Check DRUN mode has been entered */ while(MC_ME.GS.B.S_CURRENT_MODE != # DEFINE DRUN_MODE 0x3); / Note: In the device configuration flow, in order to take effect all changes in all clock and mode ... -
Page 32: Figure 12.Spc570Sx Clock Generation
SPC570Sx initialization example AN5010 Figure 12.SPC570Sx Clock Generation 32/44 DocID030311 Rev 1... - Page 33 AN5010 SPC570Sx initialization example This family devices boot from the internal 16 MHz RC oscillator (IRCOSC) and use this as a backup clock in the event of a PLL or oscillator failure. See also “Mode Entry Module (MC_ME)” chapter listed into D.1: Reference documents.
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Page 34: Blink Led Application
Blink LED application AN5010 Blink LED application As soon the core has ended its own initialization flow (see Section 4: SPC570Sx initialization example) the user can finally execute his application. In the example described application). in this document a blink led code is shown (see Figure 13: Blink LED After the pin configuration through MSCR register inside SIUL2 peripheral (see D.1:... -
Page 35: Appendix A Copy Initialized Data
AN5010 Copy Initialized Data Appendix A Copy Initialized Data When the applications boot from flash, the program image stored in flash will contain the various data segments created by the C compiler and linker. Initialized read-write data must be copied from read-only flash to read-writable SRAM before execution flow reaches the application. - Page 36 Copy Initialized Data AN5010 e_bdnz SDATACPYLOOP ;# Branch if more bytes to load from ROM ROMCPYEND: Note: __DATA_SIZE, __DATA_ROM_ADDR, __DATA_SRAM_ADDR, __SDATA_SIZE, __SDATA_ROM_ADDR, __SDATA_SRAM_ADDR have to be defined in the linker file 36/44 DocID030311 Rev 1...
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Page 37: Appendix B Core Registers Initialization Code
AN5010 Core registers initialization code Appendix B Core registers initialization code ;#/*==================================================================*/ ;# macro to init registers to a know value .macro REG_init ;# GPR's 0-31 e_li r0, 0 e_li r1, 0 e_li r2, 0 e_li r3, 0 e_li r4, 0 e_li r5, 0 e_li... - Page 38 Core registers initialization code AN5010 ;# Init any other CPU register which might be stacked (before being used). mtspr 1,r1;#XER mtcrf 0xFF, r1 mtspr CTR, mtspr SPRG0, r1 mtspr SPRG1, r1 mtspr SRR0, r1 mtspr SRR1, r1 mtspr CSRR0, r1 mtspr CSRR1, r1 mtspr DSRR0, r1 mtspr DSRR1, r1...
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Page 39: Appendix C Clocks And Plls Initialization Example
AN5010 Clocks and PLLs Initialization example Appendix C Clocks and PLLs Initialization example #define DRUN_MODE 0x3 #define DIVIDEBY1 0x0 #define DIVIDEBY2 0x1 #define DIVIDEBY3 0x2 #define SELCTL_16MHz_IRC 0x0/* Internal RC Osc */ #define SELCTL_CRYSTAL_OSC 0x1/* External Osc */ #define SELCTL_PLL0 0x2 /* PLL0 PHI */ #define SELCTL_PLL0_PH1 0x3 /* PLL0 PHI1 */ #define SELCTL_PLL1 0x4... - Page 40 Clocks and PLLs Initialization example AN5010 /* wait for PLL to lock - will not lock before DRUN re-entry */ while(PLLDIG.PLL0SR.B.LOCK == 0) { asm("nop"); while(PLLDIG.PLL1SR.B.LOCK == 0) { asm("nop"); MC_CGM.SC_DC1.B.DIV = DIVIDEBY2;/* Peripheral Clock Divide by 2 */ MC_CGM.SC_DC0.B.DIV = DIVIDEBY1;/* System Clock Divide by 1 */ /* Enable and configure Aux clocks */ /* AUX Clock Selector 0 */ MC_CGM.AC0_SC.B.SELCTL = SELCTL_PLL0;/* PLL0 PHI */...
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Page 41: Appendix D Further Information
AN5010 Further Information Appendix D Further Information Reference documents ® 32-bit Power Architecture microcontroller for automotive ASILD Chassis and Safety applications (RM0349, DocID024507) ® 32-bit Power Architecture microcontroller for automotive ASILD Chassis and Safety applications (Datasheet, DocID024492) Hw recommendations for SPC570Sx device family (AN4721, DocID027988) Safety Manual for SPC570S family (AN4247, DocID024209) SPC570Sx Errata sheet (ES0278, DocID026793) Transition from SPC560P50x to SPC570S50x (AN4405, DocID025566) - Page 42 Further Information AN5010 Table 7. Acronyms and abbreviations (continued) Terms Meaning Memory Protection Unit Power Management Controller Power Management Unit Phase Locked Loop SIPI Serial Interprocessor Interface System on Chip Sphere of Replication SSCM System status and configuration module STMicroelectronics STCU2 Self-Test Control Unit Software Watchdog Timer...
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Page 43: Revision History
AN5010 Revision history Revision history Table 8. Revision history Date Revision Changes 07-Feb-2017 Initial release. DocID030311 Rev 1 43/44... - Page 44 ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
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